Liquid crystal display panel

Abstract

The invention provides a liquid crystal display panel. The liquid crystal display panel comprises a plurality of pixels arranged along a row direction and a column direction, wherein the pixels comprise transistors; a plurality of data lines extending in the column direction and including a first data line and a second data line; the first data line and the second data line extend in the row direction and intersect with the multiple data lines, the first data line and the second data line are arranged between every two adjacent pixel columns, and the first data line and the second data line are partially overlapped in the thickness direction of the liquid crystal display panel. According to the invention, a 1G2D driving mode can be realized, and the problem that the aperture opening ratio is reduced can be avoided.

Description

[0001] This application is a divisional application of the application with the application date of January 19, 2020, application number 2020100611689, and invention name "Liquid Crystal Display Panel". Technical Field

[0002] The present invention relates to a liquid crystal display panel, and particularly to a liquid crystal display panel adopting a 1G2D (one gate line and two data line) driving method. Background Art

[0003] With the continuous improvement of users' requirements for display quality, the number of pixels of liquid crystal display panels has been continuously increasing. Correspondingly, the writing time of each pixel row has gradually become shorter, posing a greater challenge to the accurate writing of potentials. As one of the solutions, the 1G2D driving method has been proposed. In this 1G2D driving method, the number of scan lines equal to the number of pixel rows is set, the scan lines of two adjacent pixel rows are connected together, and the number of data lines twice the number of pixel columns is set, and the pixels in the same column are alternately connected to one or the other of the two data lines. Summary of the Invention

[0004] The present invention provides a liquid crystal display panel, including: a plurality of pixels arranged in a row direction and a column direction, the pixels including transistors; a plurality of data lines extending along the column direction and including a first data line and a second data line; and a plurality of scan lines extending along the row direction and intersecting with the plurality of data lines, wherein the first data line and the second data line are disposed between two adjacent pixel columns, and the first data line and the second data line partially overlap in the thickness direction of the liquid crystal display panel. Description of the Drawings

[0005] The drawings included in the specification and constituting a part of the specification show exemplary embodiments, features, and aspects of the present invention together with the specification, and are used to explain the principles of the present invention.

[0006] Figure 1 is a diagram schematically showing the schematic structure of a liquid crystal display device LCD related to the present invention.

[0007] Figure 2 is a diagram showing the pixel circuit of a liquid crystal display panel LCP related to the present invention.

[0008] Figure 3 is a partial enlarged view of a first example of the liquid crystal display panel LCP related to the present invention when observed from the observer side.

[0009] Figure 4 is showing Figure 3Cross-sectional view of the A-A cross-sectional structure in

[0010] Figure 5 is a view showing Figure 3 Cross-sectional view of the B-B cross-sectional structure in

[0011] Figure 6 is a partial enlarged view of the second example of the liquid crystal display panel LCP according to the present invention when viewed from the observer side.

[0012] Figure 7 is a view showing Figure 6 Cross-sectional view of the C-C cross-sectional structure in

[0013] Figure 8 is a partial enlarged view of the third example of the liquid crystal display panel LCP according to the present invention when viewed from the observer side.

[0014] Figure 9 is a view showing Figure 8 Cross-sectional view of the D-D cross-sectional structure in

[0015] Figure 10 is a partial enlarged view of the fourth example of the liquid crystal display panel LCP according to the present invention when viewed from the observer side.

[0016] Figure 11 is a partial enlarged view of the fifth example of the liquid crystal display panel LCP according to the present invention when viewed from the observer side.

[0017] Figure 12 is a partial enlarged view of the liquid crystal display panel as a comparative example when viewed from the observer side. Detailed Description of the Invention

[0018] Hereinafter, various exemplary embodiments, features, and aspects of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0019] In addition, for a better understanding of the present invention, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present invention can be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present invention.

[0020] First, the liquid crystal display device LCD and the liquid crystal display panel LCP using the 1G2D driving method according to the present invention will be described using Figure 1 and Figure 2 Figure 1 ​It is a diagram schematically showing the schematic structure of the liquid crystal display device LCD related to the present invention. Figure 2 It is a diagram showing the pixel circuit of the liquid crystal display panel LCP related to the present invention.

[0021] The liquid crystal display device LCD is an example of an image display device that displays still images or moving images. As Figure 1 shown, the liquid crystal display device LCD may include a liquid crystal display panel LCP, a liquid crystal display panel driving circuit PDC (data line driving circuit DDC, scan line driving circuit SDC), a backlight BL, and an image processing unit IPU.

[0022] The liquid crystal display panel LCP is disposed on the light-emitting side of the backlight BL. The liquid crystal display panel LCP displays a color image or a monochrome image in the image display area DSP. As Figure 2 shown, the liquid crystal display panel LCP includes a plurality of pixels PIX arranged in the row direction and the column direction.

[0023] The backlight BL is disposed on the back side of the liquid crystal display panel LCP and irradiates light to the liquid crystal display panel LCP. The backlight BL may be an LED backlight using an LED (Light Emitting Diode) as a light source, but is not limited thereto. The backlight BL may be a direct-lit LED backlight in which LEDs are arranged two-dimensionally on a substrate in a manner facing the liquid crystal display panel LCP, but may also be a side-entry type. In addition, the backlight BL may be a surface light-emitting unit that irradiates planar uniform scattered light (diffused light) by providing a diffusion plate that diffuses light from the light source.

[0024] The image processing unit IPU may be a control device including an arithmetic processing circuit such as a CPU and memories such as a ROM and a RAM, and executes various processes by the CPU reading and executing a program stored in the memory. The image processing unit IPU receives the input of display data to be displayed on the liquid crystal display panel LCP, performs various image signal processes such as color adjustment on the display data, generates an image signal representing the gray value of each pixel PIX and a timing signal representing the timing of writing the image signal to each pixel PIX, outputs the image signal to the data line driving circuit DDC, and outputs the timing signal to the scan line driving circuit SDC.

[0025] As Figure 2As shown, a data line driving circuit DDC is connected to data lines DL extending in a column direction of a liquid crystal display panel LCP. In correspondence with selection of scan lines SL of a scan line driving circuit SDC, the data line driving circuit DDC supplies a signal voltage corresponding to an image signal input from an image processing unit IPU to the data lines DL. The scan line driving circuit SDC is connected to scan lines SL extending in a row direction of the liquid crystal display panel LCP and intersecting the data lines DL. The scan line driving circuit SDC selects pixels PIX to which an image signal is to be written in accordance with a timing signal input from the image processing unit IPU, and supplies a voltage (gate-on voltage) for turning on a transistor TR of the selected pixels PIX to the scan lines SL. Each pixel PIX includes a pixel electrode PIT and a transistor TR. A gate electrode G of the transistor TR is electrically connected to the scan line SL, a drain electrode D of the transistor TR is electrically connected to the data line DL, and a source electrode S of the transistor TR is electrically connected to the pixel electrode PIT.

[0026] Thus, when the gate-on voltage is supplied from the scan line driving circuit SDC to the scan line SL, the transistor TR of the selected pixels PIX is turned on, and the signal voltage is supplied from the data line DL connected to the transistor TR to the pixel electrode PIT. An electric field is generated in the liquid crystal layer by a difference between the signal voltage supplied to the pixel electrode PIT and a common voltage supplied to a common electrode MIT. The alignment state of liquid crystal molecules in the liquid crystal layer of each pixel PIX is changed by the electric field, and the transmittance of light from a backlight BL of the liquid crystal display panel LCP is controlled for each pixel PIX. Accordingly, a desired image is displayed in an image display area DSP of the liquid crystal display panel LCP.

[0027] As Figure 2 shown, in the case of adopting a 1G2D driving method, a first scan line SL1 and a second scan line SL2 are connected to each other, and the scan line driving circuit SDC inputs a gate-on voltage (scan voltage) to the first scan line SL1 and the second scan line SL2 at the same timing. A first data line DL1 and a second data line DL2 are provided between two adjacent pixel columns, and the data line driving circuit DDC supplies signal voltages to the first data line DL1 and the second data line DL2, respectively. A drain electrode of a transistor electrically connected to one of the first scan line SL1 and the second scan line SL2 is electrically connected to one of the first data line DL1 and the second data line DL2, and a drain electrode of a transistor electrically connected to the other of the first scan line SL1 and the second scan line SL2 is electrically connected to the other of the first data line DL1 and the second data line DL2.

[0028] Specifically, in Figure 2In the example shown, the gate electrodes of the transistors of the pixels in the nth (n > 0 and n is an integer) and n + 2nd rows are electrically connected to the first scan line SL1, and the drain electrodes are electrically connected to the second data line DL2 located on the left side of the pixel. The gate electrodes of the transistors of the pixels in the n + 1st and n + 3rd rows are electrically connected to the second scan line SL2, and the drain electrodes are electrically connected to the first data line DL1 located on the right side of the pixel.

[0029] Since the two scan lines SL are connected together, the scan line driver circuit SDC can provide a pulse signal with a pulse width twice that of the pulse width when the 1G2D driving method is not adopted to the connected first scan line SL1 and second scan line SL2 as the gate turn-on voltage shared by the first scan line SL1 and the second scan line SL2, thereby extending the writing time of each pixel row.

[0030] When adopting the 1G2D driving method as described above, a wiring method that is a comparative example of the present invention is usually adopted, such as Figure 12 shown. As Figure 12 shown, in this comparative example, the first data line DL1 and the second data line DL2 extend in parallel along the column direction and are arranged side by side in the same layer between two pixel columns. Such a wiring method can be easily realized in the manufacturing process. However, the inventors of the present application found that if such a wiring method is adopted, compared with the case where the 1G2D driving method is not adopted, the increase in the data lines will force the area of the pixel electrode PIT to shrink, resulting in a problem of a decrease in the aperture ratio of the display panel.

[0031] To solve this problem, the inventors of the present application proposed a new wiring method, which partially overlaps the first data line DL1 and the second data line DL2 in the thickness direction of the liquid crystal display panel LCP, thereby reducing the area occupied by the data lines, and can both realize the 1G2D driving method and avoid the problem of a decrease in the aperture ratio. The following will combine Figure 3-11 to describe each example of the liquid crystal display panel related to the present invention in detail.

[0032] Figure 3 、 Figure 4 and Figure 5 show the first example of the liquid crystal display panel LCP related to the present invention. Among them, Figure 3 is a partial enlarged view of the liquid crystal display panel when observed from the observer side, Figure 4 is a cross-sectional view showing the cross-sectional structure of A-A in Figure 3 , Figure 5 is a view showing Figure 3Cross-sectional view of the B-B cross-sectional structure in []. In the first example, an upper-layer wiring and a lower-layer wiring formed in different layers in the thickness direction of the liquid crystal display panel LCP are connected to form a first data line DL1 and a second data line DL2, and the upper-layer wiring and the lower-layer wiring partially overlap in the thickness direction.

[0033] Specifically, as Figure 3 shown, the first data line DL1 includes a first upper-layer wiring UW1 and a first lower-layer wiring LW1 that are alternately arranged in the column direction, and the second data line DL2 includes a second upper-layer wiring UW2 and a second lower-layer wiring LW2 that are alternately arranged in the column direction.

[0034] Both the first upper-layer wiring UW1 and the second upper-layer wiring UW2 are Z-shaped, and each includes a first upper-layer wiring portion UWP1, a second upper-layer wiring portion UWP2, and a third upper-layer wiring portion UWP3. The first upper-layer wiring portion UWP1 and the second upper-layer wiring portion UWP2 extend along the column direction. The third upper-layer wiring portion UWP3 extends along the row direction and connects the first upper-layer wiring portion UWP1 and the second upper-layer wiring portion UWP2. Both the first lower-layer wiring LW1 and the second lower-layer wiring LW2 are L-shaped, and each includes a first lower-layer wiring portion LWP1 and a second lower-layer wiring portion LWP2. The first lower-layer wiring portion LWP1 extends along the column direction. The second lower-layer wiring portion LWP2 extends along the row direction and is connected to one end of the first lower-layer wiring portion LWP1. Optionally, the third upper-layer wiring portion UWP3 and the second lower-layer wiring portion LWP2 may extend in a direction other than the row direction and intersecting the column direction.

[0035] By electrically connecting the end of the first upper-layer wiring portion UWP1 of the first upper-layer wiring UW1 on the opposite side of the third upper-layer wiring portion UWP3 to the end of the second lower-layer wiring portion LWP2 of the first lower-layer wiring LW1 on the upstream side in the column direction and on the opposite side of the first lower-layer wiring portion LWP1, and electrically connecting the end of the second upper-layer wiring portion UWP2 of the first upper-layer wiring UW1 on the opposite side of the third upper-layer wiring portion UWP3 to the end of the first lower-layer wiring portion LWP1 of the first lower-layer wiring LW1 on the downstream side in the column direction and on the opposite side of the second lower-layer wiring portion LWP2, the first upper-layer wiring UW1 and the first lower-layer wiring LW1 alternately arranged in the column direction are connected to form the first data line DL1. In a similar manner, the second upper-layer wiring UW2 and the second lower-layer wiring LW2 alternately arranged in the column direction are connected to form the second data line DL2.

[0036] According to the relative positional relationship between the first data line DL1 and the second data line DL2, the liquid crystal display panel LCP may include a first overlapping region R1, a first switching region R2, a second overlapping region R3, and a second switching region R4. The first overlapping region R1, the first switching region R2, the second overlapping region R3, and the second switching region R4 are arranged in sequence along the column direction. In the first overlapping region R1, the second upper wiring portion UWP2 of the first upper wiring UW1 overlaps with the first lower wiring portion LWP1 of the second lower wiring LW2 in the thickness direction. In the first switching region R2, the first data line DL1 switches from the first upper wiring UW1 to the first lower wiring LW1 at the first switching point SP1, and the second data line DL2 switches from the second lower wiring LW2 to the second upper wiring UW2 at the second switching point SP2. In the second overlapping region R3, the first lower wiring portion LWP1 of the first lower wiring LW1 overlaps with the second upper wiring portion UWP2 of the second upper wiring UW2 in the thickness direction. In the second switching region R4, the first data line DL1 switches from the first lower wiring LW1 to the first upper wiring UW1 at the third switching point SP3, and the second data line DL2 switches from the second upper wiring UW2 to the second lower wiring LW2 at the fourth switching point SP4.

[0037] As Figure 4 shown, the first upper wiring UW1 and the second upper wiring UW2 are formed on the data line upper layer DUL, the first lower wiring LW1 and the second lower wiring LW2 are formed on the data line lower layer DLL, and the data line lower layer DLL is closer to the backlight side than the data line upper layer DUL. To reduce the mutual influence between the data lines, optionally, the data line lower layer DLL may be disposed closer to the backlight side than the scan line layer SLL on which the scan lines SL are formed, that is, the scan line layer SLL is disposed between the data line upper layer DUL and the data line lower layer DLL, so as to reduce the signal delay caused by the mutual influence. Further optionally, to simplify the process, the lower wiring, that is, the data line lower layer DLL, may be directly formed on the substrate SUB on the backlight side of the two substrates disposed opposite to each other in the liquid crystal display panel LCP, that is, the data line lower layer DLL is located between the scan line layer SLL and the substrate SUB. However, the above structure is merely exemplary, and the present invention does not limit the specific position of the data line lower layer.

[0038] As Figure 4As shown in the AA cross-sectional structure passing through the third switching point SP3, the upper end of the conductor CT penetrating the scan line layer SLL contacts the first upper wiring UW1, and the lower end contacts the left end of the first lower wiring LW1 (the end of the second lower wiring portion LWP2 located on the opposite side of the first lower wiring portion LWP1), thereby electrically connecting the first lower wiring LW1 to the first upper wiring UW1, so that the first data line DL1 is switched from the first lower wiring LW1 to the first upper wiring UW1. Figure 5 As shown in the BB cross-sectional structure in the second overlapping region R3 , the second upper wiring UW2 overlaps the first lower wiring LW1 in the thickness direction via the scanning line layer SLL.

[0039] like Figure 3 As shown, in the first switching region R2, the first scan line SL1 passes through the first switching region R2, the first switching point SP1 and the second switching point SP2 are located on both sides of the first scan line SL1, and the first upper wiring UW1 and the second upper wiring UW2 cross the first scan line SL1 above the first scan line SL1. The first upper wiring UW1 is electrically connected to the transistor TR located on its left side. In order to facilitate the connection with the first upper wiring UW1, the transistor TR is located on the side where the first upper wiring UW1 is located, that is, the right side, relative to the central part of the pixel electrode PIT to which it is connected. The second upper wiring UW2 is located on the opposite side of the first upper wiring UW1, that is, the right side.

[0040] In the second switching region R4, the second scan line SL2 passes through the second switching region R4, the third switching point SP3 and the fourth switching point SP4 are located on both sides of the second scan line SL2, and the first upper wiring UW1 and the second upper wiring UW2 cross the second scan line SL2 above the second scan line SL2. The second upper wiring UW2 is electrically connected to the transistor TR located on its right side. In order to facilitate the connection with the second upper wiring UW2, the transistor TR is located on the side where the second upper wiring UW2 is located, that is, on the left side relative to the central part of the pixel electrode PIT. The first upper wiring UW1 is located on the side of the second upper wiring UW2 opposite to the transistor, that is, on the left side.

[0041] As described above, in the first example, in the first overlapping area R1 and the second overlapping area R3, the first data line DL1 and the second data line DL2 overlap in the thickness direction, and in the first switching area R2 and the second switching area R4, the first data line DL1 and the second data line DL2 switch between the upper wiring and the lower wiring and are connected to the transistor, so that 1G2D driving can be performed while maintaining the aperture ratio.

[0042] Figure 6 and Figure 7Shows a second example of the liquid crystal display panel LCP involved in the present invention. Among them, Figure 6 is a partial enlarged view of the liquid crystal display panel when observed from the observer side, Figure 7 is to show Figure 6 The interface diagram of the C-C cross-sectional structure in. Figure 6 and 7 The main difference between the second example shown and the first example shown in Figure 3-5 is that by changing the shapes of the upper-layer wiring and the lower-layer wiring, in the first switching region R2 and the second switching region R4, the data lines not connected to the transistors are located below the scan lines.

[0043] In the first example, as described above, in the first switching region R2 and the second switching region R4, the first data line DL1 and the second data line DL2 cross the scan lines above the scan lines. Compared with the first data line DL1 and the second data line DL2, the scan lines are thicker. Therefore, when the first data line DL1 and the second data line DL2, which are thin lines, cross above the scan lines, which are thick lines, the probability of disconnection of the first data line DL1 and the second data line DL2 increases significantly. To reduce this risk, in the second example, only the one of the first data line DL1 and the second data line DL2 that is electrically connected to the transistor is located above the scan line, and the other that is not electrically connected to the transistor is located below the scan line.

[0044] Specifically, as shown in Figure 6 , the first upper-layer wiring UW1 and the second upper-layer wiring UW2 are in an L shape, each including a fourth upper-layer wiring portion UWP4 and a fifth upper-layer wiring portion UWP5. The fourth upper-layer wiring portion UWP4 extends along the column direction. The fifth upper-layer wiring portion UWP5 extends along the row direction and is connected to the fourth upper-layer wiring portion UWP4 at one end. The first lower-layer wiring LW1 and the second lower-layer wiring LW2 are in a Z shape, each including a third lower-layer wiring portion LWP3, a fourth lower-layer wiring portion LWP4, and a fifth lower-layer wiring portion LWP5. The third lower-layer wiring portion LWP3 and the fourth lower-layer wiring portion LWP4 extend along the column direction. The fifth lower-layer wiring portion LWP5 extends along the row direction and connects the third lower-layer wiring portion LWP3 and the fourth lower-layer wiring portion LWP4. Optionally, the fifth upper-layer wiring portion UWP5 and the fifth lower-layer wiring portion LWP5 can extend along a direction other than the row direction and intersecting the column direction.

[0045] By electrically connecting the end portion of the fourth upper wiring portion UWP4 of the first upper wiring UW1, which is on the opposite side of the fifth upper wiring portion UWP5, to the end portion of the fourth lower wiring portion LWP4 of the first lower wiring LW1 on the downstream side in the column direction, which is on the opposite side of the fifth lower wiring portion LWP5, and by electrically connecting the end portion of the fifth upper wiring portion UWP5 of the first upper wiring UW1, which is on the opposite side of the fourth upper wiring portion UWP4, to the end portion of the third lower wiring portion LWP3 of the first lower wiring LW1 on the upstream side in the column direction, which is on the opposite side of the fifth lower wiring portion LWP5, the first upper wiring UW1 and the first lower wiring LW1 that are alternately arranged in the column direction are connected to form the first data line DL1. In a similar manner, the second upper wiring UW2 and the second lower wiring LW2 that are alternately arranged in the column direction are connected to form the second data line DL2.

[0046] In the first overlapping region R1 ( Figure 6 not shown), the fourth upper wiring portion UWP4 of the first upper wiring UW1 overlaps with the fourth lower wiring portion LWP4 of the second lower wiring LW2. In the second overlapping region R3, the fourth upper wiring portion UWP4 of the second upper wiring UW2 overlaps with the fourth lower wiring portion LWP4 of the first lower wiring LW1.

[0047] In the first switching region R2, the first scan line SL1 passes through the first switching region R2. The first switching point SP1 and the second switching point SP2 are on the same side of the first scan line SL1. The first upper wiring UW1 crosses the first scan line SL1 above the first scan line SL1, and the second lower wiring LW2 crosses the first scan line SL1 below the first scan line SL1. The first upper wiring UW1 is electrically connected to the transistor TR on its left side. In the second switching region R4, the second scan line SL2 passes through the second switching region R4. The third switching point SP3 and the fourth switching point SP4 are on the same side of the second scan line SL2. The second upper wiring UW2 crosses the second scan line SL2 above the second scan line SL2, and the first lower wiring LW1 crosses the second scan line SL2 below the second scan line SL2. The second upper wiring UW2 is electrically connected to the transistor TR on its right side.

[0048] As Figure 7As shown in the C-C cross-sectional structure passing through the second switching point SP2, the upper end of the conductor DT passing through the scan line layer SLL contacts the right end of the second upper wiring UW2 (the end of the fifth upper wiring portion UWP5 on the side opposite to the fourth upper wiring portion UWP4), and the lower end contacts the second lower wiring LW2, thereby electrically connecting the second upper wiring UW2 and the second lower wiring LW2, so that the second data line DL2 is switched from the second lower wiring LW2 to the second upper wiring UW2.

[0049] As described above, in the second example, the data line not connected to the transistor crosses the scan line below the scan line, thereby reducing the risk of disconnection.

[0050] Figure 8 and Figure 9 FIG. shows a third example of the liquid crystal display panel LCP according to the present invention. Among them, Figure 8 is a partial enlarged view of the liquid crystal display panel when viewed from the observer side, Figure 9 is a cross-sectional view showing Figure 8 the D-D cross-sectional structure in Figure 8 and 9 The third example shown in Figure 3-5 is mainly different from the first example shown in Figure 3 in that, instead of the pixels in the same column being alternately connected to the data lines on different sides in the first example, in the third example, the pixels in the same column are connected to the data lines on the same side. Specifically, in Figure 8 in the first switching region R2, the transistor TR is connected to the data line on its right side, while in the second switching region R4, the transistor is connected to the data line on its left side, while in

[0051] In the third example, similar to the first example, both the first upper wiring UW1 and the second upper wiring UW2 are in a Z shape and each includes a first upper wiring portion UWP1, a second upper wiring portion UWP2, and a third upper wiring portion UWP3; both the first lower wiring LW1 and the second lower wiring LW2 are in an L shape and each includes a first lower wiring portion LWP1 and a second lower wiring portion LWP2. However, different from the first example, the first upper wiring portions UWP1 of the first upper wiring UW1 and the second upper wiring UW2 in the third example are both on the same side of the second upper wiring portion UWP2 ( Figure 8 shown as the right side in Figure 8With this structure, in the first switching region R2 or the second switching region R4, the first data line DL1 and the second data line DL2 that needs to be connected to the transistor alternately appear on the left side to facilitate connection with the transistor, while the other that does not need to be connected to the transistor alternately appears on the right side.

[0052] Figure 9 The DD cross-sectional structure shown passing through the fourth switching point SP4 is similar to that of Figure 4 The structure of the AA cross section shown is the same when it is turned left and right. The upper end of the conductor DT that passes through the scan line layer SLL contacts the first upper wiring UW1, and the lower end contacts the right end of the first lower wiring LW1 (the end of the second lower wiring portion LWP2 located on the opposite side of the first lower wiring portion LWP1), thereby electrically connecting the first upper wiring UW1 and the first lower wiring LW1, so that the first data line DL1 is switched from the first lower wiring LW1 to the first upper wiring UW1.

[0053] Figure 8 The case where the transistors are all connected to the data lines on the right side thereof is illustrated, but the present invention is obviously not limited to this. It can also be set that the transistors are all connected to the data lines on the left side thereof. In this case, the first data line DL1 and the second data line DL2 can be set so that the first upper wiring UW1 and the first upper wiring UWP1 of the second upper wiring UW2 are both located on the left side of the second upper wiring UWP2, and the first lower wiring LW1 and the second lower wiring LWP2 extend to the left from the first lower wiring LWP1. With this structure, in the first switching area R2 or the second switching area R4, the one of the first data line DL1 and the second data line DL2 that needs to be connected to the transistor appears alternately on the right side to facilitate connection with the transistor, while the other one that does not need to be connected to the transistor appears alternately on the left side.

[0054] In addition, the third example may also adopt the wiring structure shown in the second example, that is, the first upper wiring UW1 and the second upper wiring UW2 are both L-shaped, and each includes a fourth upper wiring portion UWP4 and a fifth upper wiring portion UWP5; the first lower wiring LW1 and the second lower wiring LW2 are both Z-shaped, and each includes a third lower wiring portion LWP3, a fourth lower wiring portion LWP4 and a fifth lower wiring portion LWP5.

[0055] Pixels in the same column are connected to the data lines on the same side, but can still be driven by 1G2D. This is due to the Figure 12The comparative example shown cannot be achieved and can only be achieved when the solution of the present invention is adopted. Thus, it can be seen that the solution of the present invention significantly improves the degree of freedom in panel design. Moreover, in the third example, all pixels can be formed in the same manner without changing the position of the transistor relative to the pixel electrode row by row as in the first and second examples, simplifying the manufacturing process.

[0056] Figure 10 Shows a fourth example of the liquid crystal display panel LCP related to the present invention. In Figure 10 In the fourth example shown, the upper-layer wiring and the lower-layer wiring are vertically flipped with respect to Figure 3 the upper-layer wiring and the lower-layer wiring of the first example shown.

[0057] Specifically, as Figure 3 shown, in the first example, the second lower-layer wiring portion LWP2 of the lower-layer wiring is connected to the end portion on the downstream side in the column direction of the first lower-layer wiring portion LWP1, the first upper-layer wiring portion UWP1 and the third upper-layer wiring portion UWP3 of the upper-layer wiring are connected to the end portion on the upstream side in the column direction of the second upper-layer wiring portion UWP2, and the first upper-layer wiring portion UWP1 of the upper-layer wiring is on the upstream side with respect to the third upper-layer wiring portion UWP3 in the column direction.

[0058] In the fourth example, after vertical flipping, as Figure 10 shown, the second lower-layer wiring portion LWP2 of the lower-layer wiring is connected to the end portion on the upstream side in the column direction of the first lower-layer wiring portion LWP1, the first upper-layer wiring portion UWP1 and the third upper-layer wiring portion UWP3 of the upper-layer wiring are connected to the end portion on the downstream side in the column direction of the second upper-layer wiring portion UWP2, and the first upper-layer wiring portion UWP1 of the upper-layer wiring is on the downstream side with respect to the third upper-layer wiring portion UWP3 in the column direction.

[0059] Figure 11 Shows a fifth example of the liquid crystal display panel related to the present invention. In Figure 11 In the fifth example shown, the upper-layer wiring and the lower-layer wiring are vertically flipped with respect to Figure 6 the upper-layer wiring and the lower-layer wiring of the second example shown.

[0060] Specifically, as Figure 6 shown, in the second example, the fifth upper-layer wiring portion UWP5 of the upper-layer wiring is connected to the end portion on the upstream side in the column direction of the fourth upper-layer wiring portion UWP4, the third lower-layer wiring portion LWP3 and the fifth lower-layer wiring portion LWP5 of the lower-layer wiring are connected to the end portion on the downstream side in the column direction of the fourth lower-layer wiring portion LWP4, and the third upper-layer wiring portion LWP3 of the lower-layer wiring is on the downstream side with respect to the fifth upper-layer wiring portion LWP5 in the column direction.

[0061] In the fifth example, after vertical flipping, as Figure 11 shown, the fifth upper wiring portion UWP5 of the upper wiring is connected to the end portion on the downstream side in the column direction of the fourth upper wiring portion UWP4, and the third lower wiring portion LWP3 and the fifth lower wiring portion LWP5 of the lower wiring are connected to the end portion on the upstream side in the column direction of the fourth lower wiring portion LWP4. The third upper wiring portion LWP3 of the lower wiring is on the upstream side with respect to the fifth upper wiring portion LWP5 in the column direction.

[0062] As a result of the vertical flipping, in the first and second examples, the data line switches from the upper wiring to the lower wiring at the downstream side in the column direction of the connection point electrically connected to the transistor, while in the fourth and fifth examples, the data line switches from the lower wiring to the upper wiring at the upstream side in the column direction of the connection point electrically connected to the transistor. Accordingly, in the fourth and fifth examples, in the first switching region R2, the transistor TR is located on the left side with respect to the central portion of the pixel electrode to which it is connected and is connected to the second data line DL2 located on its left side; in the second switching region R4, the transistor TR is located on the right side with respect to the central portion of the pixel electrode to which it is connected and is connected to the first data line DL1 located on its right side.

[0063] In addition, the fourth and fifth examples can also be combined with the third example so that Figure 10 and Figure 11 the pixels in the same column are all connected to the data lines located on the same side.

[0064] In addition, in the above examples, as Figure 6 shown by the second switching point SP2 etc., at each switching point, there is a situation where a part of the data line overlaps with the pixel electrode PIT in the thickness direction. When the overlapping area is large, the display effect will deteriorate. To alleviate this problem, at each switching point, the area where the data line overlaps with the pixel electrode in the thickness direction can be covered by a black matrix, or the corresponding part of the pixel electrode can be removed so that the data line does not overlap with the pixel electrode in the thickness direction.

[0065] In addition, in the above examples, the upper wiring and the lower wiring are designed in a Z shape or an L shape, but obviously the shapes of the upper wiring and the lower wiring can adopt any other suitable shapes. In addition, in the above examples, the first data line and the second data line are formed by repeating the same wiring pattern, but obviously each data line can also be formed by connecting different wiring patterns together.

[0066] The above examples are merely exemplary, and the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily conceive of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claimed rights.

Claims

1. A liquid crystal display panel, comprising: A plurality of pixels arranged in a row direction and a column direction, the pixels including transistors; A plurality of data lines extending in the column direction and including a first data line and a second data line; And A plurality of scan lines extending in the row direction and intersecting with the plurality of data lines, wherein at least a part of the first data line and a part of the second data line are disposed between two directly adjacent pixel columns, and at least a part of the first data line and a part of the second data line partially overlap in the thickness direction of the liquid crystal display panel, The first data line includes a first upper wiring arranged in the column direction and a first lower wiring electrically connected to the first upper wiring, The second data line includes a second upper wiring arranged in the column direction and a second lower wiring electrically connected to the second upper wiring, The first upper wiring, which is a part of the first data line and a part of the second data line, partially overlaps with the second lower wiring in the thickness direction, and the second upper wiring, which is a part of the first data line and a part of the second data line, partially overlaps with the first lower wiring in the thickness direction, The liquid crystal display panel includes an upper layer of the data line and a lower layer of the data line on the backlight side of the liquid crystal display panel with respect to the upper layer of the data line, The first upper wiring and the second upper wiring are formed on the upper layer of the data line, The first lower wiring and the second lower wiring are formed on the lower layer of the data line, The liquid crystal display panel further includes a scan line layer, and the scan lines are formed on the scan line layer, The scan line layer is located between the upper layer of the data line and the lower layer of the data line.

2. The liquid crystal display panel according to claim 1, wherein, The liquid crystal display panel further includes two substrates disposed opposite to each other, The lower layer of the data line is located between the scan line layer and the substrate on the backlight side.

3. A liquid crystal display panel, comprising: A plurality of pixels arranged in a row direction and a column direction, the pixels including transistors; A plurality of data lines extending in the column direction and including a first data line and a second data line; And A plurality of scan lines extending in the row direction and intersecting with the plurality of data lines, wherein at least a part of the first data line and a part of the second data line are disposed between two directly adjacent pixel columns, and at least a part of the first data line and a part of the second data line partially overlap in the thickness direction of the liquid crystal display panel, The first data line includes a first upper wiring arranged in the column direction and a first lower wiring electrically connected to the first upper wiring, The second data line includes a second upper wiring arranged in the column direction and a second lower wiring electrically connected to the second upper wiring, The first upper wiring, which is a part of the first data line and a part of the second data line, partially overlaps with the second lower wiring in the thickness direction, and the second upper wiring, which is a part of the first data line and a part of the second data line, partially overlaps with the first lower wiring in the thickness direction, The first overlapping region, the first switching region, the second overlapping region, and the second switching region are arranged in sequence along the column direction. In the first overlapping region, the first upper-layer wiring overlaps with the second lower-layer wiring in the thickness direction. In the first switching region, the first data line switches from the first upper-layer wiring to the first lower-layer wiring at a first switching point, and the second data line switches from the second lower-layer wiring to the second upper-layer wiring at a second switching point. In the second overlapping region, the first lower-layer wiring overlaps with the second upper-layer wiring in the thickness direction. In the second switching region, the first data line switches from the first lower-layer wiring to the first upper-layer wiring at a third switching point, and the second data line switches from the second upper-layer wiring to the second lower-layer wiring at a fourth switching point. In one of the first switching region and the second switching region, the first upper-layer wiring is electrically connected to one of the transistors, and in the other of the first switching region and the second switching region, the second upper-layer wiring is electrically connected to the other of the transistors.

4. The liquid crystal display panel according to claim 3, wherein, The scanning line includes a first scanning line and a second scanning line adjacent to the first scanning line in the column direction. The first scanning line passes through the first switching region. The second scanning line passes through the second switching region. When observing the liquid crystal display panel from the observer side, the first switching point and the second switching point are located on both sides of the first scanning line, the third switching point and the fourth switching point are located on both sides of the second scanning line, and the first upper-layer wiring and the second upper-layer wiring cross the first scanning line and the second scanning line.

5. The liquid crystal display panel according to claim 3, wherein, The scanning line includes a first scanning line and a second scanning line adjacent to the first scanning line in the column direction. The first scanning line passes through the first switching region. The second scanning line passes through the second switching region. When observing the liquid crystal display panel from the observer side, the first switching point and the second switching point are located on the same side of the first scanning line, the third switching point and the fourth switching point are located on the same side of the second scanning line, and the first upper-layer wiring and the second lower-layer wiring cross the first scanning line, or the first lower-layer wiring and the second upper-layer wiring cross the second scanning line.

6. The liquid crystal display panel according to claim 4, wherein, Each of the first upper-layer wiring and the second upper-layer wiring includes a first upper-layer wiring portion and a second upper-layer wiring portion extending along the column direction, and a third upper-layer wiring portion extending along a direction crossing the column direction and connecting the first upper-layer wiring portion and the second upper-layer wiring portion. Each of the first lower-layer wiring and the second lower-layer wiring includes a first lower-layer wiring portion extending along the column direction, and a second lower-layer wiring portion extending along a direction crossing the column direction and having one end connected to the first lower-layer wiring portion. The second upper wiring portion of the first upper wiring, which is a part of the first data line and a part of the second data line, partially overlaps with the first lower wiring portion of the second lower wiring, and the second upper wiring portion of the second upper wiring, which is a part of the first data line and a part of the second data line, partially overlaps with the first lower wiring portion of the first lower wiring. For each of the first data line and the second data line, an end of the second upper wiring portion on the opposite side of the third upper wiring portion is electrically connected to an end of the first lower wiring portion on the opposite side of the second lower wiring portion, and an end of the first upper wiring portion on the opposite side of the third upper wiring portion is electrically connected to an end of the second lower wiring portion on the opposite side of the first lower wiring portion.

7. The liquid crystal display panel according to claim 5, wherein, Each of the first upper wiring and the second upper wiring includes a fourth upper wiring portion extending along the column direction and a fifth upper wiring portion extending along a direction intersecting the column direction and having one end connected to the fourth upper wiring portion. Each of the first lower wiring and the second lower wiring includes a third lower wiring portion and a fourth lower wiring portion extending along the column direction and a fifth lower wiring portion extending along a direction intersecting the column direction and connecting the third lower wiring portion and the fourth lower wiring portion. The fourth upper wiring portion of the first upper wiring, which is a part of the first data line and a part of the second data line, partially overlaps with the fourth lower wiring portion of the second lower wiring, and the fourth upper wiring portion of the second upper wiring, which is a part of the first data line and a part of the second data line, partially overlaps with the fourth lower wiring portion of the first lower wiring. For each of the first data line and the second data line, an end of the fourth upper wiring portion on the opposite side of the fifth upper wiring portion is electrically connected to an end of the fourth lower wiring portion on the opposite side of the fifth lower wiring portion, and an end of the fifth upper wiring portion on the opposite side of the fourth upper wiring portion is electrically connected to an end of the third lower wiring portion on the opposite side of the fifth lower wiring portion.

8. The liquid crystal display panel according to claim 1, wherein, The transistors of the n-th row pixels and the (n + 1)-th row pixels are connected to a scan line that inputs a scan voltage at the same timing, where n > 0 and n is an integer. The first data line and the second data line are disposed between the i-th column pixels and the (i + 1)-th column pixels, where i > 0 and i is an integer. The transistor of the pixel located at the n-th row and the i-th column is connected to the first data line, and the transistor of the pixel located at the (n + 1)-th row and the (i + 1)-th column is connected to the second data line.

9. The liquid crystal display panel according to claim 1, wherein, The transistors of the n-th row pixels and the (n + 1)-th row pixels are connected to a scan line that inputs a scan voltage at the same timing, where n > 0 and n is an integer. The first data line and the second data line are disposed between the i-th column pixels and the (i + 1)-th column pixels, where i > 0 and i is an integer. The transistor of the pixel located in the n-th row and the i-th column is connected to the first data line, and the transistor of the pixel located in the (n + 1)-th row and the i-th column is connected to the second data line.

10. The liquid crystal display panel according to claim 8, wherein, The pixel further includes a pixel electrode. The gate electrode of the transistor is electrically connected to the scan line, the drain electrode of the transistor is electrically connected to the corresponding first data line or the second data line, and the source electrode of the transistor is electrically connected to the pixel electrode. The transistor is located on one side where one of the connected first data line and the second data line is located with respect to the central portion of the pixel electrode. At the position where one of the first data line and the second data line is connected to the transistor, the other of the first data line and the second data line is located on the side opposite to the transistor of one of the first data line and the second data line.

11. A liquid crystal display panel, comprising: A plurality of pixels arranged in the row direction and the column direction, the pixels including transistors. A plurality of data lines extending in the column direction and including a first data line and a second data line. And A plurality of scan lines extending in the row direction and intersecting the plurality of data lines. Wherein, at least a part of the first data line and a part of the second data line are provided between two directly adjacent pixel columns, and at least a part of the first data line and a part of the second data line partially overlap in the thickness direction of the liquid crystal display panel. The transistors of the pixels in the n-th row and the (n + 1)-th row are connected to the scan lines to which a scan voltage is input at the same timing, n > 0 and n is an integer. The first data line and the second data line are provided between the pixels in the i-th column and the (i + 1)-th column, i > 0 and i is an integer. The transistor of the pixel located in the n-th row and the i-th column is connected to the first data line, and the transistor of the pixel located in the (n + 1)-th row and the (i + 1)-th column is connected to the second data line. The pixel further includes a pixel electrode. The gate electrode of the transistor is electrically connected to the scan line, the drain electrode of the transistor is electrically connected to the corresponding first data line or the second data line, and the source electrode of the transistor is electrically connected to the pixel electrode. The transistor is located on one side where one of the connected first data line and the second data line is located with respect to the central portion of the pixel electrode. At the position where one of the first data line and the second data line is connected to the transistor, the other of the first data line and the second data line is located on the side opposite to the transistor of one of the first data line and the second data line. The first data line includes a first upper layer wiring arranged in the column direction and a first lower layer wiring electrically connected to the first upper layer wiring. At the switching point where the first data line switches from the first upper layer wiring to the first lower layer wiring, the region where the data line overlaps with the pixel electrode in the thickness direction is covered by a black matrix.

12. The liquid crystal display panel according to claim 1, wherein, Further includes: A data line driving circuit for supplying a signal voltage corresponding to input display data to the transistor via the data line. And A scan line driving circuit for supplying a scan voltage for selecting a row of the pixels to be driven to the transistor via the scan line.

Images