Method for time synchronization of a system on chip and system on chip, vehicle

Abstract

This application discloses a method for time synchronization of a system-on-a-chip (SoC), an SoC, and a vehicle. The method includes: determining a daisy-chain data transmission delay between a first hardware domain and a second hardware domain; determining a system clock difference between the second hardware domain and the first hardware domain based on the daisy-chain data transmission delay; calibrating the clock of a second daisy-chain counter based on the system clock difference to synchronize the clocks of the second daisy-chain counter and the first daisy-chain counter; determining a timestamp of the second subsystem based on first subsystem time information sent from the first hardware domain; wherein the first subsystem time information includes the timestamp of the first subsystem and the clock information of the first daisy-chain counter; and updating the system time of the second subsystem based on the timestamp of the second subsystem to synchronize the system time of the second subsystem with that of the first subsystem. Using this application, time synchronization between subsystems of an SoC can be achieved.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a method for time synchronization of a system-on-a-chip, as well as the system-on-a-chip and a vehicle. Background Technology

[0002] In related technologies, the methods for achieving time synchronization between subsystems of a multi-core heterogeneous SoC (System on Chip) mainly include: (1) Each subsystem of the multi-core heterogeneous SoC is connected to the same external device, such as a switching device, and the external device performs time synchronization uniformly. (2) The subsystems of the multi-core heterogeneous SoC achieve time synchronization through a virtual network port based on the PTP (Precision Time Protocol) tool.

[0003] However, the aforementioned method of unifying time synchronization through external devices requires additional physical connections, increasing costs. On the other hand, the aforementioned method of time synchronization through a virtual network port, which is purely software-based, suffers from significant network jitter, resulting in lower time synchronization accuracy. Summary of the Invention

[0004] The purpose of this application is to provide a method for time synchronization of a system-on-a-chip, as well as the system-on-a-chip and a vehicle.

[0005] In a first aspect, embodiments of this application provide a method for time synchronization of an on-chip system. The on-chip system includes a first subsystem and at least one second subsystem. Both the first and second subsystems include multiple hardware domains. One hardware domain in the first subsystem is a first hardware domain, and one hardware domain in the second subsystem is a second hardware domain. The first hardware domain is a root node, and the second hardware domain is a leaf node. The root node and at least one leaf node are electrically connected via a daisy chain. The first hardware domain includes a first daisy chain counter, and the second hardware domain includes a second daisy chain counter. The method includes:

[0006] The first real-time clock module of the first subsystem synchronizes the time of each hardware domain of the first subsystem.

[0007] Determine the daisy-chain data transmission latency between the first hardware domain and the second hardware domain;

[0008] The system clock difference between the second hardware domain and the first hardware domain is determined based on the daisy chain data transmission delay.

[0009] Based on the system clock difference, the clock of the second daisy chain counter is calibrated to synchronize the clock of the second daisy chain counter with that of the first daisy chain counter.

[0010] The timestamp of the second subsystem is determined based on the time information of the first subsystem sent from the first hardware domain; wherein the time information of the first subsystem includes the timestamp of the first subsystem and the clock information of the first daisy chain counter.

[0011] Update the system time of the second subsystem based on the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with that of the first subsystem;

[0012] The second real-time clock module of the second subsystem synchronizes the time of each hardware domain of the second subsystem.

[0013] Secondly, embodiments of this application provide a system-on-a-chip (SoC) comprising a first subsystem and at least one second subsystem. Both the first and second subsystems include multiple hardware domains. One hardware domain in the first subsystem is a first hardware domain, and one hardware domain in the second subsystem is a second hardware domain. The first hardware domain is a root node, and the second hardware domain is a leaf node. The root node and at least one leaf node are electrically connected via a daisy-chain configuration. The first hardware domain includes a first daisy-chain counter, and the second hardware domain includes a second daisy-chain counter. The first subsystem includes a first real-time clock module, and the second subsystem includes a second real-time clock module.

[0014] The first real-time clock module is configured to synchronize the time of each hardware domain of the first subsystem;

[0015] The second hardware domain is configured to determine the daisy-chain data transfer latency between the first hardware domain and the second hardware domain.

[0016] The second hardware domain is configured to determine the system clock difference between the second hardware domain and the first hardware domain based on the daisy chain data transmission delay.

[0017] The second hardware domain is configured to calibrate the clock of the second daisy chain counter based on the system clock difference, so that the clock of the second daisy chain counter is synchronized with that of the first daisy chain counter.

[0018] The second hardware domain is configured to determine the timestamp of the second subsystem based on the first subsystem time information sent from the first hardware domain; wherein the first subsystem time information includes the timestamp of the first subsystem and the clock information of the first daisy-chain counter.

[0019] The second hardware domain is configured to update the system time of the second subsystem based on the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with that of the first subsystem.

[0020] The second real-time clock module is configured to synchronize the time of each hardware domain of the second subsystem.

[0021] Thirdly, embodiments of this application provide a vehicle including the system-on-a-chip as described in the above embodiments.

[0022] Fourthly, embodiments of this application provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the on-chip system time synchronization method provided in any of the above embodiments.

[0023] The on-chip system time synchronization method provided in this application first synchronizes the time of each hardware domain of the first subsystem. Then, it synchronizes the clocks of the first daisy-chain counter of the first subsystem with the clocks of the second daisy-chain counter of the second subsystem. Next, it uses the clock synchronization of the two daisy-chain counters to achieve system time synchronization between the first and second subsystems. Finally, it synchronizes the time of each hardware domain of the second subsystem. This achieves time synchronization between the first and second subsystems of the on-chip system, as well as time synchronization of each hardware domain within the first and second subsystems. By using daisy-chain counters to achieve time synchronization between the first and second subsystems of the on-chip system, this application not only reduces the impact of communication path delays and jitter on time synchronization accuracy, thereby improving the accuracy of on-chip system time synchronization, but also eliminates the need for additional hardware costs. Attached Figure Description

[0024] Figure 1 A flowchart illustrating a time synchronization method for an on-chip system provided in an embodiment of this application;

[0025] Figure 2 This is a flowchart illustrating step S10 in an embodiment of this application;

[0026] Figure 3 This is a flowchart illustrating step S20 in an embodiment of this application;

[0027] Figure 4 This is a flowchart illustrating step S30 in an embodiment of this application;

[0028] Figure 5 This is a flowchart illustrating step S50 in an embodiment of this application;

[0029] Figure 6 This is a flowchart illustrating step S70 in an embodiment of this application;

[0030] Figure 7 This application provides a schematic diagram of the structure of a system-on-a-chip (SoC) according to an embodiment of the present application.

[0031] Figure 8 This is a schematic diagram of another system-on-a-chip provided in an embodiment of this application. Detailed Implementation

[0032] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0033] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0034] Time synchronization is a widely used practical requirement in embedded systems. Specifically, in multi-core heterogeneous SoC systems, various subsystems and domains also need to perform time synchronization with a certain degree of precision to meet the time requirements of some time-sensitive applications.

[0035] Before providing a detailed description of the embodiments of this application, the technical names and terms involved in the embodiments of this application will be explained first.

[0036] DCI (Daisy Chain Interface), often referred to as a "daisy link," is a serial or parallel communication interface technology that connects multiple devices.

[0037] This application is based on DCI (Daisy Chain Interface) technology to realize time synchronization between subsystems. It can not only reduce the time delay of communication paths between subsystems, but also reduce the impact of jitter on the time synchronization accuracy, thereby improving the time synchronization accuracy of the on-chip system, but also does not require additional hardware costs.

[0038] The following detailed description, with reference to the accompanying drawings, illustrates a method for time synchronization of an on-chip system provided in this application. This application provides a method for time synchronization of an on-chip system. (See attached figures.) Figure 7 As shown, the system-on-a-chip includes a first subsystem and at least one second subsystem. Both the first and second subsystems include multiple hardware domains. One hardware domain in the first subsystem is called the first hardware domain, and one hardware domain in the second subsystem is called the second hardware domain. The first hardware domain is the root node, and the second hardware domain is the leaf node. The root node and at least one leaf node are electrically connected in a daisy chain manner. The first hardware domain includes a first daisy chain counter, and the second hardware domain includes a second daisy chain counter. Figure 7 In the diagram, subsystem 1 represents the first subsystem, subsystem 2 represents the second subsystem, and subsystem n represents the nth subsystem, where n is an integer greater than or equal to 1.

[0039] Figure 1This is a flowchart illustrating a method for time synchronization of a system-on-a-chip (SoC) according to an embodiment of this application. The method first synchronizes the time of each hardware domain of a first subsystem. Then, it synchronizes the system time of the first subsystem with the system time of any second subsystem on a daisy chain, for example, synchronizing the system time of the first subsystem with the system time of the fifth second subsystem on the daisy chain. Finally, it synchronizes the time of each hardware domain of the fifth second subsystem, thereby achieving time synchronization between the first and second subsystems of the SoC, as well as time synchronization between the first subsystem and each hardware domain within the second subsystem. In other words, the SoC time synchronization method provided in this embodiment is a method for synchronizing the time of the first subsystem of the SoC with one of the second subsystems on a daisy chain. The second hardware domain in steps S10 to S70 below refers to the second hardware domain of the same second subsystem.

[0040] For details, see Figure 1 As shown, the methods for time synchronization of an on-chip system include:

[0041] S10 synchronizes the time of each hardware domain of the first subsystem through the first real-time clock module of the first subsystem;

[0042] See Figure 7 The first subsystem also includes a first real-time clock module (RTC, Real_Time Clock). The first real-time clock module is used to provide a time reference for the first subsystem. Using the first real-time clock module, the various hardware domains of the first subsystem where the first real-time clock module is located can be synchronized in time.

[0043] S20, determine the daisy-chain data transmission delay between the first hardware domain and the second hardware domain;

[0044] For example, the daisy-chain data transmission delay between the first hardware domain and the second hardware domain can be determined by the second hardware domain, or the daisy-chain data transmission delay between the first hardware domain and the second hardware domain can be determined by the first hardware domain. This application does not make any special limitation.

[0045] In this example, determining the daisy-chain data transfer delay between the first hardware domain and the second hardware domain can refer to determining the daisy-chain data transfer delay between the first hardware domain and the second hardware domain of any second subsystem.

[0046] For example, determining the daisy-chain data transmission delay between the first hardware domain and the second hardware domain of the first second subsystem, or determining the daisy-chain data transmission delay between the first hardware domain and the second hardware domain of the fifth second subsystem.

[0047] S30, determine the system clock difference between the second hardware domain and the first hardware domain based on the daisy chain data transmission delay;

[0048] For example, the system clock difference between the second hardware domain and the first hardware domain can be determined by the second hardware domain based on the daisy-chain data transmission delay, or the system clock difference between the second hardware domain and the first hardware domain can be determined by the first hardware domain based on the daisy-chain data transmission delay. This application does not impose any particular limitation.

[0049] S40, calibrate the clock of the second daisy chain counter according to the system clock difference, so that the clock of the second daisy chain counter is synchronized with that of the first daisy chain counter;

[0050] For example, the clock of the second daisy chain counter in the second hardware domain can be calibrated according to the system clock difference, so that the clock of the second daisy chain counter in the second hardware domain is synchronized with the clock of the first daisy chain counter in the first hardware domain.

[0051] S50, based on the time information of the first subsystem sent from the first hardware domain, determine the timestamp of the second subsystem; wherein, the time information of the first subsystem includes the timestamp of the first subsystem and the clock information of the first daisy-chain counter;

[0052] For example, the first hardware domain sends first subsystem time information to the second hardware domain, wherein the first subsystem time information includes the timestamp of the first subsystem and the clock information of the first daisy-chain counter. The second hardware domain receives the first subsystem time information and determines the timestamp of the second subsystem to which the second hardware domain resides based on the first subsystem time information.

[0053] A timestamp is data generated using digital signature technology, used to synchronize the system time of the second subsystem with that of the first subsystem.

[0054] S60, based on the timestamp of the second subsystem, update the system time of the second subsystem so that the system time of the second subsystem is synchronized with that of the first subsystem;

[0055] For example, the system time of the second subsystem to which the second hardware domain resides can be updated by the second hardware domain according to the timestamp of the second subsystem to which the second hardware domain resides, so that the system time of the second subsystem to which the second hardware domain resides is synchronized with the system time of the first subsystem.

[0056] The S70 synchronizes the time of each hardware domain of the second subsystem through the second real-time clock module of the second subsystem.

[0057] See Figure 7The second subsystem also includes a second real-time clock module (RTC, Real_Time Clock). The second real-time clock module is used to provide a time base for the second subsystem. Using the second real-time clock module, the various hardware domains of the second subsystem where the second real-time clock module is located can be synchronized in time.

[0058] The on-chip system time synchronization method provided in this application first synchronizes the time of each hardware domain of the first subsystem. Then, it synchronizes the clocks of the first daisy-chain counter of the first subsystem with the clocks of the second daisy-chain counter of the second subsystem. Next, it uses the clock synchronization of the two daisy-chain counters to achieve system time synchronization between the first and second subsystems. Finally, it synchronizes the time of each hardware domain of the second subsystem. This achieves time synchronization between the first and second subsystems of the on-chip system, as well as time synchronization of each hardware domain within the first and second subsystems. By using daisy-chain counters to achieve time synchronization between the first and second subsystems of the on-chip system, this application not only reduces the impact of communication path delays and jitter on time synchronization accuracy, thereby improving the accuracy of on-chip system time synchronization, but also eliminates the need for additional hardware costs.

[0059] It should be noted that the above-described on-chip system time synchronization method involves synchronizing the time of the first subsystem with one of the second subsystems in all the second subsystems on the daisy link.

[0060] To synchronize the time of the first subsystem with all second subsystems, a preset time synchronization order can be followed. The preset time synchronization order can be: the first subsystem synchronizes with the 1st second subsystem, the 2nd second subsystem, ..., the nth second subsystem, until synchronization is complete. Alternatively, the preset time synchronization order can be: the first subsystem synchronizes with the nth second subsystem, ..., the 2nd second subsystem, and the 1st second subsystem, until synchronization is complete. Another preset time synchronization order can be: the first subsystem synchronizes with the 3rd second subsystem, the 2nd second subsystem, the nth second subsystem, ..., until synchronization is complete.

[0061] The hardware domain in this application embodiment can be a protection domain, application domain, multi-functional domain, security domain, etc. Optionally, the first hardware domain can be one of the following: protection domain, application domain, multi-functional domain, and security domain; the second hardware domain can be one of the following: protection domain, application domain, multi-functional domain, and security domain. Figure 8In the illustrated embodiment, both the first hardware domain and the second hardware domain are application domains. Of course, both the first and second hardware domains can also be protection domains, or the first hardware domain can be an application domain and the second hardware domain can be a multi-functional domain, etc. This application does not impose any particular limitations.

[0062] In some embodiments, see Figure 8 As shown, the first subsystem includes at least an application domain, a multi-function domain, a protection domain, and a security domain; the first real-time clock module includes a first real-time clock chip and a second real-time clock chip.

[0063] See Figure 2 The first real-time clock module of the first subsystem synchronizes the time of each hardware domain of the first subsystem, including:

[0064] S101, the application domain, multi-function domain and security domain are clocked through the first real-time clock chip, and the security domain is clocked through the second real-time clock chip;

[0065] S102, obtain the timestamp of the first real-time clock chip through one of the application domain, the multi-function domain and the protection domain, and transmit the timestamp of the first real-time clock chip to the security domain through inter-domain communication;

[0066] S103, the security domain writes the timestamp of the first real-time clock chip to the second real-time clock chip, so that the clocks of the first real-time clock chip and the second real-time clock chip are synchronized, so that the time of the application domain, the multi-function domain, the protection domain and the security domain are synchronized.

[0067] In this embodiment, inter-domain communication methods may include asynchronous message passing via a mailbox mechanism and cross-hardware domain data sharing via a shared memory mechanism.

[0068] In this embodiment, the application domain, multi-function domain, and protection domain share a first real-time clock chip, while the security domain uses a second real-time clock chip. Any one of the application domain, multi-function domain, and protection domain obtains the timestamp of the first real-time clock chip and transmits the timestamp of the first real-time clock chip to the security domain via a mailbox. The security domain writes the timestamp of the first real-time clock chip to the second real-time clock chip, thereby synchronizing the clocks of the first real-time clock chip and the second real-time clock chip. This synchronizes the time of the application domain, multi-function domain, protection domain, and security domain, and consequently, synchronizes the time of each hardware domain of the first subsystem.

[0069] Optionally, before synchronizing the time of each hardware domain of the first subsystem through the first real-time clock module of the first subsystem, the process includes: the first subsystem acquiring a standard time from an external source. The standard time serves as the reference time for time synchronization of the various hardware domains of the first subsystem.

[0070] For example, the first subsystem can obtain standard time from the outside via Ethernet, or it can use PTP (Precision Time Protocol) to synchronize the local area network time to the first subsystem so that the first subsystem can obtain standard time.

[0071] The standard time and the first real-time clock module are used to synchronize the time of each hardware domain of the first subsystem.

[0072] In some embodiments, see Figure 3 As shown, determining the daisy-chain data transmission delay between the first hardware domain and the second hardware domain includes:

[0073] S202, based on the timing instruction obtained from the first hardware domain, control the second daisy chain counter to keep time; wherein, the first hardware domain controls the first daisy chain counter to keep time while sending the timing instruction;

[0074] S203, a stop timing command is sent from the second hardware domain to the first hardware domain and the second daisy chain counter is synchronously controlled to stop timing, so that the first hardware domain controls the first daisy chain counter to stop timing according to the stop timing command;

[0075] S204, based on the read instruction obtained from the first hardware domain, read the clock value of the second daisy chain counter and use it as the second clock value; wherein, the first hardware domain reads the clock value of the first daisy chain counter and uses it as the first clock value at the same time as sending the read instruction.

[0076] S205, based on the first clock value and the second clock value obtained from the first hardware domain, determine the daisy-chain data transmission delay between the first hardware domain and the second hardware domain.

[0077] In some embodiments, see continue to see Figure 3 Before controlling the second daisy-chain counter to start timing based on the timing instructions obtained from the first hardware domain, the following steps are included:

[0078] S201, based on the initialization instruction obtained from the first hardware domain, control the initialization of the second daisy chain counter; wherein, the first hardware domain controls the initialization of the first daisy chain counter at the same time as sending the initialization instruction.

[0079] For example, when n=1, the on-chip system includes a first subsystem and one second subsystem on a daisy chain. The process of determining the daisy chain data transmission delay between the first hardware domain and the second hardware domain is described in detail below. Let t be the daisy chain data transmission delay between the first hardware domain and the second hardware domain, t1 be the daisy chain data transmission delay from the first hardware domain to the second hardware domain, and t2 be the daisy chain data transmission delay from the second hardware domain to the first hardware domain.

[0080] Specifically, when determining the daisy-chain data transmission delay, all other communications on the daisy-chain bus are temporarily shut down. Therefore, t1 and t2 can be considered approximately equal. Thus, the average daisy-chain data transmission delay, i.e., the daisy-chain data transmission delay between the first hardware domain and the second hardware domain, is t = (t1 + t2) / 2.

[0081] First, the first hardware domain sends an initialization command to the second hardware domain and synchronously controls the initialization of the first daisy chain counter; the second hardware domain controls the initialization of the second daisy chain counter based on the initialization command obtained from the first hardware domain; at this time, both the first and second daisy chain counters are set to zero.

[0082] Next, the first hardware domain sends a timing command to the second hardware domain and synchronously controls the first daisy chain counter to start timing. The first daisy chain counter starts timing immediately. Based on the timing command obtained from the first hardware domain, the second hardware domain controls the second daisy chain counter to start timing. The second daisy chain counter starts timing after a delay of t.

[0083] Next, the second hardware domain sends a stop timing command to the first hardware domain and synchronously controls the second daisy chain counter to stop timing. The second daisy chain counter immediately stops timing. The first hardware domain controls the first daisy chain counter to stop timing according to the stop timing command. The first daisy chain counter starts to stop timing after a delay of t.

[0084] Next, the first hardware domain sends a read command to the second hardware domain and synchronously reads the clock value of the first daisy chain counter as the first clock value C0; the second hardware domain reads the clock value of the second daisy chain counter based on the read command obtained from the first hardware domain and uses it as the second clock value C1.

[0085] Finally, based on the first clock value C0 and the second clock value C1 obtained from the first hardware domain, the second hardware domain obtains the daisy-chain data transmission delay t between the first hardware domain and the second hardware domain according to the formula t=(C0-C1) / 2.

[0086] For example, when n=3, the on-chip system includes a first subsystem and three second subsystems on a daisy chain. It should be noted that the length of the daisy chain bus connecting any two adjacent hardware domains is equal; therefore, the daisy chain data transmission delay between two adjacent hardware domains is equal. The process of determining the daisy chain data transmission delay between the first hardware domain and the second hardware domain of the third second subsystem is described in detail below. Let t be the daisy chain data transmission delay between two adjacent hardware domains, and t3 be the daisy chain data transmission delay from the first hardware domain of the first subsystem to the second hardware domain of the third second subsystem, where t3 = 3t.

[0087] Specifically, when the daisy-chain data transmission delay is determined, all other communications on the daisy-chain bus are temporarily shut down.

[0088] First, the first hardware domain sends an initialization command to the second hardware domain of the third second subsystem and synchronously controls the initialization of the first daisy chain counter; the second hardware domain of the third second subsystem controls the initialization of the second daisy chain counter based on the initialization command obtained from the first hardware domain; at this time, both the first daisy chain counter and the second daisy chain counter are set to zero.

[0089] Next, the first hardware domain sends a timing command to the second hardware domain of the third second subsystem and synchronously controls the first daisy chain counter to start timing. The first daisy chain counter starts timing immediately. Based on the timing command obtained from the first hardware domain, the second hardware domain of the third second subsystem controls the second daisy chain counter to start timing. The second daisy chain counter starts timing after a delay of 3t.

[0090] Next, the second hardware domain of the third second subsystem sends a stop timing command to the first hardware domain and synchronously controls the second daisy chain counter to stop timing. The second daisy chain counter immediately stops timing. The first hardware domain controls the first daisy chain counter to stop timing according to the stop timing command. After a delay of t, the first daisy chain counter starts to stop timing.

[0091] Next, the first hardware domain sends a read instruction to the second hardware domain of the third second subsystem, and synchronously reads the clock value of the first daisy chain counter as the first clock value C0; the second hardware domain of the third second subsystem reads the clock value of the second daisy chain counter based on the read instruction obtained from the first hardware domain and uses it as the second clock value C1.

[0092] Finally, the second hardware domain of the third second subsystem obtains the daisy-chain data transmission delay t between two adjacent hardware domains based on the first clock value C0 and the second clock value C1 obtained from the first hardware domain, according to the formula t = (C0-C1) / 4, and obtains the daisy-chain data transmission delay t3 between the first hardware domain and the second hardware domain of the third second subsystem according to the formula t3 = 3t.

[0093] Since there is no other data on the daisy-chain bus during the above signal transmission process, each communication between the first hardware domain and the second hardware domain only involves the transmission delay on the daisy-chain physical link, and this transmission delay is stable.

[0094] In some embodiments, see Figure 4 As shown, the system clock difference between the second hardware domain and the first hardware domain is determined based on the daisy-chain data transmission delay, including:

[0095] S301, based on the first sampling instruction obtained from the first hardware domain, the clock of the second daisy chain counter is sampled and a second sampled value is obtained; wherein, the first hardware domain samples the clock of the first daisy chain counter and obtains the first sampled value at the same time as sending the first sampling instruction;

[0096] S302, based on the second sampling instruction obtained from the first hardware domain, the clock of the second daisy chain counter is sampled and a fourth sample value is obtained; wherein, while sending the second sampling instruction, the first hardware domain samples the clock of the first daisy chain counter and obtains a third sample value.

[0097] S303, based on the first and third sampled values ​​obtained from the first hardware domain, as well as the second and fourth sampled values ​​and the daisy-chain data transmission delay, determine the system clock difference between the second hardware domain and the first hardware domain.

[0098] For example, when n=1, the on-chip system includes a first subsystem and one second subsystem on a daisy chain. The process of determining the system clock difference between the second hardware domain of the second subsystem and the first hardware domain of the first subsystem is described in detail below. t is set as the daisy chain data transmission delay between the first hardware domain and the second hardware domain.

[0099] First, the first hardware domain sends a first sampling instruction to the second hardware domain and simultaneously samples the clock of the first daisy chain counter to obtain a first sampled value C01; after a delay of t, the second hardware domain samples the clock of the second daisy chain counter based on the first sampling instruction obtained from the first hardware domain and obtains a second sampled value C11.

[0100] Next, after a preset time, the first hardware domain sends a second sampling instruction to the second hardware domain and simultaneously samples the clock of the first daisy chain counter to obtain a third sample value C02; after a delay of t, the second hardware domain samples the clock of the second daisy chain counter based on the second sampling instruction obtained from the first hardware domain and obtains a fourth sample value C12.

[0101] Finally, the second hardware domain determines the system clock difference d between the second hardware domain and the first hardware domain based on the first sampled value C01 and the third sampled value C02 obtained from the first hardware domain, as well as the second sampled value C11, the fourth sampled value C12, and the daisy-chain data transmission delay t.

[0102] Specifically, the system clock difference d can be calculated using the following formula;

[0103]

[0104] The calculation yields d = ((C11+C12)-(C01+C02)) / 2+t.

[0105] For example, when n=3, the on-chip system includes a first subsystem and three second subsystems on a daisy chain. The process of determining the system clock difference between the second hardware domain of the third second subsystem and the first hardware domain of the first subsystem is described in detail below. Let t be the daisy chain data transmission delay between two adjacent hardware domains, and t3 be the daisy chain data transmission delay from the first hardware domain of the first subsystem to the second hardware domain of the third second subsystem, where t3 = 3t.

[0106] First, the first hardware domain sends a first sampling instruction to the second hardware domain and simultaneously samples the clock of the first daisy chain counter to obtain a first sampled value C01; after a delay of 3t, the second hardware domain of the third second subsystem samples the clock of the second daisy chain counter based on the first sampling instruction obtained from the first hardware domain and obtains a second sampled value C11.

[0107] Next, after a preset time, the first hardware domain sends a second sampling instruction to the second hardware domain and simultaneously samples the clock of the first daisy chain counter to obtain a third sample value C02; after a delay of 3t, the second hardware domain of the third second subsystem samples the clock of the second daisy chain counter based on the second sampling instruction obtained from the first hardware domain and obtains a fourth sample value C12.

[0108] Finally, the second hardware domain determines the system clock difference d between the second hardware domain of the third second subsystem and the first hardware domain based on the first sampled value C01 and the third sampled value C02 obtained from the first hardware domain, the second sampled value C11, the fourth sampled value C12, and the daisy-chain data transmission delay 3t between the first hardware domain and the second hardware domain of the third second subsystem.

[0109] Specifically, the system clock difference d can be calculated using the following formula;

[0110]

[0111] The calculation yields d = ((C11+C12)-(C01+C02)) / 2+3t.

[0112] The above describes in detail the specific process of determining the daisy-chain data transmission delay and system clock difference between the first hardware domain and the second hardware domains of the first and third second subsystems. The specific process of determining the daisy-chain transmission delay and system clock difference between the first hardware domain and the second hardware domains of the second, fourth, ... second subsystems is similar to the above process and will not be repeated here.

[0113] After determining the system clock difference d between the second hardware domain and the first hardware domain, the second hardware domain calibrates the clock of its second daisy chain counter according to the system clock difference d, so that the clock of the second daisy chain counter of the second hardware domain is synchronized with the clock of the first daisy chain counter of the first hardware domain.

[0114] The aforementioned method of achieving time synchronization between two subsystems using a daisy-chain counter reduces the impact of communication path delays and jitter on time synchronization accuracy. Time synchronization accuracy can reach the microsecond level. In this embodiment, the clock synchronization accuracy of the two daisy-chain counters is less than 1 microsecond. Therefore, in practical applications, the first hardware domain can send the time information of the first subsystem to the second hardware domain of the second subsystem through various communication links. For example, it can send the time information of the first subsystem to the second hardware domain of the second subsystem through virtual network cards, SPI, I2C, etc., thus enabling more flexible responses to various practical scenarios.

[0115] In some embodiments, the first subsystem further includes a first virtual network interface card (NIC), and the second subsystem further includes a second virtual NIC.

[0116] The first hardware domain sends the first subsystem time information to the second hardware domain through the first virtual network card, daisy-chain bus, and second virtual network card.

[0117] Optionally, the first and second virtual network cards can be ulink virtual network cards based on DCI technology.

[0118] Optionally, the first hardware domain and the second hardware domain are connected via a TCP network. Specifically, the first hardware domain sequentially sends the first subsystem time information to the second hardware domain through the first TCP / IP protocol stack, the first virtual network interface card (NIC), the daisy-chain bus, the second virtual NIC, and the second TCP / IP protocol stack; wherein, the first subsystem time information includes the timestamp of the first subsystem and the clock information of the first daisy-chain counter.

[0119] In some embodiments, see Figure 5 Based on the time information of the first subsystem sent from the first hardware domain, the timestamp of the second subsystem is determined, including:

[0120] S501, obtain the clock information of the second daisy chain counter;

[0121] S502, determine the network data transmission delay based on the clock information of the first daisy chain counter and the clock information of the second daisy chain counter;

[0122] S503, determine the timestamp of the second subsystem based on the network data transmission delay and the timestamp of the first subsystem.

[0123] For example, based on DCI-based virtual network interface card (NIC) technology, the first hardware domain of the first subsystem establishes a TCP network connection with the second hardware domain of the second subsystem. Specifically, the first hardware domain (root node) sequentially sends the first subsystem's time information to the second hardware domain (leaf node) through the first TCP / IP protocol stack, the first virtual NIC, the daisy-chain bus, the second virtual NIC, and the second TCP / IP protocol stack. The first subsystem's time information includes the first subsystem's timestamp and the clock information of the first daisy-chain counter.

[0124] Specifically, the first hardware domain packages and sends the first subsystem time information DCI_CA to the second hardware domain via the TCP network. The first subsystem time information DCI_CA includes the first subsystem's timestamp Timestamp_A and the clock information root DCI counter of the first daisy chain counter.

[0125] The second hardware domain acquires the clock information of the second daisy chain counter, the leaf DCI counter.

[0126] The second hardware domain determines the network data transmission delay delta_DCI based on the clock information of the first daisy chain counter (root DCI counter) and the clock information of the second daisy chain counter (leaf DCI counter); that is, delta_DCI = leaf DCI counter - root DCI counter.

[0127] The second hardware domain obtains the timestamp of the second subsystem, Timestamp_B, based on the network data transmission delay delta_DCI and the timestamp of the first subsystem, Timestamp_A, according to the formula Timestamp_B = Timestamp_A + delta_DCI.

[0128] The second hardware domain updates the system time of the second subsystem based on the timestamp Timestamp_B of the second subsystem, so that the system time of the second subsystem is synchronized with that of the first subsystem.

[0129] In some embodiments, see Figure 8 As shown, the second subsystem includes at least an application domain, a multi-function domain, a protection domain, and a security domain; the second real-time clock module includes a third real-time clock chip and a fourth real-time clock chip.

[0130] See Figure 6 As shown, the second real-time clock module of the second subsystem synchronizes the time of each hardware domain of the second subsystem, including:

[0131] S701, the application domain, multi-function domain and security domain are clocked through a third real-time clock chip, and the security domain is clocked through a fourth real-time clock chip;

[0132] S702 obtains the timestamp of the third real-time clock chip through one of the application domain, multi-function domain, and protection domain, and transmits the timestamp of the third real-time clock chip to the security domain through inter-domain communication.

[0133] S703, the security domain writes the timestamp of the third real-time clock chip to the fourth real-time clock chip, so that the clocks of the third real-time clock chip and the fourth real-time clock chip are synchronized, thereby synchronizing the time of the application domain, the multi-function domain, the protection domain and the security domain.

[0134] In this embodiment, inter-domain communication methods may include asynchronous message passing via a mailbox mechanism and cross-hardware domain data sharing via a shared memory mechanism.

[0135] In this embodiment, the application domain, multi-function domain, and protection domain share a third real-time clock chip, while the security domain uses a fourth real-time clock chip. Any one of the application domain, multi-function domain, and protection domain obtains the timestamp of the third real-time clock chip and transmits the timestamp of the third real-time clock chip to the security domain via a mailbox. The security domain writes the timestamp of the third real-time clock chip to the fourth real-time clock chip, thereby synchronizing the clocks of the third and fourth real-time clock chips. This ensures time synchronization of the application domain, multi-function domain, protection domain, and security domain, and consequently, time synchronization of the various hardware domains of the second subsystem.

[0136] Based on the same inventive concept, embodiments of this application provide a system-on-a-chip, combined with Figure 7 As shown, the system-on-a-chip includes a first subsystem and at least one second subsystem. Both the first and second subsystems include multiple hardware domains. One hardware domain in the first subsystem is called the first hardware domain, and one hardware domain in the second subsystem is called the second hardware domain. The first hardware domain is the root node, and the second hardware domain is the leaf node. The root node and at least one leaf node are electrically connected via a daisy chain. The first hardware domain includes a first daisy chain counter, and the second hardware domain includes a second daisy chain counter. The first subsystem includes a first real-time clock module, and the second subsystem includes a second real-time clock module. Figure 7 In the diagram, subsystem 1 represents the first subsystem, subsystem 2 represents the second subsystem, and subsystem n represents the nth subsystem, where n is an integer greater than or equal to 1.

[0137] The first real-time clock module is configured to synchronize the time of each hardware domain of the first subsystem;

[0138] The second hardware domain is configured to determine the daisy-chain data transfer latency between the first hardware domain and the second hardware domain.

[0139] The second hardware domain is configured to determine the system clock difference between the second hardware domain and the first hardware domain based on the daisy chain data transmission delay.

[0140] The second hardware domain is configured to calibrate the clock of the second daisy chain counter based on the system clock difference, so that the clock of the second daisy chain counter is synchronized with that of the first daisy chain counter.

[0141] The second hardware domain is configured to determine the timestamp of the second subsystem based on the first subsystem time information sent from the first hardware domain; wherein the first subsystem time information includes the timestamp of the first subsystem and the clock information of the first daisy-chain counter.

[0142] The second hardware domain is configured to update the system time of the second subsystem based on the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with that of the first subsystem.

[0143] The second real-time clock module is configured to synchronize the time of each hardware domain of the second subsystem.

[0144] The system-on-a-chip (SoC) provided in this application includes a first subsystem and at least one second subsystem. Both the first and second subsystems include multiple hardware domains. One hardware domain in the first subsystem is a first hardware domain, and one hardware domain in the second subsystem is a second hardware domain. The first hardware domain is a root node, and the second hardware domain is a leaf node. The root node and at least one leaf node are electrically connected via a daisy chain. The first hardware domain includes a first daisy chain counter, and the second hardware domain includes a second daisy chain counter. The first subsystem includes a first real-time clock module, and the second subsystem includes a second real-time clock module. First, the time of each hardware domain in the first subsystem is synchronized. Then, the clocks of the first daisy chain counter in the first subsystem and the second daisy chain counter in the second subsystem are synchronized. Next, the clocks of the two daisy chain counters are synchronized to achieve system time synchronization between the first and second subsystems. Finally, the time of each hardware domain in the second subsystem is synchronized, thereby achieving time synchronization between the first and second subsystems of the SoC, as well as time synchronization between the hardware domains within the first and second subsystems. This application achieves time synchronization between the first and second subsystems of an on-chip system by using a daisy-chain counter. This not only reduces the impact of time delay and jitter on the time synchronization accuracy of the communication path between subsystems, thereby improving the time synchronization accuracy of the on-chip system, but also does not require additional hardware costs.

[0145] In some embodiments, see Figure 7As shown, the output terminal of the first hardware domain of the first subsystem is electrically connected to the input terminal of the second hardware domain of the first second subsystem via a daisy-chain bus, the output terminal of the second hardware domain of the first second subsystem is electrically connected to the input terminal of the second hardware domain of the next second subsystem via a daisy-chain bus, and the output terminal of the second hardware domain of the last second subsystem is electrically connected to the input terminal of the first hardware domain of the first subsystem via a daisy-chain bus.

[0146] Optionally, the daisy-chain buses connecting any two adjacent hardware domains are of equal length.

[0147] In some embodiments, see Figure 8 As shown, the first subsystem includes at least an application domain, a multi-function domain, a protection domain, and a security domain; the first real-time clock module includes a first real-time clock chip and a second real-time clock chip.

[0148] In this embodiment, the application domain, multi-function domain, and protection domain share a first real-time clock chip, while the security domain uses a second real-time clock chip. Any one of the application domain, multi-function domain, and protection domain obtains the timestamp of the first real-time clock chip and transmits the timestamp of the first real-time clock chip to the security domain via a mailbox. The security domain writes the timestamp of the first real-time clock chip to the second real-time clock chip, thereby synchronizing the clocks of the first real-time clock chip and the second real-time clock chip. This synchronizes the time of the application domain, multi-function domain, protection domain, and security domain, and consequently, synchronizes the time of each hardware domain of the first subsystem.

[0149] In some embodiments, see Figure 8 As shown, the second subsystem includes at least an application domain, a multi-function domain, a protection domain, and a security domain; the second real-time clock module includes a third real-time clock chip and a fourth real-time clock chip.

[0150] In this embodiment, the application domain, multi-function domain, and protection domain share a third real-time clock chip, while the security domain uses a fourth real-time clock chip. Any one of the application domain, multi-function domain, and protection domain obtains the timestamp of the third real-time clock chip and transmits the timestamp of the third real-time clock chip to the security domain via a mailbox. The security domain writes the timestamp of the third real-time clock chip to the fourth real-time clock chip, thereby synchronizing the clocks of the third and fourth real-time clock chips. This ensures time synchronization of the application domain, multi-function domain, protection domain, and security domain, and consequently, time synchronization of the various hardware domains of the second subsystem.

[0151] Based on the same inventive concept, this application provides a vehicle including the system-on-a-chip as described in the above embodiments. The implementation and effects of the vehicle provided in this application can be referred to the foregoing embodiments, and will not be repeated here.

[0152] In this application, "vehicle" can refer to "automobile," "vehicle," or "complete vehicle," or other similar terms, including general motor vehicles such as sedans, SUVs, MPVs, buses, trucks, and other freight or passenger vehicles; water transport vehicles including various boats and vessels; and aircraft, including hybrid vehicles, electric vehicles, gasoline vehicles, plug-in hybrid vehicles, fuel cell vehicles, and other alternative fuel vehicles. Hybrid vehicles refer to vehicles with two or more power sources, and electric vehicles include pure electric vehicles and range-extended electric vehicles; this application does not specifically limit their use.

[0153] This application also provides an electronic device, including a processor and a memory, wherein the memory stores an executable program, and the memory executes the executable program to perform the steps of the method described above. The implementation and effects of the electronic device provided in this application can be referred to the foregoing embodiments, and will not be repeated here.

[0154] This application also provides a storage medium carrying one or more computer programs, which, when executed by a processor, implement the steps of the method described above.

[0155] This application also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the method described above.

[0156] It should be understood that in the embodiments of this application, the processor may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0157] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0158] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated into the processor.

[0159] It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.

[0160] It should also be understood that the first, second, third, fourth and various numerical designations used herein are merely for descriptive convenience and are not intended to limit the scope of this application.

[0161] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0162] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0163] In the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0164] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0165] In the several embodiments provided in this application, it should be understood that the disclosed methods, accelerators, and electronic devices can be implemented in other ways. For example, the accelerator embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0166] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0167] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0168] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0169] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for time synchronization of an on-chip system, characterized in that, The system-on-a-chip includes a first subsystem and at least one second subsystem. Both the first subsystem and the second subsystem include multiple hardware domains. One hardware domain in the first subsystem is a first hardware domain, and one hardware domain in the second subsystem is a second hardware domain. The first hardware domain is a root node, and the second hardware domain is a leaf node. The root node and at least one of the leaf nodes are electrically connected in a daisy chain manner. The first hardware domain includes a first daisy-chain counter, the second hardware domain includes a second daisy-chain counter, and the method includes: The first real-time clock module of the first subsystem synchronizes the time of each hardware domain of the first subsystem. Determine the daisy-chain data transmission delay between the first hardware domain and the second hardware domain; Based on the daisy-chain data transmission delay, determine the system clock difference between the second hardware domain and the first hardware domain; Based on the system clock difference, the clock of the second daisy chain counter is calibrated so that the clock of the second daisy chain counter is synchronized with that of the first daisy chain counter. The timestamp of the second subsystem is determined based on the first subsystem time information sent from the first hardware domain; wherein the first subsystem time information includes the timestamp of the first subsystem and the clock information of the first daisy chain counter. Update the system time of the second subsystem according to the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with that of the first subsystem; The second real-time clock module of the second subsystem synchronizes the time of each hardware domain of the second subsystem.

2. The method for time synchronization of an on-chip system according to claim 1, characterized in that, Determining the daisy-chain data transmission delay between the first hardware domain and the second hardware domain includes: Based on the timing command obtained from the first hardware domain, the second daisy chain counter is controlled to keep time; wherein, the first hardware domain controls the first daisy chain counter to keep time while sending the timing command. The second hardware domain sends a stop timing command to the first hardware domain and synchronously controls the second daisy chain counter to stop timing, so that the first hardware domain controls the first daisy chain counter to stop timing according to the stop timing command; Based on the read instruction obtained from the first hardware domain, the clock value of the second daisy chain counter is read and used as the second clock value; wherein, the first hardware domain reads the clock value of the first daisy chain counter and uses it as the first clock value at the same time as sending the read instruction. Based on the first clock value and the second clock value obtained from the first hardware domain, the daisy-chain data transmission delay between the first hardware domain and the second hardware domain is determined.

3. The method for time synchronization of an on-chip system according to claim 2, characterized in that, Before controlling the second daisy-chain counter to start timing based on the timing command obtained from the first hardware domain, the following steps are included: Based on the initialization instruction obtained from the first hardware domain, the second daisy chain counter is initialized; wherein, the first hardware domain initializes the first daisy chain counter at the same time as sending the initialization instruction.

4. The method for time synchronization of an on-chip system according to claim 1, characterized in that, Determining the system clock difference between the second hardware domain and the first hardware domain based on the daisy-chain data transmission delay includes: Based on the first sampling instruction obtained from the first hardware domain, the clock of the second daisy chain counter is sampled and a second sample value is obtained; wherein, the first hardware domain samples the clock of the first daisy chain counter and obtains the first sample value at the same time as sending the first sampling instruction. Based on the second sampling instruction obtained from the first hardware domain, the clock of the second daisy chain counter is sampled to obtain a fourth sample value; wherein, while sending the second sampling instruction, the first hardware domain samples the clock of the first daisy chain counter to obtain a third sample value. Based on the first sampled value and the third sampled value obtained from the first hardware domain, as well as the second sampled value, the fourth sampled value, and the daisy-chain data transmission delay, the system clock difference between the second hardware domain and the first hardware domain is determined.

5. The method for time synchronization of an on-chip system according to claim 1, characterized in that, The first subsystem further includes a first virtual network interface card (NIC), and the second subsystem further includes a second virtual NIC; The first hardware domain sends the first subsystem time information to the second hardware domain through the first virtual network card, the daisy-chain bus, and the second virtual network card.

6. The method for time synchronization of an on-chip system according to claim 1, characterized in that, Determining the timestamp of the second subsystem based on the first subsystem time information sent from the first hardware domain includes: Obtain the clock information of the second daisy chain counter; The network data transmission delay is determined based on the clock information of the first daisy chain counter and the clock information of the second daisy chain counter. The timestamp of the second subsystem is determined based on the network data transmission delay and the timestamp of the first subsystem.

7. The method for time synchronization of an on-chip system according to claim 1, characterized in that, The first subsystem includes at least an application domain, a multi-function domain, a protection domain, and a security domain; the first real-time clock module includes a first real-time clock chip and a second real-time clock chip. The step of synchronizing the time of each hardware domain of the first subsystem through the first real-time clock module of the first subsystem includes: The application domain, the multi-function domain, and the security domain are clocked through the first real-time clock chip, and the security domain is clocked through the second real-time clock chip. The timestamp of the first real-time clock chip is obtained through one of the application domain, the multi-function domain, and the protection domain, and the timestamp of the first real-time clock chip is transmitted to the security domain through inter-domain communication. The security domain writes the timestamp of the first real-time clock chip to the second real-time clock chip, thereby synchronizing the clocks of the first real-time clock chip and the second real-time clock chip, and thus synchronizing the time of the application domain, the multi-function domain, the protection domain, and the security domain.

8. A system-on-a-chip, characterized in that, The system includes a first subsystem and at least one second subsystem. Both the first and second subsystems include multiple hardware domains. One hardware domain in the first subsystem is designated as a first hardware domain, and one hardware domain in the second subsystem is designated as a second hardware domain. The first hardware domain is a root node, and the second hardware domain is a leaf node. The root node and at least one leaf node are electrically connected via a daisy-chain configuration. The first hardware domain includes a first daisy-chain counter, and the second hardware domain includes a second daisy-chain counter. The first subsystem includes a first real-time clock module, and the second subsystem includes a second real-time clock module. The first real-time clock module is configured to synchronize the time of each hardware domain of the first subsystem; The second hardware domain is configured to determine the daisy-chain data transfer latency between the first hardware domain and the second hardware domain; The second hardware domain is configured to determine the system clock difference between the second hardware domain and the first hardware domain based on the daisy-chain data transmission delay. The second hardware domain is configured to calibrate the clock of the second daisy chain counter according to the system clock difference, so that the clock of the second daisy chain counter is synchronized with the clock of the first daisy chain counter; The second hardware domain is configured to determine the timestamp of the second subsystem based on the first subsystem time information sent from the first hardware domain; wherein the first subsystem time information includes the timestamp of the first subsystem and the clock information of the first daisy-chain counter; The second hardware domain is configured to update the system time of the second subsystem based on the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with that of the first subsystem. The second real-time clock module is configured to synchronize the time of each hardware domain of the second subsystem.

9. A vehicle comprising the system-on-a-chip as claimed in claim 8.

10. A computer program product comprising a computer program / instructions which, when executed by a processor, implement the steps of the time synchronization method for a system-on-chip as claimed in any one of claims 1 to 7.

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