A cache unit, circuit structure thereof and cache management method

Abstract

The embodiment of the present application discloses a cache unit, a circuit structure and a cache management method. The embodiment of the present application receives a cache management command including at least one address structure body with corresponding physical page address information, traverses each cache tag in the cache unit, determines whether there is an address structure body consistent with the address information of the corresponding cache tag in each address structure body, determines the cache tag consistent with the address information of any address structure body as a target cache tag, and performs a target data management operation on the cache data corresponding to the target cache tag. Therefore, the embodiment can search whether the cache tag in the cache unit hits by issuing a cache management command, the search frequency is relatively low, the number of commands issued by the manager module can be reduced, the system load and power consumption are reduced, and the system performance is improved.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and more specifically, to a cache unit, its circuit structure, and a cache management method. Background Technology

[0002] In a computer system, a cache maintains a small amount of frequently accessed data. This data is a mirror image of the data in main memory. When the computer accesses this data, the access behavior ends at the cache rather than the main memory, thereby reducing the access latency of this data. Therefore, the amount of data cached is much smaller than the size of the system's main memory.

[0003] In computer systems, data management is typically done at the physical page level. Data within the same page shares the same base address, and data is located within a page using offsets. In specific application scenarios, data accessed through the cache may reside across multiple physical pages. However, due to the characteristics of the cache, only a small amount of frequently accessed data is cached within it. Furthermore, the computer cannot know in advance which data is cached and which is not. When the system needs to manage cache resources, the administrator (operating system, driver software, etc.) usually only knows the maximum range of data space accessed through the cache, but cannot predict in advance which data is already cached. Finding and manipulating this maximum range of cached data is very difficult, and unoptimized operations are highly inefficient, introducing significant performance and power consumption overhead. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a cache unit and its circuit structure and cache management method, which traverses and searches the cache tags in the cache unit to see if they are hit by issuing cache management commands, thereby reducing the number of searches and the number of commands issued by the manager module, reducing system load and power consumption, and improving system performance.

[0005] In a first aspect, embodiments of the present invention provide a cache management method, the method comprising:

[0006] Receive a cache management command, wherein the cache management command includes at least one address structure corresponding to the data to be managed, and the address structure includes the address information of the corresponding physical page;

[0007] Traverse each cache tag in the cache unit to determine whether there is an address structure in each address structure that is consistent with the address information of the corresponding cache tag;

[0008] The cache tag that matches the address information of any of the address structures is determined as the target cache tag;

[0009] Perform target data management operations on the cached data corresponding to the target cache tag.

[0010] Secondly, embodiments of the present invention provide a circuit structure for a cache unit, the circuit structure of which includes:

[0011] The tag storage module is configured to store cache tags, wherein the cache tag is a unique identifier for the cached data stored in the cache unit;

[0012] The search engine is configured to receive cache management commands and read corresponding cache tags from the tag storage module. The cache management commands include at least one address structure corresponding to the data to be managed, and the address structure includes the address information of the corresponding physical page.

[0013] The first matching module is configured to receive the currently read cache tag sent by the search engine and each of the address structures carried by the cache management command, and to perform address consistency comparison between the currently read cache tag and each of the address structures. In response to the current read cache tag being consistent with the address information in any of the address structures, the cache tag is determined as the target cache tag.

[0014] The data execution module is configured to perform target management operations on cached data corresponding to target cache tags received from the matching module.

[0015] Thirdly, embodiments of the present invention provide a cache management system, the cache management system comprising:

[0016] The circuit structure of the cache unit as described above;

[0017] The manager module is configured to receive and parse data access requests, generate cache management commands or cache access commands, and send the cache management commands or cache access commands to the circuit structure of the cache unit for processing.

[0018] Fourthly, embodiments of the present invention provide a caching unit, the caching unit comprising:

[0019] The cache space is configured to store cached data.

[0020] The circuit structure of the cache unit as described above.

[0021] Fifthly, embodiments of the present invention provide an electronic device, the electronic device comprising:

[0022] The cache unit as described above;

[0023] The manager module is configured to receive and parse data access requests, generate cache management commands or cache access commands, and send the cache management commands or cache access commands to the cache unit for processing.

[0024] Main memory is used to store data.

[0025] In a sixth aspect, embodiments of the present invention provide a computer-readable storage medium storing a computer program or data, wherein the computer program, when executed by a processor, implements the method described above.

[0026] This invention discloses a cache unit, its circuit structure, and a cache management method. The invention receives a cache management command including at least one address structure with address information corresponding to a physical page, and traverses each cache tag in the cache unit to determine if any address structure exists that matches the address information of the corresponding cache tag. The cache tag matching the address information of any address structure is identified as the target cache tag, and target data management operations are performed on the cache data corresponding to the target cache tag. Therefore, this embodiment can traverse and search the cache unit for cache tag hits by issuing cache management commands, resulting in a relatively low number of searches. It also reduces the number of commands issued by the manager module, lowering system load and power consumption, and improving system performance. Attached Figure Description

[0027] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a data diagram of the cache unit and main memory according to an embodiment of the present invention;

[0029] Figure 2 This is a flowchart of a proportional cache management method;

[0030] Figure 3 This is a schematic diagram of the circuit structure of a proportional cache unit;

[0031] Figure 4 This is a flowchart of a cache management method according to an embodiment of the present invention;

[0032] Figure 5 This is a flowchart of a matching method according to an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of a matching process according to an embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of another matching process according to an embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of another matching process according to an embodiment of the present invention;

[0036] Figure 9 This is a flowchart of another cache management method according to an embodiment of the present invention;

[0037] Figure 10 This is a schematic diagram of the circuit structure of the cache unit according to an embodiment of the present invention;

[0038] Figure 11 This is a schematic diagram of a cache unit according to an embodiment of the present invention;

[0039] Figure 12 This is a schematic diagram of a cache management system according to an embodiment of the present invention;

[0040] Figure 13 This is a schematic diagram of a cache data management device according to an embodiment of the present invention;

[0041] Figure 14 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0042] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0043] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0044] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0045] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0046] The solutions described in this specification and embodiments, if involving the processing of personal information, will be processed only under the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be processed within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0047] Figure 1 This is a schematic diagram of the cache unit and main memory according to an embodiment of the present invention. It should be understood that the cache unit and main memory in this embodiment are merely exemplary and do not represent the cache and main memory in an actual computer system. Figure 1 As shown, in practical applications, two physical pages, PageA and PageB, in main memory 12 can be accessed through cache unit 11. Physical page PageA has a size of 8 data blocks, and physical page PageB has a size of 4 data blocks. Each of these data blocks has a unique logical tag, which is the address of the corresponding data block. Furthermore, the address of a data block is composed of the base address of the corresponding physical page and the offset address within the page. For example, the logical tag (PageA,5) identifies the 5th data block within physical page PageA. Therefore, PageA contains 8 data blocks (PageA,0)-(PageA,7), and PageB contains 4 data blocks (PageB,0)-(PageA,3).

[0048] Cache unit 11 has a total capacity of 4 physical cache tags, consisting of two cache sets, Set1 and Set2. Each cache set includes 2 cache ways. In a computer system, a cache tag within a cache set constitutes a way. Figure 1 As shown, cache unit 11 caches (PageA,0), (PageB,3), (PageA,5), and an empty cache tag. Furthermore, (PageA,0) and (PageB,3) are located in the same cache group Set1, while (PageA,5) and the empty cache tag are located in the same cache group Set2. Other data blocks, such as {PageB,0}, which are not in cache unit 11, may have been cached in cache unit 11 before, but due to low access frequency of non-hot data, they were replaced with the currently cached data blocks. Therefore, of the 12 logical tags corresponding to the 12 data blocks in the two physical pages PageA and PageB, only 3 are mapped to the physical cache tags in cache unit 11.

[0049] It is evident that the amount of data cached in cache unit 11 is far less than the amount of data in main memory. In practical applications, if multiple physical pages in main memory are accessed, the management module cannot anticipate which logical tags being accessed are already cached in cache unit 11. Therefore, it must sequentially send commands corresponding to all logical tags in the accessed physical pages to cache unit 11 for searching. If the logical tag in the command matches a physical cache tag in cache unit 11, the corresponding data operation is performed; otherwise, no operation is performed. Clearly, in this situation, the number of commands required (the number of logical tags in the accessed physical pages) is large, the number of searches is high, and the system's performance and power consumption are significant.

[0050] Figure 2 This is a flowchart of a proportional cache management method. For example... Figure 2 As shown in the comparative example, after the search and matching process corresponding to the data management operation within the cache unit begins, search commands corresponding to each logical label are sequentially sent to the cache unit for search and matching. The specific process includes the following steps:

[0051] Step S110: Obtain the current physical page being traversed. Figure 1 Taking main memory 12 as an example, after the search and matching process begins, PageA can be traversed first.

[0052] Step S120: Obtain the current logical label for traversal in the current physical page. Taking PageA as an example, the physical page being traversed can be traversed sequentially from small to large based on the offset addresses of each data block in PageA. Then, the current logical label obtained when starting the traversal in PageA is (PageA, 0).

[0053] Step S130: Send the search command corresponding to the current logical tag to the cache unit for matching. Taking the current logical tag as (PageA,0) as an example, match each address bit of the current logical tag (PageA,0) with the address bits of each cache tag in each cache group in the cache unit one by one.

[0054] Step S140: Determine if a match is found. If the address values ​​of a cache tag in the cache unit are all the same as the address values ​​of the current logical tag, then the current match is found to be found. If there is no cache tag in the cache unit whose address values ​​are all the same as the current logical tag, then the current match is found to be ...

[0055] In step S150, in response to the current match, the corresponding data management operation is executed, that is, the corresponding data management operation is performed on the cached data corresponding to the matched cached tag in the cache, such as deleting the cached data or reading the cached data. After executing the data management operation corresponding to the currently matched cached tag, step S160 continues.

[0056] Step S160: Determine if the current physical page has been completely traversed. That is, after a no-match or a match has been found and the corresponding data management operation has been performed, determine if the current physical page has been completely traversed. If the current physical page has not been completely traversed, continue with step S120, which means continuing to traverse the current physical page to obtain the next current logical tag. For example, if the current logical tag is (PageA, 0), after performing the search matching operation, if it is determined that the corresponding current physical page PageA has not been completely traversed, then continue to traverse PageA to obtain the next current logical tag (PageA, 1), repeating steps S130-S160 until PageA is completely traversed, that is, the search matching operation for logical tag (PageA, 7) is completed. Further, if the current physical page has been completely traversed, continue with step S170.

[0057] Step S170: Determine if all physical pages have been traversed. After all logical tags in the current physical page have completed their corresponding search and matching, determine if there are any untraversed physical pages among all the physical pages to be accessed. If there are still untraversed physical pages, continue executing steps S110-S160 to sequentially traverse the search and matching operations of each logical tag in that physical page until all physical pages in main memory have been traversed. If there are no untraversed physical pages, proceed to step S180.

[0058] Step S180: After traversing all the required physical pages, the current search and matching process is considered complete. Furthermore, the corresponding operation results can be fed back, such as feedback that the corresponding cached data has been deleted, or feedback on the cached data read.

[0059] Figure 3 This is a schematic diagram of the circuit structure of a proportional cache unit. (Example) Figure 3As shown, the Manager module 10 sequentially sends search commands carrying logical tags to the cache unit 30 through the Cache Interface 20, enabling the cache unit 30 to perform corresponding search matching and data management operations. Specifically, the circuit structure of the cache unit 30 includes a Tag Unit 31, an Exact Match Unit 32, and an Execution Unit 33. The Tag Unit 31 stores physical cache tags, and the Exact Match Unit 32 performs precise matching of cache tags. Specifically, it compares each cache tag read from the Tag Unit 31 with each address bit of the logical tag carried by the received search command. If a cache tag exists where all address bits match the logical tag, a match is determined; otherwise, a miss is determined. Further, the Match Unit 32 sends the match result to the Execution Unit 33 for corresponding cache data management operations. That is, this comparison is performed through the Manager module and the cache unit to execute steps S110-S170, which will not be described in detail here.

[0060] by Figure 1 Taking cache unit 11 and main memory 12 as examples, and accessing Page A and Page B in main memory 12, the administrator module does not know which data blocks in the two physical pages Page A and Page B are already cached in cache unit 11. Therefore, it can only completely edit all logical tags in Page A and Page B, and send these logical tags as search commands to cache unit 11 for precise matching. Only when the cached tags already cached in cache unit 11 are exactly the same as the logical tags will the corresponding management operation be performed. It can be seen that this access will generate a total of 12 search commands to cache unit 11, of which only 3 commands can generate effective management operations, and 9 commands become invalid commands due to no match. These invalid commands will waste the bandwidth and power consumption of cache unit 11. In addition, all commands need to be initiated by the administrator module, and the administrator module needs to control the traversal process. In the traditional solution, this will occupy the processing time of the administrator module for 12 commands. Since the administrator module is usually the main processor such as the CPU, the time occupied by the main processor will further reduce the system performance.

[0061] Therefore, this invention provides a cache unit, its circuit structure, and a cache management method, which uses cache management commands to traverse and search the cache unit to check if the cache tags are hit, resulting in a relatively low number of searches. At the same time, it can reduce the number of commands issued by the manager module, reduce system load and power consumption, and improve system performance.

[0062] Figure 4This is a flowchart of a cache management method according to an embodiment of the present invention. Figure 4 As shown, the cache management method of this invention includes the following steps:

[0063] Step S210: Receive a cache management command. The cache management command includes at least one address structure corresponding to the data to be managed. The address structure includes the address information of the corresponding physical page.

[0064] In one optional implementation, the manager module parses the corresponding data access requests and determines whether they meet the conditions for using the cache management method of this embodiment based on the type of the data access request. If the conditions are met, a cache management command corresponding to the data access request is generated and sent to the cache unit. Further, in this embodiment, the data access request can be parsed to determine whether the cached data requiring cache management in the accessed physical page is managed on a physical page basis, thereby determining whether the cache management process meets the conditions for using the cache management method of this embodiment. Optionally, the manager module can parse recent data access requests to determine that some physical pages cached in the cache unit have low data access frequency, and can generate a cache management command to clear the cached data corresponding to these physical pages in the cache unit. It should be understood that this embodiment does not limit the specific type of data access request that meets the conditions for using the cache management method of this embodiment; it can be configured based on the actual situation.

[0065] Further, in an optional implementation, at least one address structure in the cache management command is determined by filtering from the address structures of the physical pages accessed from the cache unit. Further, at least one address structure in the cache management command may include the address structure of the physical page requiring corresponding management operation among all physical pages accessed through the cache unit. Optionally, the corresponding management operation for cached data in the cache unit may be clearing the corresponding cached data of the corresponding physical page in the cache unit. For example, if four physical pages in main memory are accessed through the cache unit, and these four physical pages have corresponding four address structures, assuming that management needs to be performed on two of these physical pages, to find and clear the cached data that may be cached in the cache unit in these two physical pages, then the address structures corresponding to these two physical pages need to be sent to the cache unit through the cache management command to perform search and matching processing. This embodiment mainly uses cache clearing operation as an example for illustration; it should be understood that this embodiment is not limited to this, and it can be configured and determined according to actual application conditions.

[0066] Therefore, this embodiment can merge multiple physical pages that require management operations and are accessed through the cache unit into a single cache management command and send it to the cache unit, thereby reducing the number of commands issued by the manager module, reducing system load and power consumption, and improving system performance.

[0067] Furthermore, the address information of the address structure in this embodiment is determined based on the data address to be accessed in the data access request. The data address includes the page base address of the physical page it resides in and the page offset within that physical page.

[0068] In one optional implementation, the address information in the address structure of this embodiment includes the physical page base address and the page offset address. Optionally, each piece of data accessed in the data access request has a corresponding address structure. This implementation can accommodate both application scenarios requiring precise matching and those requiring fuzzy matching. It should be understood that precise matching in this embodiment means precisely matching the data operation within the corresponding data. However, since many application scenarios in computer systems involve simultaneous data operations on the entire physical page, fuzzy matching can be performed based on the physical page as a unit. That is, as long as the portion representing the physical page base address corresponding to the cache tag in the cache unit matches the portion representing the physical page base address in the address information carried in the cache management command, a hit is determined. Fuzzy matching can further reduce the number of address structures in the cache management command, further reduce the number of search and matching operations, reduce the corresponding computational load, and thus reduce system power consumption.

[0069] Optionally, in this embodiment, for each physical page accessed by the data access request, a data address is selected from at least one set of data located within the same physical page as the address information in the corresponding address structure. That is, this embodiment allows each physical page accessed in the data access request to have a corresponding address structure, further reducing the computational load of subsequent search and matching, and lowering system power consumption. It should be understood that only when all cached data in the corresponding physical page cached in the cache unit is managed simultaneously can each physical page have a corresponding address structure to ensure the accuracy of the data management operation. For example, the data management operation could be to clear all cached data in the cache unit that resides in a certain physical page in main memory.

[0070] In another optional implementation, the address information of the address structure in this embodiment includes the corresponding physical page address and the corresponding physical page size. The corresponding physical page size represents the amount of data or the number of data blocks that the corresponding physical page can store. Further, the physical page address in the address structure of this embodiment can be represented by a data address within that physical page; that is, the format of the address structure can be {Page Address, Page Size}. Further optionally, this embodiment can determine the address bits of the physical page base address in the corresponding data address based on the corresponding physical page size to obtain the physical page base address. In this case, the physical page address in the address information of the address structure of this embodiment is the physical page base address; that is, the format of the address structure can be {Page Base Address, Page Size}.

[0071] Furthermore, different physical pages have different page sizes, meaning different numbers of data blocks within a physical page, resulting in different amounts of data that can be stored within that page. For physical pages capable of storing more data, a larger offset address range is needed to represent all the data within the page. Therefore, the number of bits occupied by the offset address in the data address differs for physical pages of different page sizes. For physical pages with larger page sizes, the offset address occupies even more bits in the corresponding data address. With the total number of bits in the data address being the same, physical pages with larger page sizes have longer offset addresses and shorter physical page base addresses. It should be understood that the specific address lengths of the physical page base address and offset address in the data address corresponding to physical pages of different page sizes can be determined based on the specific configuration of the computer system, and this embodiment does not impose any limitations on this.

[0072] Furthermore, in this embodiment, the offset address in the data address can be calculated first, and the low-order bits occupied by the offset address in the data address can be determined based on the size of the offset address, thereby determining the address bit length of the physical page base address in the high-order bits. Optionally, Page Offset = Log(Page Size), where Page Size is the amount of data that the corresponding physical page can store. It should be understood that this embodiment does not limit the method for determining the address bits of the physical page base address in the data address.

[0073] Furthermore, this embodiment can determine the address bit lengths of the physical page base address and offset address of the corresponding physical page based on the pre-determined total length of the data address, the physical page base address corresponding to each page size, and the physical page size corresponding to the accessed data. Then, based on the physical page base address length, corresponding address bits are extracted from the data address of the accessed data to obtain the base address of the physical page containing the accessed data. Subsequently, a corresponding address structure {Page Base Address, Page Size} can be generated based on the physical page base address. Optionally, in this embodiment, the high-order bits of the data address are used to store the physical page base address, and the low-order bits are used to store the offset address within the page. This embodiment can extract corresponding address bits from the high-order bits of the corresponding data address based on the physical page base address length to obtain the corresponding physical page base address.

[0074] Furthermore, assuming that the cache management command is used to instruct corresponding data management operations on the data in the physical pages PageA and PageB cached in the cache unit, the address structure in the cache management command may include {PageAAddress, PageA Size}, {PageB Address, PageB Size}, or the address structure in the cache management command may include {PageA Base Address, PageA Size}, {PageB Base Address, PageB Size}.

[0075] Step S220: Traverse each cache tag in the cache unit to determine whether there is an address structure in each address structure that is consistent with the address information of the corresponding cache tag.

[0076] In one optional implementation, this embodiment can sequentially traverse each cache tag in the cache unit and perform an address consistency comparison between the currently acquired cache tag and each address structure in the cache management command to determine whether the currently acquired cache tag matches any address structure in the management command, that is, whether any address structure exists that matches the address information of the corresponding cache tag. Further, this embodiment sequentially traverses the cache groups in the cache unit and sequentially traverses the cache tags in the cache groups until all cache tags in the cache unit have been traversed. As described above, the number of cache tags in the cache unit is significantly reduced compared to the number of logical tags in the accessed physical page; therefore, the number of traversal searches is also reduced compared to the above comparative method, further reducing system power and performance overhead.

[0077] Figure 5This is a flowchart of a matching method according to an embodiment of the present invention. The matching method in this embodiment describes the fuzzy address matching process between a cache tag and an address structure. It should be understood that, if a parallel matching method is used, the fuzzy address matching process between the cache tag and multiple address structures can be performed in parallel according to the following matching method, or multiple cache tags can be respectively matched with multiple address structures. For example... Figure 5 As shown, the consistency comparison step between the currently traversed cache tag and the corresponding address structure in this embodiment includes:

[0078] Step 221: Determine the address comparison bit between the address structure and the currently traversed cache tag based on the physical page size in the address structure.

[0079] Step 222: In response to the fact that the address comparison bit of the address structure matches the value of the address structure, it is determined that the address information of the currently traversed cache tag is consistent with the address information in the address structure, that is, it is determined that the currently traversed cache tag has been hit.

[0080] In one optional implementation, the physical page address in the address information of the address structure includes the physical page base address and the corresponding offset address within the page. The address information in the address structure also includes the corresponding physical page size. Further, this embodiment can determine the base address length of the physical page corresponding to the address structure based on the physical page size in the address structure, and then compare the corresponding address bits by taking a screenshot from the address structure and the address information of the currently traversed cache tag based on this base address length. It should be understood that the physical page base address length corresponding to various physical page sizes is predetermined and can be determined based on the memory data storage configuration.

[0081] Figure 6 This is a schematic diagram of a matching process according to an embodiment of the present invention. This embodiment uses the example of the physical page base address being located in the high-order bits of the data address and the page offset address being located in the low-order bits of the data address. Figure 6 As shown, the physical page address in the address information of address structure A1 includes the physical page base address = A and the corresponding page offset address = b. Further, in this embodiment, the physical page base address length of the data address in the physical page is determined based on the physical page size (PageSize) in address structure A1, and the high-order bits of the physical page address 61 and the cache tag 62 in address structure A1 are truncated based on this physical page base address length to obtain the address comparison bits corresponding to address structure A1 and the address comparison bits corresponding to cache tag 62 (i.e., the physical page base address). Further, in this embodiment, the address comparison bits of address structure A1 and cache tag 62 are compared.

[0082] This embodiment uses fuzzy matching to handle cache data management operations on a physical page basis, such as... Figure 6 As shown, both the address comparison bit corresponding to address structure A1 and the address comparison bit corresponding to cache tag 62 are A. Even if the page offset address corresponding to address structure A1 is b and the page offset address corresponding to cache tag 62 is c, which are not the same, it can still be determined that the cache tag 62 has been hit, and the corresponding data caching operation can be performed on its corresponding cached data.

[0083] In another optional implementation, the physical page address in the address information of the address structure only includes the physical page base address. The address information in the address structure also includes the corresponding physical page size. Further, this embodiment can determine the base address length of the physical page corresponding to the address structure based on the physical page size in the address structure, and then compare the corresponding address bits by taking a screenshot from the address structure and the address information of the currently traversed cache tag based on this base address length. It should be understood that the physical page base address length corresponding to various physical page sizes is predetermined, and it can be determined based on the memory data storage configuration.

[0084] Figure 7 This is a schematic diagram of another matching process according to an embodiment of the present invention. This embodiment uses the example where the physical page base address is located in the high-order bits of the data address, and the page offset address is located in the low-order bits of the data address. For example... Figure 7 As shown, the physical page address in the address information of address structure A2 includes the physical page base address = A. Further, in this embodiment, the physical page base address length of the data address in the physical page is determined based on the physical page size in address structure A2, and the high-order bits of cache tag 72 are truncated based on this physical page base address length to obtain the address comparison bit corresponding to cache tag 72. Further, in this embodiment, the physical page base address 71 (i.e., the address comparison bit) obtained from address structure A2 is compared with the address comparison bit corresponding to cache tag 72 to ensure address consistency.

[0085] This embodiment uses fuzzy matching to handle cache data management operations on a physical page basis, such as... Figure 7 As shown, the address comparison bits corresponding to the physical page base address 71 and cache tag 72 in address structure A2 are both A. In the case of fuzzy matching, there is no need to match the offset address. Therefore, the cache tag 72 can be hit, and the corresponding cache data can be cached.

[0086] In a further optional implementation, for the cache tag obtained during the current traversal, this embodiment can perform the address consistency comparison operation between the cache tag and each address structure in parallel, thereby improving the matching efficiency of the cache tag and thus improving the overall execution efficiency of the cache management command.

[0087] Figure 8 This is a schematic diagram of another matching process according to an embodiment of the present invention. Figure 8 As shown, assuming the cache management command includes address structures A1-A3, it can perform parallel comparisons of the high-order bits of the address information corresponding to the cache tag 'tag1' obtained during the current traversal with the address information of address structures A1-A3. For example... Figure 8 As shown, if the comparison result shows that the high bits of the cache tag 'tag1' and the address structure A1 are consistent, then the cache tag 'tag1' is determined to be a hit, and the corresponding cache data is cached accordingly.

[0088] Furthermore, taking a cache tag tag1 as an example, which is 64 bytes in size and has a value of 0x0001020304050607, and address structures A1-A3 as {Page Address=0x0001020304050000, Page Size=4KB}, {Page Address=0x00010203040abcde, Page Size=1GB}, and {Page Address=0x0001020304060123, PageSize=64KB}.

[0089] For the first address structure A1, the Page Size is 4KB. Based on this Page Size, the high-order bits of the Page Address of the cache tag tag1 and the address structure A1 are truncated, and the result is 0x0001020304050. Therefore, it can be determined that the cache tag tag1 hits the first address structure A1.

[0090] For the second address structure A2, the Page Size is 1GB. Based on this Page Size, the high-order bits of the Page Address of the cache tag tag1 and the address structure A2 are truncated, and the result is 0x00010203040. Therefore, it can be determined that the cache tag tag1 hits the second address structure A2.

[0091] For the third address structure A3, the Page Size is 64KB. Based on this Page Size, the result of truncating the high bits of the cache tag tag1 is 0x0x000102030405. However, the result of truncating the high bits of the Page Address of address structure A3 is 0x000102030406. The two truncated results are not the same. Therefore, it can be determined that the cache tag tag1 did not hit the third address structure A3.

[0092] Therefore, this embodiment does not need to determine the address bit of the physical page base address of the cache tag. It only needs to determine the high-order address comparison bit used for comparison through the address information in the address structure. Even if there is a possibility that the cache tag hits multiple address structures as in the example above, since this embodiment only needs to determine whether the cache tag hits to perform the corresponding cache data management operation, it does not need to know exactly which physical page base address it is completely consistent with. Thus, this embodiment can ensure the accuracy of the cache tag hit result while further reducing the amount of calculation in the search and matching process, improving the search and matching efficiency, and reducing the system power consumption through fuzzy matching.

[0093] In other alternative implementations, this embodiment may first determine the physical page base address corresponding to the cache tag, and then compare it with the address base address of each address structure to more accurately determine which address structure the cache tag hits. This embodiment does not limit the specific fuzzy matching method.

[0094] In another alternative implementation, this embodiment can also perform the traversal search and matching operations of each cache tag in the cache unit in parallel to further improve the search and matching efficiency.

[0095] Step S230: The cache tag that matches the address information of any address structure is determined as the target cache tag. In this embodiment, if the address information of any address structure matches the cache tag, the cache tag is determined to have hit the target cache tag. Further, if the address information of no address structure matches the cache tag, the cache tag is determined to have missed the target cache tag, and no corresponding data management operation is performed on the cache data corresponding to the cache tag.

[0096] Step S240 involves performing target data management operations on the cached data corresponding to the target cache tag. These target data management operations can be configured according to specific system requirements, such as corresponding cache data clearing operations. This embodiment does not limit the specific operations.

[0097] This invention embodiment receives a cache management command including at least one address structure with address information corresponding to a physical page, and traverses each cache tag in the cache unit to determine whether there is an address structure in each address structure that matches the address information of the corresponding cache tag. The cache tag that matches the address information of any address structure is determined as the target cache tag, and target data management operations are performed on the cache data corresponding to the target cache tag. Therefore, compared to... Figure 2 As shown in the comparative example, the manager module in this embodiment does not need to generate and issue corresponding search commands to the cache unit for each data block in the accessed physical page, greatly reducing the number of commands issued and thus avoiding excessive performance and power consumption overhead on the manager module. Furthermore, this embodiment uses cache tags in the cache unit as the search object, significantly reducing the number of searches, further reducing system load and power consumption, and improving system performance. Simultaneously, for data management operations at the physical page level, this embodiment can also use fuzzy matching for parallel matching, further reducing the computational load of search matching, improving matching efficiency, reducing system power consumption, and improving system performance.

[0098] Figure 9 This is a flowchart of another cache management method according to an embodiment of the present invention. This embodiment describes the method by sequentially traversing each cache group in a cache unit and sequentially traversing the cache tags within each cache group. It should be understood that the cache groups in a cache unit and the cache tags within each cache group can also be traversed in parallel. The specific traversal method can be set according to specific requirements and system performance. Figure 9 As shown, the cache management method of this invention includes the following steps:

[0099] Step S310: Receive a cache management command. The cache management command includes at least one address structure corresponding to the data to be managed. The address structure includes the address information of the corresponding physical page.

[0100] Step S320: Obtain the current cache group being traversed. In this embodiment, the cache tags in the cache unit are stored in the form of cache groups. Figure 1 Taking cache unit 11 as an example, after the search and matching process begins, cache group Set1 can be traversed first.

[0101] Step S330: Obtain the current cache tag in the current cache group. Taking the current cache group Set1 as an example, the tags can be selected based on the storage order of each cache tag in the cache group Set1. For example, the current cache tag obtained when starting to traverse the cache group Set1 is (PageA, 0).

[0102] Step S340: Parallel comparison of the current cache tag with the addresses of each address structure in the cache management command is performed. Taking the current cache tag as (PageA,0) as an example, the address consistency of the current cache tag (PageA,0) with the address information in each address structure is performed in parallel. Optionally, in the parallel matching of this embodiment, a fuzzy matching method can be selected based on the corresponding data management operation (e.g., data management operation based on physical pages). The specific comparison process can be found in [reference needed]. Figures 4-8 The illustrated embodiments will not be described in detail here. In other optional implementations, if the current data management command is not a data management operation based on physical pages, a precise matching process is required. This involves matching each address bit of the address information of the current cache tag (PageA,0) with the address bits of the address information in the address structure one by one to locate the specific data location and perform the corresponding data management operation.

[0103] Step S350: Determine if a match is found. If one or more address structures in the cache management command match the address information of the current cache tag, then the current cache tag is determined to be a match, and step S360 is executed. If no address structure in the cache management command matches the address information of the current cache tag, then the current cache tag is determined to be a miss, and step S370 is executed.

[0104] In step S360, in response to the current match, the corresponding data management operation is executed, that is, the corresponding data management operation is performed on the cache data corresponding to the matched cache tag in the cache, such as deleting the cache data or reading the cache data. After executing the data management operation corresponding to the currently matched cache tag, step S370 continues.

[0105] Step S370: Determine if the current cache group has been completely traversed. That is, after a no-match or a match has been found and the corresponding data management operation has been performed, determine if the current cache group has been completely traversed. If the current cache group has not been completely traversed, continue with step S330, which means continuing to traverse the current cache group to obtain the next current cache tag. For example, if the current cache tag is (PageA, 0), after performing the search matching operation, if it is determined that the corresponding current cache group Set1 has not been completely traversed, then continue to traverse the current cache group Set1 to obtain the next current cache tag (PageB, 3), repeating steps S340-S370 until cache group Set1 is completely traversed, that is, the search matching operation for cache tag (PageB, 3) is completed. Further, if the current cache group has been completely traversed, continue with step S380.

[0106] Step S380: Determine if all cache groups have been traversed. After all cache tags in the current cache group have completed the corresponding search and matching, determine if there are any untraversed cache groups in the cache unit. If there are still untraversed cache groups, continue executing steps S320-S370 to sequentially traverse the search and matching operation of each cache tag in the cache group until all cache groups in the cache unit have been traversed. If there are no untraversed cache groups, proceed to step S390.

[0107] Step S390: After traversing all cache groups in the cache unit, determine that the current search and matching process is complete. Furthermore, the corresponding operation results can be fed back, such as feedback that the corresponding cached data has been deleted, or feedback on the cached data read.

[0108] by Figure 1 Taking cache unit 11 and main memory 12 as examples, and accessing Page A and Page B in main memory 12, since the administrator module does not know which data blocks in the two physical pages Page A and Page B are already cached in cache unit 11, it can only completely edit all logical tags in Page A and Page B, and send these logical tags as search commands to cache unit 11 for precise matching. Only when the cached tags already cached in cache unit 11 are exactly the same as the logical tags will the corresponding management operation be performed. It can be seen that this access will generate a total of 12 search commands to cache unit 11, of which only 3 commands can generate effective management operations, and 9 commands become invalid commands because they cannot be matched. These invalid commands will waste the bandwidth and power consumption of cache unit 11.

[0109] In this embodiment, the physical pages requiring cache management can be sent to the cache unit via a cache management command. Compared to existing technologies, the manager module does not generate invalid commands that cannot be hit, thus avoiding waste of the cache unit's bandwidth and power consumption. Furthermore, in this embodiment, the manager module only needs to send data management commands and does not need to control the traversal process, reducing the time the cache management process occupies in the manager module and further improving system performance.

[0110] This embodiment of the invention receives a cache management command that includes at least one address structure with address information corresponding to a physical page, and traverses each cache tag in the cache unit to determine whether there is an address structure in each address structure that matches the address information of the corresponding cache tag. The cache tag that matches the address information of any address structure is identified as the target cache tag, and target data management operations are performed on the cache data corresponding to the target cache tag. Therefore, this embodiment can traverse and search the cache unit for cache tag hits by issuing cache management commands, resulting in a relatively low number of searches. It also reduces the number of commands issued by the manager module, lowers system load and power consumption, and improves system performance.

[0111] Figure 10 This is a schematic diagram of the circuit structure of the cache unit according to an embodiment of the present invention. Figure 10 As shown, the circuit structure 100 of the cache unit in this embodiment of the invention includes a tag storage module 101, a search engine 102, a first matching module 103, and a data execution module 104.

[0112] The Manager module 10 parses and processes the data access request, generates a cache management command cmd1, and sends the cache management command cmd1 to the circuit structure 100 of the cache unit through the Cache Interface 20. The cache management command includes at least one address structure corresponding to the data to be managed, and the address structure includes the address information of the corresponding physical page. The address information in the address structure can be referred to the description in the above embodiment, and will not be repeated here.

[0113] The tag storage module 101 is configured to store cache tags. The cache tag is a unique identifier for the cached data stored in the cache unit.

[0114] The search engine 102 is configured to receive the cache management command cmd1 and read the corresponding cached tags from the tag storage module 101. Further optionally, the search engine 102 can be based on... Figure 9 The traversal method shown refers to sequentially traversing each cache group in the cache unit and sequentially traversing the cache tags within each cache group to read the corresponding cache tags from the tag storage module 101. In other optional implementations, the search engine 102 can also traverse the cache groups in the cache unit and the cache tags within the cache groups in parallel. The method by which the search engine 102 obtains cache tags from the tag storage module 101 in this embodiment can be set based on actual application conditions (e.g., performance, power consumption requirements, hardware configuration, etc.), and this embodiment does not impose any limitations on this.

[0115] The first matching module 103 is configured to receive the currently read cache tags and address structures carried by the cache management command cmd1 sent by the search engine 102, and to perform address consistency comparison between the currently read cache tags and each address structure. If the currently read cache tag matches the address information in any of the address structures, the cache tag is determined as the target cache tag. Further, the first matching module 103 is further configured to perform the address consistency comparison operation between the currently read cache tags and each address structure in parallel. Optionally, the address information in the address structure includes the corresponding physical page address and the corresponding physical page size. The first matching module 103 is further configured to determine the address comparison bit between the address structure and the currently read cache tag based on the physical page size in the address structure. If the value of the address comparison bit matches the value of the address comparison bit, the currently traversed cache tag is determined to match the address information in the address structure. The address comparison bit represents the data bit storing the base address of the corresponding physical page, and the length of the base address of the corresponding physical page is determined based on the physical page size in the corresponding address structure.

[0116] The specific matching process of the first matching module 103 in this embodiment, which performs parallel fuzzy matching between the currently read cache tag and each address structure, is similar to that in the above embodiments and will not be repeated here. Specifically, if the currently read cache tag matches the address information in any address structure, it is determined that the cache tag has been matched; that is, the cache data corresponding to the cache tag needs to undergo corresponding data management operations, and it is sent as the target cache tag to the data execution module 104. The data execution module 104 is configured to perform target management operations on the cache data corresponding to the target cache tag received from the matching module.

[0117] This invention embodiment receives a cache management command including at least one address structure with address information corresponding to a physical page, and traverses each cache tag in the cache unit to determine whether there is an address structure in each address structure that matches the address information of the corresponding cache tag. The cache tag that matches the address information of any address structure is determined as the target cache tag, and target data management operations are performed on the cache data corresponding to the target cache tag. In this embodiment, the physical pages that need cache management can be sent to the cache unit through a cache management command, relative to... Figure 2As shown in the comparative example, the manager module does not generate invalid commands that cannot be matched, thus avoiding waste of bandwidth and power consumption in the cache unit. Furthermore, in this embodiment, the manager module only needs to issue data management commands and does not need to control the traversal process, reducing the time spent by the manager module on cache management and further improving system performance. Furthermore, this embodiment uses cache tags in the cache unit as the search object, greatly reducing the number of searches, further reducing system load and power consumption, and improving system performance. Simultaneously, for data management operations at the physical page level, this embodiment can also use fuzzy matching for parallel matching, further reducing the computational load of search matching, improving matching efficiency, reducing system power consumption, and improving system performance.

[0118] In an optional implementation, the tag storage module 101 is further configured to receive a cache access command cmd2, which includes the data address of the data to be accessed. The data address includes the physical page base address and the corresponding offset address. It should be understood that if the administrator module 10 parses the corresponding data access request and determines that the search matching mode of the search engine 102 and the first matching module 103 cannot be used to perform the corresponding cache data management operation (e.g., a cache data management operation accurate to the corresponding data block is required), the administrator module 10 generates the corresponding cache access command cmd2 based on the accessed data block and sends it to the tag storage module 101.

[0119] Furthermore, the circuit structure 100 of the cache unit also includes a second matching module 105. The second matching module 105 is configured to receive the data address of the data to be accessed from the tag storage module 101, and perform an address consistency comparison between the cache tag read from the tag storage module 101 and the data address of the data to be accessed. In response to the read cache tag matching the data address of the data to be accessed, it determines that the cache access command cmd2 hits the cache, and sends the hit result to the data execution module 104. The data execution module 104 is further configured to perform the corresponding data access operation based on the hit result. It should be understood that the search and matching process of the cache access command cmd2 is basically the same as the process in the comparative example above, and will not be described again in this embodiment.

[0120] Therefore, the circuit structure 100 of the cache unit in this embodiment provides search and matching hardware for handling data management commands in different situations. While ensuring the accuracy of command execution by the cache unit, it also improves the execution accuracy by adding a search engine and a first matching module 103. Figures 4-9 The various implementation methods shown reduce the number of commands issued by the management module, thereby reducing system load and power consumption and improving system performance.

[0121] In other alternative implementations, in the circuit structure design of the cache unit in this embodiment, the first matching module 103 and the second matching module 105 can also be integrated together, and the search engine 102, the first matching module 103 and the second matching module 105 can also be integrated together. That is, this embodiment does not limit the specific design of the hardware circuit of the cache unit's circuit structure, as long as it can achieve the above functions.

[0122] Figure 11 This is a schematic diagram of a cache unit according to an embodiment of the present invention. Figure 11 As shown, the cache unit 11 of this embodiment includes a cache space 111 and a circuit structure 112. The cache space 111 is configured to store cached data. The circuit structure 112 of the cache unit is used to receive a cache management command including at least one address structure with address information corresponding to a physical page, and to traverse each cache tag in the cache unit to determine whether there is an address structure in each address structure that matches the address information of the corresponding cache tag. The cache tag matching the address information of any address structure is determined as the target cache tag, and target data management operations are performed on the cache data corresponding to the target cache tag. Therefore, this embodiment can traverse and search the cache unit for cache tags by issuing cache management commands, resulting in a relatively low number of searches. It also reduces the number of commands issued by the manager module, lowers system load and power consumption, and improves system performance. It should be understood that the specific structure and data processing process of the circuit structure 112 of the cache unit can be referred to the above embodiment, and will not be repeated here.

[0123] Figure 12 This is a schematic diagram of a cache management system according to an embodiment of the present invention. Figure 12 As shown, the cache management system 12 of this embodiment includes a manager module 121 and a cache unit circuit structure 122. The manager module 121 is configured to receive and parse data access requests, generate the aforementioned cache management command cmd1 or cache access command cmd2, and send the cache management command cmd1 or cache access command cmd2 to the cache unit circuit structure 122 for processing.

[0124] The circuit structure 122 of the cache unit is used to receive a cache management command including at least one address structure with address information corresponding to a physical page, and to traverse each cache tag in the cache unit to determine whether there is an address structure in each address structure that matches the address information of the corresponding cache tag. The cache tag that matches the address information of any address structure is determined as the target cache tag, and target data management operations are performed on the cache data corresponding to the target cache tag. Further, the circuit structure 122 of the cache unit is also used to receive a cache access command including the address information of the physical page to be accessed, and to perform an address consistency comparison between the read cache tag and the address information of the physical page to be accessed. In response to the read cache tag matching the address information of the physical page to be accessed, it is determined that the cache access command has hit the cache, and corresponding data management operations are performed on the hit cache data.

[0125] It should be understood that the parsing process of the cache management command cmd1 or cache access command cmd2 generated by the manager module 121, as well as the specific structure and data processing process of the circuit structure 122 of the cache unit, can be referred to the above embodiments, and will not be repeated here.

[0126] The cache management system of this invention receives a cache management command that includes at least one address structure with address information corresponding to a physical page, and traverses each cache tag in the cache unit to determine whether there is an address structure in each address structure that matches the address information of the corresponding cache tag. The cache tag that matches the address information of any address structure is determined as the target cache tag, and target data management operations are performed on the cache data corresponding to the target cache tag. In this embodiment, the physical pages that need cache management can be sent to the cache unit through a cache management command, relative to... Figure 2 As shown in the comparative example, the manager module does not generate invalid commands that cannot be matched, thus avoiding waste of bandwidth and power consumption in the cache unit. Furthermore, in this embodiment, the manager module only needs to issue data management commands and does not need to control the traversal process, reducing the time spent by the manager module on cache management and further improving system performance. Furthermore, this embodiment uses cache tags in the cache unit as the search object, greatly reducing the number of searches, further reducing system load and power consumption, and improving system performance. Simultaneously, for data management operations at the physical page level, this embodiment can also use fuzzy matching for parallel matching, further reducing the computational load of search matching, improving matching efficiency, reducing system power consumption, and improving system performance.

[0127] Meanwhile, the cache management system in this embodiment provides search and matching hardware for handling data management commands in different situations. While ensuring the accuracy of command execution by the cache unit, it also executes commands through a newly added search engine and the first matching module 103. Figures 4-9 The various implementation methods shown reduce the number of commands issued by the management module, thereby reducing system load and power consumption and improving system performance.

[0128] Figure 13 This is a schematic diagram of a cache data management device according to an embodiment of the present invention. Figure 13 As shown, the cache data management device 13 of this embodiment includes a command receiving unit 131, a traversal unit 132, a determination unit 133, and an execution unit 134.

[0129] Command receiving unit 131 is configured to receive cache management commands, the cache management commands including at least one address structure corresponding to the data to be managed, the address structure including the address information of the corresponding physical page. Traversal unit 132 is configured to traverse each cache tag in the cache unit to determine whether there is an address structure in each address structure that matches the address information of the corresponding cache tag. Determination unit 133 is configured to determine the cache tag that matches the address information of any address structure as the target cache tag. Execution unit 134 is configured to perform target data management operations on the cache data corresponding to the target cache tag.

[0130] This embodiment of the invention receives a cache management command that includes at least one address structure with address information corresponding to a physical page, and traverses each cache tag in the cache unit to determine whether there is an address structure in each address structure that matches the address information of the corresponding cache tag. The cache tag that matches the address information of any address structure is identified as the target cache tag, and target data management operations are performed on the cache data corresponding to the target cache tag. Therefore, this embodiment can traverse and search the cache unit for cache tag hits by issuing cache management commands, resulting in a relatively low number of searches. It also reduces the number of commands issued by the manager module, lowers system load and power consumption, and improves system performance.

[0131] Figure 14 This is a schematic diagram of an electronic device according to an embodiment of the present invention. (For example...) Figure 14As shown, the electronic device 14 in this embodiment includes a cache unit 141, a manager module 142, and main memory 143. The cache unit 141 is used to receive cache management commands from address structures containing address information of at least one corresponding physical page, and to traverse each cache tag in the cache unit to determine whether there exists an address structure in each address structure that matches the address information of the corresponding cache tag. The cache tag matching the address information of any address structure is identified as the target cache tag, and target data management operations are performed on the cache data corresponding to the target cache tag. The manager module 142 is configured to receive and parse data access requests, generate cache management commands or cache access commands, and send the cache management commands or cache access commands to the cache unit for processing. The main memory 143 is used to store data. Further, the main memory 143 includes multiple physical pages, and each physical page includes multiple data blocks, as detailed in the following reference. Figure 1 The diagram shown is shown in the image.

[0132] It should be understood that the parsing process of the manager module 142 generating cache management commands or cache access commands, as well as the specific structure and data processing process of the cache unit 141, can be referred to the above embodiments, and will not be repeated here.

[0133] Furthermore, the manager module 142 in this embodiment is implemented through an operating system and a corresponding processor (e.g., a CPU or other processor). Main memory 143, as a non-volatile computer-readable storage medium, can be used to store accessed data, as well as non-volatile software programs, non-volatile computer-executable programs, and modules. It should be understood that non-volatile software programs, non-volatile computer-executable programs, and modules can also be implemented using other non-volatile memories, and this embodiment does not limit this.

[0134] Main memory 143 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store an option list, etc. Furthermore, main memory 143 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, main memory 143 may optionally include memory remotely configured relative to the manager module 142 and cache unit 141, and these remote memories may be connected to external devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0135] The above-mentioned products can perform the methods provided in the embodiments of this application, and have the corresponding functional modules and beneficial effects of performing the methods. For technical details not described in detail in this embodiment, please refer to the methods provided in the embodiments of this application.

[0136] The cache management system of this invention receives a cache management command that includes at least one address structure with address information corresponding to a physical page, and traverses each cache tag in the cache unit to determine whether there is an address structure in each address structure that matches the address information of the corresponding cache tag. The cache tag that matches the address information of any address structure is determined as the target cache tag, and target data management operations are performed on the cache data corresponding to the target cache tag. In this embodiment, the physical pages that need cache management can be sent to the cache unit through a cache management command, relative to... Figure 2 As shown in the comparative example, the manager module does not generate invalid commands that cannot be matched, thus avoiding waste of bandwidth and power consumption in the cache unit. Furthermore, in this embodiment, the manager module only needs to issue data management commands and does not need to control the traversal process, reducing the time spent by the manager module on cache management and further improving system performance. Furthermore, this embodiment uses cache tags in the cache unit as the search object, greatly reducing the number of searches, further reducing system load and power consumption, and improving system performance. Simultaneously, for data management operations at the physical page level, this embodiment can also use fuzzy matching for parallel matching, further reducing the computational load of search matching, improving matching efficiency, reducing system power consumption, and improving system performance.

[0137] Meanwhile, the cache management system in this embodiment provides search and matching hardware for handling data management commands in different situations. While ensuring the accuracy of command execution by the cache unit, it also executes commands through a newly added search engine and the first matching module 103. Figures 4-9 The various implementation methods shown reduce the number of commands issued by the management module, thereby reducing system load and power consumption and improving system performance.

[0138] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program for use by a computer to execute some or all of the above-described method embodiments.

[0139] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0140] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A cache management method, characterized in that, The method includes: Receive a cache management command, wherein the cache management command includes at least one address structure corresponding to the data to be managed, and the address structure includes the address information of the corresponding physical page; Traverse each cache tag in the cache unit to determine whether there is an address structure in each address structure that is consistent with the address information of the corresponding cache tag. When the address structure is consistent with the physical page base address of the cache tag, it is determined that the address structure is consistent with the address information of the cache tag. The cache tag that matches the address information of any of the address structures is determined as the target cache tag; Perform target data management operations on the cached data corresponding to the target cache tag.

2. The method according to claim 1, characterized in that, The step of traversing each cache tag in the cache unit to determine whether there is an address structure in each address structure that matches the address information of the corresponding cache tag includes: Determine the cached tag being traversed; The cache tag being traversed is compared with the address consistency of each address structure in parallel to determine whether there is an address structure in each address structure that is consistent with the address information of the cache tag being traversed.

3. The method according to claim 1, characterized in that, The address information in the address structure includes the corresponding physical page address and the corresponding physical page size.

4. The method according to claim 3, characterized in that, The consistency comparison steps between the currently traversed cache tags and their corresponding address structures include: The address comparison bits between the address structure and the currently traversed cache tag are determined based on the physical page size in the address structure; In response to the fact that the address comparison bit value of the address structure matches that of the currently traversed cache tag, it is determined that the address information of the currently traversed cache tag is consistent with that of the address structure.

5. The method according to claim 4, characterized in that, The step of determining the address comparison bits between the address structure and the currently traversed cache tag based on the physical page size in the address structure includes: The base address length of the physical page corresponding to the address structure is determined based on the physical page size in the address structure; Based on the base address length, the corresponding address comparison bit is extracted from the address structure and the address information of the currently traversed cache tag.

6. A circuit structure for a cache unit, characterized in that, The circuit structure of the cache unit includes: The tag storage module is configured to store cache tags, wherein the cache tag is a unique identifier for the cached data stored in the cache unit; The search engine is configured to receive cache management commands and read corresponding cache tags from the tag storage module. The cache management commands include at least one address structure corresponding to the data to be managed, and the address structure includes the address information of the corresponding physical page. The first matching module is configured to receive the currently read cache tag sent by the search engine and each of the address structures carried by the cache management command, and to perform address consistency comparison between the currently read cache tag and each of the address structures. In response to the current read cache tag being consistent with the address information in any of the address structures, the cache tag is determined as the target cache tag. Specifically, when the physical page base address of the address structure is consistent with the physical page base address of the cache tag, the address information of the address structure is determined to be consistent with the address information of the cache tag. The data execution module is configured to perform target management operations on cached data corresponding to target cache tags received from the matching module.

7. The circuit structure of the cache unit according to claim 6, characterized in that, The first matching module is further configured to perform parallel operations to compare the address consistency of the currently read cache tag with each of the address structures.

8. The circuit structure of the cache unit according to claim 6, characterized in that, The address information in the address structure includes the corresponding physical page address and the corresponding physical page size; The first matching module is further configured to determine the address comparison bit between the address structure and the currently read cache tag based on the physical page size in the address structure. In response to the value of the address comparison bit between the address structure and the currently read cache tag being consistent, it is determined that the currently traversed cache tag is consistent with the address information in the address structure. The address comparison bit represents the data bit storing the base address of the corresponding physical page, and the length of the base address of the corresponding physical page is determined based on the physical page size in the corresponding address structure.

9. The circuit structure of the cache unit according to claim 6, characterized in that, The tag storage module is also configured to receive cache access commands, the cache access commands including the data address of the data to be accessed, and the circuit structure of the cache unit further includes: The second matching module is configured to receive the data address of the data to be accessed from the tag storage module, and perform an address consistency comparison between the cache tag read from the tag storage module and the data address of the data to be accessed. In response to the read cache tag matching the data address of the data to be accessed, the module determines that the cache access command hits the cache and sends the hit result to the data execution module. The data execution module is further configured to perform corresponding data access operations based on the hit result.

10. A cache management system, characterized in that, The cache management system includes: The circuit structure of the cache unit as described in any one of claims 6-9; The manager module is configured to receive and parse data access requests, generate cache management commands or cache access commands, and send the cache management commands or cache access commands to the circuit structure of the cache unit for processing.

11. A cache unit, characterized in that, The cache unit includes: The cache space is configured to store cached data. The circuit structure of the cache unit as described in any one of claims 6-9.

12. An electronic device, characterized in that, The electronic device includes: The cache unit as described in claim 11; The manager module is configured to receive and parse data access requests, generate cache management commands or cache access commands, and send the cache management commands or cache access commands to the cache unit for processing. Main memory is used to store data.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or data, which, when executed by a processor, implements the method as described in any one of claims 1-5.

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