FPGA test method and device, medium and terminal

Abstract

The invention provides an FPGA test method and device, a medium and a terminal. The method comprises the following steps: periodically checking a magic head in a data register until the checking is passed; checking a copy bit in the state register until the copy bit indicates that data can be copied; carrying the data in the data register to a cache, and configuring the copy bit to be incapable of data copy; checking the data length in the cache until the data length is equal to the data mirror image header length; if the mirror image header signature is correct, transferring the carrying data to a buffer area address; and checking an execution flag in the state register until the execution flag indicates that execution can be started, and executing the executable firmware data transported in the RAM according to the FPGA. According to the FPGA testing method, the testing range of the FPGA can be expanded, so that the number of times of FPGA version manufacturing is reduced, and the iteration speed of a chip verification link is increased.

Description

Technical Field

[0001] The present disclosure belongs to the field of FPGA testing, and relates to an FPGA testing method, in particular to an FPGA testing method, device, medium, and terminal. Background Art

[0002] When a specific firmware is incorporated during FPGA design and runs directly on the hardware, it can simplify subsequent configuration and inspection of test parameters. After the traditional FPGA version is produced, the built-in logic usually cannot be modified. The production of an FPGA version is a process involving multiple steps and tools, which takes at least several hours and at most half a day. In traditional FPGA design, the configuration test value can only be configured once and cannot be dynamically changed to meet the performance requirements in some special scenarios. Therefore, the current FPGA testing method has the problem of a small FPGA testing range. Summary of the Invention

[0003] The purpose of the present disclosure is to provide an FPGA testing method, device, medium, and terminal, which are used to solve the problem of a small FPGA testing range existing in the FPGA testing method.

[0004] In a first aspect, an embodiment of the present disclosure provides an FPGA testing method, including: a receiving end periodically checks a magic header in a data register until the check passes; the receiving end checks a copy bit in a status register until the copy bit indicates that data can be copied; the receiving end moves the data in the data register to a buffer, and configures the copy bit as unable to copy data after the data in the data register is moved to the buffer; the receiving end checks the data length in the buffer until the data length is equal to the data mirror header length; if the mirror header signature is correct, the receiving end places the moved data at the buffer address, otherwise the receiving end configures an error bit in the status register as an error; the receiving end checks an execution flag in the status register until the execution flag indicates that execution can start, and executes the executable firmware data moved in the FPGA execution RAM, and the moved data is the moved executable firmware data.

[0005] Through the interaction between the data register and the status register and the receiving end, the testing range of the FPGA can be extended according to the data in the data register, thereby reducing the number of FPGA version productions and accelerating the iteration speed of the chip verification link.

[0006] In an embodiment of the present disclosure, the method for the receiving end to periodically check the magic header in the data register until the check passes includes: the receiving end periodically checks the data register to obtain check data; the receiving end judges the check data and the first magic header to obtain a judgment result, where the judgment result is that the check data is equal to the first magic header or the check data is not equal to the first magic header; if the judgment result is that the check data is equal to the first magic header, it means that the check passes and the value in the data register is set to the second magic header, otherwise it means that the check fails and the data register continues to be checked.

[0007] In an embodiment of the present disclosure, the FPGA testing method further includes: the receiving end checks the parity bit in the status register until the parity bit indicates the start of verification; the receiving end calculates the data in the buffer to obtain a first checksum; the receiving end compares the first checksum with the data in the checksum register to obtain a comparison result; when the comparison result is that the checksum is not the same as the data in the checksum register, the receiving end configures the error bit in the status register as an error.

[0008] In an embodiment of the present disclosure, if the mirror header signature is correct, the method for the receiving end to place the transfer data at a new buffer address, otherwise the receiving end configures the error bit in the status register as an error includes: the receiving end parses the mirror in the buffer to obtain the mirror header signature; the receiving end judges the mirror header signature to obtain a judgment result; if the judgment result is that the mirror header signature is correct, the receiving end updates the buffer address according to the mirror header to obtain the buffer address, and the receiving end places the transfer data at the buffer address; otherwise the receiving end configures the error bit in the status register as an error.

[0009] In an embodiment of the present disclosure, the FPGA testing method further includes: the sending end writes the first magic header into the data register; the sending end checks the data register until the value in the data register is equal to the second magic header; the sending end checks the copy bit in the status register until the copy bit indicates that data can be written; the sending end writes data into the data register; the sending end updates the data in the status register; if the transmission file is transmitted completely, the sending end configures the execution flag in the status register as able to start execution, otherwise the sending end checks the error bit in the status register until the error bit is an error to stop transmitting data.

[0010] In one embodiment of the present disclosure, the implementation method for the sending end to update the data in the status register includes: the sending end checks the parity bit in the status register until the parity bit indicates the start of verification; the sending end calculates the written data to obtain a second check code; the sending end writes the second check code into the check register; the sending end configures the copy bit in the status register to enable data copying.

[0011] In one embodiment of the present disclosure, the value in the data register may include a cycle node value and a frame gap configuration value associated with the cycle node value.

[0012] In a second aspect, the present disclosure provides an FPGA test device, including: a magic number check module for periodically checking the magic header in the data register until the check passes; a status check module for checking the copy bit in the status register until the copy bit indicates that data copying is possible; a data transfer module for transferring the data in the data register to the cache and configuring the copy bit to be unable to copy data; a cache check module for checking the data length in the cache until the data length is equal to the data mirror header length; a mirror check module for, if the mirror header signature is correct, placing the transferred data at the buffer address, otherwise configuring the error bit in the status register as an error; a data execution module for checking the execution flag in the status register until the execution flag indicates that execution can start, and executing the executable firmware data transferred in the FPGA execution RAM according to the transferred data, where the transferred data is the transferred executable firmware data.

[0013] In a third aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, it implements the FPGA test method according to any one of the first aspects.

[0014] In a fourth aspect, the present disclosure provides an electronic terminal, including a memory, a processor, and a computer program stored on the memory, and the processor executes the computer program to implement the FPGA test method according to any one of the first aspects.

[0015] As described above, the FPGA test method, device, medium, and terminal of the present application have the following beneficial effects: through the interaction between the data register and the status register and the receiving end, the test scope of the FPGA can be extended according to the data in the data register, thereby reducing the number of FPGA version productions and accelerating the iteration speed of the chip verification link. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It shows a schematic structural diagram of the FPGA test system according to an embodiment of the present disclosure.

[0017] Figure 2 It shows a flowchart of the FPGA testing method according to an embodiment of the present disclosure.

[0018] Figure 3 It shows a flowchart of the implementation method for the receiving end to periodically check the phantom header in the data register until the check passes according to an embodiment of the present disclosure.

[0019] Figure 4 It shows a flowchart of the FPGA testing method according to an embodiment of the present disclosure.

[0020] Figure 5 It shows a flowchart of the implementation method for the receiving end to place the transferred data at the buffer address if the mirror header signature is correct, otherwise configure the error bit in the status register as an error according to an embodiment of the present disclosure.

[0021] Figure 6 It shows a flowchart of the FPGA testing method according to an embodiment of the present disclosure.

[0022] Figure 7 It shows a flowchart of the implementation method for the sending end to update the copy bit according to an embodiment of the present disclosure.

[0023] Figure 8 It shows a flowchart of the sending end of the FPGA testing method according to an embodiment of the present disclosure.

[0024] Figure 9 It shows a flowchart of the receiving end of the FPGA testing method according to an embodiment of the present disclosure.

[0025] Figure 10 It shows a schematic structural diagram of an FPGA testing device according to an embodiment of the present disclosure.

[0026] Figure 11 It shows a schematic block diagram of an electronic terminal according to an embodiment of the present disclosure. Detailed implementation manners

[0027] The following uses specific specific examples to illustrate the implementation manners of the present disclosure. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. The present disclosure can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0028] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present disclosure schematically. Therefore, only the components related to the present disclosure are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0029] The following will describe in detail the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure.

[0030] Figure 1 It is a schematic structural diagram showing the FPGA test system in the embodiments of the present disclosure. The FPGA test system includes the FPGA to be tested and external devices. The external devices include a sending end, and the firmware in the ROM of the FPGA to be tested includes a receiving end. The sending end can interact with the firmware inside the FPGA through an MDIO (Management Data Input / Output). The MDIO interface can be flexibly designed according to actual situations, and this will not be elaborated in this embodiment.

[0031] The following will elaborate in detail the principles and implementation manners of the FPGA test method and the FPGA test device in the embodiments of the present disclosure, so that those skilled in the art can understand the FPGA test method and the FPGA test device in the embodiments of the present disclosure without creative labor.

[0032] Figure 2 It is a flowchart showing the FPGA test method in the embodiments of the present disclosure. As Figure 2 shown, this embodiment provides an FPGA test method, and the FPGA test method includes:

[0033] S11, the receiving end periodically checks the magic header in the data register until the check passes.

[0034] Optionally, when the value of the magic header is equal to a specific value, the check passes; otherwise, the check fails. When the check fails, the receiving end will continue to periodically check the magic header in the data register. The magic header is the magicheader, and can also be called the magic head.

[0035] Optionally, the magic header in the data register can include a first magic header and a second magic header. The receiving end periodically checking the magic header in the data register can refer to the receiving end periodically checking the value of the first magic header in the data register.

[0036] S12, the receiving end checks the copy bit in the status register until the copy bit indicates that data replication is possible.

[0037] Optionally, when the copy bit is 1, it can indicate that data copying is possible. The data copying can refer to retrieving data from a data register. When the copy bit is 0, it can indicate that data copying is not possible. The initial value of the copy bit can be 0. When the copy bit is 0, the FPGA testing method is in a paused state. The FPGA testing method being in a paused state can mean that the program running the FPGA testing method is in a waiting state.

[0038] S13. The receiving end transfers the data in the data register to the cache, and after the data in the data register is transferred to the cache, configures the copy bit to indicate that data copying is not possible.

[0039] Optionally, the receiving end transferring the data in the data register to the cache can refer to moving the data in the register to the cache. Configuring the copy bit to indicate that data copying is not possible means configuring the copy bit in the status register to 0.

[0040] Optionally, the data in the data register can refer to the data of the transmission file.

[0041] S14. The receiving end checks the length of the data in the cache until the data length is equal to the data mirror header length.

[0042] Optionally, data mirroring refers to the entire file data transmitted through the MDIO interface. At the very front of this file, there are several bytes as the mirror header, which records information about the entire file, such as signature (to judge whether it is legal), length, load address, and run address, etc.

[0043] Optionally, when the receiving end checks the length of the data in the cache and the data length is not equal to the data mirror header length, it continues to check whether the copy bit in the status register is 1.

[0044] S15. If the mirror header signature is correct, the receiving end places the transferred data at the buffer address. Otherwise, the receiving end configures the error bit in the status register to indicate an error.

[0045] Optionally, the buffer address is the buffer address updated according to the content in the data mirror header. The mirror header can have the buffer address, and the buffer is located in the RAM.

[0046] Optionally, the err bit can be marked as 1 to indicate an error, and the err bit can be 0 to indicate correctness. When the err bit indicates an error, this transmission ends. The initial value of the err bit can be 0.

[0047] S16. The receiving end checks the execution flag in the status register until the execution flag indicates that execution can start, and executes the executable firmware data transferred in the FPGA execution RAM according to the transferred data, where the transferred data is the transferred executable firmware data.

[0048] Optionally, the execution flag can be an execution bit, that is, an execution bit. When the execution flag is 1, it can indicate that execution can start, and when the execution flag is not 1, it indicates that execution cannot start. During the process of checking the execution flag in the status register at the receiving end, when the execution flag indicates that execution cannot start, the receiving end checks the copy bit in the status register, and when the copy bit indicates that data copying is possible, the data in the data register is transferred to the cache.

[0049] Optionally, when the execution flag is 1, that is, the executable firmware data transferred in the FPGA execution RAM can be executed according to the FPGA. Executing the executable firmware data transferred in the FPGA execution RAM according to the FPGA refers to the process of testing the FPGA according to the executable firmware, and this method can expand the test scope of the FPGA.

[0050] According to the above description, the FPGA testing method includes: the receiving end periodically checks the magic header in the data register until the check passes; the receiving end checks the copy bit in the status register until the copy bit indicates that data copying is possible; the receiving end transfers the data in the data register to the cache and configures the copy bit as not being able to copy data; the receiving end checks the data length in the cache until the data length is equal to the data mirror header length; if the mirror header signature is correct, the receiving end places the transferred data at the buffer address, otherwise the receiving end configures the error bit in the status register as an error; the receiving end checks the execution flag in the status register until the execution flag indicates that execution can start, and executes the executable firmware data transferred in the FPGA execution RAM according to the FPGA, where the transferred data is the transferred executable firmware data.

[0051] Through the interaction between the data register and the status register and the receiving end, the test scope of the FPGA can be expanded, thereby reducing the number of FPGA version productions and accelerating the iteration speed of the chip verification link.

[0052] Figure 3 It is a flowchart showing the implementation method of the receiving end in the embodiment of the present disclosure for periodically checking the magic header in the data register until the check passes. As Figure 3 shown, the embodiment of the present disclosure provides an implementation method for the receiving end to periodically check the magic header in the data register until the check passes, including:

[0053] S21, The receiving end periodically checks the data register to obtain check data.

[0054] Optionally, the check data may refer to the data in the data register.

[0055] S22, The receiving end determines the check data and the first magic header to obtain a judgment result, where the judgment result is that the check data is equal to the first magic header or the check data is not equal to the first magic header.

[0056] S23, If the judgment result is that the check data is equal to the first magic header, it means the check passes and the value in the data register is set to the second magic header; otherwise, it means the check fails and the data register is continuously checked.

[0057] Optionally, the first magic header and the second magic header may be two different magic header values.

[0058] Figure 4 is a flowchart showing the FPGA test method according to an embodiment of the present disclosure. As Figure 4 shown, an embodiment of the present disclosure provides an FPGA test method, including:

[0059] S31, The receiving end checks the parity bit in the status register until the parity bit indicates the start of verification.

[0060] Optionally, when the parity bit (check bit) is 1, it may indicate the start of verification, and when the parity bit is 0, it may indicate the non - start of verification. The initial value of the parity bit may be 1.

[0061] S32, The receiving end calculates the data in the cache to obtain a first checksum.

[0062] Optionally, the process of calculating the checksum for the data in the cache can be implemented through relevant checksum calculation algorithms, which will not be elaborated in this embodiment.

[0063] S33, The receiving end compares the first checksum with the data in the checksum register to obtain a comparison result.

[0064] Optionally, the comparison result is that the first checksum is equal to the data in the checksum register or the first checksum is not equal to the data in the checksum register.

[0065] S34, When the comparison result is that the first checksum is not equal to the data in the checksum register, the receiving end configures the error bit in the status register as an error.

[0066] Optionally, when the comparison result indicates that the check code is not equal to the data in the check register, it indicates a check exception; when the comparison result indicates that the check code is equal to the data in the check register, it indicates a normal check.

[0067] Figure 5 FIG. is a flowchart showing an implementation method of an embodiment of the present disclosure. If the mirror header signature is correct, the receiving end places the transferred data at the buffer address; otherwise, the receiving end configures the error bit in the status register as an error. As Figure 5 shown, an embodiment of the present disclosure provides an implementation method. If the mirror header signature is correct, the receiving end places the transferred data at the buffer address; otherwise, the receiving end configures the error bit in the status register as an error, including:

[0068] S41, the receiving end parses the mirror in the cache to obtain the mirror header signature.

[0069] Optionally, the implementation method of parsing the mirror in the cache to obtain the mirror header signature includes: extracting the mirror header signature from the mirror in the cache. The mirror can refer to the transmission file described above.

[0070] S42, the receiving end judges the mirror header signature to obtain a judgment result.

[0071] Optionally, the judgment result is that the mirror header signature is correct or the mirror header signature is incorrect.

[0072] S43, if the judgment result is that the mirror header signature is correct, the receiving end updates the buffer address according to the mirror header to obtain the buffer address, and the receiving end places the transferred data at the buffer address.

[0073] Optionally, the buffer address where the transferred data is placed is the buffer address updated according to the mirror header.

[0074] S44, otherwise the receiving end configures the error bit in the status register as an error.

[0075] Figure 6 FIG. is a flowchart showing an FPGA test method according to an embodiment of the present disclosure. As Figure 6 shown, an embodiment of the present disclosure provides an FPGA test method, including:

[0076] S51, the sending end writes the first magic header into the data register.

[0077] Optionally, the first magic header is the value checked by the receiving end.

[0078] S52, the sending end checks the data register. If the result of the check is that the value in the data register is equal to the second magic header, proceed; otherwise, exit.

[0079] Optionally, "proceed" may refer to the continued execution of the FPGA test method, and "exit" may refer to the exit of the FPGA test method. If the FPGA test method is implemented by a program, "proceed" may refer to the program executing the next step, and "exit" may refer to the program exiting.

[0080] Optionally, there may be multiple data registers. The register in which the sending end writes the first magic header and checks whether the value is equal to the second magic header can be one of the data registers. For example, the data registers include data register 0 and data register 1. Only write the first magic header to data register 0 and check data register 0.

[0081] S53, the sending end checks the copy bit in the status register until the copy bit indicates that data can be written.

[0082] Optionally, when the copy bit is 0, the above-mentioned implementation program waits.

[0083] S54, the sending end writes data into the data register.

[0084] Optionally, "writing data into the data register" may refer to the sending end writing data into all the data registers. For example, the sending end writes data into data registers 0 and 1.

[0085] S55, the sending end updates the copy bit.

[0086] Optionally, "the sending end updates the copy bit" may refer to the sending end updating the copy bit from 0 to 1, that is, updating the copy bit that indicates data can be written to the copy bit that indicates the receiving end can start moving data.

[0087] S56, if the transmission of the file is completed, the sending end configures the execution flag in the status register to be able to start execution; otherwise, the sending end checks the error bit in the status register until the error bit indicates an error and stops transmitting data.

[0088] Optionally, when the execution flag is 1, it indicates that execution can start; when the execution flag is 0, it indicates that execution cannot start. The initial value of the execution flag can be 0.

[0089] Optionally, when the error bit is an error, i.e., when the error bit is 1, stopping data transmission may refer to the program running the FPGA test method exiting. When the error bit is not an error, i.e., when the error bit is 0, the program continues to execute downward to transmit the next segment of data.

[0090] Figure 7 is a flowchart showing an implementation method for the sender in an embodiment of the present disclosure to update the replication bit. As Figure 7 shown, an embodiment of the present disclosure provides an implementation method for the sender to update the replication bit, including:

[0091] S61, the sender checks the parity bit in the status register until the parity bit indicates the start of verification.

[0092] Optionally, when the parity bit is 1, it indicates the start of verification, and it is necessary to calculate the parity code and write it into the parity register. When the parity bit is 0, it indicates that the verification does not start.

[0093] S62, the sender calculates the written data to obtain a second parity code.

[0094] Optionally, the process of calculating the second parity code from the written data can be implemented through relevant parity code algorithms, which will not be elaborated in this embodiment. The first parity code is the parity code calculated by the receiver, and the second parity code is the parity code calculated by the sender, which are distinguished by "first" and "second".

[0095] S63, the sender writes the second parity code into the parity register.

[0096] S64, the sender configures the replication bit in the status register to enable data replication.

[0097] In an embodiment of the present disclosure, the value in the data register may include a cycle node value and a frame gap configuration value associated with the cycle node value.

[0098] Optionally, the frame gap represents the gap between data frames, which is used to ensure that the network device has enough time for signal recovery and synchronization after receiving and processing one data frame to prepare for the next data frame. The frame gap configuration value refers to the value configured for the frame gap, and the frame gap configuration value may be different at different cycle nodes. By dynamically configuring the value of the frame gap at different cycle nodes, it is possible to dynamically configure the frame gap as a floating-point data, which macroscopically avoids the limitation of only being able to configure it as an integer, thereby fully expanding the test range of the FPGA.

[0099] In an embodiment of the present disclosure, a method for testing an FPGA is provided. When manufacturing the FPGA, a ROM model is embedded and a firmware supporting the present disclosure is loaded. After the FPGA is powered on, the built-in firmware runs.

[0100] The FPGA testing method is divided into a sending end and a receiving end. The firmware in the FPGA version ROM includes the receiving end. The sending end is located on an external device and interacts with the firmware inside the FPGA through the MDIO interface.

[0101] During the interaction, several registers are used for the interaction, which are divided into 3 categories in total. The first category is the status register, which is used for the communication status of the interaction port. Generally, only 1 is needed, and different BITS represent different meanings, and at least include definitions such as copy, exec, check, and err. The second category is the data verification register, which confirms the reliability of data transmission. Generally, only 1 is needed. The third category is the data register, which is used for data interaction. Generally, more than 1 is needed, and increasing the quantity helps to improve the transmission efficiency. In this embodiment, two data registers are used for specific description.

[0102] The sending end includes:

[0103] 1. Write Magic Header1 to data register 0, and this value needs to be the same as the value checked by the receiving end.

[0104] 2. The program checks whether the value of data register 0 is equal to the specific value Magic Header2. If the values are equal (Yes), the program performs the next operation. If the values are not equal (No), the program exits.

[0105] 3. Check the status register. When the copy BIT is 0, it means that data can be written to the data register. If the value is not 0 (No), the program waits.

[0106] 4. Write data to data registers 0 and 1; check the status register. When the check BIT is 1, the checksum needs to be calculated and written to the check register; set the copy BIT of the status register to 1 to inform the receiving end that it can start moving the data.

[0107] 5. Determine whether all the transmitted files have been transmitted. If so (Yes), set the exec flag to 1, and the receiving end starts to execute the incoming file. If the file has not been completely transmitted (No), check the err flag. If the value of err is equal to 1 (Yes), exit. If the value of err is not equal to 1 (No), the program continues to execute downward to transmit the next segment of data.

[0108] Figure 8Shown is the flowchart of the transmitting end of the FPGA testing method, which will not be elaborated in this embodiment.

[0109] The receiving end includes:

[0110] 1. The firmware built into the FPGA periodically checks Data Register 0 to determine whether its value is equal to the specific value MagicHeader1; if the values are equal (Yes), the program proceeds to the next step and sets the value in Data Register 0 to MagicHeader2; if the values are not equal (No), continue the check.

[0111] 2. Check the status register. When the copy BIT (copy) is 1 (Yes), it means data can be retrieved from the data register; if the value is not 1 (No), the program waits.

[0112] 3. Move the data from the data register to the cache.

[0113] 4. Check the status register. When the check BIT (check) is 1, calculate the checksum of the data in the cache and compare it with the check register; if the check passes, proceed to the next step; if the check is abnormal, mark the error (err) in the status register as 1 and end this transmission.

[0114] 5. After the data is moved from the data register to the cache, configure the copy BIT (copy) of the status register to 0.

[0115] 6. Determine whether the length of the data in the cache is equal to the length of the data mirror header itself. If they are equal (Yes), proceed to the next step; if not (No), continue to check whether the copy BIT (copy) of the status register is 1.

[0116] 7. Parse the mirror in the cache and determine whether the mirror header signature is correct. If it is correct (Yes), update the buffer address (the buffer is in the RAM) according to the content in the header, and then place the transported data at the new address; if it is incorrect (No), mark the error (err) in the status register as 1 and end this transmission.

[0117] 8. Check the status register and judge the execution flag (exec). If it is equal to 1 (Yes), the program proceeds to the next step and jumps to the firmware in the RAM to start execution; if (No), the program continues to check whether the copy BIT (copy) of the status register is 1 and execute the data transfer step.

[0118] Figure 9 Shown is the flowchart of the receiving end of the FPGA testing method, which will not be elaborated in this embodiment.

[0119] The FPGA test method can fully expand the FPGA test scope. The following is the usage method in the scenario of dynamically fine-tuning the IFG. The IFG (Inter-Frame Gap) plays a crucial role in Ethernet. It ensures that after a network device receives and processes a data frame, there is enough time for signal recovery and synchronization to prepare for receiving the next data frame. This time interval effectively avoids conflicts between data frames and improves the stability and reliability of network transmission.

[0120] How to adjust the IFG length in FPGA testing is a key step. In traditional FPGA designs, the IFG value can only be configured once and cannot be dynamically changed to meet the performance requirements in some special scenarios. In this scenario, after being loaded by the method of the present invention, the IFG can be dynamically configured as a floating-point value, which macroscopically circumvents the limitation of only being able to be configured as an integer.

[0121] The implementation solution of this example interacts through 5 registers. It is also possible to use different BIT positions in one register. For example, BIT[15:0] represents freq1, and BIT[31:16] represents freq2 to reduce the number of registers used. In this example, data register 0 is the Magic Header, and data registers 1 and 2 are freq1 and freq2 representing the fine-tuning cycle nodes (the cycle node values mentioned above). Data registers 3 and 4 are the configuration values of the IFG (the frame gap configuration values mentioned above). Data registers 0, 1, 2, 3, and 4 can all be modified through the SMI interface.

[0122] This example uses 0xF (hexadecimal) ticks as the loop adjustment period. At different tick points, the configuration makes the effective duration of the IFG1 and IFG2 configuration values dynamically adjusted. The overall IFG change range is from a to (a + 1). The following table shows one of the situations:

[0123] tick 0 1 2 3 4 5 6 7 IFG a a a a a+1 a+1 a+1 a+1 tick 8 9 10 11 12 13 14 15 IFG a+1 a+1 a+1 a+1 a+1 a+1 a+1 a+1

[0124] Table 1

[0125] In Table 1, when tick is 0, the IFG value is configured as a, and when tick is 4, the IFG value is configured as (a + 1). The IFG value of a occupies 4 ticks, and the IFG value of (a + 1) occupies 12 ticks. Therefore, in this example, the macroscopic IFG value is (a + 0.75). Tick is the cycle node mentioned above, and IFG is the frame gap mentioned above.

[0126] The protection scope of the FPGA test method described in the embodiments of the present disclosure is not limited to the execution order of the steps listed in this embodiment. Any solution achieved by adding or subtracting steps of the prior art and replacing steps according to the principles of the present disclosure is included in the protection scope of the present disclosure.

[0127] Figure 10 It is a schematic structural diagram showing the FPGA test device 100 according to an embodiment of the present disclosure. As Figure 10 shown, this embodiment provides an FPGA test device, including:

[0128] A magic number check module 1010, configured to periodically check the magic header in the data register until the check passes.

[0129] A status check module 1020, configured to check the copy bit in the status register until the copy bit indicates that data replication is possible.

[0130] A data transfer module 1030, configured to transfer the data in the data register to the cache and configure the copy bit as not allowing data replication.

[0131] A cache check module 1040, configured to check the data length in the cache until the data length is equal to the data mirror header length.

[0132] A mirror check module 1050, configured to, if the mirror header signature is correct, place the transferred data at the buffer address; otherwise, configure the error bit in the status register as an error.

[0133] A data execution module 1060, configured to check the execution flag in the status register until the execution flag indicates that execution can start, and execute the executable firmware data transferred in the FPGA execution RAM according to the transferred data, where the transferred data is the transferred executable firmware data.

[0134] In several embodiments provided by the present disclosure, it should be understood that the disclosed device or method can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of modules / units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some interfaces. The indirect coupling or communication connection of devices or modules or units can be in an electrical, mechanical or other form.

[0135] The modules / units described as separate components may or may not be physically separated, and the components shown as modules / units may or may not be physical modules, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected according to actual needs to achieve the objectives of the embodiments of the present disclosure. For example, in the various embodiments of the present disclosure, each functional module / unit can be integrated into a processing module, or each module / unit can exist physically alone, or two or more modules / units can be integrated into one module / unit.

[0136] Those of ordinary skill in the art should further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present disclosure.

[0137] Figure 11 is a schematic block diagram of an electronic terminal provided by an embodiment of the present application. As Figure 11 shown, the electronic terminal 1100 includes: at least one processor 1101, a memory 1102, at least one network interface 1103, and a user interface 1105. Each component in the device is coupled together through a bus system 1104. It can be understood that the bus system 1104 is used to realize the connection and communication between these components. In addition to including a data bus, the bus system 1104 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 11 all kinds of buses are labeled as the bus system.

[0138] Among them, the user interface 1105 may include a display, a keyboard, a mouse, a trackball, a click gun, a button, a touchpad, or a touch screen, etc.

[0139] It can be understood that the memory 1102 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM, Read Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM, Static Random Access Memory), synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory). The memory described in the embodiments of the present invention is intended to include but not limited to these and any other suitable categories of memories.

[0140] The memory 1102 in the embodiments of the present invention is used to store various categories of data to support the operation of the electronic terminal 1100. Examples of these data include: any executable programs for operating on the electronic terminal 1100, such as the operating system 11021 and application programs 11022; the operating system 11021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application programs 11022 can include various application programs, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. Implementing the probability table update method provided by the embodiments of the present invention can be included in the application programs 11022.

[0141] The method disclosed in the embodiments of the present invention above can be applied to the processor 1101 or implemented by the processor 1101. The processor 1101 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor 1101 or the instructions in the form of software. The above-mentioned processor 1101 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1101 can implement or execute each method, step, and logic block diagram disclosed in the embodiments of the present invention. The general-purpose processor 1101 may be a microprocessor or any conventional processor, etc. Combining the steps of the accessory optimization method provided in the embodiments of the present invention can be directly embodied as being completed by the hardware decoding processor, or completed by a combination of the hardware and software modules in the decoding processor. The software module may be located in the storage medium, and this storage medium is located in the memory. The processor reads the information in the memory and combines its hardware to complete the steps of the foregoing method.

[0142] In an exemplary embodiment, the electronic terminal 1100 may be an application-specific integrated circuit (ASIC), a DSP, a programmable logic device (PLD), or a complex programmable logic device (CPLD) for executing the foregoing method.

[0143] The embodiments of the present disclosure also provide a computer-readable storage medium. Those of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above embodiments can be completed by instructing the processor through a program. The program can be stored in the computer-readable storage medium, and the storage medium is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disc, and any combination thereof. The above storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid-state disk (SSD)), etc.

[0144] Embodiments of the present disclosure may also provide a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the processes or functions according to the embodiments of the present disclosure are wholly or partially generated. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, a computer, or a data center to another website, a computer, or a data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.).

[0145] When the computer program product is executed by a computer, the computer executes the method described in the foregoing method embodiments. The computer program product may be a software installation package. In the case where the foregoing method is required, the computer program product may be downloaded and executed on the computer.

[0146] The descriptions of the processes or structures corresponding to the foregoing respective drawings have their own focuses. For parts not detailed in a certain process or structure, reference may be made to the relevant descriptions of other processes or structures.

[0147] The foregoing embodiments merely illustrate the principles and effects of the present disclosure, rather than limiting the present disclosure. Any person familiar with this technology may make modifications or changes to the foregoing embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present disclosure should still be covered by the claims of the present disclosure.

Claims

1. A FPGA testing method, characterized in that: include: The receiving end periodically checks the phantom header in the data register until the check passes; The receiving end checks the copy bit in the status register until the copy bit indicates that data copy is possible; The receiving end moves the data in the data register to the cache, and after the data in the data register is moved to the cache, configures the copy bit to disable data copy; The receiving end checks the length of the data in the buffer until the data length is equal to the length of the data mirror header; If the image header signature is correct, the receiving end puts the transported data into the buffer address, otherwise the receiving end configures the error bit in the status register as an error; The receiving end checks the execution flag in the status register until the execution flag indicates that execution can start, and executes the executable firmware data transferred in the RAM according to the FPGA, wherein the transferred data is the transferred executable firmware data.

2. The FPGA testing method according to claim 1, characterized in that: The receiving end periodically checks the phantom header in the data register until the check passes. The implementation method includes: The receiving end periodically checks the data register to obtain the inspection data; The receiving end judges the inspection data and the first phantom header to obtain a judgment result, wherein the judgment result is that the inspection data is equal to the first phantom header or the inspection data is not equal to the first phantom header; If the judgment result is that the inspection data is equal to the first phantom head, it means that the inspection is passed and the value in the data register is set to the second phantom head, otherwise it means that the inspection is not passed and the data register is continued to be inspected.

3. The FPGA testing method according to claim 1, characterized in that: Also includes: The receiving end checks the check bit in the status register until the check bit indicates the start of checking; The receiving end calculates the data in the cache to obtain a first check code; The receiving end compares the first check code with the data in the check register to obtain a comparison result; When the comparison result is that the first check code is different from the data in the check register, the receiving end configures the error bit in the status register as an error.

4. The FPGA testing method according to claim 1, characterized in that: If the image header signature is correct, the receiving end puts the transported data into the buffer address, otherwise the receiving end configures the error bit in the status register as an error. The implementation method includes: The receiving end parses the image in the cache to obtain the image header signature; The receiving end judges the image header signature to obtain a judgment result; If the judgment result is that the image header signature is correct, the receiving end updates the buffer address according to the image header to obtain the buffer address, and the receiving end puts the transported data into the buffer address; Otherwise the receiving end configures the error bit in the status register as an error.

5. The FPGA testing method according to claim 4, characterized in that: Also includes: The transmitting end writes the first phantom header into the data register; The sending end checks the data register, and if the check result is that the value in the data register is equal to the second phantom header, then continue, otherwise exit; The sending end checks the copy bit in the status register until the copy bit indicates that data can be written; The sending end writes data into the data register; The sending end updates the copy bit; If the transmission of the transmission file is completed, the sending end configures the execution flag in the status register to be able to start execution, otherwise the sending end checks the error bit in the status register and stops transmitting data until the error bit is an error.

6. The FPGA testing method according to claim 4, characterized in that: The implementation method of updating the copy bit at the sending end includes: The sending end checks the check bit in the status register until the check bit indicates the start of checking; The sending end calculates the written data to obtain a second check code; The sending end writes the second check code into the check register; The sending end configures the copy bit in the status register to enable data copying.

7. The FPGA testing method according to claim 6, characterized in that: The value in the data register may include a cycle node value and a frame gap configuration value associated with the cycle node value.

8. An FPGA testing device, characterized in that: include: The magic number check module is used to periodically check the magic header in the data register until the check passes; A status checking module, used for checking a copy bit in a status register until the copy bit indicates that data copying is possible; A data transfer module, used for transferring the data in the data register to a cache and configuring the copy bit to disable data copy; A cache checking module, used for checking the length of data in the cache until the data length is equal to the length of the data mirror header; An image checking module, used for placing the transported data into a buffer address if the image header signature is correct, otherwise configuring the error bit in the status register as an error; The data execution module is used to check the execution flag in the status register until the execution flag indicates that execution can start, and execute the executable firmware data transferred in the RAM according to the FPGA, wherein the transferred data is the transferred executable firmware data.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the FPGA testing method according to any one of claims 1 to 7 is implemented.

10. An electronic terminal comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the FPGA testing method according to any one of claims 1 to 7.

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