Transmission mode conversion circuit, chip and electronic equipment

Abstract

The invention relates to a transmission mode conversion circuit, a chip and electronic equipment. The circuit comprises a data conversion module and a control signal generation module, the plurality of data input ports and the plurality of data output ports are connected with the data conversion module and are used for transmitting different types of data signals; the plurality of control signal input ports and the plurality of control signal output ports are connected with the control signal generation module and are used for transmitting different types of control signals; the data conversion module is used for converting the data signal of the original transmission mode input by the gated data input port to generate a data signal of a target transmission mode, and outputting the data signal of the target transmission mode from the gated data output port; and the control signal generation module is used for generating a plurality of target control signals according to the original control signals input by the gated control signal input port, and outputting the target control signals through the gated control signal output port. According to the embodiment of the invention, multiplexing of the circuit can be realized, and the workload of repeated development is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a transmission mode conversion circuit, a chip, and an electronic device. Background Art

[0002] As chips become more and more complex, in chip design, multiple data transmission modes are often used. Therefore, it is necessary to design multiple transmission mode conversion circuits to convert between multiple data transmission modes.

[0003] Currently, the conversion between various transmission modes is implemented using separate modules, and the designs of the conversion circuits are also different. Each time a conversion is performed in the circuit, a corresponding module needs to be designed. This will increase the design cost and verification complexity, and is not conducive to the reliability and stability of the product. Summary of the Invention

[0004] In view of this, the present disclosure provides a transmission mode conversion circuit, including: a data conversion module, a control signal generation module; a plurality of data input ports and a plurality of data output ports connected to the data conversion module for transmitting different types of data signals; a plurality of control signal input ports and a plurality of control signal output ports connected to the control signal generation module for transmitting different types of control signals;

[0005] The data conversion module is configured to convert the data signal of the original transmission mode input by the selected data input port, generate a data signal of the target transmission mode, and output it from the selected data output port; wherein, the unselected data input port and data output port are floating.

[0006] The control signal generation module is configured to generate a plurality of target control signals according to the original control signal input by the selected control signal input port, and output them through the selected control signal output port, wherein the unselected control signal input port and control signal output port are floating.

[0007] In a possible implementation manner, the data conversion module includes: a parallel-to-serial conversion module configured to convert a parallelly transmitted data signal into a serially transmitted data signal;

[0008] The parallel-to-serial conversion module includes:

[0009] a write data conversion module configured to convert parallel write data to obtain a serial write data signal and output it through a write data port;

[0010] a read data conversion module configured to convert parallel read data to obtain a serial read data signal and output it through a read data port;

[0011] A data address conversion module, which is used to convert parallel data addresses to obtain serial data address signals and output them through a data address port.

[0012] In a possible implementation, the original control signals input through the control signal input port include: a read-write control signal, a peripheral selection signal, and a transmission control signal;

[0013] The control signal generation module includes: a first AND gate and a second AND gate;

[0014] The first AND gate is used to perform an AND operation on the read-write control signal, the peripheral selection signal, and the transmission control signal to obtain a read data output signal, and the read data output signal is used to control the read data conversion module to perform operations;

[0015] The second AND gate is used to perform an AND operation on the inverted signal of the read-write control signal, the peripheral selection signal, and the transmission control signal to obtain a write data output signal, and the write data output signal is used to control the write data conversion module to perform operations.

[0016] In a possible implementation, the target control signals output through the control signal output port include: a read control signal, a write control signal, and a target peripheral selection signal;

[0017] The control signal generation module includes: a read control signal generation module, a write control signal generation module, and a target peripheral selection signal generation module;

[0018] The read control signal generation module is used to start generating a read control signal output and start counting with a first counter when receiving the read data output signal, and end generating the read controller signal when the first counter reaches its full count;

[0019] The write control signal generation module is used to start generating a write control signal output and start counting with a second counter when receiving the write data output signal, and end generating the write controller signal when the second counter reaches its full count;

[0020] The target peripheral selection signal generation module is used to start generating a target peripheral selection signal output and start counting with a third counter when receiving the peripheral selection signal, and end generating the target peripheral selection signal when the third counter reaches its full count, where the full count value is the number of bits of the received parallel transmission data signal minus 1.

[0021] In a possible implementation, the control signal generation module includes: a first delay register and a second delay register;

[0022] The first delay register is connected to the input ends of the first AND gate and the second AND gate, and is configured to delay the input read / write control signal and input the delayed read / write control signal into the first AND gate and the second AND gate respectively;

[0023] The second delay register is connected to the output ends of the first AND gate and the second AND gate, and is configured to delay the read data output signal, the write data output signal, and the target peripheral selection signal, and transmit the delayed read data output signal to the read control signal generation module, transmit the delayed write data output signal to the write control signal generation module, and transmit the delayed target peripheral selection signal to the target peripheral selection signal generation module.

[0024] In a possible implementation manner, the data conversion module includes: a serial-to-parallel conversion module configured to convert the serially transmitted data signal to generate a parallelly transmitted data signal; the serially transmitted data signal includes a data content signal and a data address signal;

[0025] The serial-to-parallel conversion module includes: a serial-to-parallel conversion flip-flop, a first selector, and a second selector;

[0026] The serial-to-parallel conversion flip-flop is configured to convert the serial data content signal to obtain a parallel data content signal, and convert the serial data address signal to obtain a parallel data address signal;

[0027] The first selector is configured to output and hold the parallel data content signal;

[0028] The second selector is configured to output and hold the parallel data address signal.

[0029] In a possible implementation manner, the data conversion module includes: a third delay register;

[0030] The third delay register is configured to delay the data content signal output by the first selector and input the delayed data content signal into the first selector, and delay the data address signal output by the second selector and input the delayed data address signal into the second selector;

[0031] The first selector selects between the parallel data content signal output by the serial-to-parallel conversion flip-flop and the delayed data content signal, and inputs the output parallel data content signal into the third delay register again for delay to keep the output parallel data content signal to the data output port;

[0032] The second selector selects between the parallel data address signal output by the serial-to-parallel conversion flip-flop and the delayed data address signal, and inputs the output parallel data address signal into the third delay register again for delay, so as to keep the output parallel data address signal to the data output port.

[0033] In a possible implementation, the third delay register is used to delay the read control signal input from the selected control signal input port to obtain a delayed read control signal;

[0034] The control signal generation module includes: a third AND gate, which performs an AND operation on the inverted signal of the input read control signal and the delayed read control signal to obtain a first pulse signal, and uses the first pulse signal as the selection signal of the first selector and inputs it into the first selector; and outputs the first pulse signal as a read / write control signal through the control signal output port.

[0035] When the first pulse signal is at a high level, the first selector selects and outputs the parallel data content signal output by the serial-to-parallel conversion flip-flop; after the first pulse signal drops to a low level, the first selector selects and outputs the delayed data content signal output by the third delay register.

[0036] In a possible implementation, the third delay register is used to delay the target peripheral selection signal input from the selected control signal input port to obtain a delayed target peripheral selection signal;

[0037] The control signal generation module includes: a fourth AND gate, which performs an AND operation on the inverted signal of the input target peripheral selection signal and the delayed target peripheral selection signal to obtain a second pulse signal, and uses the second pulse signal as the selection signal of the second selector and inputs it into the second selector;

[0038] When the second pulse signal is at a high level, the second selector selects and outputs the parallel data address signal output by the serial-to-parallel conversion flip-flop; after the second pulse signal drops to a low level, the second selector selects and outputs the delayed data address signal output by the third delay register.

[0039] In a possible implementation, the third delay register is used to delay the second pulse signal output by the fourth AND gate to obtain a delayed second pulse signal;

[0040] The control signal generation module includes: an OR gate, which performs an OR operation on the second pulse signal and the delayed second pulse signal to obtain a third pulse signal, and outputs the third pulse signal as a peripheral selection signal through the control signal output port.

[0041] In a possible implementation, the third delay register is configured to delay the second pulse signal and output the delayed second pulse signal as a transmission control signal through a control signal output port.

[0042] In a possible implementation, the control signal generation module includes: a transmission completion signal generation module, configured to generate a target data transmission completion signal based on a received original data transmission completion signal, a read / write control signal generated by the control signal generation module, and a peripheral selection signal, where the target data transmission completion signal is used to indicate that the data signal of the target transmission mode has been transmitted.

[0043] According to one aspect of the present disclosure, there is provided a chip including the above-mentioned transmission mode conversion circuit provided by the present disclosure.

[0044] According to one aspect of the present disclosure, there is provided an electronic device including the above-mentioned transmission mode conversion circuit provided by the present disclosure.

[0045] In the embodiment of the present disclosure, in the transmission mode conversion circuit, a plurality of transmission ports are provided for the user to select, making full use of the multiplexing of the circuit. In different application scenarios, the user can select the corresponding transmission port and transmission mode according to actual needs, without separately developing a conversion circuit for each transmission mode, and thus without verifying the circuit multiple times, which not only reduces the workload of repeated development but also reduces the verification complexity brought by repeated development.

[0046] According to the following detailed description of exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present disclosure will become clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are included in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and are used to explain the principles of the present disclosure.

[0048] Figure 1 The block diagram of a transmission mode conversion circuit according to an embodiment of the present disclosure is shown.

[0049] Figure 2 The schematic diagram of an actual application scenario of a parallel-to-serial conversion circuit provided by the present disclosure is shown.

[0050] Figure 3 The schematic diagram of an actual application scenario of a serial-to-parallel conversion circuit provided by the present disclosure is shown.

[0051] Figure 4 The schematic diagram of an actual application scenario of a transmission mode conversion circuit provided by the present disclosure is shown.

[0052] Figure 5 Schematic diagram showing an actual application scenario of another transmission mode conversion circuit provided by the present disclosure. Detailed implementation manners

[0053] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. Identical reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0054] The special term "exemplary" here means "serving as an example, embodiment, or illustration". Any embodiment described as "exemplary" here is not necessarily to be construed as superior to or better than other embodiments.

[0055] In addition, for better illustration of the present disclosure, numerous specific details are given in the following detailed implementation manners. Those skilled in the art should understand that the present disclosure can also be implemented without some specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0056] In the design of the transmission mode conversion circuit, non - reusability of the circuit is a significant problem. For multiple transmission mode conversion functions in the circuit, corresponding conversion circuit modules need to be designed, and these modules often cannot be reused in different transmission scenarios, thus increasing the design workload and verification complexity.

[0057] Figure 1 Shows a block diagram of a transmission mode conversion circuit according to an embodiment of the present disclosure. As Figure 1 shown, the transmission mode conversion circuit 10 includes: a data conversion module 101, a control signal generation module 102; a plurality of data input ports 103 and a plurality of data output ports 104 connected to the data conversion module 101 for transmitting different types of data signals; a plurality of control signal input ports 105 and a plurality of control signal output ports 106 connected to the control signal generation module 102 for transmitting different types of control signals;

[0058] The data conversion module 101 is configured to convert the data signal of the original transmission mode input from the selected data input port 103, generate a data signal of the target transmission mode, and output it from the selected data output port 104; wherein, the unselected data input port 103 and the data output port 104 are left floating;

[0059] The control signal generation module 102 is configured to generate a plurality of target control signals based on the original control signal input through the selected control signal input port 104 and output them through the selected control signal output port 105. Among them, the unselected control signal input port 105 and the control signal output port 106 are floating.

[0060] The transmission mode conversion is to achieve flexible conversion between different data transmission modes. Taking the transmission modes including serial transmission and parallel transmission as an example, the transmission mode conversion circuit can achieve serial-to-parallel conversion. In this circuit, data is input in a serial manner, that is, the data bits are transmitted sequentially. The data conversion module inside the circuit will receive these serial data and convert them into a parallel format, that is, the data bits will appear on multiple parallel channels simultaneously, thus improving the data transmission rate and efficiency.

[0061] The transmission mode conversion circuit can also achieve parallel-to-serial conversion. In this implementation, the data conversion module will receive parallel data and convert it bit by bit into a serial format for transmission. The control signal generation module is responsible for generating control signals to ensure the correct transmission and reception of serial data.

[0062] When converting the data transmission mode, it mainly involves converting the data itself and converting the control signals, among which:

[0063] The control signal is a signal used to indicate, control, or manage the flow of data signals during the data transmission process, enabling the transmitted data signals to be transmitted in a predetermined manner, at the correct time, and under the correct conditions.

[0064] Exemplarily, the control signals include peripheral selection signals (psel), write enable signals (pwrite), transfer enable signals (penable), etc. These signals work together to ensure that the data signals can be transmitted correctly and error-free on the bus. It should be noted that the bus mentioned here can be the Advanced Peripheral Bus (APB) protocol, and can also be applicable to other protocols, not limited to this.

[0065] Among them, the peripheral selection signal is used to select a specific peripheral for data transmission. When the received psel signal is valid, it indicates that the current circuit is the selected peripheral and can participate in data transmission. The write enable signal is used to indicate that the current data transmission is a write operation. When the pwrite signal is valid, it indicates that a data write operation is in progress. The transfer enable signal is used to control the start and end of data transmission. When the penable signal is valid, it indicates that data is being transmitted.

[0066] A data signal is data that needs to be transmitted between different devices or modules. In a circuit, data is usually transmitted in parallel or serial form. Parallel transmission can be that data is transmitted simultaneously in groups on multiple parallel channels; while serial transmission can be that data is transmitted bit by bit in sequence.

[0067] Exemplarily, the data signal includes a data content signal (pdata) and a data address signal (paddr). The pdata is used to transmit the actual data content, while the paddr is used to indicate the memory address where the data should be written or read.

[0068] The control signal and the data signal are inseparable during the data transmission process. The control signal is responsible for managing and indicating the flow of the data signal, while the data signal is the actual information content to be transmitted. Without the guidance of the control signal, the data cannot be transmitted in a predetermined manner; similarly, without the support of the data, the control signal will lose its meaning of existence.

[0069] When the main controller needs to write data to a certain peripheral device, it will first select the peripheral device by sending the psel signal, and then indicate that a write operation is in progress by sending the pwrite signal. Next, the main controller will send the pdata signal (containing the actual data to be written) and the paddr signal (specifying the address where the data should be written) through the data line. Finally, when the data transmission is completed, the main controller will end the transmission process by sending the falling edge of the penable signal.

[0070] The data input port and the data output port are interfaces in the transmission mode conversion circuit for transmitting data signals. Among them, the data input port is used to receive the data signal in the original transmission mode, while the data output port is used to output the data signal in the converted target transmission mode. For example, a parallel data input port can receive 8-bit parallel data, while a serial data output port can output the serial data converted from the 8-bit data.

[0071] The control signal input port and the control signal output port are interfaces in the transmission mode conversion circuit for transmitting control signals. Among them, the control signal input port is used to receive the original control signal, while the control signal output port is used to output the generated target control signal. The original control signal is a signal used to control the transmission of the data signal in the original transmission mode, and the target control signal is a signal used to control the transmission of the data signal in the target transmission mode. Since the data signal in the original transmission mode will be converted to the target transmission mode, the original control signal can be converted to the target control signal to control the transmission of the data signal in the target transmission mode, facilitating the receiving end to accurately receive the data signal in the target transmission mode.

[0072] The ports in the transmission mode conversion circuit can be selected and left floating according to actual usage requirements. The selected state indicates that a certain port or module is selected and in the working state, while the floating state indicates that a certain port or module is not selected and in the non - working state. In the selected state, the port or module will receive and process signals; while in the floating state, the port or module will not receive or process signals.

[0073] During the data conversion process, the selected data input port and data output port will participate in the reading and output of data, while the unselected ports are in the floating state. Similarly, during the control signal generation process, the selected control signal input port and control signal output port will participate in the generation and output of control signals, while the unselected ports are in the floating state.

[0074] The data conversion module can receive the data signal of the original transmission mode input from the selected data input port, then convert the received data signal to generate a data signal that conforms to the target transmission mode, and then output the converted data signal from the selected data output port. During this process, the unselected data input port and data output port remain in the floating state and do not participate in data transmission.

[0075] The control signal generation module can generate multiple target control signals based on the original control signal input from the selected control signal input port. The generated target control signals are output through the selected control signal output port. The unselected control signal input port and control signal output port also remain in the floating state.

[0076] The selection and floating mechanism of the ports allows the circuit to be flexibly configured according to actual needs. For specific possible implementation methods, reference can be made to those provided in this disclosure, which will not be elaborated here.

[0077] In the embodiments of this disclosure, in the transmission mode conversion circuit, multiple transmission ports are provided for users to select, making full use of the circuit multiplexing. In different application scenarios, users can select the corresponding transmission ports and transmission modes according to actual needs, without having to develop a conversion circuit separately for each transmission mode, and thus without having to verify the circuit multiple times. This not only reduces the workload of repeated development but also reduces the verification complexity brought by repeated development.

[0078] There can be various transmission mode conversion circuits provided in this disclosure. For example, it can be a parallel - to - serial conversion circuit or a serial - to - parallel conversion circuit. The following will describe in detail the various implementation methods of the transmission mode conversion circuit provided in this disclosure.

[0079] In a possible implementation, the data conversion module includes: a parallel-to-serial conversion module for converting a parallelly transmitted data signal into a serially transmitted data signal. The parallel-to-serial conversion module includes: a write data conversion module for converting parallel write data into a serial write data signal and outputting it through a write data port; a read data conversion module for converting parallel read data into a serial read data signal and outputting it through a read data port; and a data address conversion module for converting parallel data addresses into a serial data address signal and outputting it through a data address port.

[0080] In this implementation, the transmission mode conversion circuit is implemented as a parallel-to-serial conversion circuit, that is, converting parallelly transmitted data into serially transmitted data. Then, the transmission mode conversion circuit includes a parallel-to-serial conversion module. That is to say, the transmission mode conversion circuit can convert a parallelly transmitted data signal into a serially transmitted data signal. That is, the multiple bits of data received in parallel are serially sent out bit by bit.

[0081] The write data conversion module is used to convert the parallel write data signal (i.e., the data written to the target device) into a serial write data signal. The read data conversion module is used to convert the parallel read data signal (i.e., the data read back from the target device) into a serial read data signal. The data address conversion module is used to convert the parallel data address signal (i.e., the address pointing to a specific location in the target device) into a serial data address signal.

[0082] The data output ports of the transmission mode conversion circuit include: a write data port, a read data port, and a data address port. The design of these ports fully considers the diversity and flexibility requirements in practical applications, and users can flexibly select according to the transmission requirements. For the data input ports of the transmission mode conversion circuit, no limitations are imposed here.

[0083] The write data port is used to write the data of the source device to the target device. The read data port, opposite to the write data port, is used to write the data read back from the target device back to the source device. The data address port is used to transmit the target address for storing data to ensure that the data is accurately sent to the correct location of the target device.

[0084] When designing the circuit, users can select the corresponding ports according to actual needs to achieve circuit multiplexing. In one example, in the architecture of a master device and a slave device, the master device needs to send data and addresses to the slave device for data processing and read back the data (without an address) processed by the slave device. In the initial stage of circuit design, according to the above requirements, it can be achieved by selecting different data ports in the transmission mode conversion circuit.

[0085] To meet the requirement of the master device transmitting data to the slave device, the write data port and the data address port are selected in the design of the transmission mode conversion circuit. After the circuit is manufactured and put into use, a specific parallel-to-serial conversion circuit is formed based on the selected write data port and data address port. This parallel-to-serial conversion circuit is used to convert the parallel data signal and address signal sent by the master device into a serial signal. The master device sends the converted serial data signal and address signal to the slave device through the selected write data port and data address port. After receiving these signals, the slave device converts them back into parallel data signals and address signals through an internal serial-to-parallel conversion circuit and performs data processing.

[0086] To meet the requirement of the slave device transmitting the read-back data to the master device, the read data port is selected in the design of the transmission mode conversion circuit. After the circuit is manufactured and put into use, another specific parallel-to-serial conversion circuit is formed based on the selected read data port (although it has the same physical structure as the parallel-to-serial conversion circuit in the write process, it is logically independent). This parallel-to-serial conversion circuit is used to convert the parallel data signal sent by the slave device into a serial signal. The slave device sends the converted serial data signal to the master device through the selected read data port. After receiving these signals, the master device converts them back into parallel data signals through an internal serial-to-parallel conversion circuit and performs subsequent processing.

[0087] Those skilled in the art can understand that in the circuit design stage, by selecting different data ports, corresponding parallel-to-serial conversion circuits can be planned for different data transmission paths, realizing the reuse of the transmission mode conversion circuit, supporting different data transmission paths, and eliminating the need to design independent hardware circuits for each requirement, thus reducing the amount of repeated development and verification.

[0088] In a possible implementation, the original control signals input through the control signal input port include: read-write control signal, peripheral selection signal, and transmission control signal; the control signal generation module includes: a first AND gate and a second AND gate; the first AND gate is used to perform an AND operation on the read-write control signal, peripheral selection signal, and transmission control signal to obtain a read data output signal, and the read data output signal is used to control the read data conversion module to perform an operation; the second AND gate is used to perform an AND operation on the inverted signal of the read-write control signal, peripheral selection signal, and transmission control signal to obtain a write data output signal, and the write data output signal is used to control the write data conversion module to perform an operation.

[0089] The original control signals input through the control signal input port are used to control the data signals in the original transmission mode. After the data signals are converted into the target transmission mode, the control signal generation module will also convert the original control signals. The original control signals include: read-write control signal, peripheral selection signal, and transmission control signal, where:

[0090] A read / write control signal, which is used to indicate whether the current operation is a read operation or a write operation. For example, when this signal is at a high level, it can represent a read operation; when the signal is at a low level, it may represent a write operation (or vice versa, depending on the specific design convention).

[0091] A peripheral selection signal, which is used to select or specify which target device should respond to the current read / write operation. In a multi-device system, this signal enables data to be sent to the correct target device or read from the correct source.

[0092] A transmission control signal, which is used to enable or trigger the data transmission process. When this signal is valid (e.g., at a high level), it indicates the start of data transmission; when the signal is invalid (e.g., at a low level), the system does not perform data transmission.

[0093] The control signal generation module includes two AND gates. An AND gate is a type of logic gate. These two AND gates are used to combine the above control signals to generate a target control signal. In addition, these two AND gates can also generate signals for controlling the data conversion module.

[0094] Specifically, the inputs of the first AND gate include the read / write control signal, the peripheral selection signal, and the transmission control signal. When all three of these signals are true (i.e., at a high level), the AND gate outputs a high-level signal. The signal output by the AND gate is the read data output signal. When the read data output signal is valid, it controls the read data conversion module to start executing the data conversion process for the read operation and outputs the converted serial data signal.

[0095] The inputs of the second AND gate include: the inverted signal of the read / write control signal (if the original read / write control signal is at a high level indicating a write operation, then its inverted signal is at a low level, and vice versa), the peripheral selection signal, and the transmission control signal. When the inverted signal of the read / write control signal is false (i.e., its original signal is true, indicating that a write operation is in progress), the peripheral selection signal, and the transmission control signal are all true, the AND gate outputs a high-level signal, and this signal can be used as the write data output signal. When the write data output signal is valid, it controls the write data conversion module to start executing the data conversion process for the write operation and outputs the converted serial data signal.

[0096] In an embodiment of the present disclosure, through a first AND gate, an AND operation is performed on the read / write control signal, the peripheral selection signal, and the transmission control signal to obtain a read data output signal, so as to control the read data conversion module to perform an operation; through a second AND gate, an AND operation is performed on the inverted signal of the read / write control signal, the peripheral selection signal, and the transmission control signal to obtain a write data output signal, so as to control the write data conversion module to perform an operation. Thus, the control signal generation module can flexibly control the operations of the read data conversion module and the write data conversion module according to the input original control signals, thereby realizing effective control of data transmission.

[0097] In a possible implementation manner, the target control signals output by the control signal output port include: a read control signal, a write control signal, and a target peripheral selection signal; the control signal generation module includes: a read control signal generation module, a write control signal generation module, and a target peripheral selection signal generation module; the read control signal generation module is configured to start generating a read control signal output and start counting by a first counter when receiving the read data output signal, and end generating the read control signal when the first counter is full; the write control signal generation module is configured to start generating a write control signal output and start counting by a second counter when receiving the write data output signal, and end generating the write control signal when the second counter is full; the target peripheral selection signal generation module is configured to start generating a target peripheral selection signal output and start counting by a third counter when receiving the peripheral selection signal, and end generating the target peripheral selection signal when the third counter is full, where the full value is the number of bits of the received parallel transmission data signal minus 1.

[0098] In the transmission mode conversion circuit for serial-to-parallel conversion, the target control signals output by the control signal output port include a read control signal, a write control signal, and a target peripheral selection signal. These three target control signals are all output by their respective corresponding control signal output ports and can be selected according to transmission requirements in practical applications.

[0099] These three target control signals are generated by different modules respectively: a read control signal generation module, a write control signal generation module, and a target peripheral selection signal generation module. The specific signal generation process is described as follows:

[0100] The read control signal generation module starts generating a read control signal when receiving the read data output signal, and this signal is used to indicate the valid state of the read operation serial signal to ensure that data can be correctly received at the receiving end.

[0101] Meanwhile, the transmission mode conversion circuit starts a counter (the first counter) to count. The full count value of the counter is related to the number of bits of the received parallel transmission data signal. Specifically, it can be the number of bits minus 1 to ensure the integrity of the outgoing serial data. When the counter is full, the generation of the read control signal ends, indicating that the read operation has been completed.

[0102] When a serial read data signal needs to be output, the output port of the read control signal, the read data port, and their related ports can be selected to implement the parallel-to-serial conversion circuit for the read data, without the need to design a separate hardware circuit for the parallel-to-serial conversion of each read operation.

[0103] The write control signal generation module starts generating the write control signal when it receives the write data output signal. This signal is used to indicate the valid state of the write operation serial signal to ensure that the data can be correctly received at the receiving end.

[0104] Similar to the read control signal generation module, the write control signal generation module can also start a counter (the second counter) to count to ensure the integrity of the data. When the counter is full, the generation of the write control signal ends, indicating that the write operation has been completed.

[0105] When a serial write data signal needs to be output, the output port of the write control signal, the write data port, and their related ports can be selected to implement the parallel-to-serial conversion circuit for the write data, without the need to design an independent hardware circuit for the parallel-to-serial conversion of each write operation.

[0106] The target peripheral selection signal generation module starts generating the target peripheral selection signal when it receives the peripheral selection signal. This signal is used to select or specify which receiving device should respond to the current read and write operations. A counter (the third counter) is also started in the circuit to count to ensure the stability and accuracy of the signal. When the counter is full, the generation of the target peripheral selection signal ends, indicating the completion of the peripheral selection.

[0107] By selecting the output port of the target peripheral selection signal, the selection of the peripheral can be achieved.

[0108] In the embodiments of the present disclosure, those skilled in the art can understand that in the circuit design stage, according to the data transmission requirements, different data transmissions can be achieved by selectively enabling the read control signal, the write control signal, and the target peripheral selection signal as needed, realizing the reuse of the transmission mode conversion circuit. In addition, by combining the counter to control the generation of the target control signal, the integrity of the transmitted data and the stability of the signal can be ensured.

[0109] In a possible implementation, the control signal generation module includes: a first delay register and a second delay register; the first delay register is connected to the input ends of the first AND gate and the second AND gate, and is configured to delay the input read-write control signal and input the delayed read-write control signal into the first AND gate and the second AND gate respectively; the second delay register is connected to the output ends of the first AND gate and the second AND gate, and is configured to delay the read data output signal, the write data output signal and the target peripheral selection signal, and transmit the delayed read data output signal to the read control signal generation module, transmit the delayed write data output signal to the write control signal generation module, and transmit the delayed target peripheral selection signal to the target peripheral selection signal generation module.

[0110] The first delay register is connected to the input ends of the first AND gate and the second AND gate. The first delay register is used to perform a delay process on the input read-write control signal. The precise timing of the control signal is crucial for ensuring correct data transmission and processing. Since the signal takes time to propagate in the circuit and there may be mismatches and delays in the circuit, the directly received control signal may not be suitable for immediately triggering subsequent logic operations.

[0111] By delaying the input read-write control signal through the first delay register, it can be ensured that when the read-write control signal reaches the AND gate, other related signals (such as data signals, etc.) are also in a suitable state, thereby avoiding timing conflicts and data errors. The delay through the first delay register helps to achieve synchronization between signals, enabling data to be read or written under stable control signals.

[0112] The second delay register is connected to the output ends of the first AND gate and the second AND gate, and is used to delay the read data output signal, the write data output signal and the target peripheral selection signal. These signals are the outputs of the control signal generation module, and delaying these signals is also for ensuring the correctness of the timing.

[0113] The read data output signal needs to be transmitted to the read control signal generation module after the data signal is stable, so that the receiving end can read complete and accurate data according to the read control signal. Similarly, the write data output signal and the target peripheral selection signal also need to be appropriately delayed to synchronize them with the data signal output by the circuit, so as to correctly execute data transmission and enable the receiving end to read complete and accurate data.

[0114] It should be noted that the specific delay duration of the first delay register and the second delay register can be determined according to the actual situation, and the present disclosure does not make specific limitations on this.

[0115] Figure 2A schematic diagram of an actual application scenario of a parallel-to-serial conversion circuit provided by the present disclosure is shown. The parallel-to-serial conversion circuit includes: a first delay register, a second delay register, a first AND gate, a second AND gate, a first counter, a second counter, a third counter, a write control signal generation module, a read control signal generation module, a target peripheral selection signal generation module, a write data conversion module, a read data conversion module, and a data address conversion module.

[0116] Among them, the input ports of the circuit include: each port for inputting a clock signal clk, a read / write control signal p2s_pwrite, a peripheral selection signal p2s_psel, a transmission control signal p2s_penable, an input data content signal p2s_pwdata, and an input data address signal p2s_paddr. The output ports include: each port for outputting a write control signal wr_rdy, a read control signal rd_rdy, a target peripheral selection signal sel_rdy, a serial read data prdata_do, a serial write data pwdata_do, and a serial data address signal paddr_do.

[0117] For the above ports, they can be selected according to actual requirements during circuit design.

[0118] In this parallel-to-serial conversion circuit, the clock signal clk is input through the clock signal input port to provide a timing reference for the entire circuit. The read / write control signal p2s_pwrite is input through the read / write control signal input port and is used to indicate whether the current operation is a read or a write. The peripheral selection signal p2s_psel is input through the peripheral selection signal input port and is used to select the target peripheral. The transmission control signal p2s_penable is input through the transmission control signal input port and is used to start or stop data transmission.

[0119] The first delay register delays the input read / write control signal p2s_pwrite and inputs the delayed read / write control signal p2s_pwrite_1r into the first AND gate and the second AND gate respectively;

[0120] The first AND gate performs an AND operation on p2s_psel, p2s_penable, and p2s_pwrite_1r to obtain a write data output signal p2s_write; the first AND gate performs an AND operation on the inverted signals of p2s_psel, p2s_penable, and p2s_pwrite_1r to obtain a read data output signal p2s_read;

[0121] The second delay register delays p2s_write, p2s_read, and p2s_psel to obtain the delayed write data output signal p2s_write_ff, read data output signal p2s_read_ff, and target peripheral selection signal p2s_psel_ff.

[0122] p2s_write and p2s_read will be used as the enable signals for the write data conversion module and the read data conversion module respectively. When p2s_write is valid, it will control the write data conversion module to perform parallel-to-serial conversion on the data content signal p2s_wdata and output the serial write data pwdata_do; when p2s_read is valid, it will control the read data conversion module to perform parallel-to-serial conversion on the data content signal p2s_wdata and output the serial read data pwdata_do; in addition, p2s_psel will be used as the enable signal for the data address conversion module. When p2s_psel is valid, it will control the data address conversion module to perform parallel-to-serial conversion on the data address signal p2s_paddr and output the serial data address signal.

[0123] When outputting the converted serial data signal, read control signal rd_rdy, write control signal wr_rdy, and target peripheral selection signal sel_rdy can also be generated to indicate the relevant operations for the receiving end to receive the data.

[0124] Specifically, the delayed write data output signal p2s_write_ff, read data output signal p2s_read_ff, and target peripheral selection signal p2s_psel_ff will be input to the write control signal generation module, read control signal generation module, and target peripheral selection signal generation module respectively to generate the read control signal rd_rdy, write control signal wr_rdy, and target peripheral selection signal sel_rdy.

[0125] The read control signal rd_rdy, write control signal wr_rdy, and target peripheral selection signal sel_rdy will be held by the first counter, second counter, and third counter respectively until all parallel data is converted into serial data. The first counter will generate the first count signal clk_cnt_wr, the second counter will generate the second count signal clk_cnt_rd, and the third counter will generate the third count signal sel_clk_cnt to control the write control signal generation module, read control signal generation module, and target peripheral selection signal generation module to keep the output wr_rdy, rd_rdy, and sel_rdy valid to notify the receiving end to receive the serial data.

[0126] In a possible implementation, the data conversion module includes: a serial-to-parallel conversion module for converting a serially transmitted data signal into a parallelly transmitted data signal; the serially transmitted data signal includes a data content signal and a data address signal; the serial-to-parallel conversion module includes: a serial-to-parallel conversion flip-flop, a first selector, and a second selector; the serial-to-parallel conversion flip-flop is configured to convert the serial data content signal into a parallel data content signal and convert the serial data address signal into a parallel data address signal; the first selector is configured to output and hold the parallel data content signal; the second selector is configured to output and hold the parallel data address signal.

[0127] In this implementation, the transmission mode conversion circuit is implemented as a serial-to-parallel conversion circuit, that is, converting serially transmitted data into parallelly transmitted data. Then, the transmission mode conversion circuit includes a serial-to-parallel conversion module, that is to say, the transmission mode conversion circuit can convert a serially transmitted data signal into a parallelly transmitted data signal. The specific implementation of the serial-to-parallel conversion module can be a shift register, and in addition, it can also be other implementation manners, which will not be elaborated in this disclosure.

[0128] When serially input, the data can include a data content signal or a data address signal. The data content signal and the data address signal are input into the circuit in a serial manner. That is, the data is transmitted bit by bit.

[0129] The serial-to-parallel conversion flip-flop can receive the serial data content signal and the data address signal, and then use the internal logic circuit or timing control mechanism to convert these serial signals into parallel data content signals and data address signals. That is, the data can be transmitted simultaneously in the form of multiple bits (such as 8 bits, 16 bits, or 32 bits, etc.), greatly improving the data transmission rate and efficiency.

[0130] The parallel data content signal and data address signal output by the serial-to-parallel conversion flip-flop can be held so that the receiving end can receive them stably. Specifically, it can be implemented based on the first selector and the second selector.

[0131] The first selector is configured to receive the converted parallel data content signal, output it to the receiving end, and at the same time maintain the stable state of this signal. Specifically, it can maintain the stable state of this signal by continuously receiving the delay signal of the parallel data content signal and selectively outputting it.

[0132] The second selector is used to receive the converted parallel data address signal, output it to the receiving end, and maintain the stable state of the signal. Specifically, the stable state of the signal can be maintained by continuously receiving the delay signal of the parallel data address signal and selectively outputting it.

[0133] In the embodiment of the present disclosure, the transmission mode conversion circuit is implemented as a serial-to-parallel conversion circuit. Through the serial-to-parallel conversion module in the transmission mode conversion circuit, the serial data signal can be efficiently converted into a parallel format, thereby significantly improving the speed and efficiency of data transmission. Moreover, the stable output of the converted data content signal and data address signal is ensured by the first selector and the second selector.

[0134] Those skilled in the art can understand that during the circuit design stage, it is possible to determine whether to select the output port of the data address signal as needed, to achieve the multiplexing of the transmission mode conversion circuit, thereby reducing the design workload and verification complexity of the serial-to-parallel conversion circuit.

[0135] In a possible implementation manner, the data conversion module includes: a third delay register; the third delay register is used to delay the data content signal output by the first selector, input the delayed data content signal into the first selector, and delay the data address signal output by the second selector, and input the delayed data address signal into the second selector; the first selector selects between the parallel data content signal output by the serial-to-parallel conversion flip-flop and the delayed data content signal, and inputs the output parallel data content signal into the third delay register again for delay, so as to maintain the output parallel data content signal to the data output port; the second selector selects between the parallel data address signal output by the serial-to-parallel conversion flip-flop and the delayed data address signal, and inputs the output parallel data address signal into the third delay register again for delay, so as to maintain the output parallel data address signal to the data output port.

[0136] In this implementation manner, a third delay register is further included in the data conversion module to enhance the stability and synchronization of data transmission. In a data transmission system, in order to ensure the accurate transmission of data and the stable operation of the system, appropriate delay processing can be performed on the data.

[0137] The third delay register can delay the data content signal output by the first selector, and also perform the same delay operation on the data address signal output by the second selector. The duration of the specific delay operation can be determined according to the actual situation. For example, it can be one clock cycle, and the present disclosure does not limit this. Then the delayed signal is fed back to the respective selectors again so that the selectors output the delayed signal.

[0138] Specifically, the first selector selects between the parallel data content signal directly output by the serial-to-parallel conversion flip-flop and the data content signal after being delayed by the third delay register. The output data content signal is sent to the third delay register again for a new round of delay, and then re-input to the first selector after the delay. Such cyclic operation ensures that the data content signal can continuously output from the data output port, which helps to eliminate signal jitter and maintain the stability of the data content signal.

[0139] Similarly, the second selector also makes a selection between the parallel data address signal output by the serial-to-parallel conversion flip-flop and the delayed data address signal, and sends the selected data address signal to the third delay register again for delay, so as to maintain the stable output of the data address signal.

[0140] In the embodiment of the present disclosure, by introducing the third delay register to delay the data content signal and the data address signal to be output, and continuously outputting the delayed data content signal and data address signal through the first selector and the second selector, the stable output of the data content signal and the data address signal is achieved, and the stability of the output data is improved.

[0141] In a possible implementation manner, the third delay register is used to delay the write control signal input from the selected control signal input port to obtain a delayed write control signal; the control signal generation module includes: a third AND gate, which is used to perform an AND operation on the inverted signal of the input write control signal and the delayed write control signal to obtain a first pulse signal, and use the first pulse signal as the selection signal of the first selector to input to the first selector; and output the first pulse signal as the read-write control signal through the control signal output port; the first selector, when the first pulse signal is at a high level, selects and outputs the parallel data content signal output by the serial-to-parallel conversion flip-flop; after the first pulse signal drops to a low level, selects and outputs the delayed data content signal output by the third delay register.

[0142] In this implementation manner, the third delay register not only delays the data signal, but also can delay the write control signal input from the selected control signal input port. The specific delay duration can be determined according to the actual situation, and the present disclosure does not limit this. For example, it can be a one-clock cycle delay. Thus, the timing of the write operation can be controlled more precisely, thereby ensuring the stability and accuracy of the data during the read-write process.

[0143] The control signal generation module further includes a third AND gate. The third AND gate receives two input signals: one is the inverted signal of the write control signal, and the other is the write control signal after being delayed by the third delay register. These two signals generate a first pulse signal through an AND operation. The first pulse signal has specific timing characteristics. This signal is at a high level for a short period of time (the duration of the high level is the same as the delay duration, if the delay is 1 clock cycle, the high level lasts for 1 clock cycle) after the write control signal jumps from a low level to a high level (i.e., the write operation starts), and then quickly drops to a low level.

[0144] The functions of the first pulse signal are reflected in two aspects: one is as the selection signal of the first selector to control the output of the first selector; the other is as the read-write control signal, which is output through the control signal output port so that the receiving end can sense the start of the read-write operation (read operation or write operation).

[0145] Specifically, the first selector selects the output signal according to the level state of the first pulse signal. When the first pulse signal is at a high level, the first selector selects the parallel data content signal output by the serial-parallel conversion flip-flop for output. Then, at the start of the write operation, the system can immediately obtain the latest data content signal; when the first pulse signal drops to a low level, the selector switches to select the delayed data content signal output by the third delay register for output, so that after the write control signal changes, the system can still maintain the stable output of the data content signal for a period of time, reducing the transient errors caused by signal conversion.

[0146] In the embodiment of the present disclosure, the write control signal input through the selected control signal input port is delayed by the third delay register to obtain the delayed write control signal. Through the third AND gate, an AND operation is performed on the inverted signal of the input write control signal and the delayed write control signal to obtain the first pulse signal, and the first pulse signal is output as the read-write control signal through the control signal output port, realizing the precise control of the write operation timing, and improving the stability and accuracy of data during the read-write process. At the same time, the first pulse signal is input to the first selector as the selection signal of the first selector, so that the circuit can immediately output the latest data content signal at the start of the write operation and maintain the stable output of the data content signal for a period of time, thereby improving the reliability and efficiency of data transmission.

[0147] In a possible implementation, the third delay register is configured to delay the target peripheral selection signal input through the selected control signal input port to obtain a delayed target peripheral selection signal; the control signal generation module includes: a fourth AND gate, configured to perform an AND operation on the inverted signal of the input target peripheral selection signal and the delayed target peripheral selection signal to obtain a second pulse signal, and use the second pulse signal as the selection signal of the second selector and input it to the second selector; the second selector is configured to select and output the parallel data address signal output by the serial-parallel conversion flip-flop when the second pulse signal is at a high level; after the second pulse signal drops to a low level, it selects and outputs the delayed data address signal output by the third delay register.

[0148] In this implementation, the third delay register not only delays the write control signal, but also can delay the target peripheral selection signal input through the selected control signal input port, so as to obtain a delayed target peripheral selection signal. The specific delay duration can be determined according to the actual situation, and the present disclosure does not limit this, for example, it can be a delay of one clock cycle. Thereby, the timing of the write operation can be controlled more precisely, ensuring the stability and accuracy of data during the read and write processes.

[0149] The control signal generation module also includes a fourth AND gate. The input signals received by the fourth AND gate include: the inverted signal of the target peripheral selection signal, and the target peripheral selection signal after being delayed by the third delay register. The second pulse signal is generated by performing an AND operation (AND operation) on these two signals. The second pulse signal has specific timing characteristics. This signal is at a high level for a short period of time (the duration of the high level is the delay duration, if the delay is 1 clock cycle, the duration of the high level is 1 clock cycle) after the target peripheral selection signal jumps from a low level to a high level, and then quickly drops to a low level.

[0150] The second pulse signal can be used as the selection signal of the second selector. Specifically, the second selector selects the output signal according to the level state of the second pulse signal. When the second pulse signal is at a high level, the second selector selects and outputs the parallel data address signal output by the serial-parallel conversion flip-flop. That is, at the moment when the target peripheral is selected, the circuit can immediately output the latest data address signal.

[0151] When the second pulse signal drops to a low level, the second selector then selects and outputs the delayed data address signal output by the third delay register. This enables the circuit to still maintain a stable output of the data address signal for a period of time, reducing positioning errors or data access errors caused by signal conversion.

[0152] In the embodiments of the present disclosure, the target peripheral selection signal is delayed by a third delay register, and a second pulse signal is generated in combination with a fourth AND gate, achieving precise control over the timing of the target peripheral selection signal. Meanwhile, using the second pulse signal as the selection signal of a second selector enables the circuit to immediately output the latest data address signal at the moment the target peripheral is selected and maintain a stable output of the data address signal for a period of time, improving the reliability and stability of data transmission.

[0153] In a possible implementation manner, the third delay register is configured to delay the second pulse signal output by the fourth AND gate to obtain a delayed second pulse signal; the control signal generation module includes: an OR gate, configured to perform an OR operation on the second pulse signal and the delayed second pulse signal to obtain a third pulse signal, and output the third pulse signal as a peripheral selection signal through a control signal output port.

[0154] In this implementation manner, the third delay register is used to further delay the second pulse signal output by the fourth AND gate, thereby obtaining a delayed second pulse signal. By introducing a time delay to the second pulse signal, the timing characteristics of the subsequent generated peripheral selection signal are adjusted or optimized to meet specific system requirements or resolve potential timing conflicts.

[0155] The control signal generation module further includes an OR gate. The input signals received by this OR gate include: the original second pulse signal, and the second pulse signal delayed by the third delay register. A third pulse signal is generated by performing an OR operation (OR operation) on these two signals. The function of the OR gate here is that at any moment, as long as one of the input signals is at a high level, the output signal will be at a high level. Then, the obtained third pulse signal will cover the high-level time periods in the second pulse signal and its delayed version, thereby forming a wider high-level pulse.

[0156] The third pulse signal obtained through the processing of the OR gate can be used as a peripheral selection signal and output through a control signal output port. In this way, the peripheral can be accurately selected and controlled based on this third pulse signal that combines the characteristics of the original and delayed pulses.

[0157] In the embodiments of the present disclosure, the third delay register and the OR gate are cleverly utilized. By delaying the second pulse signal and performing an OR operation on the second pulse signal and the delayed second pulse signal, a third pulse signal with specific timing characteristics is generated as a peripheral selection signal. By adjusting the delay duration of the third delay register, the high-level duration of the peripheral selection signal can be finely controlled to adapt to different peripheral response times and system timing requirements, improving the accuracy and reliability of peripheral selection and control.

[0158] In a possible implementation, the third delay register is configured to delay the second pulse signal and output the delayed second pulse signal as a transmission control signal through a control signal output port.

[0159] In this implementation, the input of the third delay register is connected to the output of the third AND gate, and the third delay register receives the second pulse signal from the third AND gate as an input. The third delay register delays the second pulse signal, shifting the input pulse backward in time by a predetermined duration. This delay duration can be set according to actual requirements.

[0160] The delayed second pulse signal is then used as a transmission control signal and output through the control signal output port. This transmission control signal is obtained by adjusting the timing of the second pulse signal to meet the timing requirements of data transmission. The transmission control signal is used to synchronize the start and end of data transmission.

[0161] In the embodiments of the present disclosure, by adjusting the delay duration of the third delay register, the high-level duration of the transmission control signal can be precisely controlled so that the signal is in timing synchronization with other signals in the circuit, thereby maintaining the accuracy and reliability of data transmission.

[0162] In a possible implementation, the control signal generation module includes: a transmission completion signal generation module, configured to generate a target data transmission completion signal based on the received original data transmission completion signal, as well as the read / write control signal and the peripheral selection signal generated by the control signal generation module. The target data transmission completion signal is used to indicate that the data signal of the target transmission mode has been transmitted.

[0163] In this implementation, the control signal generation module includes a transmission completion signal generation module, which can generate a target data transmission completion signal based on the received multiple signals. This signal is used to indicate to the receiving end that the data signal has been transmitted.

[0164] The input signals received by the transmission completion signal generation module include:

[0165] Original data transmission completion signal: This signal can come from the top layer of the circuit board and is used to indicate the completion of data transmission.

[0166] Read / write control signal: This signal is generated by the third AND gate of the control signal generation module and is used to control the read / write operation of data.

[0167] Peripheral selection signal: This signal is generated by the OR gate of the control signal generation module and is used to select a specific peripheral for data transmission.

[0168] Based on these three input signals, the transmission completion signal generation module can perform a series of logical processes. For example, analyze the timing of the read / write control signal and the peripheral selection signal to determine the exact start and end times of data transmission; monitor the status of the original data transmission completion signal to confirm whether a certain stage of data transmission has been completed; combine the results of timing analysis and status detection to comprehensively judge whether the target data transmission has been completed.

[0169] Based on the above analysis, the transmission completion signal generation module outputs a target data transmission completion signal, which indicates that the data signal has been successfully transmitted from the source end to the target end.

[0170] In the embodiment of the present disclosure, by generating a target data transmission completion signal based on multiple input signals through the transmission completion signal generation module, it is possible to accurately and reliably monitor and indicate the completion status of data transmission, accurately grasp the progress and status of data transmission, thereby improving the integrity and reliability of data transmission.

[0171] Figure 3 Fig. shows a schematic diagram of an actual application scenario of a serial-to-parallel conversion circuit provided by the present disclosure. The serial-to-parallel conversion circuit includes: a serial-to-parallel conversion flip-flop, a first selector, a second selector, a third AND gate, a fourth AND gate, an OR gate, a third delay register, a transmission completion signal generation module, and a fourth counter.

[0172] Among them, the input ports of the circuit include: ports for inputting the clock signal clk, the data content signal pwdata_di, the data address signal paddr_di, the read control signal rd_rdy, the target peripheral selection signal sel_rdy, and the original data transmission completion signal rd_clr. The output ports include: ports for outputting the transmission control signal s2p_penable, the read / write control signal s2p_pwrite, the peripheral selection signal s2p_psel, the target data transmission completion signal s2p_rd_vld, the data content signal s2p_pwdata, and the data address signal s2p_paddr

[0173] For the above ports, they can be selected according to actual requirements during circuit design.

[0174] In this serial-to-parallel conversion circuit, the clock signal clk is input through the clock signal input port to provide a timing reference for the entire circuit.

[0175] The data content signal pwdata_di and the data address signal paddr_di of the input port first enter the serial-to-parallel conversion module. The serial-to-parallel conversion flip-flop converts the serial pwdata_di to obtain the parallel data content signal wdata_tmp; the serial-to-parallel conversion flip-flop converts the serial paddr_di to obtain the parallel data address signal addr_tmp.

[0176] The parallel data content signal wdata_tmp enters the first selector; the parallel data address signal addr_tmp enters the second selector.

[0177] The third delay register delays the data content signal s2p_pwdata output by the first selector to obtain the delayed data content signal s2p_pwdata_ff.

[0178] The third delay register delays the data address signal s2p_paddr output by the second selector to obtain the delayed data address signal s2p_paddr_ff.

[0179] Then, the selector and the third delay register form a feedback loop circuit:

[0180] The first selector selects between wdata_tmp output by the serial-to-parallel conversion flip-flop and s2p_pwdata_ff, and again inputs the selected parallel data content signal s2p_pwdata into the third delay register for delay, and finally maintains the output to the data output port.

[0181] The second selector selects between addr_tmp output by the serial-to-parallel conversion flip-flop and s2p_paddr_ff, and again inputs the selected parallel data address signal s2p_paddr into the third delay register for delay, and finally maintains the output to the data output port.

[0182] The write control signal wr_rdy enters the third delay register to obtain the delayed write control signal denoted as wr_rdy_ff.

[0183] The third AND gate performs an AND operation on the inverted signal of the input wr_rdy and the delayed wr_rdy_ff to obtain the first pulse signal wr_rdy_fall, and uses wr_rdy_fall as the selection signal of the first selector, and at the same time outputs wr_rdy_fall as the read / write control signal s2p_pwrite.

[0184] The target peripheral selection signal sel_rdy enters the third delay register to obtain the delayed target peripheral selection signal denoted as sel_rdy_ff.

[0185] The fourth AND gate performs an AND operation on the inverted signal of the input sel_rdy and the delayed sel_rdy_ff to obtain the second pulse signal sel_rdy_fall, and uses sel_rdy_fall as the selection signal of the second selector.

[0186] The third delay register delays the second pulse signal sel_rdy_fall output by the fourth AND gate to obtain the delayed second pulse signal sel_rdy_fall_ff.

[0187] The OR gate performs an OR operation on wr_rdy_fall and the delayed sel_rdy_fall_ff to obtain the third pulse signal sel_rdy_out, and outputs sel_rdy_out as the peripheral selection signal s2p_psel.

[0188] The third delay register delays wr_rdy_fall and outputs the delayed wr_rdy_fall as the transfer control signal s2p_penable.

[0189] The transfer completion signal generation module receives the original data transfer completion signal rd_clr, the read / write control signal s2p_pwrite, and the peripheral selection signal s2p_psel. Based on these signals, the transfer completion signal generation module generates the target data transfer completion signal s2p_rd_vld.

[0190] In addition, the serial-to-parallel conversion circuit may further include a fourth counter for counting the serial-to-parallel conversion process. This counting does not participate in the generation of signals and is only for counting.

[0191] Figure 4 FIG. shows a schematic diagram of an actual application scenario of a transmission mode conversion circuit provided by the present disclosure. In this application scenario, the data transmission mode conversion circuit provided by the present disclosure can be applied to a system with a master-slave structure. The system includes a master device and a slave device. The master device needs to send data and addresses to the slave device for data processing and read back the data processed by the slave device (without an address). The data between the master device and the slave device is transmitted in a serial manner, while the data inside the master device or between the master device and the bus is transmitted in a parallel manner, and the data inside the slave device or between the slave device and the bus is transmitted in a parallel manner. In the initial stage of circuit design, according to the above requirements, different data ports in the gated transmission mode conversion circuit can be selected to achieve this.

[0192] To meet the requirement of the master device to transfer data to the slave device, the master device needs to transfer the data content signal and the data address signal, and convert the parallel transmission mode to the serial transmission mode. Therefore, the ports of pwdata_do and paddr_do can be selected in the parallel-to-serial conversion circuit. Since the data is written to the slave device, the port of the read control signal wr_rdy needs to be selected. In addition, the port of the target peripheral selection signal sel_rdy also needs to be selected to enable the slave device, while prdata_do and rd_rdy are left floating. The input port can be connected to the bus, where rst is the reset signal. Thus, the first parallel-to-serial conversion circuit is generated.

[0193] Based on the data reception requirement of the slave device, the ports for receiving the data content signal pwdata_di and the data address signal paddr_di, as well as the port for receiving the write control signal wr_rdy, need to be selected in the serial-to-parallel conversion circuit. In addition, the port of the target peripheral selection signal sel_rdy also needs to be selected. The clock signal clk, the reset signal rst, and the original data transfer completion signal rd_clr are sent from the top layer of the circuit board through the bus, which is not shown in the figure. The output port can be connected to the bus. Thus, the first serial-to-parallel conversion circuit is generated.

[0194] After the slave device receives the data and finishes processing it, the master device needs to read back the read-back data in the slave device. At this time, the conversion between the parallel transmission mode and the serial transmission mode also needs to be implemented. The read-back data does not require address data. Therefore, prdata_do can be selected in the parallel-to-serial conversion circuit. In addition, the port of the read control signal rd_rdy needs to be selected to indicate that the transmitted data is the read-back data, and the sel_rdy port also needs to be selected to enable the master device, while pwdata_do, paddr_do, and wr_rdy are left floating. The output port can be connected to the bus. Thus, the second parallel-to-serial conversion circuit is generated.

[0195] Based on the data reception requirement of the master device, the port for receiving the data content signal pwdata_di, as well as the ports of rd_rdy and sel_rdy, need to be selected in the serial-to-parallel conversion circuit. It should be noted that in the serial-to-parallel conversion circuit, the port of wr_rdy is used to receive the rd_rdy or wr_rdy signal to reduce the number of ports. The port of paddr_di is left floating, and the output port can be connected to the bus. Thus, the second serial-to-parallel conversion circuit is generated.

[0196] In this implementation method, the first parallel-to-serial conversion circuit and the second parallel-to-serial conversion circuit are the reuse of the same parallel-to-serial conversion circuit, only the selected data ports are different; the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit are the reuse of the same serial-to-parallel conversion circuit, only the selected data ports are different.

[0197] After the circuit is manufactured and put into use, the first parallel-to-serial conversion circuit formed based on the gated write data port and data address port can convert the parallel data signal and address signal to be sent by the master device into serial signals. The master device sends the converted serial data signal and address signal to the slave device through the gated write data port and data address port. After receiving these signals, the slave device converts them back into parallel data signals and address signals through the first serial-to-parallel conversion circuit and performs data processing.

[0198] After the slave device finishes processing the data, the second parallel-to-serial conversion circuit formed based on the gated read data port can convert the parallel read-back data to be sent by the slave device into a serial signal, and send the converted serial data signal to the master device through the gated read data port. After receiving these signals, the master device converts them back into parallel data signals through the second serial-to-parallel conversion circuit and performs subsequent processing.

[0199] Figure 5 The figure shows a schematic diagram of an actual application scenario of another transmission mode conversion circuit provided by the present disclosure. This application scenario is for monitoring and testing the performance of semiconductor circuit units. The master device sends test input data for chip performance testing to the slave device. The slave device tests the chip based on the test input data. Specifically, it monitors and tests the performance of different basic circuit units in the semiconductor process based on the RODFF test circuit composed of a ring oscillator (RO) and a D flip-flop (DFF), and obtains test result data (read-back data).

[0200] The data transmission mode conversion circuit provided by the present disclosure can be applied to a master-slave structure. In this application scenario, the parallel-to-serial conversion circuit (P2S) at the Master end converts the parallel bus data into serial data and transmits it to the Slave end. The serial-to-parallel conversion (S2P) circuit at the Slave end converts the received serial data back into parallel data and inputs it into the RODFF test circuit for testing. After the test is completed, the P2S circuit at the Slave end converts the read-back data from parallel bus data into serial data and transmits it back to the Master end. Then, the S2P circuit at the Master end converts the received serial data back into parallel bus data for further processing and analysis by the test system.

[0201] In this application scenario, the parallel-to-serial conversion circuits of the master device and the slave device can reuse the parallel-to-serial conversion circuit as shown in Figure 2 The specific gated ports are as follows:

[0202] Master-side P2S: The parallel bus data is converted into serial data through P2S. The data is output from the wdata_do port of the P2S module, the address bits are output from addr_do, wr_rdy indicates that writing data is valid, and sel_rdy indicates the peripheral selection signal. rdata_do and rd_rdy are left floating.

[0203] Slave-side P2S: wdata_do, addr_do, and wr_rdy are left floating. p2s_pwdata obtains the read-back data processed by RODFF, and then transmits it serially from prdata_do. rd_rdy indicates that reading data is valid, and sel_rdy indicates the peripheral selection signal.

[0204] In this application scenario, the serial-to-parallel conversion circuits of the master device and the slave device can share the same serial-to-parallel conversion circuit, except for the selected ports. The specific selected ports are as follows:

[0205] Slave-side S2P: The serial data transmitted from the master-side P2S needs to be converted into the parallel bus of the slave side and input to RODFF for testing after arriving at the slave side. The transmitted wdata_do, addr_do, wr_rdy, and sel_rdy are connected to the serial interface of the slave-side S2P module, and then s2p_write / s2p_wdata / s2p_addr / s2p_sel / s2p_enable are output to the RODFF parallel bus for testing.

[0206] Master-side S2P: pwdata_di receives the read-back data transmitted back from the prdata_do of RODFF, and wr_rdy is connected to the port rd_rdy of the read control signal returned by RODFF. After serial-to-parallel conversion, s2p_psel, s2p_penable, s2p_pwrite, and s2p_paddr do not need to be connected and can be left floating (only s2p_pwdata and s2p_rd_vld need to be connected).

[0207] In addition, the data transmission mode conversion circuit provided by the present disclosure can also be applied to a system with a multi-master - multi-slave device structure. For example, the system can include 4 master devices, each master device is connected to two slave devices, data is transmitted serially between the master device and the slave device, data is transmitted between the master device and the bus in parallel, and data is transmitted between the slave device and the bus in parallel. The circuit connection between the master device and the slave device can refer to Figure 5 the circuit shown, which will not be elaborated here.

[0208] According to one aspect of the present disclosure, there is provided an electronic device including the above-mentioned transmission mode conversion circuit provided by the present disclosure.

[0209] Other components of the chip or electronic device in the above embodiments can adopt various technical solutions known to those of ordinary skill in the art now and in the future, which will not be described in detail here.

[0210] The embodiments of the present disclosure have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technologies in the market, or to enable other ordinary skill in the art in the technical field to understand the disclosed embodiments.

[0211] In the description of this specification, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present disclosure.

[0212] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0213] In the present disclosure, unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or a communication connection; it may be directly connected, or indirectly connected through an intermediate medium, and may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0214] In this disclosure, unless otherwise clearly specified or limited, the first feature being "on" or "under" the second feature may include direct contact between the first and second features, or may include contact between the first and second features not being direct but through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the horizontal height of the first feature is less than that of the second feature.

[0215] The foregoing disclosure provides many different embodiments or examples for implementing different structures of the present disclosure. To simplify the disclosure of the present disclosure, components and settings of specific examples are described above. Of course, they are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0216] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of various changes or substitutions thereof, and these should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A transmission mode conversion circuit, characterized in that: include: Data conversion module, control signal generation module; A plurality of data input ports and a plurality of data output ports connected to the data conversion module, for transmitting different types of data signals; a plurality of control signal input ports and a plurality of control signal output ports connected to the control signal generation module, for transmitting different types of control signals; The data conversion module is used to convert the data signal of the original transmission mode inputted from the selected data input port, generate the data signal of the target transmission mode, and output it from the selected data output port; wherein the unselected data input port and the data output port are left hanging; The control signal generating module is used to generate multiple target control signals according to the original control signal inputted by the selected control signal input port, and output them through the selected control signal output port, wherein the unselected control signal input port and control signal output port are left floating.

2. The circuit according to claim 1, characterized in that The data conversion module includes: a parallel-to-serial conversion module, which is used to convert the data signal transmitted in parallel to generate a data signal transmitted in serial; The parallel-to-serial conversion module comprises: A write data conversion module is used to convert parallel write data to obtain a serial write data signal and output it through a write data port; A read data conversion module is used to convert parallel read data to obtain a serial read data signal and output it through a read data port; The data address conversion module is used to convert the parallel data addresses to obtain serial data address signals and output them through the data address port.

3. The circuit according to claim 2, characterized in that The original control signals inputted by the control signal input port include: read-write control signals, peripheral selection signals and transmission control signals; The control signal generating module comprises: a first AND gate and a second AND gate; The first AND gate is used to perform an AND operation on the read / write control signal, the peripheral selection signal and the transmission control signal to obtain a read data output signal, and the read data output signal is used to control the read data conversion module to perform an operation; The second AND gate is used to perform an AND operation on the inverted signal of the read / write control signal, the peripheral selection signal and the transmission control signal to obtain a write data output signal, and the write data output signal is used to control the write data conversion module to perform an operation.

4. The circuit according to claim 3, characterized in that The target control signals output by the control signal output port include: a read control signal, a write control signal and a target peripheral selection signal; The control signal generating module comprises: a read control signal generating module, a write control signal generating module and a target peripheral selection signal generating module; The read control signal generating module is used to start generating the read control signal output when receiving the read data output signal, and start counting of the first counter, and stop generating the read control signal when the first counter is full; The write control signal generating module is used to start generating the write control signal output when receiving the write data output signal, and start counting of the second counter, and stop generating the write control signal when the second counter is full; The target peripheral selection signal generating module is used to start generating the target peripheral selection signal output when receiving the peripheral selection signal, and start counting of the third counter. When the third counter is full, the generation of the target peripheral selection signal is stopped, wherein the full value is the number of bits of the received parallel transmission data signal minus 1.

5. The circuit according to claim 4, characterized in that The control signal generating module comprises: a first delay register and a second delay register; The first delay register is connected to the input ends of the first AND gate and the second AND gate, and is used to delay the input read / write control signal, and input the delayed read / write control signal to the first AND gate and the second AND gate respectively; The second delay register is connected to the output ends of the first AND gate and the second AND gate, and is used to delay the read data output signal, the write data output signal and the target peripheral selection signal, and transmit the delayed read data output signal to the read control signal generation module, transmit the delayed write data output signal to the write control signal generation module, and transmit the delayed target peripheral selection signal to the target peripheral selection signal generation module.

6. The circuit according to claim 1, characterized in that The data conversion module includes: a serial-to-parallel conversion module, which is used to convert the serially transmitted data signal to generate a parallelly transmitted data signal; the serially transmitted data signal includes a data content signal and a data address signal; The serial-to-parallel conversion module includes: a serial-to-parallel conversion trigger, a first selector, and a second selector; The serial-to-parallel conversion trigger is used to convert a serial data content signal to obtain a parallel data content signal, and to convert a serial data address signal to obtain a parallel data address signal; The first selector is used to output and maintain the parallel data content signal; The second selector is used to output and maintain the parallel data address signal.

7. The circuit according to claim 6, characterized in that The data conversion module comprises: a third delay register; The third delay register is used to delay the data content signal output by the first selector and input the delayed data content signal into the first selector, and to delay the data address signal output by the second selector and input the delayed data address signal into the second selector; The first selector selects between the parallel data content signal and the delayed data content signal output by the serial-to-parallel conversion trigger, and inputs the output parallel data content signal into the third delay register again for delay, so as to keep outputting the parallel data content signal to the data output port; The second selector selects between the parallel data address signal output by the serial-to-parallel conversion trigger and the delayed data address signal, and inputs the output parallel data address signal into the third delay register again for delay, so as to keep outputting the parallel data address signal to the data output port.

8. The circuit according to claim 7, characterized in that The third delay register is used to delay the write control signal input from the selected control signal input port to obtain a delayed write control signal; The control signal generating module includes: a third AND gate, used for performing an AND operation on the inverted signal of the input write control signal and the delayed write control signal to obtain a first pulse signal, and inputting the first pulse signal into the first selector as the selection signal of the first selector; and outputting the first pulse signal as a read-write control signal through a control signal output port; The first selector selects the parallel data content signal output by the serial-to-parallel conversion trigger for output when the first pulse signal is at a high level; and selects the delayed data content signal output by the third delay register for output after the first pulse signal drops to a low level.

9. The circuit according to claim 8, characterized in that The third delay register is used to delay the target peripheral selection signal input from the selected control signal input port to obtain the delayed target peripheral selection signal; The control signal generating module includes: a fourth AND gate, used for performing an AND operation on the inverted signal of the input target peripheral selection signal and the delayed target peripheral selection signal to obtain a second pulse signal, and inputting the second pulse signal into the second selector as the selection signal of the second selector; The second selector selects the parallel data address signal output by the serial-to-parallel conversion trigger for output when the second pulse signal is at a high level; and selects the delayed data address signal output by the third delay register for output after the second pulse signal drops to a low level.

10. The circuit according to claim 9, characterized in that The third delay register is used to delay the second pulse signal output by the fourth AND gate to obtain a delayed second pulse signal; The control signal generating module includes: an OR gate for performing an OR operation on the second pulse signal and the delayed second pulse signal to obtain a third pulse signal, and outputting the third pulse signal as a peripheral selection signal through a control signal output port.

11. The circuit according to claim 9, characterized in that The third delay register is used to delay the second pulse signal and output the delayed second pulse signal as a transmission control signal through the control signal output port.

12. The circuit according to claim 10, characterized in that The control signal generating module comprises: a transmission completion signal generating module, which is used to generate a target data transmission completion signal based on the received original data transmission completion signal, and the read / write control signal and the peripheral selection signal generated by the control signal generating module, wherein the target data transmission completion signal is used to indicate that the data signal of the target transmission mode has completed transmission.

13. A chip, characterized in that: Comprising the circuit as claimed in claims 1 to 12.

14. An electronic device, characterized in that: Comprising the circuit as claimed in claims 1 to 12.

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