Driving circuit

Abstract

The invention provides a driving circuit. The driving circuit comprises a switching circuit and a source driving circuit. The switching circuit is used for receiving input display data according to the two control signals and outputting output display data. The input display data and the output display data have different data arrangements. The source driving circuit is coupled to the switching circuit. The source driving circuit is used for outputting the output display data through the switching circuit so as to drive the display panel. The application timing of the two control signals is adjusted according to at least one adjustment signal, and the two control signals are applied to the switching group of the switching circuit according to the application timing.

Description

Technical Field

[0001] The present invention relates to a driving circuit. Background Art

[0002] An electronic device with a display function generally includes a display panel and a driving chip. The driving chip is used to drive the display panel to display an image. The driving chip is connected to the display panel through a fan-out region to output display data to drive the display panel. In order to reduce the length of the fan-out region between the driving chip and the display panel, the extended connection lines of the display panel may be arranged in the active region of the display panel. However, in order for the driving chip to drive the display panel with such a layout, the data timing output to the display panel must be changed so that the display data can correctly drive the pixels on the display panel. Summary of the Invention

[0003] The present invention provides a driving circuit that can rearrange display data to adaptively drive a display panel. In addition, the length of the fan-out region can also be reduced.

[0004] The driving circuit according to an embodiment of the present invention includes a switching circuit and a source driving circuit. The switching circuit is used to receive input display data and output output display data according to two control signals. The input display data and the output display data have different data arrangements. The source driving circuit is coupled to the switching circuit. The source driving circuit is used to output the output display data through the switching circuit to drive the display panel. The application timing of the two control signals is adjusted according to at least one adjustment signal, and the two control signals are applied to the switch group of the switching circuit according to the application timing.

[0005] To better understand the foregoing content, several embodiments accompanied by drawings are described in detail below. Brief Description of the Drawings

[0006] Figure 1 A schematic diagram showing an electronic device according to an embodiment of the present invention.

[0007] Figure 2 Showing Figure 1 A circuit diagram of the electronic device according to the embodiment.

[0008] Figure 3 Showing Figure 2 A schematic diagram of the fan-out region between the driving circuit according to the embodiment and the display panel.

[0009] Figure 4 A schematic diagram showing the driving circuit and the display panel according to an embodiment of the present invention.

[0010] Figure 5 A schematic diagram showing the adjustment of the control signals MUX1 and MUX2 according to an embodiment of the present invention.

[0011] Figure 6A An example of the control signal MUX1 in the embodiment of the present invention turning on the corresponding switch.

[0012] Figure 6B An example of the control signal MUX2 in the embodiment of the present invention turning on the corresponding switch.

[0013] Figure 7 A schematic diagram showing the adjustment of the control signals MUX1 and MUX2 in another embodiment of the present invention.

[0014] Figure 8 A schematic diagram showing the adjustment of the control signals MUX1 and MUX2 in another embodiment of the present invention.

[0015] Figure 9 A schematic diagram showing the adjustment of the control signals MUX1 and MUX2 in another embodiment of the present invention.

[0016] Explanation of the reference numerals in the drawings

[0017] 100: Electronic device

[0018] 110, 410, 510: Driving circuit

[0019] 116, 416: Source driving circuit

[0020] 117_1, 417_1, 717_1, 817_1, 917_1: First switch unit

[0021] 117_2, 417_2, 717_2, 817_2, 917_2: Second switch unit

[0022] 117, 417: Switch circuit

[0023] 120, 420: Display panel

[0024] 130: Fan-out area

[0025] 601, 602, 603, 604: Switch

[0026] CTRm, CTRdm: Adjustment signal

[0027] D1, D3, D4, D6, D71, D72, D73, D74, D75, D76, D81, D82, D83, D84, D85, D86, D91, D92, D93, D94, D95, D96: Data group

[0028] DD_IN: Input display data

[0029] DD_OUT: Output display data

[0030] DL: Data line

[0031] L: Length

[0032] MUX1, MUX2: Control signal

[0033] P1, P2, P3, P4, P5, P6, P7, P8: Position

[0034] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12: Source pad

[0035] SW_1, SW_2, SW_3, SW_4, SW_5, SW_6, SW_71, SW_72, SW_73, SW_81, SW_82, SW_83, SW_91, SW_92, SW_93: Switch group Detailed implementation manner

[0036] Embodiments are provided below to describe the present invention in detail. However, the present invention is not limited to the provided embodiments, and the provided embodiments can be appropriately combined. The terms "coupling / coupled" or "connecting / connected" used in the specification (including the claims) of this application can refer to any direct or indirect connection method. For example, "the first device is coupled to the second device" should be interpreted as "the first device is directly connected to the second device" or "the first device is indirectly connected to the second device through other devices or connection components". Additionally, the term "signal" can refer to current, voltage, charge, temperature, data, electromagnetic wave, or any one or more signals.

[0037] Figure 1 Schematic diagram of an electronic device showing an embodiment of the present invention. Figure 2 Show Figure 1 Circuit diagram of the electronic device of the embodiment. Refer to Figure 1 And Figure 2 , the electronic device 100 includes a driving circuit 110 and a display panel 120. The driving circuit 110 can be used to be coupled to the display panel 120. The display panel 120 can be a self-emitting display panel, such as an organic light-emitting diode (OLED) panel, but the present invention is not limited thereto.

[0038] The driving circuit 110 is used to drive the display panel 120 to display an image. The driving circuit 110 includes a source driving circuit 116 and a switching circuit 117. The source driving circuit 116 is used to output driving signals to drive the display panel 120 to display an image. The switching circuit 117 includes a first switching unit 117_1 and a second switching unit 117_2. The first switching unit 117_1 and the second switching unit 117_2 are respectively disposed at the output end and the input end of the source driving circuit 116. The first switching unit 117_1 and the second switching unit 117_2 are controlled by control signals MUX1 and MUX2 to rearrange the received display data to the corresponding data lines DL.

[0039] In an embodiment, the switches of the first switching unit 117_1 and the second switching unit 117_2 can be implemented by metal oxide semiconductor field effect transistors (MOSFETs). The MOSFETs on the driving circuit 110 (such as a display driver integrated circuit (DDIC)) have the characteristics of a low operating voltage, a low on-resistance, and a low power consumption.

[0040] The driving circuit 110 may include a controller circuit (not shown) to generate the control signals MUX1 and MUX2. The controller circuit can be a processor with computing capabilities. Alternatively, the controller circuit can be designed by a hardware description language (HDL) or any other digital circuit design method familiar to those skilled in the art, and can be implemented as a hardware circuit by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC). In addition, the hardware structure of the controller circuit can obtain sufficient teachings, suggestions, and implementation descriptions with reference to the common general knowledge of related technologies. In another embodiment, the controller circuit can be disposed in the application processor of the electronic device 100.

[0041] In this embodiment, the electronic device 100 may be an electronic device having a display function, a touch sensing function, and / or a fingerprint sensing function. In an embodiment, the electronic device 100 may be, but is not limited to, a smart phone, a non-smart phone, a wearable electronic device, a tablet computer, a personal digital assistant, a notebook computer, and other portable electronic devices that can operate independently and have a display function, a touch sensing function, and / or a fingerprint sensing function. In an embodiment, the electronic device 100 may be, but is not limited to, a portable or non-portable electronic device in a vehicle intelligent system. In an embodiment, the electronic device 100 may be, but is not limited to, smart household appliances, such as a television, a computer, a refrigerator, a washing machine, a telephone, an induction cooker, a table lamp, etc.

[0042] Figure 3 illustrate Figure 2 Schematic diagram of the fan-out region between the driving circuit and the display panel of the embodiment. Refer to Figure 3 , in this embodiment, the driving circuit 110 is connected to the display panel 120 through the fan-out region 130, but the present invention is not limited thereto. In an embodiment, an electrostatic discharge (ESD) protection circuit and a bendable region may be configured between the driving circuit 110 and the display panel 120.

[0043] In this embodiment, since both the first switch unit 117_1 and the second switch unit 117_2 for data rearrangement are configured in the driving circuit 110, the length L of the fan-out region 130 can be reduced. In addition, in order to further reduce the length L of the fan-out region 130, the data line layout of the display panel 120 may be implemented by fan-out in active area (FIAA). In this embodiment, the data line DL adopts the FIAA layout, so Figure 3 the length L of the fan-out region 130 is smaller than that of a display panel without the FIAA layout.

[0044] Figure 4 Schematic diagram of the driving circuit and the display panel according to an embodiment of the present invention. Refer to Figure 4 , the driving circuit 410 is used to drive a display panel 420 having a FIAA layout. The driving circuit 410 includes a switch circuit 417 and a source driver circuit 416. The source driver circuit 416 is coupled to the switch circuit 417. The source driver circuit 416 is used to output output display data DD_OUT through the switch circuit 417 to drive the display panel 420.

[0045] The switching circuit 417 is used to receive the input display data DD_IN and output the output display data DD_OUT according to two control signals MUX1 and MUX2. The input display data DD_IN and the output display data DD_OUT have different data arrangements. The application timings of the two control signals MUX1 and MUX2 are adjusted according to at least one adjustment signal CTRm and / or CTRdm. The two control signals MUX1 and MUX2 are applied to the switch groups SW_1 to SW_6 of the switching circuit 417 according to the application timings.

[0046] Specifically, the switching circuit 417 includes a first switching unit 417_1 and a second switching unit 417_2. The second switching unit 417_2 is arranged at the input end of the source driver circuit 416. The second switching unit 417_2 is used to receive the input display data DD_IN and output the input display data DD_IN according to two control signals MUX1 and MUX2. The first switching unit is arranged at the output end of the source driver circuit 416. The first switching unit is used to receive the input display data DD_IN from the source driver circuit 416 and output the output display data DD_OUT according to two control signals MUX1 and MUX2. The output display data DD_OUT will be written into the corresponding pixel.

[0047] The first switching unit 417_1 includes a plurality of first switch groups SW_1, SW_2, and SW_3. Each of the first switch groups SW_1, SW_2, and SW_3 is controlled by two control signals MUX1 and MUX2. Compared with the second switch group SW_3, the application timings of the control signals MUX1 and MUX2 have been adjusted, and the control signals MUX1 and MUX2 are applied to the first switch groups SW_1 and SW_2 according to the adjusted application timings. The application timings of the control signals MUX1 and MUX2 applied to the first switch group SW_3 remain unchanged.

[0048] On the other hand, the second switching unit 417_2 includes a plurality of second switch groups SW_4, SW_5, and SW_6. Each of the second switch groups SW_4, SW_5, and SW_6 is also controlled by two control signals MUX1 and MUX2. Corresponding to the first switching unit 417_1, in the second switching unit 417_2, the application timings of the control signals MUX1 and MUX2 are also adjusted, and the control signals MUX1 and MUX2 are applied to the second switch groups SW_4 and SW_5 according to the adjusted application timings. The application timings of the control signals MUX1 and MUX2 applied to the second switch group SW_6 remain unchanged.

[0049] In this embodiment, the application timings of the control signals MUX1 and MUX2 applied to the first switch group SW_3 and the second switch group SW_6 can be regarded as the first application timing (predetermined application timing). The application timings of the control signals MUX1 and MUX2 applied to the first switch groups SW_1 and SW_2 and the second switch groups SW_4 and SW_5 can be regarded as the second application timing. CTRm = 1 and CTRdm = 1 indicate that the application timing is adjusted from the first application timing to the second application timing. CTRm = 0 and CTRdm = 0 indicate that the application timing remains unchanged and maintains the first application timing.

[0050] Therefore, in order to output display data having the same arrangement as the output display data DD_OUT, the input display data DD_IN is rearranged by the switch circuit 417 to match the output display data DD_OUT.

[0051] Figure 5 Schematic diagram showing the adjustment of the control signals MUX1 and MUX2 according to an embodiment of the present invention. Refer to Figure 5 , in this embodiment, the data groups D4 and D6 of the input display data DD_IN do not match the data groups D1 and D3 of the output display data DD_OUT. Therefore, the control signals MUX1 and MUX2 are adjusted and applied to the first switch groups SW_1 and SW_3. In this way, the source pads S1 and S2 can output the display data D m and D m+1 , and the source pads S5 and S6 can output the display data D m-2 and D m+3 .

[0052] Specifically, Figure 6A Examples of the control signal MUX1 of the embodiment of the present invention turning on the corresponding switch are described, Figure 6B Examples of the control signal MUX2 of the embodiment of the present invention turning on the corresponding switch are described.

[0053] Taking the display data D m-3 to D m+4 of the input display data DD_IN as an example, positions P1 to P8 correspond to the source pads S1 to S8. Every two adjacent display data are divided into a data group. Each data group has a corresponding switch group and adjustment signals CTRm and CTRdm. For example, two adjacent display data D m+1 and D m are divided into the data group D4, and the data group D4 has the corresponding switch groups SW_4 and SW_1. The switch group SW_4 serves as a multiplexer circuit, and the switch group SW_1 serves as a demultiplexer circuit.

[0054] The second adjustment signal CTRm indicates whether the application timing of the control signals MUX1 and MUX2 is adjusted. When CTRm = 0 (second state), the application timing of the control signals MUX1 and MUX2 is not adjusted. When CTRm = 1 (first state), the application timing of the control signals MUX1 and MUX2 is adjusted.

[0055] The first adjustment signal CTRdm indicates whether the application timing of the control signals MUX1 and MUX2 is adjusted. When CTRdm = 0, the application timing of the control signals MUX1 and MUX2 is not adjusted. When CTRdm = 1, the application timing of the control signals MUX1 and MUX2 is adjusted.

[0056] In Figure 6A CTRdm = 1 indicates that the application timing of the control signals MUX1 and MUX2 of the switch group SW_1 is adjusted, and CTRm = 0 indicates that the application timing of the control signals MUX1 and MUX2 of the switch group SW_4 is not adjusted. When the control signal MUX1 turns on switches 601 and 602, the control signal MUX2 turns off switches 603 and 604. The display data D m+1 is transmitted from position P1 to the source pad S2 and output to the corresponding data line. Then, in Figure 6B when the control signal MUX1 turns off switches 601 and 602, the control signal MUX2 turns on switches 603 and 604. The display data D m is transmitted from position P2 to the source pad S1 and output to the corresponding data line. The display data D m+1 and D m of the data group D4 are output in a time-sharing manner.

[0057] The operation modes of other switches can refer to the operation modes of switches 601 to 604, which will not be elaborated here. In the embodiment, the driving circuit 510 may include a buffer circuit (not shown) to set the adjustment signals CTRm and CTRdm. The adjustment of the control signals MUX1 and MUX2 is controlled by the adjustment signals CTRm and CTRdm, so that the data arrangement of the output display data DD_OUT is more flexible to meet the design requirements of the display panel.

[0058] The adjustment signals CTRm and CTRdm can be set independently for each switch group. Alternatively, the adjustment signals CTRm and CTRdm can be set repeatedly for multiple switch groups. For example, every two to eight switch groups are set to have the same adjustment signals CTRm and CTRdm.

[0059] Figure 7 A schematic diagram showing the adjustment of the control signals MUX1 and MUX2 in another embodiment of the present invention is shown. Refer to Figure 7, in this embodiment, the green display data is located at the output of the switch controlled by the control signal MUX2. The data groups D71, D73, D74, and D76 include green display data and blue display data. The data groups D72 and D75 include green display data and red display data. The data groups D74, D75, and D76 of the input display data DD_IN do not match the data groups D71, D72, and D73 of the output display data DD_OUT. The control signals MUX1 and MUX2 can be adjusted and applied to the switch groups SW_71, SW_72, and SW_73. Therefore, the source pads S3, S4, S7, S8, S11, and S12 can output the display data D m , D m-1 , D m-2 , D m-3 , D m-4 , and D m-5 .

[0060] For all switch groups of the second switch unit 717_2, CTRm = 0. The two control signals MUX1 and MUX2 are applied to adjacent second switch groups in the same application order, for example, the first application order. For all switch groups of the first switch unit 717_1, starting from CTRdm = 0, CTRdm = 0 and CTRdm = 1 alternate. The two control signals MUX1 and MUX2 are applied to adjacent first switch groups in different application orders, for example, the first application order and the second application order. The output display data DD_OUT is output in a time-division manner.

[0061] Figure 8 Schematic diagram showing the adjustment of the control signals MUX1 and MUX2 according to another embodiment of the present invention. Refer to Figure 7 and Figure 8 , in this embodiment, Figure 8 the data arrangement is different from Figure 7 . In Figure 8 , the data groups D84, D85, and D86 of the input display data DD_IN still do not match the data groups D81, D82, and D83 of the output display data DD_OUT, and all data groups D81 to D86 include green display data and blue display data.

[0062] The control signals MUX1 and MUX2 are adjusted and applied to the switch groups SW_81, SW_82, and SW_83, and the source pads S3, S4, S7, S8, S11, and S12 can output the display data D m , D m-1 , D m+4 , D m+3 , D m-4 , and D m-5For all switch groups of the second switch unit 817_2, CTRm = 0. For all switch groups of the first switch unit 817_1, starting from CTRdm = 0, CTRdm = 0 and CTRdm = 1 alternate. The output display data DD_OUT is output in a time-division manner.

[0063] Figure 9 Schematic diagram showing the adjustment of the control signals MUX1 and MUX2 in another embodiment of the present invention. Refer to Figure 7 and Figure 9 , in this embodiment, Figure 9 the data arrangement is also different from Figure 7 . In Figure 9 , the data groups D94, D95, and D96 of the input display data DD_IN do not match the data groups D91, D92, and D93 of the output display data DD_OUT. The data groups D91, D93, D94, and D96 include green display data and red display data. The data groups D92 and D95 include green display data and blue display data.

[0064] The control signals MUX1 and MUX2 are adjusted and applied to the switch groups SW_91, SW_92, and SW_93, and the source pads S1, S2, S5, S6, S9, and S10 can output the display data D m , D m+1 , D m-2 , D m+3 , D m-4 and D m+5 . For all switch groups of the second switch unit 917_2, CTRm = 0. For all switch groups of the first switch unit 917_1, starting from CTRdm = 1, CTRdm = 1 and CTRdm = 0 alternate. The output display data DD_OUT is output in a time-division manner.

[0065] In summary, in the embodiments of the present invention, the data timing of the display data output from the driving circuit is rearranged to adaptively drive the display panel through the switching circuit. Two control signals are applied to control the on-state of the switching circuit, and the application timing of the two control signals is adjusted according to at least one adjustment signal. Therefore, the input display data is rearranged through the switching circuit to match the output display data. In addition, since the switching circuits for data rearrangement are all configured in the driving circuit, the length of the fan-out area can be reduced.

[0066] For those skilled in the art, various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations provided that such modifications and variations fall within the scope of the following claims and their equivalents.

Claims

1. A driving circuit, comprising: a switch circuit for receiving input display data and outputting output display data according to two control signals, wherein the input display data and the output display data have different data arrangements; as well as A source driving circuit is coupled to the switch circuit and is used to output the output display data through the switch circuit to drive the display panel. The application timing of the two control signals is adjusted according to at least one adjustment signal, and the two control signals are applied to the switch group of the switch circuit according to the application timing.

2. The driving circuit according to claim 1, wherein the switch circuit comprises: A first switch unit, configured at the output end of the source driving circuit, and used for outputting the output display data according to the two control signals; as well as The second switch unit is configured at the input end of the source driving circuit and is used for receiving and outputting the input display data according to the two control signals. 3 . The driving circuit according to claim 2 , wherein the first switch unit comprises a plurality of first switch groups, and each of the plurality of first switch groups is controlled by the two control signals. 4 . The driving circuit according to claim 3 , wherein the at least one adjustment signal comprises a first adjustment signal, and the first adjustment signal is used to indicate whether to adjust the application timing of the two control signals.

5. The driving circuit according to claim 4, wherein The first state of the first adjustment signal indicates that the application timing of the two control signals is adjusted; and The second state of the first adjustment signal indicates that the application timing of the two control signals is not adjusted. 6 . The driving circuit according to claim 4 , wherein the two control signals are applied to adjacent first switch groups at different application timings. 7 . The driving circuit according to claim 2 , wherein the second switch unit comprises a plurality of second switch groups, and each of the plurality of second switch groups is controlled by the two control signals. 8 . The driving circuit according to claim 7 , wherein the at least one adjustment signal comprises a second adjustment signal, and the second adjustment signal is used to indicate whether to adjust the application timing of the two control signals.

9. The driving circuit according to claim 8, wherein The first state of the second adjustment signal indicates that the application timing of the two control signals is adjusted; and The second state of the second adjustment signal indicates that the application timing of the two control signals is not adjusted. 10 . The driving circuit according to claim 8 , wherein the two control signals are applied to the adjacent second switch groups at the same application timing.

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