Multi-chip packaging structure body and manufacturing method thereof

Abstract

The invention relates to the field of semiconductor packaging, and discloses a multi-chip packaging structure body and a manufacturing method thereof, and the method comprises the steps: fixing a first chip on a substrate; the first electrode of the first chip is located on the surface, deviating from the substrate, of the first chip; fixing the second chip on the first chip; a second electrode of the second chip is located on the upper surface of the second chip, and the second chip and the first chip are chips with different base material types or different performances; routing is conducted between the second electrode and the first electrode, so that the second electrode is electrically connected with the first electrode; routing is conducted on the first electrode and a circuit layer on the substrate, so that the first electrode is electrically connected with the circuit layer; before the first chip is fixed on the substrate, a first insulating layer is manufactured on the upper surface of the first chip; and manufacturing a second insulating layer on the lower surface of the second chip before fixing the second chip on the upper surface of the first chip. According to the invention, the mode of stacking and packaging two different chips is simple, and the surface circuit layer of the first chip can be protected.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and particularly to a multi-chip packaging structure and a manufacturing method thereof. Background Art

[0002] Currently, when stacking and packaging multiple chips, an advanced CoWoS (Chip-on-Wafer-on-Substrate) process can be adopted. The CoWoS process is for silicon chips. Multiple active silicon chips are integrated on a passive silicon interposer, and the interposer acts as a communication layer for the top active chips. Then, the interposer and the active silicon are connected to a packaging substrate including I / O to be placed on a system PCB (Printed Circuit Board).

[0003] The CoWoS process has the following defects. First, it is necessary to fabricate through-silicon vias to conduct the top electrodes of the upper chips to the bottom of the chips through the vias, or to rewire using the sides of the chips to guide the top electrodes of the upper chips to the bottom. The process is complex, difficult, and costly. Second, the chips for stacking and packaging must be silicon-based chips, and it is impossible to achieve stacking and packaging of chips of different substrate types.

[0004] Therefore, how to solve the above technical problems should be the focus of attention of those skilled in the art. Summary of the Invention

[0005] The object of the present invention is to provide a multi-chip packaging structure and a manufacturing method thereof to achieve the packaging of multiple different chips, while simplifying the process and reducing the manufacturing difficulty.

[0006] To solve the above technical problems, the present invention provides a manufacturing method of a multi-chip packaging structure, including:

[0007] Fixing a first chip on a substrate; a first electrode of the first chip is located on an upper surface of the first chip facing away from the substrate;

[0008] Fixing a second chip on the upper surface of the first chip; a second electrode of the second chip is located on the upper surface of the second chip, and the second chip and the first chip are chips of different substrate types or different performances;

[0009] Bonding wires between the second electrode and the first electrode to electrically connect the second electrode and the first electrode;

[0010] Bonding wires between the first electrode and a circuit layer on the substrate to electrically connect the first electrode and the circuit layer;

[0011] Before fixing the first chip on the substrate, it further includes:

[0012] Fabricate a first insulating layer on the upper surface of the first chip; the first electrode is exposed from the first insulating layer;

[0013] Before fixing the second chip on the upper surface of the first chip, it further includes:

[0014] Fabricate a second insulating layer on the lower surface of the second chip.

[0015] Optionally, fabricating a first insulating layer on the upper surface of the first chip; the first electrode being exposed from the first insulating layer includes:

[0016] Fabricate the first insulating layer over the entire upper surface of the first chip;

[0017] Coat a photoresist on the upper surface of the first insulating layer to form a photoresist layer;

[0018] Expose and develop the photoresist layer to remove the photoresist layer located on the first electrode;

[0019] Remove the first insulating layer located on the first electrode;

[0020] Remove the photoresist layer.

[0021] Optionally, it further includes:

[0022] Fabricate a protective layer, where the protective layer is located on the surface of the first chip, or the protective layer is located on the surface of the circuit layer, or the protective layer is located on the surface of the multi-chip package structure.

[0023] Optionally, it further includes:

[0024] Fix a third chip on the upper surface of the second chip; a third electrode of the third chip is located on the upper surface of the third chip;

[0025] Wire bond between the third electrode and the second electrode to electrically connect the third electrode and the second electrode.

[0026] The present invention further provides a multi-chip package structure, including:

[0027] A substrate;

[0028] A first chip fixed on the substrate; a first electrode of the first chip is located on the upper surface of the first chip facing away from the substrate;

[0029] A second chip fixed on the upper surface of the first chip, a second electrode of the second chip is located on the upper surface of the second chip, and the second chip and the first chip are chips of different substrate types or different performances;

[0030] A first wire connecting the first electrode and the second electrode;

[0031] A second wire connecting the first electrode and the circuit layer of the substrate;

[0032] A first insulating layer on the upper surface of the first chip, with the first electrode exposed from the first insulating layer;

[0033] A second insulating layer on the lower surface of the second chip.

[0034] Optionally, the first insulating layer includes any one or any combination of the following laminated layers:

[0035] A silicon dioxide layer, a polyimide layer, an alumina layer, a zirconia layer.

[0036] Optionally, the first chip includes a chip with a silicon substrate, and the second chip includes a chip with any one of a gallium nitride substrate, a silicon nitride substrate, and an indium phosphide substrate.

[0037] Optionally, it further includes:

[0038] A protective layer, where the protective layer is on the surface of the first chip, or the protective layer is on the surface of the circuit layer, or the protective layer is on the surface of the multi-chip package structure.

[0039] A method for manufacturing a multi-chip package structure provided by the present invention includes: fixing a first chip on a substrate; the first electrode of the first chip is on the upper surface of the first chip facing away from the substrate; fixing a second chip on the upper surface of the first chip; the second electrode of the second chip is on the upper surface of the second chip, and the second chip and the first chip are chips of different substrate types or different performances; wire bonding between the second electrode and the first electrode to electrically connect the second electrode and the first electrode; wire bonding between the first electrode and the circuit layer on the substrate to electrically connect the first electrode and the circuit layer; before fixing the first chip on the substrate, it further includes: fabricating a first insulating layer on the upper surface of the first chip; the first electrode is exposed from the first insulating layer; before fixing the second chip on the upper surface of the first chip, it further includes: fabricating a second insulating layer on the lower surface of the second chip.

[0040] It can be seen that when manufacturing the package structure of multiple chips in the present invention, the first chip is fixed on the substrate, the second chip is stacked on the first chip, wire bonding is used to electrically connect the second electrode and the first electrode of the second chip, and wire bonding is used to connect the first electrode of the first chip and the circuit layer of the substrate. There is no need to perform a through-silicon via process or a side wiring process to lead the second electrode to the lower surface of the second chip. The process is simple and the manufacturing cost can be reduced. In addition, in the present invention, the first chip and the second chip are chips of different substrate types or different performances, and stacked packaging of different types of chips and different functional chips can be realized. That is, in the present invention, chips of different substrate types or different performances do not need to adopt the advanced CoWoS process to achieve stacked packaging, and the process is very simple. Moreover, in this application, a first insulating layer is made on the upper surface of the first chip, and a second insulating layer is made on the lower surface of the second chip. The first insulating layer can protect the surface of the first chip, reduce leakage or damage to the circuit layer caused by operations during the stacking operation. At the same time, the second insulating layer can make the insulation effect between the first chip and the second chip better and can more effectively protect the surface circuit layer of the first chip.

[0041] In addition, the present invention also provides a package structure of multiple chips having the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 The flowchart of a method for manufacturing a package structure of multiple chips provided by an embodiment of the present invention Figure 1 ;

[0044] Figure 2 The flowchart of a method for manufacturing a package structure of multiple chips provided by an embodiment of the present invention Figure 2 ;

[0045] Figure 3 The schematic structural diagram of a package structure of multiple chips provided by an embodiment of the present invention;

[0046] Figure 4 The top view schematic diagram of a package structure of multiple chips provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] To enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0048] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0049] As described in the background art section, when stacking multiple chips using the CoWoS process in the related art, there are problems such as complex process, high difficulty, and high cost, and only chips of the same type can be stacked and packaged.

[0050] In view of this, the present invention provides a method for manufacturing a multi-chip package structure. Please refer to Figure 1 , and the method includes:

[0051] Step S101: Fix the first chip on the substrate; the first electrode of the first chip is located on the upper surface of the first chip facing away from the substrate.

[0052] Adopt the DB (Die Bond, chip bonding) process to bond the first chip to the first substrate through an insulating die attach adhesive, and then bake it to fix the first chip to the substrate.

[0053] Step S102: Fix the second chip on the upper surface of the first chip; the second electrode of the second chip is located on the upper surface of the second chip, and the second chip and the first chip are chips of different substrate types or different performances.

[0054] Adopt the DB process to bond the second chip to the first chip through an insulating die attach adhesive, and then bake it to fix the second chip to the first chip.

[0055] It should be noted that in this embodiment, the types of the first chip and the second chip are not limited and can be set according to needs.

[0056] As an implementable way, when the first chip and the second chip are chips of different substrate types, the second chip can be a silicon-based chip, and the first chip can be a chip of any one of substrates such as gallium nitride, silicon nitride, indium phosphide, etc.; or, the first chip can be a silicon-based chip, and the second chip can be a chip of any one of substrates such as gallium nitride, silicon nitride, indium phosphide, etc.

[0057] As an implementable manner, when the first chip and the second chip are chips with different functions, the first chip can be a functional chip such as an ASIC (Application Specific Integrated Circuit) chip, a driver chip, a digital processing chip, an analog processing chip, an MCU (Microcontroller Unit), a DSP (Digital Signal Process) chip, etc., and the second chip can be a receiving chip, a light-emitting chip, etc., such as infrared, ultraviolet, color, brightness sensors, etc.

[0058] For example, when the first chip is a gallium nitride or silicon carbide high thermal conductivity chip, the second chip can be an LED (Light-Emitting Diode) light-emitting chip, an EEL (Edge Emitting Lasers) light-emitting chip, a VCSEL (Vertical Cavity Surface Emitting Laser) light-emitting chip, etc.

[0059] Step S103: Bond wires between the second electrode and the first electrode to electrically connect the second electrode and the first electrode.

[0060] The wire bonding is performed using the WD (wire bond) process, and the first electrode and the second electrode can be connected by a metal wire such as a gold wire. The specific operation process of wire bonding is well-known to those skilled in the art and will not be elaborated here.

[0061] Step S104: Bond wires between the first electrode and the circuit layer on the substrate to electrically connect the first electrode and the circuit layer.

[0062] The wire bonding is performed using the WD process, and the first electrode and the circuit layer can be connected by a metal wire such as a gold wire.

[0063] In this embodiment, when manufacturing a multi-chip package structure, the first chip is fixed on a substrate, the second chip is stacked on the first chip, wire bonding is used to electrically connect the second electrode and the first electrode of the second chip, and wire bonding is used to connect the first electrode of the first chip to the circuit layer of the substrate. There is no need to perform a through-silicon via process or a side wiring process to lead the second electrode to the lower surface of the second chip, and the process is simple, which can reduce the manufacturing cost. In addition, in this embodiment, the first chip and the second chip are chips of different substrate types or different performances, and stacked packaging of different types of chips and different functional chips can be realized. That is, in the present invention, chips of different substrate types or different performances do not need to adopt the advanced CoWoS process to achieve stacked packaging, and the process is very simple.

[0064] In addition, in the present invention, after different chips are stacked and co-packaged, the multi-chip package structure can be processed and transmitted faster (with smaller inductance and junction capacitance), changed from a single-function chip to a stacked chip with stronger performance, and made smaller in size.

[0065] Based on the above embodiments, in an embodiment of the present invention, a method for manufacturing a multi-chip package structure includes:

[0066] Step S201: Fabricate a first insulating layer on the upper surface of the first chip; the first electrode is exposed from the first insulating layer.

[0067] Since the second electrode of the second chip needs to be electrically connected to the first electrode, and the first electrode needs to be electrically connected to the circuit layer on the substrate, the first electrode cannot be covered by the first insulating layer.

[0068] It should be noted that in this embodiment, the manufacturing process of the first insulating layer is not limited, as long as it can achieve covering the first insulating layer on the area of the upper surface of the first chip except the first electrode.

[0069] As an implementable manner, fabricating a first insulating layer on the upper surface of the first chip; the first electrode being exposed from the first insulating layer includes:

[0070] Step S2011: Fabricate the first insulating layer on the entire upper surface of the first chip.

[0071] The manufacturing process of the first insulating layer includes but is not limited to evaporation, chemical vapor deposition, etc., and a suitable manufacturing process can be specifically selected according to the material of the first insulating layer.

[0072] It should be noted that in this embodiment, the type of the first insulating layer is not limited and depends on the situation.

[0073] As an implementable manner, the first insulating layer includes but is not limited to any one or any combination of the following laminated layers:

[0074] Silicon dioxide layer, polyimide layer, alumina layer, zirconia layer.

[0075] Step S2012: Coating a photoresist on the upper surface of the first insulating layer to form a photoresist layer.

[0076] Step S2013: Exposing and developing the photoresist layer to remove the photoresist layer located on the first electrode.

[0077] Align the mask on the first chip for exposure, and then use a developer to remove the photoresist layer on the first electrode. The remaining photoresist serves as a protective layer for the first insulating layer.

[0078] Step S2014: Removing the first insulating layer located on the first electrode.

[0079] In this embodiment, the method for removing the first insulating layer on the first electrode is not limited and depends on the situation.

[0080] For example, when the first insulating layer is a silicon dioxide layer, hydrofluoric acid etching solution can be used to react with the silicon dioxide layer without the protection of the photoresist layer to remove it.

[0081] Step S2015: Removing the photoresist layer.

[0082] Remove the photoresist with a chemical solvent or plasma cleaning.

[0083] Step S202: Fixing the first chip on the substrate; the first electrode of the first chip is located on the upper surface of the first chip facing away from the substrate.

[0084] Step S203: Fixing the second chip on the first insulating layer; the second electrode of the second chip is located on the upper surface of the second chip, and the second chip and the first chip are chips of different substrate types or different performances.

[0085] Step S204: Bonding wires between the second electrode and the first electrode to electrically connect the second electrode and the first electrode.

[0086] Step S205: Bonding wires between the first electrode and the circuit layer on the substrate to electrically connect the first electrode and the circuit layer.

[0087] In this embodiment, covering the area other than the first electrode on the upper surface of the first chip with the first insulating layer can protect the surface of the first chip and reduce leakage or damage to the circuit layer caused by operations during the stacking process.

[0088] Based on any of the above embodiments, in an embodiment of the present invention, please refer to Figure 2, a method for manufacturing a multi-chip package structure includes:

[0089] Step S301: Fabricate a first insulating layer on the upper surface of the first chip; the first electrode is exposed from the first insulating layer.

[0090] Step S302: Fix the first chip on a substrate; the first electrode of the first chip is located on the upper surface of the first chip facing away from the substrate.

[0091] Step S303: Fabricate a second insulating layer on the lower surface of the second chip.

[0092] It should be noted that the type of the second insulating layer in this embodiment is not limited and depends on the situation.

[0093] As an implementable manner, the second insulating layer includes but is not limited to any one or any combination of the following laminated layers:

[0094] Silicon dioxide layer, polyimide layer, alumina layer, zirconia layer.

[0095] It should also be noted that the manufacturing method of the second insulating layer in this embodiment is not limited and can be selected by oneself. For example, the manufacturing process of the second insulating layer includes but is not limited to evaporation coating, chemical vapor deposition, etc.

[0096] Step S304: Fix the second chip on the first insulating layer; the second electrode of the second chip is located on the upper surface of the second chip, and the second chip and the first chip are chips of different substrate types or different performances.

[0097] Step S305: Bond wires between the second electrode and the first electrode to electrically connect the second electrode and the first electrode.

[0098] Step S306: Bond wires between the first electrode and the circuit layer on the substrate to electrically connect the first electrode and the circuit layer.

[0099] Currently, 90% of the chips do not need to use the substrate as an electrical connection layer (except for the case where some power devices are used for heat dissipation). In this embodiment, by insulating the lower surface of the second chip, any structure of the package can be conveniently carried out without worrying about circuit connection problems. Moreover, when encapsulating, insulating glue is used for die bonding DB. Insulating the bottom of the second chip is also beneficial to the DB process.

[0100] In addition, when a first insulating layer is provided on the upper surface of the first chip and a second insulating layer is provided on the lower surface of the second chip, the insulating effect can be better, and the surface circuit layer of the first chip can be more effectively protected.

[0101] Based on any of the above embodiments, in an embodiment of the present invention, the method for manufacturing a multi-chip package structure may further include:

[0102] Manufacture a protective layer, where the protective layer is located on the surface of the first chip, or the protective layer is located on the surface of the circuit layer, or the protective layer is located on the surface of the multi-chip package structure.

[0103] When the protective layer is located on the surface of the first chip, the function of the protective layer is to protect the first chip; when the protective layer is located on the surface of the circuit layer of the substrate, the function of the protective layer is to protect the circuit layer on the substrate; when the protective layer is located on the surface of the multi-chip package structure, the function of the protective layer is to protect the entire multi-chip package structure.

[0104] It should be noted that in this embodiment, the material of the protective layer is not limited and depends on the situation. The material of the protective layer can be materials such as silicone or resin.

[0105] For example, when the first chip or the second chip is a functional chip, the material of the protective layer can be materials such as epoxy resin. When the first chip or the second chip is a light-emitting chip, the material of the protective layer can be silicone. The protective effect of silicone is mainly reflected in high-temperature operations (such as reflow soldering, high and low temperature shock, etc.), solving the failure caused by stress to the first chip or the second chip, or stress to the stacking process.

[0106] Based on any of the above embodiments, in an embodiment of the present invention, the method for manufacturing a multi-chip package structure may further include:

[0107] Fix the third chip on the upper surface of the second chip; the third electrode of the third chip is located on the upper surface of the third chip;

[0108] Wire bond between the third electrode and the second electrode to electrically connect the third electrode and the second electrode.

[0109] An insulating layer may also be provided on the lower surface of the third chip and the upper surface of the second chip (excluding the second electrode area). For details, reference can be made to the setting of the insulating layer between the first chip and the second chip.

[0110] The second chip can be a chip of a different substrate type from at least one of the first chip and the second chip.

[0111] It can be understood that a fourth chip can be continuously stacked on the third chip, and a fifth chip can be stacked on the fourth chip, and so on.

[0112] The present invention also provides a multi-chip package structure. Please refer to Figure 3 and Figure 4 , and this structure includes:

[0113] Substrate 1;

[0114] The first chip 2 fixed on the substrate 1; the first electrode 21 of the first chip 2 is located on the upper surface of the first chip 2 facing away from the substrate 1;

[0115] The second chip 3 fixed on the upper surface of the first chip 2, the second electrode 31 of the second chip 3 is located on the upper surface of the second chip 3, and the second chip 3 and the first chip 2 are chips of different substrate types or different performances;

[0116] The first wire 4 connecting the first electrode 21 and the second electrode 31;

[0117] The second wire 5 connecting the first electrode 21 and the circuit layer 11 of the substrate 1.

[0118] It should be noted that in this embodiment, the types of the first chip 2 and the second chip 3 are not limited and can be set according to needs.

[0119] As an implementable manner, when the first chip 2 and the second chip 3 are chips of different substrate types, the second chip 3 can be a silicon-based chip, and the first chip 2 can be a chip of any substrate such as gallium nitride, silicon nitride, indium phosphide, etc.; or, the first chip 2 can be a silicon-based chip, and the second chip 3 can be a chip of any substrate such as gallium nitride, silicon nitride, indium phosphide, etc.

[0120] As an implementable manner, when the first chip 2 and the second chip 3 are chips with different functions, the first chip 2 can be a functional chip such as an ASIC chip, a driver chip, a digital processing chip, an analog processing chip, an MCU, a DSP chip, etc., and the second chip 3 can be a receiving chip, or a light-emitting chip, etc., such as an infrared, ultraviolet, color, brightness sensor, etc.

[0121] For example, when the first chip 2 is a high thermal conductivity chip such as gallium nitride or silicon carbide, the second chip 3 can be an LED light-emitting chip, an EEL light-emitting chip, a VCSEL light-emitting chip, etc.

[0122] The first wire 4 and the second wire 5 can be metal wires such as gold wires, which are not limited in this embodiment.

[0123] When forming the encapsulation structure in this embodiment, the first chip 2 is fixed on the substrate 1, the second chip 3 is stacked on the first chip 2, wire bonding is used to electrically connect the second electrode 31 of the second chip 3 to the first electrode 21, and wire bonding is used to connect the first electrode 21 of the first chip 2 to the circuit layer 11 of the substrate 1. There is no need to use the through-silicon via process or the side wiring process to lead the second electrode 31 to the lower surface of the second chip 3. The process is simple and can reduce the manufacturing cost. In addition, in this embodiment, the first chip 2 and the second chip 3 are chips of different base material types or different performances, and the stacked encapsulation of different types of chips and different functional chips can be realized.

[0124] Based on the above embodiments, in an embodiment of the present invention, the multi-chip encapsulation structure may further include:

[0125] A first insulating layer located on the upper surface of the first chip 2, and the first electrode 21 is exposed from the first insulating layer.

[0126] It should be noted that in this embodiment, the type of the first insulating layer is not limited and depends on the situation.

[0127] As an implementable manner, the first insulating layer includes but is not limited to any one or any combination of the following laminated layers:

[0128] A silicon dioxide layer, a polyimide layer, an alumina layer, a zirconia layer.

[0129] The first insulating layer can protect the surface of the first chip 2 and reduce leakage or damage to the circuit layer 11 caused by operations during the stacking operation.

[0130] Based on any of the above embodiments, in an embodiment of the present invention, the multi-chip encapsulation structure may further include:

[0131] A second insulating layer located on the lower surface of the second chip 3.

[0132] It should be noted that in this embodiment, the type of the first insulating layer is not limited and depends on the situation.

[0133] As an implementable manner, the first insulating layer includes but is not limited to any one or any combination of the following laminated layers:

[0134] A silicon dioxide layer, a polyimide layer, an alumina layer, a zirconia layer.

[0135] The second insulating layer can insulate the lower surface of the second chip 3, facilitating the encapsulation process without worrying about circuit connection problems. Moreover, during encapsulation, the die bonding with insulating glue (DB) is always used, and insulating the bottom of the second chip 3 is also beneficial to the DB process.

[0136] Based on any of the above embodiments, in an embodiment of the present invention, the multi-chip package structure may further include:

[0137] A protective layer, where the protective layer is located on the surface of the first chip 2, or the protective layer is located on the surface of the circuit layer 11, or the protective layer is located on the surface of the multi-chip package structure.

[0138] The material of the protective layer includes but is not limited to materials such as silica gel or resin.

[0139] The following will introduce different situations of the first chip and the second chip in the multi-chip package structure of the present invention.

[0140] Example 1: Combination of a receiving chip and a processing chip: The first chip is a processing chip, and the second chip is a receiving chip.

[0141] Place the receiving chip on the upper layer. The receiving chip serves as the entrance of information. Being on the upper side can receive external signals more directly. The receiving chip can use PT (Punch Through), PD (Photo Dioder), CMOS (Complementary Metal Oxide Semiconductor), SPAD (Single Photon Avalanche Diode), etc. Place the processing chip on its lower layer. The information obtained by the receiving chip can be quickly transmitted to the processing chip for analysis and calculation. The lower-layer processing chip can be a dedicated processing chip, ASIC, MCU, etc. This combination of upper and lower layers greatly shortens the signal transmission path, reduces latency, and improves the overall processing speed and efficiency.

[0142] Example 2: Combination of a transmitting (light-emitting) chip and a driving chip: The first chip is a driving chip, and the second chip is a transmitting (light-emitting) chip.

[0143] The driving chip can use chips based on substrates such as gallium nitride (GaN) and silicon carbide (SiC). The light-emitting chip is responsible for generating efficient light radiation. The driving chip provides a stable and precise driving current for the light-emitting chip to ensure its normal and efficient operation. At the same time, the heat generated by the light-emitting chip is quickly conducted to the outside through the high-thermal-conductivity materials gallium nitride (GaN) and silicon carbide (SiC). Such an upper and lower layout structure enables the driving chip to closely support the light-emitting chip, achieving more precise light emission control and better light and heat performance.

[0144] The application of the stacking technology in the present invention not only optimizes the connection and communication between chips, but also saves space, making the entire system more compact, breaking the limitations of the traditional planar layout, making full use of the vertical space, and bringing more possibilities to chip design. At the same time, this stacked structure also helps to reduce power consumption, improve integration and enhance... With the stacking technology, it enables advanced packaging technologies such as miniaturization, precision, and the integration of RX (Receiver) + TX (Transmitter).

[0145] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts between the embodiments, reference can be made to each other.

[0146] The above has introduced in detail the multi-chip package structure and its manufacturing method provided by the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only for helping to understand the solution and core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a multi-chip package structure, characterized in that: include: Fixing a first chip on a substrate; wherein a first electrode of the first chip is located on an upper surface of the first chip away from the substrate; The second chip is fixed on the upper surface of the first chip; the second electrode of the second chip is located on the upper surface of the second chip, and the second chip and the first chip are chips of different substrate types or different performances; Bonding a wire between the second electrode and the first electrode to electrically connect the second electrode to the first electrode; Bonding a wire between the first electrode and the circuit layer on the substrate to electrically connect the first electrode to the circuit layer; Before fixing the first chip on the substrate, the method further includes: A first insulating layer is formed on the upper surface of the first chip; the first electrode is exposed on the first insulating layer; Before fixing the second chip on the upper surface of the first chip, the method further includes: A second insulating layer is formed on the lower surface of the second chip.

2. The method for manufacturing a multi-chip package structure according to claim 1, wherein: forming a first insulating layer on the upper surface of the first chip; The first electrode exposed on the first insulating layer comprises: Forming a first insulating layer on the entire upper surface of the first chip; coating a photoresist on the upper surface of the first insulating layer to form a photoresist layer; exposing and developing the photoresist layer to remove the photoresist layer located on the first electrode; removing the first insulating layer located on the first electrode; The photoresist layer is removed.

3. The method for manufacturing a multi-chip package structure according to claim 1, wherein: Also includes: A protective layer is manufactured, wherein the protective layer is located on the surface of the first chip, or the protective layer is located on the surface of the circuit layer, or the protective layer is located on the surface of a multi-chip packaging structure.

4. The method for manufacturing a multi-chip package structure according to any one of claims 1 to 3, characterized in that: Also includes: Fixing a third chip on the upper surface of the second chip; a third electrode of the third chip is located on the upper surface of the third chip; A wire is bonded between the third electrode and the second electrode to electrically connect the third electrode to the second electrode.

5. A multi-chip package structure, characterized in that: include: substrate; A first chip fixed on the substrate; a first electrode of the first chip is located on an upper surface of the first chip away from the substrate; a second chip fixed to the upper surface of the first chip, wherein the second electrode of the second chip is located on the upper surface of the second chip, and the second chip and the first chip are chips of different substrate types or different performances; a first wire connecting the first electrode and the second electrode; A second wire connecting the first electrode and the circuit layer of the substrate; a first insulating layer located on the upper surface of the first chip, the first electrode being exposed on the first insulating layer; A second insulating layer is located on the lower surface of the second chip.

6. The multi-chip package structure according to claim 5, wherein: The first insulating layer includes any one or any combination of the following stacked layers: Silicon dioxide layer, polyimide layer, aluminum oxide layer, zirconium oxide layer.

7. The multi-chip package structure according to claim 5, wherein: The first chip includes a chip made of a silicon substrate, and the second chip includes a chip made of any one of a gallium nitride substrate, a silicon nitride substrate, and an indium phosphide substrate.

8. The multi-chip package structure according to any one of claims 5 to 7, characterized in that: Also includes: A protective layer, wherein the protective layer is located on the surface of the first chip, or the protective layer is located on the surface of the circuit layer, or the protective layer is located on the surface of a multi-chip packaging structure.

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