Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a first substrate and a semiconductor device located in the first substrate; a plurality of first conductive pads connected to the semiconductor device; a plurality of second conductive pads, wherein the at least one first conductive pad and the at least one second conductive pad are electrically connected through a first conductive interconnection structure extending in a direction perpendicular to the first substrate; the filling layer fills the peripheries of the first conductive pads, the first conductive interconnection structure and the second conductive pads; wherein the first conductive interconnection structure has a surface buried by the filling layer between adjacent second conductive pads. The embodiment of the invention is at least beneficial to simplifying the steps of forming the semiconductor structure and improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the progress of technology, the integration and consolidation of semiconductor packages have been gradually enhanced, and electronic devices are developing towards miniaturization, high speed, high reliability, low cost, and low power consumption. HBM (High Bandwidth Memory) products are in short supply. To achieve high-capacity HBM, wafer-on-wafer (WoW) packaging technology or chip-on-chip (CoC) packaging technology is required.

[0003] However, in semiconductor packaging technology, secondary processing is required after wafer-level testing. To ensure a flat bonding interface, it is often necessary to deposit thick dielectric layers multiple times and perform chemical mechanical polishing to achieve flatness, and on this basis, deep hole etching or damascene process is performed on the dielectric layer. The process flow is relatively complex, and deep hole etching is likely to cause problems such as excessive by-products and poor metal contact. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which are at least beneficial to improving the electrical performance of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, a semiconductor structure is provided, including: a first substrate and semiconductor devices located in the first substrate; a plurality of first conductive pads connecting the semiconductor devices; a plurality of second conductive pads, at least one of the first conductive pads and at least one of the second conductive pads are electrically connected through a first conductive interconnect structure extending in a direction perpendicular to the first substrate; a filling layer, the filling layer filling the outer peripheries of the first conductive pads, the first conductive interconnect structure, and the second conductive pads; wherein, the first conductive interconnect structure has a surface buried by the filling layer between adjacent second conductive pads.

[0006] In some embodiments, the filling layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer covers the first conductive pad, the third dielectric layer covers the sidewalls of the second conductive pads, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and there is a first preset height difference between the top surface of the second dielectric layer and the top surface of the first conductive interconnect structure, and the range of the first preset height difference is 0 nm to 50 nm.

[0007] In some embodiments, the first dielectric layer and the second dielectric layer form a sub-fill layer; the fill layer further includes a fourth dielectric layer, and the fourth dielectric layer is located between the sub-fill layer and the first conductive interconnect structure.

[0008] In some embodiments, at least one of the second conductive pads is located on the top surface of the second dielectric layer.

[0009] In some embodiments, the second conductive pad located on the top surface of the second dielectric layer is not electrically connected to the first conductive pad, and the second conductive pad is in direct contact with the top surface of the second dielectric layer.

[0010] In some embodiments, the first conductive pad in electrical contact with the first conductive interconnect structure includes a first portion and a second portion. The second portion is in direct contact with the first conductive interconnect structure, the first portion is not in direct contact with the first conductive interconnect structure, and there is a portion of the surface of the second portion in direct contact with the first conductive interconnect structure that is lower than the surface of the first portion.

[0011] In some embodiments, the orthographic projections of at least two of the first conductive pads on the first substrate overlap with the orthographic projection of one of the first conductive interconnect structures on the first substrate.

[0012] In some embodiments, the fill layer includes a first bonding layer. The second conductive pad has a top surface exposed to the first bonding layer, and there is a second predetermined height difference between the top surface of the second conductive pad exposed to the first bonding layer and the top surface of the first bonding layer. The range of the second predetermined height difference is 0 nm to 50 nm.

[0013] In some embodiments, the semiconductor structure further includes: a second bonding layer and a third conductive pad located in the second bonding layer. The second bonding layer is directly bonded to the first bonding layer, and the third conductive pad is directly bonded to the second conductive pad.

[0014] In some embodiments, the semiconductor structure further includes: an isolation layer, and the isolation layer is located in the fill layer between adjacent first conductive pads.

[0015] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a first substrate having semiconductor devices therein; forming a plurality of first conductive pads connecting the semiconductor devices; forming a first opening exposing the surface of at least one of the first conductive pads; forming a first conductive interconnect structure filling the first opening; forming a plurality of second conductive pads on the first conductive interconnect structure such that at least one of the first conductive pads and at least one of the second conductive pads are electrically connected through the first conductive interconnect structure; wherein a filling layer is formed on the outer periphery of each of the first conductive pads, each of the second conductive pads, and the first conductive interconnect structure, and the first conductive interconnect structure has a surface buried by the filling layer between adjacent second conductive pads.

[0016] In some embodiments, the filling layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first conductive pads are formed in the first dielectric layer, the second dielectric layer is formed on the first dielectric layer, and the first dielectric layer and the second dielectric layer are formed before the first opening is formed. The first opening is formed in the first dielectric layer and the second dielectric layer. After the first conductive interconnect structure is formed in the first opening, the surface of the first conductive interconnect structure is planarized such that there is a first preset height difference between the top surface of the second dielectric layer and the top surface of the first conductive interconnect structure, and the range of the first preset height difference is 0 nm to 50 nm. After the first conductive interconnect structure is formed, the third dielectric layer is formed, and the second conductive pads electrically connected to the first conductive interconnect structure are formed in the third dielectric layer.

[0017] In some embodiments, the filling layer further includes a fourth dielectric layer, and the fourth dielectric layer is formed after the first opening is formed and before the first conductive interconnect structure is formed, such that the fourth dielectric layer is located between the first conductive interconnect structure and the first dielectric layer and the second dielectric layer.

[0018] In some embodiments, the step of forming the fourth dielectric layer includes: forming an initial fourth dielectric layer conformally covering the surface of the first opening and the top surface of the second dielectric layer, and performing a re-etching on the initial fourth dielectric layer to remove the initial fourth dielectric layer located on the top surface of the second dielectric layer and the bottom surface of the first opening, and the remaining initial fourth dielectric layer is the fourth dielectric layer; wherein, in the step of performing the re-etching on the initial fourth dielectric layer, a part of the thickness of the first conductive pad exposed by the first opening is etched away.

[0019] In some embodiments, the filling layer further includes a first bonding layer. The second conductive pad has a top surface exposed to the first bonding layer. There is a second predetermined height difference between the top surface of the second conductive pad exposed to the first bonding layer and the top surface of the first bonding layer, and the range of the second predetermined height difference is from 0 nm to 50 nm. After forming the second conductive pad, it further includes forming a second bonding layer directly bonded to the first bonding layer and a third conductive pad directly bonded to the second conductive pad.

[0020] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0021] The electrical signals in the semiconductor device are transmitted to other electrical components via the first conductive pad, the first conductive interconnect structure, and the second conductive pad, or the electrical signals in other electrical components are transmitted to the semiconductor device via the second conductive pad, the first conductive interconnect structure, and the first conductive pad. Based on this, the first conductive pad is mainly used to achieve electrical connection with the semiconductor device, the second conductive pad is mainly used to electrically connect with other electrical components, and the first conductive interconnect structure is mainly used to achieve the electrical connection between the first conductive pad and the second conductive pad.

[0022] On this basis, the first conductive interconnect structure has a surface buried by the filling layer of the adjacent second conductive pad. In other words, it is designed that the orthographic projections of at least two second conductive pads on the first substrate overlap with the orthographic projection of one first conductive interconnect structure on the first substrate, so that one first conductive interconnect structure is in electrical contact with at least two second conductive pads. On the one hand, it is beneficial to improve the transmission efficiency of electrical signals among the first conductive pad, the first conductive interconnect structure, and the second conductive pad; on the other hand, in the horizontal direction, the length of the first conductive interconnect structure is greater than the length of the second conductive pad, which is beneficial to improve the alignment accuracy between the second conductive pad and the first conductive interconnect structure, thereby being beneficial to increase the contact area between the second conductive pad and the first conductive interconnect structure to reduce the contact resistance between the two, and further improve the transmission efficiency of electrical signals. Description of the Drawings

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, the drawings in the figures do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1A schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0025] Figure 2 A schematic cross-sectional structure diagram of a first conductive interconnect structure and a filling layer in a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 3 Another schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 4 Still another schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 5 Yet another schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 6 A schematic cross-sectional structure diagram of a second conductive pad and a filling layer in a semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 7 Another schematic cross-sectional structure diagram of a second conductive pad and a filling layer in a semiconductor structure provided by an embodiment of the present disclosure;

[0031] Figure 8 Still another schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0032] Figure 9 Schematic cross-sectional structure diagrams corresponding to each step in a manufacturing method of a semiconductor structure;

[0033] Figure 10 A schematic flow diagram corresponding to a manufacturing method of a semiconductor structure provided by another embodiment of the present disclosure;

[0034] Figures 11 to 27 Schematic cross-sectional structure diagrams corresponding to each step in a manufacturing method of a semiconductor structure provided by another embodiment of the present disclosure. Detailed implementation manners

[0035] As can be seen from the background art, the electrical performance of the semiconductor structure needs to be improved.

[0036] The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, the first conductive pad is mainly used for electrically connecting with a semiconductor device, the second conductive pad is mainly used for electrically connecting with other electrical components, and the first conductive interconnect structure is mainly used for realizing the electrical connection between the first conductive pad and the second conductive pad. On this basis, the surface of the first conductive interconnect structure is buried by the filling layer of the adjacent second conductive pad. In other words, it is designed that the orthographic projections of at least two second conductive pads on the first substrate overlap with the orthographic projection of one first conductive interconnect structure on the first substrate, so that one first conductive interconnect structure is in electrical contact with at least two second conductive pads. On the one hand, it is beneficial to improve the transmission efficiency of electrical signals among the first conductive pad, the first conductive interconnect structure, and the second conductive pad. On the other hand, in the horizontal direction, the length of the first conductive interconnect structure is greater than the length of the second conductive pad, which is beneficial to improving the alignment accuracy between the second conductive pad and the first conductive interconnect structure, thereby being beneficial to increasing the contact area between the second conductive pad and the first conductive interconnect structure to reduce the contact resistance therebetween, and further improving the transmission efficiency of electrical signals.

[0037] The following will elaborate on the embodiments of the present disclosure with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are presented to help readers better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can still be implemented.

[0038] An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, for the convenience of description and to clearly show the characteristics of the semiconductor structure, Figures 1 to 8 are all partial structure schematic diagrams of the semiconductor structure.

[0039] Refer to Figure 1 , Figure 1A schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure. The semiconductor structure includes: a first substrate 100 and semiconductor devices (not shown in the figure) located in the first substrate 100; a plurality of first conductive pads 101 connected to the semiconductor devices; a plurality of second conductive pads 105, at least one first conductive pad 101 and at least one second conductive pad 105 are electrically connected through a first conductive interconnect structure 103 extending along a direction X perpendicular to the first substrate 100; a filling layer 142, the filling layer 142 fills the outer periphery of each first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105; wherein, the first conductive interconnect structure 103 has a surface 103b buried by the filling layer 142 between adjacent second conductive pads 105. In some cases, the electrical signals in the semiconductor devices are transmitted to other electrical devices through the first conductive pads 101, the first conductive interconnect structure 103, and the second conductive pads 105, or the electrical signals in other electrical devices are transmitted to the semiconductor devices through the second conductive pads 105, the first conductive interconnect structure 103, and the first conductive pads 101. Based on this, the first conductive pads 101 are mainly used to achieve electrical connection with the semiconductor devices, the second conductive pads 105 are mainly used to electrically connect with other electrical devices, and the first conductive interconnect structure 103 is mainly used to achieve the electrical connection between the first conductive pads 101 and the second conductive pads 105.

[0040] In addition, the first conductive interconnect structure 103 has a surface 103b buried by the filling layer 142 between adjacent second conductive pads 105, which is beneficial to making the orthographic projections of at least two second conductive pads 105 on the first substrate 100 overlap with the orthographic projection of the same first conductive interconnect structure 103 on the first substrate 100, so that one first conductive interconnect structure 103 is in electrical contact with at least two second conductive pads 105. On this basis, designing one first conductive interconnect structure 103 that connects at least two adjacent second conductive pads 105 at the same time, on the one hand, such a design is beneficial to improving the transmission efficiency of electrical signals among the first conductive pads 101, the first conductive interconnect structure 103, and the second conductive pads 105; on the other hand, along the horizontal direction Y, the length of the first conductive interconnect structure 103 is greater than the length of a single second conductive pad 105, which is beneficial to improving the alignment accuracy between the second conductive pad 105 and the first conductive interconnect structure 103, and is more beneficial to the entire single second conductive pad 105 being in electrical contact with the first conductive interconnect structure 103, thereby being beneficial to increasing the contact area between the second conductive pad 105 and the first conductive interconnect structure 103 to reduce the contact resistance between the two, and further improving the transmission efficiency of electrical signals.

[0041] It should be noted that with reference to Figure 1, the direction perpendicular to the first substrate 100 is the vertical direction X. In some cases, the vertical direction X can also be the direction from the first conductive pad 101 to the second conductive pad 105; the horizontal direction Y can be perpendicular to the vertical direction X. In addition, Figure 1 Take an example where one first conductive interconnect structure 103 is in electrical contact with three second conductive pads 105. Among the three second conductive pads 105, two second conductive pads 105 are entirely in electrical contact with the first conductive interconnect structure 103, and a partial area of the remaining one second conductive pad 105 is in electrical contact with the first conductive interconnect structure 103. In practical applications, firstly, for any second conductive pad 105 in electrical contact with the first conductive interconnect structure 103, there is no limit to the contact area between the second conductive pad 105 and the first conductive interconnect structure 103, that is, the entire area of the second conductive pad 105 can be in electrical contact with the first conductive interconnect structure 103, or a partial area of the second conductive pad 105 can be in electrical contact with the first conductive interconnect structure 103; secondly, there is no limit to the number of second conductive pads 105 in electrical contact with the same first conductive interconnect structure 103, as long as it is not less than 2.

[0042] In some embodiments, referring to Figure 1 , the semiconductor structure may further include: an isolation layer 151, and at least a part of the isolation layer 151 is located in the filling layer 142 between adjacent first conductive pads 101. Thus, it is beneficial to improve the insulation effect between adjacent first conductive pads 101 through the isolation layer 151 whose dielectric constant is lower than that of the filling layer 142, and avoid crosstalk of signals on adjacent first conductive pads 101.

[0043] In some embodiments, the isolation layer 151 can be an air gap.

[0044] In some embodiments, referring to Figure 1 and Figure 2 , the filling layer 142 includes a first dielectric layer 122, a second dielectric layer 132, and a third dielectric layer 124. The first dielectric layer 122 covers the first conductive pad 101, the third dielectric layer 124 at least wraps the sidewalls of the second conductive pad 105, the second dielectric layer 132 is located between the first dielectric layer 122 and the third dielectric layer 124, and there is a first preset height difference H1 between the top surface 132a of the second dielectric layer 132 and the top surface 103a of the first conductive interconnect structure 103. The range of the first preset height difference H1 is 0nm to 50nm.

[0045] Wherein, Figure 2 is a schematic cross-sectional structure diagram of a first conductive interconnect structure and a filling layer in a semiconductor structure provided by an embodiment of the present disclosure. In some cases, referring to Figure 1, the first preset height difference H1 can be 0 nm, that is, the top surface 132a of the second dielectric layer 132 is flush with the top surface 103a of the first conductive interconnect structure 103; in some other cases, refer to Figure 2 , the top surface 103a of the first conductive interconnect structure 103 is a concave surface that is recessed in the direction towards the first substrate 100 (refer to Figure 1 ). In this case, the first preset height difference H1 is greater than 0 and less than or equal to 50 nm; in some other cases, the top surface of the first conductive interconnect structure can also be a convex surface that protrudes in the direction away from the first substrate. In this case, the first preset height difference H1 is greater than 0 and less than or equal to 50 nm.

[0046] It should be noted that in an embodiment of the present disclosure, only the first preset height difference H1 between the top surface 132a of the second dielectric layer 132 and the top surface 103a of the first conductive interconnect structure 103 is defined. However, based on the first substrate 100, it is not restricted which one of the top surface 132a of the second dielectric layer 132 and the top surface 103a of the first conductive interconnect structure 103 is higher or lower, and it can be adjusted according to the actual situation.

[0047] In addition, Figure 2 defines the first preset height difference H1 between the top surface 132a of the second dielectric layer 132 and the top surface 103a of the first conductive interconnect structure 103 as: along the vertical direction X, the maximum vertical distance between each point on the top surface 132a of the second dielectric layer 132 and each point on the top surface 103a of the first conductive interconnect structure 103. Moreover, the surface 103b of the first conductive interconnect structure 103 that is buried by the filling layer 142 between adjacent second conductive pads 105 is a part of the top surface 103a of the first conductive interconnect structure 103.

[0048] In some embodiments, refer to Figure 1 , the filling layer 142 includes a first dielectric layer 122 that coats the first conductive pad 101, a third dielectric layer 124 that coats the sidewalls of the second conductive pads 105, and a second dielectric layer 132 located between the first dielectric layer 122 and the third dielectric layer 124; based on this, the isolation layer 151 is located in the first dielectric layer 122. In other words, the first dielectric layer 122 has the isolation layer 151. It should be noted that in actual applications, the isolation layer may also be located in the second dielectric layer.

[0049] In some embodiments, refer to Figure 1 , the first dielectric layer 122 and the second dielectric layer 132 form a sub-filling layer 102; the filling layer 142 may further include a fourth dielectric layer 106, and the fourth dielectric layer 106 is located between the sub-filling layer 102 and the first conductive interconnect structure 103.

[0050] In some cases, in the step of forming the first conductive interconnect structure 103, it is necessary to form a first opening in the sub-fill layer 102 to accommodate the first conductive interconnect structure 103, and use the fourth dielectric layer 106 to protect the sidewalls of the first opening to prevent the sub-fill layer 102 forming the sidewalls of the first opening from being etched, so that the sidewalls of the first opening have a relatively flat interface, which is convenient for forming a first conductive interconnect structure 103 with regular dimensions subsequently.

[0051] In some embodiments, referring to Figure 3 , Figure 3 FIG. 13 is another cross-sectional structure schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. At least one second conductive pad 105 is located on the top surface 132a of the second dielectric layer 132. In some examples, at least one second conductive pad 105 may be in contact with the top surface 132a of the second dielectric layer 132; in other embodiments, at least one second conductive pad 105 may not be in direct contact with the top surface 132a of the second dielectric layer 132.

[0052] It should be noted that the second conductive pad 105 in contact with the top surface 132a of the second dielectric layer 132 is not electrically connected to the first conductive pad 101. Further, the second conductive pad 105 in contact with the top surface 132a of the second dielectric layer 132 may also not be electrically connected to the semiconductor device. In other words, no electrical signal may be transmitted on the second conductive pad 105 in contact with the top surface 132a of the second dielectric layer 132.

[0053] In this case, on the one hand, when an external film layer structure is bonded to the second conductive pad 105, if there are other conductive pads in the external film layer structure, signal transmission occurs between some of the other conductive pads and the second conductive pad 105 in electrical contact with the first conductive interconnect structure 103, but there are still remaining other conductive pads in the external film layer structure. Based on this, designing the second conductive pad 105 in contact with the top surface 132a of the second dielectric layer 132 is beneficial to balancing the distribution density of the conductive pads in the external film layer structure and the distribution density of the second conductive pads 105 in the third dielectric layer 124, so that when the second conductive pad 105 is bonded to the external film layer structure, the degrees of influence of thermal expansion on the two bonding interfaces in contact with each other are similar, which is beneficial to improving the bonding strength between the second conductive pad 105 and the external film layer structure, so as to improve the contact performance between the second conductive pad 105 and the external film layer structure.

[0054] On the other hand, when an external film layer structure is bonded to the second conductive pad 105, there is a difference between the coefficient of thermal expansion of the external film layer structure itself and the overall coefficient of thermal expansion of the second conductive pad 105 and the third dielectric layer 124. By designing the second conductive pad 105 in contact with the top surface 132a of the second dielectric layer 132, it is also beneficial to adjust the distribution density of the second conductive pad 105 in the third dielectric layer 124, so that when the second conductive pad 105 is bonded to the external film layer structure, the degrees of influence of thermal expansion on the two bonding interfaces in contact with each other are similar, thereby facilitating the improvement of the bonding strength between the second conductive pad 105 and the external film layer structure, and improving the contact performance between the second conductive pad 105 and the external film layer structure.

[0055] In some embodiments, referring to Figure 1 , the first conductive pad 101 in electrical contact with the first conductive interconnect structure 103 includes a first portion 111 and a second portion 121. The second portion 121 is in direct contact with the first conductive interconnect structure 103, the first portion 111 is not in direct contact with the first conductive interconnect structure 103, and there is a portion of the surface of the second portion 121 in direct contact with the first conductive interconnect structure 103 that is lower than the surface of the first portion 111.

[0056] In some cases, with reference to the top surface 100a of the first substrate 100, the top surface 121a of the second portion 121 is lower than the top surface 111a of the first portion 111.

[0057] The corresponding relationship between the first conductive pad 101 and the first conductive interconnect structure 103 includes at least the following two embodiments:

[0058] In some embodiments, referring to Figure 1 or Figure 3 , only the orthographic projection of one first conductive pad 101 on the first substrate 100 overlaps with the orthographic projection of one first conductive interconnect structure 103 on the first substrate 100, that is, the first conductive pad 101 and the first conductive interconnect structure 103 are in a one-to-one relationship.

[0059] It should be noted that Figure 1 and Figure 3 both take the example that in the horizontal direction Y, the length of the first conductive pad 101 is greater than the length of the first conductive pad 101 in electrical contact with the first conductive interconnect structure 103. In practical applications, when the first conductive pad 101 and the first conductive interconnect structure 103 are in a one-to-one relationship, the size relationship between the lengths of the first conductive pad 101 and the first conductive interconnect structure 103 in the horizontal direction Y is not limited.

[0060] In some cases, when the first conductive pad 101 and the first conductive interconnect structure 103 are in a one-to-one correspondence, the first conductive pad 101 can be a wiring layer, and this wiring layer can be located in the peripheral region of the semiconductor structure. Refer to Figure 3 , the first conductive pad 101 includes a first wiring layer 131 and a second wiring layer 141. Along the length direction Y, the first length L1 of the first wiring layer 131 is greater than the second length L2 of the second wiring layer 141.

[0061] It should be noted that the first wiring layer 131 and the second wiring layer 141 in the first conductive pad 101 can be regarded as the same-layer structure, that is, they are both located within the film layer interval where the first conductive pad 101 is located. However, the first wiring layer 131 and the second wiring layer 141 can be insulated from each other to realize the electrical connection between different conductive structures. In addition, in addition to the first wiring layer 131 and the second wiring layer 141, the first conductive pad 101 can also include a third wiring layer, a fourth wiring layer, or a fifth wiring layer, etc. Moreover, the first wiring layer 131 and the second wiring layer 141 can be an integrally formed structure, that is, except for the different functions realized, such as being electrically connected to different semiconductor devices, the film layer structure and materials of the first wiring layer 131 and the second wiring layer 141 are the same. Figure 3 The same filling method is used to draw the first wiring layer 131 and the second wiring layer 141 in

[0062] In some embodiments, continue to refer to Figure 3 , along the horizontal direction Y, there can also be an isolation layer 151 between the first wiring layer 131 and the second wiring layer 141. For example, there is an isolation layer 151 in the first dielectric layer 122, which is beneficial to improving the insulation effect between the first wiring layer 131 and the second wiring layer 141 through the isolation layer 151.

[0063] In some embodiments, refer to Figure 4 , Figure 4 This is another cross-sectional structure schematic diagram of the semiconductor structure provided by an embodiment of the present disclosure. In some embodiments, the first conductive pad 101 includes a barrier layer 161 and a conductive layer 171. Along the vertical direction X, the conductive layer 171 has opposite first and second sides, and the barrier layer 161 covers at least the first side and the second side.

[0064] It can be understood that the barrier layer 161 is used to prevent the conductive ions in the conductive layer 171 from diffusing and migrating into the sub-filling layer 102, avoiding the reduction of the self-conductive performance of the conductive layer 171 due to the diffusion and migration of conductive ions, and avoiding the reduction of the self-insulating performance of the sub-filling layer 102 due to the migration of conductive ions. That is, it is beneficial to ensure the high conductivity of the conductive layer 171 itself and the high insulation performance of the sub-filling layer 102 itself.

[0065] It should be noted that in combination with reference toFigure 3 and Figure 4 For the first wiring layer 131 and the second wiring layer 141, both may include a barrier layer 161 and a conductive layer 171. In practical applications, the first conductive pad 101 may also include only the conductive layer 171.

[0066] In some embodiments, the material of the barrier layer 161 is at least one of titanium or titanium nitride, and the material of the conductive layer 171 is aluminum. In this way, the barrier layer 161 is beneficial to preventing the electromigration of aluminum ions.

[0067] In some other embodiments, referring to Figure 5 , Figure 5 FIG. is a schematic cross-sectional structure diagram of still another semiconductor structure provided by an embodiment of the present disclosure. The orthographic projection of at least two first conductive pads 101 on the first substrate 100 overlaps with the orthographic projection of a first conductive interconnect structure 103 on the first substrate 100. In this way, a first conductive interconnect structure 103 is in electrical contact with at least two first conductive pads 101. On the one hand, it is beneficial to improve the transmission efficiency of electrical signals among the first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105. On the other hand, along the horizontal direction Y, the length of the first conductive interconnect structure 103 is greater than the length of a single first conductive pad 101, which is beneficial to improving the alignment accuracy between the first conductive pad 101 and the first conductive interconnect structure 103, and is more beneficial to the overall electrical contact between a single first conductive pad 101 and the first conductive interconnect structure 103, thereby being beneficial to increasing the contact area between the first conductive pad 101 and the first conductive interconnect structure 103 to reduce the contact resistance therebetween, and further improving the transmission efficiency of electrical signals.

[0068] In still some other embodiments, a first conductive pad 101 is correspondingly connected to a first conductive interconnect structure 103 to form a connection path separately between each first conductive pad 101 and the corresponding second conductive pad 105.

[0069] In some cases, when the first conductive pads 101 and the first conductive interconnect structures 103 are many-to-one, the first conductive pads 101 may be signal extraction layers. For example, the signal extraction layer may be an I / O signal extraction layer or a power signal extraction layer or other types of signal extraction layers.

[0070] In some embodiments, in combination with reference to Figure 1 and Figure 6 , or in combination with reference to Figure 1 and Figure 7, the filling layer 142 may further include a first bonding layer 134. The second conductive pad 105 has a top surface 105a exposed to the first bonding layer 134. There is a second predetermined height difference H2 between the top surface 105a of the second conductive pad 105 exposed to the first bonding layer 134 and the top surface 134a of the first bonding layer 134. The range of the second predetermined height difference H2 is from 0 nm to 50 nm.

[0071] In some cases, the third dielectric layer 124 and the first bonding layer 134 together form the dielectric layer 104, and the second conductive pad 105 penetrates the dielectric layer 104 in the vertical direction X.

[0072] In some cases, refer to Figure 1 or Figure 7 for the second conductive pad D, the second predetermined height difference H2 (refer to Figure 6 ) can be 0 nm, that is, the top surface 134a of the first bonding layer 134 is flush with the top surface 105d of the second conductive pad D or, or with Figure 1 the top surface 105a of the second conductive pad 105 in Figure 7 . In other cases, refer to Figure 1 , the top surface 105e of the second conductive pad E is a concave surface recessed in the direction towards the first substrate 100 (refer to Figure 6 ). In this case, the second predetermined height difference H2 (refer to Figure 6 ) is greater than 0 and less than or equal to 50 nm. In still other cases, refer to Figure 7 or Figure 1 for the second conductive pad F in Figure 6 , the top surface 105a of the second conductive pad 105 is a convex surface protruding in the direction away from the first substrate 100 (refer to ). In this case, the second predetermined height difference H2 (refer to

[0073] ) is greater than 0 and less than or equal to 50 nm. It should be noted that Figure 6 is a schematic cross-sectional structure diagram of the second conductive pad and the filling layer in the semiconductor structure provided by an embodiment of the present disclosure; Figure 7 is another schematic cross-sectional structure diagram of the second conductive pad and the filling layer in the semiconductor structure provided by an embodiment of the present disclosure. In addition, to distinguish Figure 7 the three different second conductive pads 105 in Figure 7 , the three different second conductive pads 105 are respectively marked as D, E, and F, and the top surfaces 105a of the three different second conductive pads 105 are respectively marked as 105d, 105e, and 105f.

[0074] It should be noted that in an embodiment of the present disclosure, only the second predetermined height difference H2 between the top surface 134a of the first bonding layer 134 and the top surface 105a of the second conductive pad 105 is defined. However, based on the first substrate 100, it is not limited which one of the top surface 134a of the first bonding layer 134 and the top surface 105a of the second conductive pad 105 is higher or lower, and it can be adjusted according to the actual situation.

[0075] In addition, Figure 6 the second preset height difference H2 between the top surface 134a of the first bonding layer 134 and the top surface 105a of the second conductive pad 105 is defined as: along the vertical direction X, the maximum vertical distance between each point on the top surface 134a of the first bonding layer 134 and each point on the top surface 105a of the second conductive pad 105.

[0076] It should be noted that Figure 7 only exemplary descriptions of different morphologies of the top surface 105a of the second conductive pad 105 are given. The morphologies of the top surfaces 105a of different second conductive pads 105 in the same semiconductor structure can be the same or different, and can be adjusted according to the actual situation.

[0077] In some cases, when the first conductive pad 101 is an I / O signal lead-out layer, in the horizontal direction Y, the distance between adjacent first conductive pads 101 is small and the length of the first conductive pad 101 itself is small, so that the distance between the corresponding adjacent second conductive pads 105 is also small and the length of the second conductive pad 105 itself is also small. Based on this, by adjusting the process parameters for preparing the second conductive pad 105, the top surface 105a of the second conductive pad 105 is designed to be similar to Figure 6 shown, which is a convex surface protruding in the direction away from the first substrate 100 (refer to Figure 1 ). This is beneficial to improving the alignment accuracy when the second conductive pad 105 is subsequently bonded to the conductive pad in the external film layer structure and increasing the contact area between the second conductive pad 105 and the conductive pad in the external film layer structure, so as to improve the transmission efficiency of electrical signals between the two.

[0078] In some embodiments, referring to Figure 4 , the filling layer 142 includes a first dielectric layer 122 and a second dielectric layer 132. The first dielectric layer 122 and the second dielectric layer 132 form a sub-filling layer 102, and the sub-filling layer 102 has a first opening for wrapping the first conductive interconnect structure 103; the first conductive interconnect structure 103 includes: a first diffusion barrier layer 113, conformally covering the sidewalls and bottom surface of the first opening; a first seed layer 123, conformally covering the sidewalls and bottom surface of the first diffusion barrier layer 113; and a first electroplated layer 133, filling the remaining part of the first opening.

[0079] It should be noted that the first diffusion barrier layer 113 is used to block the diffusion and migration of conductive ions in the first seed layer 123 and the first electroplated layer 133 into the sub-fill layer 102, so as to prevent the self-conductivity of the first seed layer 123 and the first electroplated layer 133 from decreasing due to the diffusion and migration of conductive ions, and to prevent the self-insulation performance of the sub-fill layer 102 from decreasing due to the influx of conductive ions. That is, it is beneficial to the high conductivity of the first seed layer 123 and the first electroplated layer 133 themselves and the high insulation performance of the sub-fill layer 102 itself.

[0080] In some cases, the material of the first diffusion barrier layer 113 is at least one of tantalum or tantalum nitride, and the materials of the first seed layer 123 and the first electroplated layer 133 are copper. In this way, the first diffusion barrier layer 113 is beneficial to preventing the electromigration of copper ions.

[0081] In some embodiments, with continued reference to Figure 4 , the fill layer 142 includes a third dielectric layer 124, and the third dielectric layer 124 has a second opening that wraps the second conductive pad 105; the second conductive pad 105 includes: a second diffusion barrier layer 115 that conformally covers the sidewalls and bottom surface of the second opening; a second seed layer 125 that conformally covers the sidewalls and bottom surface of the second diffusion barrier layer 115; and a second electroplated layer 135 that fills the remaining part of the second opening.

[0082] It should be noted that the second diffusion barrier layer 115 is used to block the diffusion and migration of conductive ions in the second seed layer 125 and the second electroplated layer 135 into the third dielectric layer 124, so as to prevent the self-conductivity of the second seed layer 125 and the second electroplated layer 135 from decreasing due to the diffusion and migration of conductive ions, and to prevent the self-insulation performance of the third dielectric layer 124 from decreasing due to the influx of conductive ions. That is, it is beneficial to the high conductivity of the second seed layer 125 and the second electroplated layer 135 themselves and the high insulation performance of the third dielectric layer 124 itself.

[0083] In some embodiments, the material of the second diffusion barrier layer 115 is at least one of tantalum or tantalum nitride, and the materials of the second seed layer 125 and the second electroplated layer 135 are copper. In this way, the second diffusion barrier layer 115 is beneficial to preventing the electromigration of copper ions.

[0084] It should be noted that Figure 4 the same filling method is used to draw the first diffusion barrier layer 113 and the second diffusion barrier layer 115 in . In practical applications, the materials of the first diffusion barrier layer 113 and the second diffusion barrier layer 115 can be the same or different.

[0085] In some embodiments, with reference to Figure 8 , Figure 8Another cross-sectional structure diagram of the semiconductor structure provided by an embodiment of the present disclosure. The semiconductor structure may further include: a second bonding layer 234 and a third conductive pad 205 located in the second bonding layer 234. The second bonding layer 234 is directly bonded to the first bonding layer 134, and the third conductive pad 205 is directly bonded to the second conductive pad 105.

[0086] It should be noted that the second bonding layer 234 and the first bonding layer 134 are directly bonded without using an adhesive. The direct bonding of the third conductive pad 205 and the second conductive pad 105 can achieve the electrical connection between the two.

[0087] In some embodiments, the third conductive pads 205 and the second conductive pads 105 may correspond one by one.

[0088] It should be noted that Figure 8 In the example, the orthographic projections of the third conductive pad 205 and the second conductive pad 105 on the first substrate 100 coincide. In practical applications, the size relationship between the orthographic projection areas of the third conductive pad 205 and the second conductive pad 105 on the first substrate 100 is not limited and can be adjusted according to actual needs. In addition, with reference to Figure 4 , the film layer structure inside the third conductive pad 205 is similar to the film layer structure inside the second conductive pad 105, which will not be elaborated here. In other words, the third conductive pad 205 also includes a diffusion barrier layer, a seed layer, and an electroplated layer.

[0089] In some embodiments, continuing to refer to Figure 8 , the semiconductor structure may further include: a second conductive interconnect structure 203, at least one third conductive pad 205 is in electrical contact with the same second conductive interconnect structure 203; a second filling layer 242, the second filling layer 242 fills the outer periphery and the space between each third conductive pad 205 and the second conductive interconnect structure 203; a second substrate 200, the second filling layer 242 is located in the second substrate 200.

[0090] It should be noted that Figure 8 In the example, three third conductive pads 205 are in electrical contact with the same second conductive interconnect structure 203. In practical applications, the number of third conductive pads 205 in electrical contact with the same second conductive interconnect structure 203 is not limited and can be adjusted according to the actual situation. In addition, the third conductive pad 205 is the other conductive pad in the external film layer structure described in the foregoing embodiments.

[0091] In some cases, the first substrate 100, the filling layer 142 located in the first substrate 100, and the first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105 located in the filling layer 142 are all components of the first semiconductor chip. The second substrate 200, the second filling layer 242 located in the second substrate 200, and the second conductive interconnect structure 203 and the third conductive pad 205 located in the second filling layer 242 are all components of the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are bonded at the first bonding layer 134, and electrical signal transmission is achieved through the bonding connection between the second conductive pad 105 and the third conductive pad 205.

[0092] It should be noted that, firstly, with reference to Figure 4 , the film layer structure inside the second conductive interconnect structure 203 is similar to the film layer structure inside the first conductive interconnect structure 103, which will not be elaborated here. In other words, the second conductive interconnect structure 203 also includes a diffusion barrier layer, a seed layer, and an electroplated layer. Secondly, with reference to Figure 4 , the film layer structure inside the second filling layer 242 is similar to the film layer structure inside the filling layer 142, which will not be elaborated here. In other words, the second filling layer 242 also includes multiple dielectric layers. Thirdly, the semiconductor devices included in the second substrate 200 and the semiconductor devices included in the first substrate 100 can be the same or different. If the semiconductor devices included in the second substrate 200 and the semiconductor devices included in the first substrate 100 are the same, the first semiconductor chip and the second semiconductor chip are of the same type. If the semiconductor devices included in the second substrate 200 and the semiconductor devices included in the first substrate 100 are different, the first semiconductor chip and the second semiconductor chip are of different types.

[0093] In summary, the first conductive pad 101 is mainly used to achieve electrical connection with a semiconductor device, the second conductive pad 105 is mainly used to achieve electrical connection with other electrical components, and the first conductive interconnect structure 103 is mainly used to achieve electrical connection between the first conductive pad 101 and the second conductive pad 105. On this basis, it is designed that the orthographic projection of at least two second conductive pads 105 on the first substrate 100 overlaps with the orthographic projection of one first conductive interconnect structure 103 on the first substrate 100, so that one first conductive interconnect structure 103 is in electrical contact with at least two second conductive pads 105. On the one hand, it is beneficial to improve the transmission efficiency of electrical signals among the first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105. On the other hand, along the horizontal direction Y, the length of the first conductive interconnect structure 103 is greater than the length of a single second conductive pad 105, which is beneficial to improving the alignment accuracy between the second conductive pad 105 and the first conductive interconnect structure 103, and is more beneficial to the overall electrical contact of a single second conductive pad 105 with the first conductive interconnect structure 103, thereby being beneficial to increasing the contact area between the second conductive pad 105 and the first conductive interconnect structure 103 to reduce the contact resistance between the two, and further improving the transmission efficiency of electrical signals.

[0094] Another embodiment of the present disclosure further provides a manufacturing method of a semiconductor structure for preparing the semiconductor structure described in the foregoing embodiment. The following will describe in detail the manufacturing method of the semiconductor structure provided in another embodiment of the present disclosure with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiment will not be elaborated herein. Through analysis, it is found that referring to Figure 9 In 9a of [reference document], in order to lead out the electrical connection layer 10 in the semiconductor structure, after forming the electrical connection layer 10 and the first isolation layer 11 wrapping the electrical connection layer 10, the first isolation layer 11 will be patterned to form an opening 12 exposing the electrical connection layer 10. In this patterning step, it is easy to cause etching damage to the exposed surface of the electrical connection layer 10, affecting the electrical connection performance between the subsequent electrical connection layer 10 and the conductive pillar.

[0095] It should be noted that Figure 9 9a to 9d in [reference document] are schematic cross-sectional structure diagrams corresponding to each step in a manufacturing method of a semiconductor structure.

[0096] With reference to Figure 9 9a and 9b in [reference document], a large second isolation layer 13 is deposited in the opening 12. In this deposition step, due to the existence of the opening 12, there is a large height difference, that is, step high, between the second isolation layer 13 formed on the top surface of the first isolation layer 11 and the second isolation layer 13 formed at the opening 12.

[0097] With reference to Figure 9For 9b and 9c, perform chemical mechanical polishing (CMP) on the second isolation layer 13. As Figure 9 there is a large height difference between different regions of the second isolation layer 13 as shown in b, which exacerbates the difficulty of achieving a flat surface of the second isolation layer 13 by chemical mechanical polishing.

[0098] Refer to Figure 9 In 9c, pattern the second isolation layer 13 after chemical mechanical polishing to form vias 14 exposing the electrical connection layer 10. To expose the electrical connection layer 10, the aspect ratio of the vias 14 is relatively large, such that in the step of etching the second isolation layer 13 to form the vias 14, the etching by-products formed in the vias 14 are not easily removed, and it is easy to have etching residues in the vias 14.

[0099] Combined with reference to Figure 9 In 9c and 9d, form conductive posts 15 in the vias 14. The presence of etching residues easily reduces the conductivity of the conductive posts 15, that is, increases the overall resistance of the conductive posts 15, and further easily causes poor contact between the conductive posts 15 and the electrical connection layer 10.

[0100] Continue to refer to Figure 9 In 9d, form a third isolation layer 16, and use a damascene process to form a conductive layer 17 in the third isolation layer 16.

[0101] As can be seen from the above description, in order to lead out the electrical connection layer 10 in the semiconductor structure, it is often necessary to deposit dielectric layers (for example, the first isolation layer 11, the second isolation layer 13, and the third isolation layer 16) and perform chemical mechanical polishing multiple times to achieve a flat surface. In this step, the difficulty of chemical mechanical polishing depends on the film uniformity of the formed isolation layer. Moreover, based on this, deep hole etching or damascene process is performed on the isolation layer, etc. The process flow is relatively complex, and deep hole etching easily causes problems such as poor contact between the electrical connection layer 10 and the conductive posts 15 due to excessive by-products.

[0102] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. Hereinafter, the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Figure 10 is a schematic flow chart corresponding to the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure; Figures 11 to 27 is a schematic cross-sectional structure diagram corresponding to each step in the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. It should be noted that, for the convenience of description and to clearly illustrate the steps of the semiconductor structure manufacturing method, the Figures 11 to 27 are all partial structure schematic diagrams of the semiconductor structure.

[0103] Refer to Figures 10 to 27, A method for manufacturing a semiconductor structure includes the following steps: S101: Provide a first substrate 100 having semiconductor devices therein, and form a plurality of first conductive pads 101 connecting the semiconductor devices; S102: Form a first opening 112 that exposes the surface of at least one first conductive pad 101; S103: Form a first conductive interconnect structure 103 filling the first opening 112; S104: Form a plurality of second conductive pads 105 on the first conductive interconnect structure 103 such that at least one first conductive pad 101 and at least one second conductive pad 105 are electrically connected through the first conductive interconnect structure 103.

[0104] Wherein, a filling layer 142 is formed on the outer periphery of each first conductive pad 101, each second conductive pad 105, and the first conductive interconnect structure 103. The first conductive interconnect structure 103 has a surface 103b buried by the filling layer 142 between adjacent second conductive pads 105 (refer to Figure 1 ).

[0105] It can be understood that, firstly, after forming the first opening 112 exposing the first conductive pad 101, no isolation layer filling the first opening 112 is formed, avoiding the step high problem of the subsequent formed isolation layer, further reducing the steps of chemical mechanical polishing, and thus facilitating the simplification of the process steps for manufacturing the semiconductor structure; secondly, the first conductive interconnect structure 103 can be formed in the first opening 112. On the one hand, it is beneficial to increase the contact area between the first conductive interconnect structure 103 and the first conductive pad 101 to reduce the contact resistance between the first conductive interconnect structure 103 and the first conductive pad 101. On the other hand, there is no need to form the first conductive interconnect structure 103 in contact connection with the first conductive pad 101 by means of deep hole etching, avoiding the etching by-products remaining between the first conductive pad 101 and the first conductive interconnect structure 103 or remaining in the first conductive interconnect structure 103, which is beneficial to improving the conductivity of the first conductive interconnect structure 103 itself, reducing the contact resistance between the first conductive interconnect structure 103 and the first conductive pad 101, and avoiding poor contact between the first conductive interconnect structure 103 and the first conductive pad 101.

[0106] In some embodiments, with continued reference to Figures 10 to 27 , the filling layer 142 may include a first dielectric layer 122, a second dielectric layer 132, and a third dielectric layer 124. The first conductive pad 101 is formed in the first dielectric layer 122, the second dielectric layer 132 is formed on the first dielectric layer 122, and the first dielectric layer 122 and the second dielectric layer 132 are formed before forming the first opening 112. The first opening 112 is formed in the first dielectric layer 122 and the second dielectric layer 132. How to form the first conductive pad 101 will be described in detail later.

[0107] The following will describe each step in the manufacturing method provided by an embodiment of the present disclosure in more detail with reference to the accompanying drawings. Refer to Figures 11 to 18 , S101: Provide a first substrate 100 having semiconductor devices therein, and form a plurality of first conductive pads 101 connecting the semiconductor devices. S102: Form a first opening 112, and the first opening 112 exposes the surface of at least one first conductive pad 101.

[0108] In some embodiments, the filling layer 142 includes a sub-filling layer 102 wrapping the first conductive pad 101, and the sub-filling layer 102 has a first opening 112 that at least exposes a partial top surface of the first conductive pad 101.

[0109] In some embodiments, forming the sub-filling layer 102 having the first opening 112 includes the following steps:

[0110] Refer to Figures 11 to 14 , the first substrate 100 without the first opening 112 formed (refer to Figure 15 ) includes the first conductive pad 101 and the sub-filling layer 102 wrapping the first conductive pad 101. It should be noted that Figures 11 to 14 the sub-filling layer 102 shown in Figures 12 to 14 seals and wraps all surfaces of the first conductive pad 101, and a first opening 112 will be formed inside the sub-filling layer 102 later. For the convenience of description, the reference numerals of the sub-filling layer after the first opening 112 is formed in Figures 15 to 27 and subsequent

[0111] are not distinguished. Figure 12 In some embodiments, refer to Figure 12 and subsequent Figure 13 and Figure 14 , the first dielectric layer 122 and the second dielectric layer 132 of the sub-filling layer 102 are the first dielectric layer and the second dielectric layer before the first opening 112 is formed. For the convenience of description, the reference numerals of the first dielectric layer and the second dielectric layer after the first opening 112 is formed in Figures 12 to 14 and subsequent Figures 15 to 27 are not distinguished.

[0112] It can be understood that in addition to the first conductive pad 101, the semiconductor structure also has other semiconductor devices, such as transistor structures, word lines, bit lines, and capacitor structures, etc. The first dielectric layer 122 and the second dielectric layer 132 together achieve electrical insulation between the first conductive pad 101 and other semiconductor devices in the semiconductor structure.

[0113] In some embodiments, the material of the first dielectric layer 122 is silicon oxide, and the material of the second dielectric layer 132 is silicon nitride. Thus, it is beneficial to improve the electrical insulation performance between the first conductive pad 101 and other conductive structures in the semiconductor structure by using silicon oxide, and at the same time, improve the hardness of the sub-fill layer 102 wrapping the first conductive pad 101 by using silicon nitride, that is, improve the overall structural stability of the sub-fill layer 102.

[0114] In some embodiments, referring to Figure 13 , the first conductive pad 101 may include a first wiring layer 131 and a second wiring layer 141. Along the horizontal direction Y, the first length L1 of the first wiring layer 131 is greater than the second length L2 of the second wiring layer 141. The partial surface of the first conductive pad 101 exposed by the subsequently formed first opening 112 includes: the partial surface of the first wiring layer 131 exposed by the first opening 112.

[0115] In some cases, the first conductive pad 101 may be a wiring layer, and this wiring layer may be in the peripheral area of the semiconductor structure. In one example, this wiring layer includes the above-mentioned first wiring layer 131 and second wiring layer 141. Based on this, there is a one-to-one relationship between the subsequently formed first conductive pad 101 and the first conductive interconnect structure 103.

[0116] It can be understood that the partial surface of the first wiring layer 131 exposed by the subsequently formed first opening 112 is used to contact and connect with the electrical connection layer in other semiconductor structures subsequently, so as to realize the electrical connection between two semiconductor structures. The second wiring layer 141 located in the sub-fill layer 102 can be used to realize the electrical connection between two conductive structures in the same semiconductor structure. In addition, along the horizontal direction Y, the first length L1 of the first wiring layer 131 is greater than the second length L2 of the second wiring layer 141, which is beneficial to forming a larger-sized first opening 112 subsequently to expose a larger area of the first wiring layer 131.

[0117] It should be noted that the first wiring layer 131 and the second wiring layer 141 in the first conductive pad 101 can be regarded as the same-layer structure, that is, both are located in the film layer interval where the first conductive pad 101 is located. However, the first wiring layer 131 and the second wiring layer 141 can be insulated from each other to realize the electrical connection between different conductive structures. In addition, in addition to the first wiring layer 131 and the second wiring layer 141, the first conductive pad 101 may also include a third wiring layer, a fourth wiring layer, or a fifth wiring layer, etc. Moreover, the first wiring layer 131 and the second wiring layer 141 can be an integrally formed structure, that is, except for the different functions realized by the first wiring layer 131 and the second wiring layer 141, the film layer structure and materials are the same. Figure 5 The first wiring layer 131 and the second wiring layer 141 are drawn by using the same filling method in

[0118] In some embodiments, with continued reference to Figure 13 , in the horizontal direction Y, an isolation layer 151 may further be provided between the first wiring layer 131 and the second wiring layer 141. For example, the isolation layer 151 is provided in the first dielectric layer 122, which is conducive to improving the insulation effect between the first wiring layer 131 and the second wiring layer 141 through the isolation layer 151.

[0119] In some embodiments, the isolation layer 151 may be an air gap.

[0120] In some embodiments, with reference to Figure 14 , the first conductive pad 101 may include: a barrier layer 161 and a conductive layer 171. Wherein, along the vertical direction X, the conductive layer 171 has opposite first and second sides, and the barrier layer 161 covers at least the first and second sides. It can be understood that the barrier layer 161 is used to prevent the conductive ions in the conductive layer 171 from diffusing and migrating into the sub-fill layer 102, avoiding the reduction of the conductivity of the conductive layer 171 due to the diffusion and migration of the conductive ions, and avoiding the reduction of the insulation performance of the sub-fill layer 102 due to the migration of the conductive ions, that is, it is conducive to ensuring the high conductivity of the conductive layer 171 itself and the high insulation performance of the sub-fill layer 102 itself.

[0121] It should be noted that, with combined reference to Figure 13 and Figure 14 , both the first wiring layer 131 and the second wiring layer 141 may include a barrier layer 161 and a conductive layer 171. The following description of subsequent steps is given by taking the semiconductor structure shown in Figure 14 as an example. In practical applications, the first conductive pad 101 may also only include the conductive layer 171.

[0122] In some embodiments, the material of the barrier layer 161 is at least one of titanium or titanium nitride, and the material of the conductive layer 171 is aluminum. In this way, the barrier layer 161 is conducive to preventing the electromigration of aluminum ions.

[0123] With combined reference to Figure 14 and Figure 15 , the sub-fill layer 102 is patterned to form a first opening 112, and the first opening 112 exposes a partial surface of the first conductive pad 101.

[0124] In some embodiments, with reference to Figure 14, on the basis that the sub-fill layer 102 includes a first dielectric layer 122 and a second dielectric layer 132 stacked along the vertical direction X, after the first opening 112 is formed, the first opening 112 is jointly surrounded by the remaining first dielectric layer 122 and the remaining second dielectric layer 132. It can be understood that in the step of patterning the sub-fill layer 102, both the first dielectric layer 122 and the second dielectric layer 132 are patterned.

[0125] In some embodiments, referring to Figure 15 , a damaged portion 107 exists on a part of the surface of the first conductive pad 101.

[0126] In some embodiments, the damage 107 on the surface of the first conductive pad 101 includes etching damage and probe contact damage. Among them, the etching damage may be the etching damage caused to the surface of the first conductive pad 101 by the etching process when patterning the first dielectric layer 122 to form the first opening 112; the probe contact damage is the probe mark left by the physical contact between the test probe and the first conductive pad 101 when testing the semiconductor structure using the exposed first conductive pad 101 after the first opening 112 exposes the surface of the first conductive pad 101. The probe mark damages the surface of the first conductive pad 101, for example, causing the surface of the first conductive pad 101 to bulge. It can be understood that whether it is etching damage or probe contact damage, the damage 107 will affect the electrical contact performance between the first conductive interconnect structure 103 formed in the first opening 112 later (refer to Figure 21 ) and the first conductive pad 101.

[0127] It should be noted that Figure 15 takes the number of damages 107 on the first conductive pad 101 as 2 as an example. In actual applications, the number of damages 107 on the first conductive pad 101 is determined according to the actual situation, and another embodiment of the present disclosure does not limit it. Moreover, Figure 15 the shape of the damage 107 is only an example, and an embodiment of the present disclosure does not limit it.

[0128] In some embodiments, continuing to refer to Figure 15 , on the basis that the first conductive pad 101 includes a barrier layer 161 and a conductive layer 171, in the step of patterning the sub-fill layer 102 to form the first opening 112, a layer of the barrier layer 161 is also etched to expose the first opening 112, that is, the first opening 112 exposes the barrier layer 161, so that the subsequently formed first conductive interconnect structure 103 is directly in contact with the conductive layer 171.

[0129] In some embodiments, referring to Figures 15 to 22, the filling layer 142 may further include a fourth dielectric layer 106, which is formed after the formation of the first opening 112 and before the formation of the first conductive interconnect structure 103, such that the fourth dielectric layer 106 is located between the first conductive interconnect structure 103 and the first dielectric layer 122 and the second dielectric layer 132.

[0130] The steps of forming the fourth dielectric layer 106 are described in detail below.

[0131] Reference Figures 15 to 22 , after the formation of the first opening 112 and before the formation of the first conductive interconnect structure 103, the manufacturing method may further include the following steps: forming the fourth dielectric layer 106 and removing at least part of the damage 107 on the first conductive pad 101, and the fourth dielectric layer 106 is located on the sidewall of the first opening 112.

[0132] It should be noted that Figure 18 taking the example that all the damage 107 on the first conductive pad 101 is removed, in actual applications, due to the limitations of the etching process or other requirements, a small amount of the damage 107 on the first conductive pad 101 may be retained.

[0133] Forming the fourth dielectric layer 106 and removing at least part of the damage 107 on the first conductive pad 101 includes at least the following two embodiments.

[0134] In some embodiments, reference Figure 16 , a first opening 112 exposes a part of the top surface of a first conductive pad 101. The thickness of the first conductive pad 101 whose top surface is exposed by the first opening 112 is a first thickness D1, and the thickness of the first conductive pad 101 whose top surface is not exposed by the first opening 112 is a second thickness D2, and the first thickness D1 is less than the second thickness D2.

[0135] It can be understood that the first conductive pad 101 whose top surface is exposed by the first opening 112 is the second part 121, the first thickness D1 is the thickness of the second part 121, the first conductive pad 101 whose top surface is not exposed by the first opening 112 is the first part 111, and the second thickness D2 is the thickness of the first part 111. Since in the step of forming the first opening 112, a part of the thickness of the second part 121 is also etched, the first thickness D1 is less than the second thickness D2, so that with the top surface 100a of the first substrate 100 as a reference, the top surface 121a of the second part 121 is lower than the top surface 111a of the first part 111.

[0136] In other embodiments, for the formation of Figure 5Taking the semiconductor structure shown as an example, the same first opening 112 exposes the top surfaces of a plurality of first conductive pads 101. Thus, the orthographic projections of at least two first conductive pads 101 on the first substrate 100 overlap with the orthographic projection of a first conductive interconnect structure 103 formed in one first opening 112 on the first substrate 100 subsequently, such that the first conductive pads 101 and the first conductive interconnect structure 103 are in a many-to-one relationship.

[0137] In some embodiments, the steps of forming the fourth dielectric layer 106 and removing at least part of the damage 107 on the first conductive pad 101 may include: with reference to Figure 16 and Figure 17 , an initial fourth dielectric layer 116 is formed, and the initial fourth dielectric layer 116 conformally covers the surface of the first opening 112 and the top surface 102a of the sub-fill layer 102. It can be understood that the initial fourth dielectric layer 116 will cover the damage 107, and the top surface 102a of the sub-fill layer 102 is the top surface 132a of the second dielectric layer 132 (refer to Figure 2 ).

[0138] It should be noted that when the first conductive pad 101 includes a first wiring layer 131 and a second wiring layer 141, the exposed wiring layer is the first wiring layer 131.

[0139] With reference to Figure 17 and Figure 18 , the initial fourth dielectric layer 116 is re-etched to remove the initial fourth dielectric layer 116 located on the top surface 102a of the sub-fill layer 102 and the bottom surface of the first opening 112, and the remaining initial fourth dielectric layer 116 is the fourth dielectric layer 106; wherein, in the step of re-etching the initial fourth dielectric layer 116, along the vertical direction X, a part of the thickness of the first conductive pad 101 exposed by the first opening 112 is also etched, in other words, a part of the thickness of the first conductive pad 101 exposed by the first opening 112 is etched away.

[0140] It can be understood that in the step of performing re-etching on the initial fourth dielectric layer 116 to form the fourth dielectric layer 106, the etching process removes the initial fourth dielectric layer 116 located at the bottom surface of the first opening 112, and also removes the damage 107 covered by the initial fourth dielectric layer 116, that is, etches the second portion 121, so as to achieve the purpose of removing at least part of the damage 107. At the same time, by using the fourth dielectric layer 106 located on the sidewall of the first opening 112, the sub-fill layer 102 constituting the sidewall of the first opening 112 is prevented from being etched. In addition, the steps of forming the fourth dielectric layer 106 and removing at least part of the damage 107 can be carried out synchronously. In this way, it is beneficial to use the fourth dielectric layer 106 to protect the sidewall of the first opening 112 during the step of etching the damage 107, and prevent the first dielectric layer 122 constituting the sidewall of the first opening 112 from being etched, so that the sidewall of the first opening 112 has a relatively flat interface, which is convenient for forming a first conductive interconnect structure 103 with regular dimensions subsequently. In addition, during the step of etching the damage 107, the etching process can also be used to remove possible contaminants on the surface of the first conductive pad 101, which is beneficial to further reducing the contact resistance between the subsequently formed first conductive interconnect structure 103 and the first conductive pad 101.

[0141] In practical applications, according to the adjustment of the etching process parameters, the thickness of the second portion 121 to be etched is adjusted to ensure that all of the damage 107 is removed.

[0142] In some embodiments, with continued reference to Figure 18 , in the step of performing re-etching on the initial fourth dielectric layer 116 to form the fourth dielectric layer 106 based on the conductive layer 171 exposed in the first opening 112, in the vertical direction X, the etching process may also etch a part of the thickness of the conductive layer 171, that is, etch at least part of the thickness of the second portion 121. In practical applications, the first opening may expose a barrier layer. In the step of performing re-etching on the initial fourth dielectric layer to form the fourth dielectric layer, the etching process will at least remove a barrier layer exposed in the first opening, so that the subsequently formed first conductive interconnect structure is directly in contact connection with the conductive layer.

[0143] It should be noted that Figures 16 to 18 in, the first portion 111 and the second portion 121 are demarcated by a thick dashed line. The demarcation of the first portion 111 and the second portion 121 in the first conductive pad 101 depends on the area of the first conductive pad 101 exposed in the first opening 112.

[0144] In other embodiments, with reference to Figure 16, the first conductive pad 101 whose top surface is exposed by the first opening 112 is the second part 121, and the first conductive pad 101 whose top surface is not exposed by the first opening 112 is the first part 111, and the exposed surface of the second part 121 has damage 107; the steps of forming the fourth dielectric layer 106 and removing at least part of the damage 107 on the first conductive pad 101 may include: referring to Figure 16 and Figure 19 , a mask layer 108 is formed, and the mask layer 108 is located on the sidewall of the first opening 112 and the top surface 102a of the sub-fill layer 102. The mask layer 108 exposes a part of the top surface of the first conductive pad 101 exposed by the remaining first opening 112, that is, a part of the top surface of the second part 121.

[0145] Referring to Figure 19 and Figure 20 , using the mask layer 108 as a mask to etch the damage 107, so as to etch a part of the thickness of the first conductive pad 101 exposed by the first opening 112 in the vertical direction X. In this way, it is beneficial to protect the sub-fill layer 102 through the mask layer 108 in the step of etching the damage 107.

[0146] Referring to Figure 20 and Figure 18 , the mask layer 108 is removed and the fourth dielectric layer 106 is formed.

[0147] It should be noted that the method for forming the fourth dielectric layer 106 after removing the mask layer 108 is not limited in the manufacturing method provided by another embodiment of the present disclosure. In some embodiments, the step of forming the fourth dielectric layer 106 may include: first forming a protective film that conformally covers the first opening and the second top surface of the first dielectric layer after removing the mask layer, and then performing a back-etching on the protective film to form the fourth dielectric layer 106.

[0148] It can be understood that after removing the damage 107, the fourth dielectric layer 106 is formed, avoiding the protective film for the next fourth dielectric layer 106 from being exposed in the etching environment for too long, which is beneficial to improving the film layer uniformity of the formed fourth dielectric layer 106, so as to improve the blocking effect of the fourth dielectric layer 106 on the diffusion and migration of conductive ions in the first conductive interconnect structure 103 formed subsequently.

[0149] S103: Form a first conductive interconnect structure 103 that fills the first opening 112. In some embodiments, referring to Figure 15 and Figure 21 , the fourth dielectric layer is not formed on the sidewall of the sub-fill layer 102, and the first conductive interconnect structure 103 is directly formed in the first opening 112. In practical applications, if there is damage 107 on the first conductive pad 101, the first conductive interconnect structure 103 covers the damage 107.

[0150] In some other embodiments, with reference to Figure 18 and Figure 22 , on the basis of forming the fourth dielectric layer 106, i.e., removing the damage 107 (refer to Figure 16 ), the step of filling the first conductive interconnect structure 103 into the first opening 112 includes: filling the remaining part of the first opening 112 with the first conductive interconnect structure 103. It can be understood that the fourth dielectric layer 106 and the first conductive interconnect structure 103 together fill the first opening 112 completely.

[0151] It should be noted that the subsequent semiconductor structure shown in Figure 18 will be used to describe in detail the formation of the first conductive interconnect structure 103 and the second conductive pad 105.

[0152] In some embodiments, with reference to Figure 18 and Figure 23 , the step of forming the first conductive interconnect structure 103 may include: forming a first diffusion barrier layer 113, the first diffusion barrier layer 113 conformally covering the inner wall of the first opening 112 and the top surface 102a of the sub-fill layer 102; forming a first seed layer 123, the first seed layer 123 conformally covering the surface of the first diffusion barrier layer 113; forming a first electroplated layer 133, the first electroplated layer 133 filling the remaining part of the first opening 112 and located at the top surface 123a of the first seed layer 123 away from the sub-fill layer 102.

[0153] With reference to Figure 23 and Figure 24 , the first diffusion barrier layer 113, the first seed layer 123 and the first electroplated layer 133 are planarized until the top surface 102a of the sub-fill layer 102 is exposed, and the remaining first diffusion barrier layer 113, the remaining first seed layer 123 and the remaining first electroplated layer 133 constitute the first conductive interconnect structure 103.

[0154] It can be understood that forming the first electroplated layer 133 by electroplating based on the first seed layer 123 is beneficial to improving the conductivity of the first electroplated layer 133, so as to further improve the overall conductivity of the first conductive interconnect structure 103. In addition, the first diffusion barrier layer 113 is used to block the diffusion and migration of conductive ions in the first seed layer 123 and the first electroplated layer 133 into the sub-fill layer 102, avoiding the reduction of the conductivity of the first seed layer 123 and the first electroplated layer 133 due to the diffusion and migration of conductive ions, and avoiding the reduction of the insulation performance of the sub-fill layer 102 due to the introduction of conductive ions, that is, it is beneficial to the high conductivity of the first seed layer 123 and the first electroplated layer 133 themselves and the high insulation performance of the sub-fill layer 102 itself.

[0155] In some embodiments, the material of the first diffusion barrier layer 113 is at least one of tantalum or tantalum nitride, and the materials of the first seed layer 123 and the first electroplated layer 133 are copper. Thus, the first diffusion barrier layer 113 helps prevent the electromigration of copper ions.

[0156] In some embodiments, after forming the first conductive interconnect structure 103 in the first opening 112, the surface of the first conductive interconnect structure 103 is planarized, referring to Figure 2 , such that there is a first preset height difference H1 between the top surface 132a of the second dielectric layer 132 and the top surface 103a of the first conductive interconnect structure 103, and the range of the first preset height difference H1 is 0 nm to 50 nm.

[0157] In some embodiments, referring to Figures 24 to 27 , S104: Form a plurality of second conductive pads 105 on the first conductive interconnect structure 103, such that at least one first conductive pad 101 and at least one second conductive pad 105 are electrically connected through the first conductive interconnect structure 103.

[0158] In some embodiments, referring to Figures 24 to 27 , after forming the first conductive interconnect structure 103, a dielectric layer 104 is formed, and second conductive pads 105 electrically connected to the first conductive interconnect structure 103 are formed in the third dielectric layer 104.

[0159] In some embodiments, referring to Figure 27 , the step of forming the second conductive pads 105 may include: forming at least two second conductive pads 105 in contact connection with the top surface 103a of a first conductive interconnect structure 103 away from the first conductive pad 101. It can be understood that a first conductive interconnect structure 103 being in contact connection with at least two second conductive pads 105 helps improve the transmission efficiency of electrical signals among the first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pads 105.

[0160] It should be noted that Figure 27 takes a first conductive interconnect structure 103 being in contact connection with three second conductive pads 105 as an example. In actual applications, the number of second conductive pads 105 in contact connection with the same first conductive interconnect structure 103 can be determined according to actual needs, for example, it can be 1, 2, 4, 5, etc.

[0161] In some embodiments, forming at least two second conductive pads 105 may include the following steps:

[0162] Referring to Figure 25 , a dielectric layer 104 is formed on the top surface jointly formed by the sub-fill layer 102 and the first conductive interconnect structure 103.

[0163] In some embodiments, with continued reference to Figure 25 , a third dielectric layer 124 and a first bonding layer 134 are stacked on the second dielectric layer 132, and the third dielectric layer 124 and the first bonding layer 134 constitute the dielectric layer 104. It can be understood that the third dielectric layer 124 and the first bonding layer 134 together achieve electrical insulation between the second conductive pad 105 formed subsequently in the dielectric layer 104 and other conductive structures in the semiconductor structure.

[0164] In some embodiments, the material of the third dielectric layer 124 is silicon oxide, and the material of the first bonding layer 134 is silicon nitride. In this way, it is beneficial to improve the electrical insulation performance between the second conductive pad 105 formed subsequently in the third dielectric layer 124 and other conductive structures in the semiconductor structure by using silicon oxide, and at the same time, improve the hardness of the dielectric layer 104, that is, improve the mechanical stability of the overall structure, by using silicon nitride.

[0165] With combined reference to Figure 25 and Figure 26 , the dielectric layer 104 is patterned to form a plurality of second openings 114 spaced apart from each other. At least two second openings 114 expose different regions of the top surface 103a of the same first conductive interconnect structure 103, and other second openings 114 expose the top surface 102a of the sub-fill layer 102 in the fill layer 142.

[0166] It can be understood that the first conductive interconnect structure 103 in contact connection with the second conductive pad 105 has already been formed in the sub-fill layer 102. Only by forming the second openings 114 in the dielectric layer 104 and then forming the second conductive pads 105 that fill the second openings 114, the depth of the second openings 114 for forming the second conductive pads 105 is only related to the thickness of the dielectric layer 104. Even if the width of the second openings 114 in the horizontal direction Y is smaller than the width of the first conductive interconnect structure 103 in the horizontal direction Y, the aspect ratio of the second openings 114 will not be very large, and it is not easy to have residues of etching by-products at the contact between the first conductive interconnect structure 103 and the second conductive pad 105. The etching by-products here mainly originate from the step of patterning the dielectric layer 104.

[0167] With combined reference to Figure 26 and Figure 27 , a second diffusion barrier layer 115 is formed, and the second diffusion barrier layer 115 conformally covers the inner walls of the second openings 114; a second seed layer 125 is formed, and the second seed layer 125 conformally covers the surface of the second diffusion barrier layer 115; a second electroplated layer 135 is formed, and the second electroplated layer 135 fills the remaining part of the second openings 114. The second diffusion barrier layer 115, the second seed layer 125, and the second electroplated layer 135 constitute the second conductive pad 105.

[0168] It can be understood that forming the second electroplated layer 135 based on the second seed layer 125 by electroplating is beneficial to improving the conductivity of the second electroplated layer 135, so as to further improve the overall conductivity of the second conductive pad 105. In addition, the second diffusion barrier layer 115 is used to block the diffusion and migration of conductive ions in the second seed layer 125 and the second electroplated layer 135 into the dielectric layer 104, avoiding the reduction of the self-conductivity of the second seed layer 125 and the second electroplated layer 135 due to the diffusion and migration of conductive ions, and avoiding the reduction of the self-insulation performance of the dielectric layer 104 due to the influx of conductive ions, that is, it is beneficial to the relatively high conductivity of the second seed layer 125 and the second electroplated layer 135 themselves and the relatively high insulation performance of the dielectric layer 104 itself.

[0169] In some embodiments, the material of the second diffusion barrier layer 115 is at least one of tantalum or tantalum nitride, and the materials of the second seed layer 125 and the second electroplated layer 135 are copper. In this way, the second diffusion barrier layer 115 is beneficial to preventing the electromigration of copper ions.

[0170] It should be noted that Figure 27 the first diffusion barrier layer 113 and the second diffusion barrier layer 115 are drawn using the same filling method. In practical applications, the materials of the first diffusion barrier layer 113 and the second diffusion barrier layer 115 may be the same or different.

[0171] In some embodiments, referring to Figure 8 , the filling layer may further include a first bonding layer 134. The second conductive pad 105 has a top surface exposed to the first bonding layer 134. There is a second predetermined height difference H2 between the top surface of the second conductive pad 105 exposed to the first bonding layer 134 and the top surface of the first bonding layer 134. The range of the second predetermined height difference H2 is 0 nm to 50 nm. After forming the second conductive pad 105, the manufacturing method may further include: forming a second bonding layer 234 directly bonded to the first bonding layer 134 and a third conductive pad 205 directly bonded to the second conductive pad 105.

[0172] It should be noted that the steps of forming the third conductive pad 205 are similar to the steps of forming the second conductive pad 105, and will not be elaborated here.

[0173] In summary, after forming the first opening 112 exposing the first conductive pad 101, a first conductive interconnect structure 103 is formed in the first opening 112, reducing the steps of forming an isolation layer filling the first opening 112 and forming a through hole for forming a conductive pillar in the isolation layer, which is beneficial to simplifying the process steps of fabricating a semiconductor structure. Moreover, forming the first conductive interconnect structure 103 in the first opening 112 is beneficial in increasing the contact area between the first conductive interconnect structure 103 and the first conductive pad 101 to reduce the contact resistance therebetween. On the other hand, there is no need to form the first conductive interconnect structure 103 in contact connection with the first conductive pad 101 by means of deep hole etching, that is, avoiding the generation of etching by-products that are difficult to remove, so as to prevent the etching by-products from remaining between the first conductive pad 101 and the first conductive interconnect structure 103 or remaining in the first conductive interconnect structure 103. Therefore, it is beneficial to improve the conductivity of the first conductive interconnect structure 103 itself, reduce the contact resistance between the first conductive interconnect structure 103 and the first conductive pad 101, avoid poor contact between the first conductive interconnect structure 103 and the first conductive pad 101, and improve the electrical performance of the semiconductor structure.

[0174] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present disclosure. In practical applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A first substrate and semiconductor devices located in the first substrate; A plurality of first conductive pads connecting the semiconductor devices; A plurality of second conductive pads, at least one of the first conductive pads and at least one of the second conductive pads being electrically connected by a first conductive interconnect structure extending in a direction perpendicular to the first substrate; A filling layer filling the outer peripheries of the respective first conductive pads, the first conductive interconnect structure, and the respective second conductive pads; Wherein, the first conductive interconnect structure has a surface buried by the filling layer between adjacent second conductive pads.

2. The semiconductor structure according to claim 1, characterized in that, The filling layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer covers the first conductive pad, the third dielectric layer covers the sidewalls of the second conductive pad, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and there is a first preset height difference between the top surface of the second dielectric layer and the top surface of the first conductive interconnect structure, and the range of the first preset height difference is 0nm to 50nm.

3. The semiconductor structure according to claim 2, characterized in that, The first dielectric layer and the second dielectric layer constitute a sub-filling layer; the filling layer further includes a fourth dielectric layer located between the sub-filling layer and the first conductive interconnect structure.

4. The semiconductor structure according to claim 2, characterized in that, At least one of the second conductive pads is located on the top surface of the second dielectric layer.

5. The semiconductor structure according to claim 4, characterized in that, The second conductive pad located on the top surface of the second dielectric layer is not electrically connected to the first conductive pad, and the second conductive pad is in direct contact with the top surface of the second dielectric layer.

6. The semiconductor structure according to claim 1, characterized in that, The first conductive pad in electrical contact with the first conductive interconnect structure includes a first portion and a second portion. The second portion is in direct contact with the first conductive interconnect structure, the first portion is not in direct contact with the first conductive interconnect structure, and there is a portion of the surface of the second portion in direct contact with the first conductive interconnect structure that is lower than the surface of the first portion.

7. The semiconductor structure according to claim 1, characterized in that, The orthographic projections of at least two of the first conductive pads on the first substrate overlap with the orthographic projection of one of the first conductive interconnect structures on the first substrate.

8. The semiconductor structure according to claim 1, characterized in that, The filling layer includes a first bonding layer, and the second conductive pad has a top surface exposed to the first bonding layer. There is a second predetermined height difference between the top surface of the second conductive pad exposed to the first bonding layer and the top surface of the first bonding layer, and the range of the second predetermined height difference is 0nm to 50nm.

9. The semiconductor structure according to claim 8, characterized in that, Further comprising: A second bonding layer and third conductive pads located in the second bonding layer. The second bonding layer is directly bonded to the first bonding layer, and the third conductive pads are directly bonded to the second conductive pads.

10. The semiconductor structure according to claim 1, characterized in that, Further comprising: An isolation layer located in the filling layer between adjacent first conductive pads.

11. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a first substrate having semiconductor devices therein; Forming a plurality of first conductive pads connecting the semiconductor devices; Forming a first opening exposing the surface of at least one of the first conductive pads; Forming a first conductive interconnect structure filling the first opening; Form a plurality of second conductive pads on the first conductive interconnect structure such that at least one of the first conductive pads and at least one of the second conductive pads are electrically connected through the first conductive interconnect structure; Wherein, a filling layer is formed on the outer periphery of each of the first conductive pads, each of the second conductive pads, and the first conductive interconnect structure, and the first conductive interconnect structure has a surface buried by the filling layer between adjacent second conductive pads.

12. The manufacturing method according to claim 11, characterized in that, The filling layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first conductive pad is formed in the first dielectric layer, the second dielectric layer is formed on the first dielectric layer, and the first dielectric layer and the second dielectric layer are formed before the first opening is formed. The first opening is formed in the first dielectric layer and the second dielectric layer; After the first conductive interconnect structure is formed in the first opening, planarize the surface of the first conductive interconnect structure such that there is a first preset height difference between the top surface of the second dielectric layer and the top surface of the first conductive interconnect structure, and the range of the first preset height difference is 0nm to 50nm; After the first conductive interconnect structure is formed, form the third dielectric layer, and form the second conductive pad electrically connected to the first conductive interconnect structure in the third dielectric layer.

13. The manufacturing method according to claim 12, characterized in that, The filling layer further includes a fourth dielectric layer, and the fourth dielectric layer is formed after the first opening is formed and before the first conductive interconnect structure is formed, such that the fourth dielectric layer is located between the first conductive interconnect structure and the first dielectric layer and the second dielectric layer.

14. The manufacturing method according to claim 13, characterized in that, The step of forming the fourth dielectric layer includes: forming an initial fourth dielectric layer that conformally covers the surface of the first opening and the top surface of the second dielectric layer, and performing a re-etching on the initial fourth dielectric layer to remove the initial fourth dielectric layer located on the top surface of the second dielectric layer and the bottom surface of the first opening, and the remaining initial fourth dielectric layer is the fourth dielectric layer; wherein, in the step of performing the re-etching on the initial fourth dielectric layer, a part of the thickness of the first conductive pad exposed by the first opening is etched off.

15. The manufacturing method according to claim 11, characterized in that, The filling layer further includes a first bonding layer, the second conductive pad has a top surface exposed to the first bonding layer, and there is a second predetermined height difference between the top surface of the second conductive pad exposed to the first bonding layer and the top surface of the first bonding layer, and the range of the second predetermined height difference is 0nm to 50nm; after the second conductive pad is formed, it further includes forming a second bonding layer directly bonded to the first bonding layer and a third conductive pad directly bonded to the second conductive pad.

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