Gate drive circuit for switching converter

Abstract

The invention discloses a gate driving circuit for a switching converter. The gate driving circuit comprises a high-side driving circuit, a low-side driving circuit and a conduction duration control circuit, the high-side drive circuit provides a first gate drive signal to a high-side power switch of the switching converter, and the low-side drive circuit provides a second gate drive signal to a low-side power switch of the switching converter. The conduction duration control circuit responds to the first conduction duration control signal and a feedback signal indicating the state of the second gate drive signal to provide a first conduction duration adjusting signal, and responds to the second conduction duration control signal and the feedback signal indicating the state of the first gate drive signal to provide a second conduction duration adjusting signal. The first gate drive signal is generated in response to a first on-time adjustment signal, and the second gate drive signal is generated in response to a second on-time adjustment signal. According to the gate drive circuit, direct connection between the high-side power switch and the low-side power switch is avoided.

Description

Technical Field

[0001] The present disclosure relates to power circuits, and more particularly, to switching converters. Background Art

[0002] Power converters, such as switching regulators, are widely used to supply power to electronic devices. For example, a buck converter includes two power switches and an inductor, and is configured to convert an input voltage into an output voltage. Specifically, a first end of a high-side power switch is coupled to a voltage source (e.g., an input voltage terminal Vin), a second end of the high-side power switch is coupled to a first end of a low-side power switch (e.g., forming a switch node SW), and a second end of the low-side power switch is coupled to a reference ground. An output capacitor is coupled to an output voltage terminal Vout to filter the output voltage. A gate drive circuit is configured to provide gate drive signals to the two power switches. The gate drive circuit receives a pulse-width modulation (PWM) control signal and provides a first gate drive signal to a control end of the high-side power switch and a second gate drive signal to a control end of the low-side power switch. The high-side power switch alternately turns on and off in response to the first gate drive signal, and the low-side power switch alternately turns on and off in response to the second gate drive signal.

[0003] To prevent shoot-through caused by simultaneous conduction of the high-side power switch and the low-side power switch, a dead time is added before the low-side power switch turns on. However, for high-frequency switching converters, the conduction duration of the power switch is a very short pulse. For example, when the switching frequency of a buck converter is 18 MHz, each switching cycle is about 56 ns, and the conduction duration (e.g., 15 ns) may be less than the duration of the control logic delay, which may result in shoot-through of a large current. Therefore, it is necessary to propose a gate driver to control the conduction and turn-off of the power switch to prevent shoot-through. Summary of the Invention

[0004] Therefore, an object of the present disclosure is to solve the above technical problems of the prior art, and a gate drive circuit for a switching converter is proposed.

[0005] According to an embodiment of the present disclosure, a gate driving circuit for a switching converter is provided, including a high-side driving circuit, a low-side driving circuit, and a conduction duration control circuit. The high-side driving circuit is configured to provide a first gate driving signal to a high-side power switch of the switching converter. The low-side driving circuit is configured to provide a second gate driving signal to a low-side power switch of the switching converter. The conduction duration control circuit is configured to receive a first conduction duration control signal, a second conduction duration control signal, a first feedback signal indicating the state of the first gate driving signal, and a second feedback signal indicating the state of the second gate driving signal. The conduction duration control circuit is configured to provide a first conduction duration adjustment signal in response to the first conduction duration control signal and the second feedback signal, and provide a second conduction duration adjustment signal in response to the second conduction duration control signal and the first feedback signal. The first gate driving signal is generated in response to the first conduction duration adjustment signal, and the second gate driving signal is generated in response to the second conduction duration adjustment signal. The conduction duration of the first conduction duration adjustment signal is greater than the conduction duration of the first conduction duration control signal, and the conduction duration of the second conduction duration adjustment signal is greater than the conduction duration of the second conduction duration control signal.

[0006] According to an embodiment of the present disclosure, a gate driving circuit for a switching converter is provided, including a high-side driving circuit, a low-side driving circuit, and a conduction duration control circuit. The high-side driving circuit is configured to provide a first gate driving signal to a high-side power switch of the switching converter. The low-side driving circuit is configured to provide a second gate driving signal to a low-side power switch of the switching converter. The conduction duration control circuit is configured to receive a first conduction duration control signal, a second conduction duration control signal, a first feedback signal indicating the state of the first gate driving signal, and a second feedback signal indicating the state of the second gate driving signal. The conduction duration control circuit is configured to provide a first conduction duration adjustment signal in response to the first conduction duration control signal and the second feedback signal, and provide a second conduction duration adjustment signal in response to the second conduction duration control signal and the first feedback signal. The first gate driving signal is generated in response to the first conduction duration adjustment signal, and the second gate driving signal is generated in response to the second conduction duration adjustment signal.

[0007] According to an embodiment of the present disclosure, a gate driving circuit for a switching converter is provided, including a high-side driving circuit, a low-side driving circuit, and a conduction duration control circuit. The high-side driving circuit is configured to provide a first gate driving signal to a high-side power switch of the switching converter. The low-side driving circuit is configured to provide a second gate driving signal to a low-side power switch of the switching converter. The conduction duration control circuit is configured to receive a first conduction duration control signal, a second conduction duration control signal, a first feedback signal indicating the state of the first gate driving signal, and a second feedback signal indicating the state of the second gate driving signal. The conduction duration control circuit is configured to provide a first conduction duration adjustment signal in response to the first conduction duration control signal and the second feedback signal, and provide a second conduction duration adjustment signal in response to the second conduction duration control signal and the first feedback signal. The first gate driving signal is generated in response to the first conduction duration adjustment signal, and the second gate driving signal is generated in response to the second conduction duration adjustment signal. The first feedback signal is generated in response to the first conduction duration adjustment signal and a first delay, and the second feedback signal is generated in response to the second conduction duration adjustment signal and a second delay.

[0008] Compared with the conventional technology, the gate driving circuit of the present disclosure avoids shoot-through between the high-side power switch and the low-side power switch in a high-frequency switching converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a better understanding of the present disclosure, the present disclosure will be described in detail with reference to the following drawings:

[0010] Figure 1 A circuit block diagram of a power converter 100 according to an embodiment of the present disclosure;

[0011] Figure 2 A circuit structure diagram of a switching converter 10 with current-mode control according to an embodiment of the present disclosure;

[0012] Figure 3A A schematic diagram of simulation waveforms of signals of a gate driving circuit according to an embodiment of the present disclosure;

[0013] Figure 3B A schematic diagram of simulation waveforms of signals of a gate driving circuit according to an embodiment of the present disclosure;

[0014] Figure 4 A circuit block diagram of a gate driving circuit 400 for a switching converter 30 according to an embodiment of the present disclosure;

[0015] Figure 5 A circuit block diagram of a gate driving circuit 500 for a switching converter according to another embodiment of the present disclosure;

[0016] Figure 6Circuit diagram of a gate drive circuit 600 for a switching converter according to another embodiment of the present disclosure;

[0017] Figure 7 Circuit diagram of a gate drive circuit 700 for a switching converter according to another embodiment of the present disclosure;

[0018] In the drawings, the same or corresponding reference numerals are used to denote the same or corresponding elements. Detailed Description of the Embodiments

[0019] Specific embodiments of the present disclosure will be described in detail below. It should be noted that the embodiments described here are only for illustrative purposes and are not intended to limit the present disclosure. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those of ordinary skill in the art that: the present disclosure does not have to be practiced with these specific details. In other instances, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present disclosure.

[0020] Throughout the specification, references to "one embodiment", "an embodiment", "one example", or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment", "in an embodiment", "one example", or "an example" appearing throughout the specification do not necessarily all refer to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. It should be understood that when an element is referred to as being "coupled to" or "connected to" another element, it may be directly coupled or connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, no intervening elements are present. The same reference numerals indicate the same elements. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0021] Figure 1 Circuit diagram of a power converter 100 according to an embodiment of the present disclosure. As Figure 1 shown, the power converter 100 includes a switching converter 10, a gate driver 20, a feedback circuit 30, and a loop control circuit 40. The switching converter 10 includes at least one power switch that converts an input voltage V IN to an output voltage V OUT。In one embodiment, the switching converter 10 is a buck converter. In another embodiment, the switching converter 10 is a boost converter. In yet another embodiment, the switching converter 10 is a buck-boost converter. However, the present disclosure is not limited thereto. In different embodiments, the switching converter 10 can be any type of switched-mode power converter.

[0022] The feedback circuit 30 receives the output voltage V OUT and provides a feedback signal V OUT proportional to the output voltage V FB 。The loop control circuit 40 receives the feedback signal V FB and provides a PWM control signal S PWM to the gate driver 20. PWM In response to the PWM control signal S D , the gate driver 20 provides a drive signal (e.g., S

[0023] Figure 2 to at least one power switch of the switching converter. Figure 2 FIG. shows a circuit configuration diagram of a switching converter 10 with current-mode control according to an embodiment of the present disclosure. As FB shown, the loop control circuit 200 includes a compensation circuit 210, a current sensing ramp circuit 220, a comparison circuit 230, and a logic circuit 240. The compensation circuit 210 (e.g., an error amplifier) receives the feedback signal V REF and a reference signal V FB and, in response to the feedback signal V REF and the reference signal V

[0024] produces a compensation signal Comp. The current sensing ramp circuit 220 senses the inductor current IL and, in response to the inductor current IL, produces a ramp signal Ramp. In some embodiments, a ramp compensation circuit is employed to generate the ramp signal Ramp. The comparison circuit 230 (e.g., a comparator CMP) receives the compensation signal Comp and the ramp signal Ramp and provides a comparison signal. The logic circuit 240 (e.g., an RS latch) receives the comparison signal and a clock signal Clk and provides a PWM control signal PWM. IN The switching converter 10 includes at least one power switch that, in response to the PWM control signal PWM, converts an input voltage V OUT into an output voltage V

[0025] AsFigure 2 As shown, the power converter 10 includes a high-side power switch HS and a low-side power switch LS. To prevent shoot-through between the high-side power switch HS and the low-side power switch LS, it is necessary to detect whether the high-side power switch HS or the low-side power switch LS is conducting. One method is to detect the current flowing through the high-side power switch HS and the low-side power switch LS. However, for a high-frequency switching converter, since the current detection signal has a long settling time, using the current detection signal is not an ideal way. In one embodiment, the switching frequency of the buck converter is 18 MHz, and each switching cycle is about 56 ns. In such a short time, it is difficult to detect the current due to the influence of the settling time. Therefore, instead of detecting the current, the present disclosure detects the gate drive signal.

[0026] Figure 3A It is a schematic diagram of the simulation waveform of the signal of the gate drive circuit according to an embodiment of the present disclosure. As Figure 3A shown, the signal SPWM is the PWM control signal provided to the switching converter, the signal HSON is the on-time control signal for controlling the high-side power switch (such as Figure 2 the high-side power switch HS shown), and the signal LSON is the on-time control signal for controlling the low-side power switch (such as Figure 2 the low-side power switch LS shown). In this embodiment, the gate drive signal (such as obtaining the gate feedback signal HSFB / LSFB) is detected to prevent the inverted power switch (such as LS / HS) from conducting. That is, when the high-side power switch is conducting, the low-side power switch cannot conduct. In this embodiment, the on-time control signal LSON is completely complementary to the on-time control signal HSON. However, in some embodiments, there may be a dead time between turning off one power switch and turning on another power switch. There is a delay in the control loop. Therefore, when the on-time control signal HSON transitions to a logic high level at time t1, the detected gate feedback signal HSFB transitions to a logic high level at time t2. Specifically, at time t3 (i.e., the falling edge of the on-time control signal HSON), the gate feedback signal HSFB is at a logic high level, so the low-side power switch LS will not conduct (i.e., the on-time control signal LSB is at a logic low level). The low-side power switch LS is controlled by the on-time control signal LSB and conducts after time t3 (such as at time t4, i.e., after the detected gate feedback signal HSFB transitions to a logic low level). Therefore, shoot-through will not occur.

[0027] However, when the switching frequency of the buck converter is 18 MHz, each switching cycle is about 56 ns, and the on-time (such as 15 ns) may be less than the duration of the control logic delay, which may cause a large current shoot-through between the high-side power switch HS and the low-side power switch LS. AsFigure 3B As shown, since the conduction duration of the power switch (e.g., the duration when the signal HSON / LSON is at a logic high level) is a short pulse, the detected gate feedback signal HSFB changes to a logic high level at time t2', and time t2' is later than time t3' when the conduction duration control signal HSON changes to a low level. That is to say, the delay (i.e., the duration when the signal SDT is at a high level) is greater than the conduction duration of the high-side power switch M1. Therefore, the gate feedback signal HSFB fails to be detected between time t3' and time t2' due to the delay, resulting in shoot-through. For example, as Figure 3B shown, since the gate feedback signal HSFB is delayed and is at a logic low level between time t3' and time t2', the gate feedback signal HSFB cannot prevent the conduction of the low-side power switch LS. Therefore, the low-side power switch LS may conduct at time t3', that is, overlap with the falling edge of the conduction duration control signal HSON, resulting in shoot-through (as shown in time periods 362 and 372, for example). That is to say, when the delay duration is greater than the conduction duration of the power switch, since the gate drive signal is delayed and cannot be detected, the falling edge of one gate drive signal overlaps with the rising edge of another gate drive signal, resulting in shoot-through.

[0028] Figure 4 FIG. is a circuit block diagram of a gate drive circuit 400 for a switch converter 30 according to an embodiment of the present disclosure. In one embodiment, the switch converter 40 is a buck converter and has a high-side power switch and a low-side power switch. In one embodiment, the power switch is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFETs), and each MOSFET has a first terminal (e.g., a drain), a second terminal (e.g., a source), and a control terminal (e.g., a gate). The MOSFET can be n-type (i.e., NMOS) or p-type (i.e., PMOS). In one embodiment, the gate drive signal G1 / G2 is at a logic high level to turn on the power switch (e.g., M1 / M2), and the gate drive signal G1 / G2 is at a logic low level to turn off the power switch (e.g., M1 / M2). It should be noted that: for NMOS, a high level (gate-source voltage V GS ≥ threshold voltage Vth) is used to turn on the transistors M1 / M2, and a low level (gate-source voltage V GS < threshold voltage Vth) is used to turn off the transistors M1 / M2. For PMOS, a low level is used to turn on the transistors M1 / M2, and a high level is used to turn off the transistors M1 / M2.

[0029] The gate drive circuit 400 includes a conduction time control circuit 410, a high-side drive circuit 420, and a low-side drive circuit 430. In this embodiment, the gate drive signal (such as G1 / G2) is detected to prohibit the conduction of the inverted power switch (such as M2 / M1). Specifically, the conduction time control circuit 410 receives the conduction time control signal HS ON and the feedback signal indicating the state of the gate drive signal G2. In one embodiment, the feedback signal G2FB is obtained by detecting the gate drive signal G2. The conduction time control circuit 410 responds to the conduction time control signal HS ON and the feedback signal G2FB, and provides a conduction time adjustment signal HS ADJ . The high-side drive circuit 420 responds to the conduction time adjustment signal HS ADJ , generates the gate drive signal G1, and provides the gate drive signal G1 to the high-side power switch M1. The conduction time of the conduction time adjustment signal HS ADJ is longer than the conduction time of the conduction time control signal HS ON .

[0030] In one embodiment, the first conduction time T1 is generated in response to the feedback signal G1FB and the conduction time control signal HS ON . For example, by extending the conduction time of the conduction time control signal HS ON until the feedback signal G1FB is detected, the conduction time adjustment signal HS ADJ is generated.

[0031] In another embodiment, a first delay D1 is applied to the feedback signal G1FB. For example: the feedback signal G1FB is delayed to generate the conduction time adjustment signal HS ADJ , thereby prohibiting the conduction of the low-side power switch LS.

[0032] The conduction time control circuit 410 further receives the conduction time control signal LS ON and the feedback signal indicating the state of the gate drive signal G1. In one embodiment, this feedback signal is the gate drive signal G1. The conduction time control circuit 410 responds to the conduction time control signal LS ON and the feedback signal G1FB, and provides a conduction time adjustment signal LS ADJ . The low-side drive circuit 430 responds to the conduction time adjustment signal LS ADJ , generates the gate drive signal G2, and provides the gate drive signal G2 to the high-side power switch M2. The conduction time of the conduction time adjustment signal LS ADJ is longer than the conduction time of the conduction time control signal LS ON .

[0033] In one embodiment, the second conduction time T2(Figure 4 (not shown) in response to the feedback signal G2FB and the conduction duration control signal LS ON and is generated. Similarly, for example, the conduction duration control signal LS can be extended ON until the feedback signal G2FB is detected, to generate the conduction duration adjustment signal LS ADJ .

[0034] In another embodiment, the second delay D2 is applied to the feedback signal G2FB. For example: the feedback signal G2FB is delayed to generate the conduction duration adjustment signal LS ADJ , thereby prohibiting the high-side power switch HS from conducting.

[0035] Figure 5 is a circuit block diagram of the gate drive circuit 500 for a switching converter according to another embodiment of the present disclosure. As Figure 5 shown, the gate drive circuit 500 includes a conduction duration control circuit 510, a high-side drive circuit 520, and a low-side drive circuit 530.

[0036] In one embodiment, both the high-side drive circuit 520 and the low-side drive circuit 530 include a level shifter and an inverter circuit. In this embodiment, the conduction duration control circuit 500 is of the delayed feedback type. In one embodiment, the conduction duration control circuit 510 includes a logic circuit (for example: 4 RS latches SR1 to SR4). For example, the set terminal of the RS latch SR1 receives the conduction duration control signal HSON, and the RS latch SR1 is reset by the feedback signal LS_FB indicating the state of the gate drive signal G2, and provides the conduction duration adjustment signal HS1. Additional latches are added to both the high-side control and the low-side control to ensure that the conduction durations of the high / low-side switches are both greater than the propagation delay duration, thereby avoiding shoot-through.

[0037] Specifically, the RS latch SR2 receives the conduction duration adjustment signal HS1 and provides an output signal to the delay circuit T fdly . The delay circuit T fdly is used to extend the pulse of the signal. In one embodiment, the delay of the falling edge is extended. For example, the delay circuit T can be implemented by a complementary metal-oxide-semiconductor (CMOS) inverter with a resistor-capacitor (RC) circuit fdly。The delayed output signal is used to reset the RS latch SR2. The OR gate receives the delayed output signal and the output signal of the RS latch SR2, and generates a feedback signal HS_FB indicating the state of the gate drive signal G1. That is, the conduction duration of the conduction duration control signal HSON is extended to obtain the feedback signal HS_FB to prohibit the low-side power switch LSFET from conducting. In one embodiment, a first delay duration D1 is applied to the output signal of the RS latch SR2, so the feedback signal HS_FB is extended by the first delay duration D1. When the feedback signal HS_FB of logic high level is received, the conduction duration adjustment signal LS1 changes to logic low level to turn off the low-side power switch LSFET. Therefore, the low-side power switch LSFET does not conduct until the falling edge of the feedback signal HS_FB is detected (i.e., the low-side power switch LSFET conducts after the high-side power switch HSFET turns off).

[0038] Figure 6Circuit diagram of a gate drive circuit 600 for a switching converter according to another embodiment of the present disclosure. In this embodiment, the on-time control circuit 610 includes a logic circuit, and the logic circuit includes four RS latches SR1 to SR4. In one embodiment, the gate drive circuit 600 further includes level shifters 622, 632, 662, and 672. In this embodiment, both the high-side gate drive signal HSG and the low-side gate drive signal LSG are detected to ensure that each power switch conducts and turns off without shoot-through. For example, for the high-side gate drive circuit, not only the gate feedback signal LSG_FB of the low-side power switch LSFET is detected, but also an additional RS latch SR1 is added to detect the gate feedback signal HSG_FB of the high-side power switch HSFET. When the high-side power switch HSFET conducts (i.e., the on-time control signal HSON is at a logic high level), the high-side power switch HSFET cannot be turned off until the gate feedback signal HSG_FB transitions to a logic high level, to ensure that the high-side power switch HSFET is in the conducting state (i.e., the low-side power switch LSFET should be turned off) during the propagation delay of the control logic caused by the level shifter 672. That is, even when the on-time control signal HSON transitions to a logic low level and the gate feedback signal HSG_FB remains at a logic low level due to the propagation delay, the high-side power switch HSFET is still turned on by the drive signal HS1 (i.e., the low-side power switch LSFET is turned off) to avoid shoot-through. On the other hand, the RS latch SR4 is reset by the gate feedback signal HSG_FB. That is, after the falling edge of the gate feedback signal HSG_FB is detected (i.e., after the high-side power switch HSFET is turned off), the low-side power switch LSFET can conduct. Therefore, the gate drive circuit 600 of the present disclosure can avoid shoot-through without knowing the exact duration of the propagation delay of the control logic.

[0039] As Figure 6 shown, the RS latch SR1 receives the on-time control signal HSON, is reset by the gate feedback signal HSG_FB, and generates a set signal HS_SET. Optionally, an AND gate is used to receive the on-time control signal HSON and the inverted signal LS_SET generated by the RS latch SR3. Specifically, after receiving the delayed gate feedback signal LSG_FB, the RS latch SR1 is reset. That is, the on-time of the set signal HS_SET is extended, so that the RS latch SR2 can be reset by the gate feedback signal LSG_FB of the low-side power switch LSFET. In one embodiment, the RS latches SR1 and SR3 are implemented by NOR gates. In one embodiment, the RS latches SR2 and SR4 are implemented by NAND gates.

[0040] It should be noted that: AsFigure 6 As shown, since the high-side power switch HSFET is a PMOS, the gate feedback signal is inverted and then resets the RS latches SR1 and SR4.

[0041] Figure 7 FIG. 700 is a circuit diagram of a gate drive circuit for a switching converter according to another embodiment of the present disclosure. In this embodiment, instead of detecting the gate drive signal, a delay circuit T is used fdly to extend the pulse of the drive signal HS1 to generate a feedback signal HS1D. In one embodiment, the delay circuit T fdly extends the delay of the falling edge. The RS latch SR1 is reset by the feedback signal HS1D. That is, the conduction duration of the set signal HS_SET is extended, so that the RS latch SR2 can be reset by the feedback signal LS1D of the low-side power switch LSFET.

[0042] It should be understood that the control circuits and related elements, circuit structures, signals, and waveforms described or illustrated in the present disclosure above are for illustrative purposes only, and the present disclosure is not limited thereto. Those skilled in the art can understand that: according to actual applications, the control circuits of the present disclosure can be implemented by any other circuits with different circuit structures, and correspondingly controlled by different types of signals to achieve the corresponding functions. For example, the gate drive circuit and the logic circuit can be implemented by digital circuits, analog circuits, software, or circuits automatically generated by a hardware description language, or a combination of the above methods.

[0043] Although the present disclosure has been described with reference to several exemplary embodiments, it should be understood that the terms used are descriptive and exemplary, rather than restrictive. Since the present disclosure can be embodied in many forms without departing from the spirit or essence of the disclosure, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be broadly construed within the spirit and scope defined by the appended claims. Therefore, all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A gate drive circuit for a switching converter, comprising: a high-side driver circuit configured to provide a first gate drive signal to a high-side power switch of the switching converter; a low-side driver circuit configured to provide a second gate drive signal to a low-side power switch of the switching converter; as well as A conduction time control circuit is configured to receive a first conduction time control signal, a second conduction time control signal, a first feedback signal indicating a state of a first gate drive signal, and a second feedback signal indicating a state of a second gate drive signal, and provide a first conduction time adjustment signal in response to the first conduction time control signal and the second feedback signal, and provide a second conduction time adjustment signal in response to the second conduction time control signal and the first feedback signal; wherein The first gate drive signal is generated in response to the first on-time adjustment signal, and the second gate drive signal is generated in response to the second on-time adjustment signal, and the on-time of the first on-time adjustment signal is greater than the on-time of the first on-time control signal, and the on-time of the second on-time adjustment signal is greater than the on-time of the second on-time control signal. 2 . The gate driving circuit of claim 1 , wherein the on-time control circuit is further configured to generate a first on-time in response to a first feedback signal and a first on-time control signal.

3. The gate driving circuit according to claim 2, wherein the on-time control circuit is further configured to generate a first set signal, wherein: When the first on-time control signal is at a logic high level, the first set signal is at a logic high level, and when the logic high level of the first feedback signal is received, the first set signal is changed to a logic low level; When the first setting signal is at a logic high level, the first on-time adjustment signal is at a logic high level, and when the logic high level of the second feedback signal is received, the first on-time adjustment signal is changed to a logic low level; and The high-side power switch is turned on in response to a logic high level of the first on-time adjustment signal, and is turned off in response to a logic low level of the first on-time adjustment signal. 4 . The gate driving circuit of claim 1 , wherein the on-time duration control circuit is further configured to generate a second on-time duration in response to a second feedback signal and a second on-time duration control signal.

5. The gate driving circuit according to claim 4, wherein the on-time control circuit is further configured to generate a second set signal, wherein: When the second on-time control signal is at a logic high level, the second set signal is at a logic high level, and when the logic high level of the second feedback signal is received, the second set signal is changed to a logic low level; When the second setting signal is at a logic high level, the second on-time adjustment signal is at a logic high level, and when the logic high level of the first feedback signal is received, the second on-time adjustment signal is changed to a logic low level; and The low-side power switch is turned on in response to a logic high level of the second on-time adjustment signal, and is turned off in response to a logic low level of the second on-time adjustment signal.

6. The gate driving circuit according to claim 1, wherein the conduction time control circuit comprises: A first delay circuit is configured to receive a first on-time adjustment signal and provide a first feedback signal; as well as The second delay circuit is configured to receive a second on-time adjustment signal and provide a second feedback signal.

7. The gate driving circuit according to claim 1, wherein the conduction time control circuit comprises: A first logic circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the first logic circuit is configured to receive a first conduction duration control signal, the second input terminal of the first logic circuit is configured to receive a first feedback signal, and the output terminal of the first logic circuit is configured to provide a first set signal; A second logic circuit has a first input terminal, a second input terminal and an output terminal, the first input terminal of the second logic circuit is configured to receive a first set signal, the second input terminal of the second logic circuit is configured to receive a second feedback signal, and the output terminal of the second logic circuit is configured to provide a first on-time adjustment signal; a third logic circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the third logic circuit is configured to receive a second conduction duration control signal, the second input terminal of the third logic circuit is configured to receive a second feedback signal, and the output terminal of the third logic circuit is configured to provide a second set signal; as well as A fourth logic circuit has a first input terminal, a second input terminal and an output terminal, the first input terminal of the fourth logic circuit is configured to receive a second set signal, the second input terminal of the fourth logic circuit is configured to receive a first feedback signal, and the output terminal of the fourth logic circuit is configured to provide a second on-time adjustment signal.

8. The gate driving circuit according to claim 1, wherein: When the first on-time control signal is at a logic high level, the first on-time adjustment signal is at a logic high level, and when the second feedback signal is at a logic high level, the first on-time adjustment signal is changed to a logic low level, wherein the second feedback signal is generated in response to the second on-time adjustment signal and the second delay; and The high-side power switch is turned on in response to a logic high level of the first on-time adjustment signal, and is turned off in response to a logic low level of the first on-time adjustment signal.

9. The gate driving circuit according to claim 1, wherein: When the second on-time control signal is at a logic high level, the second on-time adjustment signal is at a logic high level, and when the logic high level of the first feedback signal is received, the second on-time adjustment signal is changed to a logic low level, wherein the first feedback signal is generated in response to the first on-time adjustment signal and the first delay; and The low-side power switch is turned on in response to a logic high level of the second on-time adjustment signal, and is turned off in response to a logic low level of the second on-time adjustment signal.

10. The gate driving circuit according to claim 1, wherein the on-time control circuit comprises: A first logic circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the first logic circuit is configured to receive a first on-time control signal, the second input terminal of the first logic circuit is configured to receive a second feedback signal, and the output terminal of the first logic circuit is configured to provide a first on-time adjustment signal; A second logic circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the second logic circuit is configured to receive a first on-time adjustment signal, the second input terminal of the second logic circuit is configured to receive a first delay, and the output terminal of the second logic circuit is configured to provide a first feedback signal; A third logic circuit has a first input terminal, a second input terminal and an output terminal, the first input terminal of the third logic circuit is configured to receive a second on-time control signal, the second input terminal of the third logic circuit is configured to receive a first feedback signal, and the output terminal of the third logic circuit is configured to provide a second on-time adjustment signal; as well as A fourth logic circuit has a first input terminal, a second input terminal and an output terminal, the first input terminal of the fourth logic circuit is configured to receive a second on-time adjustment signal, the second input terminal of the fourth logic circuit is configured to receive a second delay, and the output terminal of the fourth logic circuit is configured to provide a second feedback signal.

11. A gate drive circuit for a switching converter, comprising: a high-side driver circuit configured to provide a first gate drive signal to a high-side power switch of the switching converter; a low-side driver circuit configured to provide a second gate drive signal to a low-side power switch of the switching converter; as well as A conduction time control circuit is configured to receive a first conduction time control signal, a second conduction time control signal, a first feedback signal indicating a state of a first gate drive signal, and a second feedback signal indicating a state of a second gate drive signal, and provide a first conduction time adjustment signal in response to the first conduction time control signal and the first feedback signal, and provide a second conduction time adjustment signal in response to the second conduction time control signal and the second feedback signal; wherein The first gate driving signal is generated in response to the first on-time adjustment signal, and the second gate driving signal is generated in response to the second on-time adjustment signal.

12. The gate driving circuit according to claim 11, further comprising: A first level shifter configured to receive a first gate drive signal and provide a first feedback signal; as well as The second level shifter is configured to receive a second gate driving signal and provide a second feedback signal.

13. The gate driving circuit according to claim 11, wherein: When the first on-time control signal is at a logic high level, the first on-time adjustment signal is at a logic high level. When the logic high level of the first feedback signal is received, the first on-time adjustment signal is converted to a logic low level.

14. The gate driving circuit of claim 13, wherein the on-time control circuit is further configured to generate a first driving signal, wherein: When the first on-time adjustment signal is at a logic high level, the first drive signal is at a logic high level, and when the logic high level of the second feedback signal is received, the first drive signal is converted to a logic low level; and The high-side power switch is turned on in response to a logic high level of the first drive signal, and is turned off in response to a logic low level of the first drive signal.

15. The gate driving circuit according to claim 11, wherein the on-time control circuit comprises: A first logic circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the first logic circuit is configured to receive a first on-time control signal, the second input terminal of the first logic circuit is configured to receive a first feedback signal, and the output terminal of the first logic circuit is configured to provide a first on-time adjustment signal; a second logic circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the second logic circuit is configured to receive a first conduction duration adjustment signal, the second input terminal of the second logic circuit is configured to receive a second feedback signal, and the output terminal of the second logic circuit is configured to provide a first driving signal; a third logic circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the third logic circuit is configured to receive a second on-time control signal, the second input terminal of the third logic circuit is configured to receive a second feedback signal, and the output terminal of the third logic circuit is configured to provide a second on-time adjustment signal; as well as A fourth logic circuit has a first input terminal, a second input terminal and an output terminal. The first input terminal of the fourth logic circuit is configured to receive a second on-time adjustment signal, the second input terminal of the fourth logic circuit is configured to receive a first feedback signal, and the output terminal of the fourth logic circuit is configured to provide a second drive signal.

16. The gate driving circuit as claimed in claim 15, wherein the on-time control circuit further comprises: A first delay circuit is configured to receive a first driving signal and provide a first feedback signal; as well as The second delay circuit is configured to receive the second driving signal and provide a second feedback signal.

17. The gate driving circuit according to claim 11, wherein: When the second on-time control signal is at a logic high level, the second on-time adjustment signal is at a logic high level. When the logic high level of the second feedback signal is received, the second on-time adjustment signal is converted to a logic low level.

18. The gate driving circuit of claim 17, wherein the on-time control circuit is further configured to generate a second driving signal, wherein: When the second on-time adjustment signal is at a logic high level, the second drive signal is at a logic high level, and when the logic high level of the first feedback signal is received, the second drive signal is converted to a logic low level; and The low-side power switch is turned on in response to a logic high level of the second drive signal, and is turned off in response to a logic low level of the second drive signal.

19. A gate drive circuit for a switching converter, comprising: a high-side driver circuit configured to provide a first gate drive signal to a high-side power switch of the switching converter; a low-side driver circuit configured to provide a second gate drive signal to a low-side power switch of the switching converter; as well as A conduction time control circuit is configured to receive a first conduction time control signal, a second conduction time control signal, a first feedback signal indicating a state of a first gate drive signal, and a second feedback signal indicating a state of a second gate drive signal, and provide a first conduction time adjustment signal in response to the first conduction time control signal and the second feedback signal, and provide a second conduction time adjustment signal in response to the second conduction time control signal and the first feedback signal; wherein The first gate drive signal is generated in response to the first on-time adjustment signal, the second gate drive signal is generated in response to the second on-time adjustment signal, the first feedback signal is generated in response to the first on-time adjustment signal and the first delay, and the second feedback signal is generated in response to the second on-time adjustment signal and the second delay.

20. The gate driving circuit of claim 19, wherein: When the first on-time control signal is at a logic high level, the first on-time adjustment signal is at a logic high level, and when the logic high level of the second feedback signal is received, the first on-time adjustment signal is converted to a logic low level; wherein The high-side power switch is turned on in response to a logic high level of the first on-time adjustment signal, and is turned off in response to a logic low level of the first on-time adjustment signal.

21. The gate driving circuit of claim 20, wherein: When the second on-time adjustment signal is at a logic high level, the second feedback signal is at a logic high level, and the second feedback signal is converted to a logic low level in response to the second delay.

22. The gate driving circuit of claim 19, wherein: When the second on-time control signal is at a logic high level, the second on-time adjustment signal is at a logic high level, and when the logic high level of the first feedback signal is received, the second on-time adjustment signal is changed to a logic low level; in The low-side power switch is turned on in response to a logic high level of the second on-time adjustment signal, and is turned off in response to a logic low level of the second on-time adjustment signal.

23. The gate drive circuit of claim 22, wherein: When the first on-time adjustment signal is at a logic high level, the first feedback signal is at a logic high level, and the first feedback signal is converted to a logic low level in response to the first delay.

24. The gate driving circuit according to claim 19, wherein the on-time control circuit comprises: A first logic circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the first logic circuit is configured to receive a first on-time control signal, the second input terminal of the first logic circuit is configured to receive a second feedback signal, and the output terminal of the first logic circuit is configured to provide a first on-time adjustment signal; A second logic circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the second logic circuit is configured to receive a first on-time adjustment signal, the second input terminal of the second logic circuit is configured to receive a first delay, and the output terminal of the second logic circuit is configured to provide a first feedback signal; A third logic circuit has a first input terminal, a second input terminal and an output terminal, the first input terminal of the third logic circuit is configured to receive a second on-time control signal, the second input terminal of the third logic circuit is configured to receive a first feedback signal, and the output terminal of the third logic circuit is configured to provide a second on-time adjustment signal; as well as A fourth logic circuit has a first input terminal, a second input terminal and an output terminal, the first input terminal of the fourth logic circuit is configured to receive a second on-time adjustment signal, the second input terminal of the fourth logic circuit is configured to receive a second delay, and the output terminal of the fourth logic circuit is configured to provide a second feedback signal.

Images