Boost switch driver for high speed signal switching

Abstract

The invention relates to a boost switch driver for high speed signal switching. An example boost switch driver circuit includes two branches. The first branch includes a first transistor. The second branch includes a second transistor and a level shifter circuit. One of the transistors is an N-type transistor and the other is a P-type transistor. The circuit is configured to divide the input clock signal between the first branch and the second branch such that a portion of the input clock signal divided into the first branch is provided to the first transistor, and a portion of the input clock signal divided to the second branch is level shifted by the level shifter circuit to produce a level shifted input clock signal, and the level shifted input clock signal is provided to the second transistor. The circuit is further configured to combine the output of the first transistor with the output of the second transistor to produce an output clock signal.

Description

[0001] This application is a divisional application of the patent application for invention titled "Boosted Switch Driver for High-Speed Signal Switching" with the application date of August 13, 2021, application number 202110928221.5.

[0002] Cross-reference to Related Applications

[0003] This application claims the benefit of U.S. Patent Application No. 63 / 065,590, filed on August 14, 2020, titled "BOOSTED SWITCH DRIVERS FOR HIGH-SPEED SIGNAL SWITCHING", the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] The present disclosure generally relates to electronic devices and systems, and more particularly to switch drivers. Background Art

[0005] In electronic instrumentation and signal processing, a switch driver is a device that controls switches. For example, a sample-and-hold analog-to-digital converter (ADC) includes multiple switches and multiple switch drivers configured to control different switches. A switch driver can be described as "boosted" when the output voltage swing of the driver can exceed the core supply rail in a given circuit. For example, a boosted switch driver can be used in a radio frequency (RF) sampling ADC to control switches with high gate voltages while being able to handle large signal swings.

[0006] The cost, quality, and robustness of a boosted switch driver can be affected by various factors. Physical limitations (such as space / surface area) can further limit the requirements or specifications of a boosted switch driver, and thus trade-offs and ingenuity must be employed when designing the best boosted switch driver for a given application. Designing a boosted switch driver for high-speed signal switching (e.g., for an RF ADC) is particularly challenging. Summary of the Invention

[0007] According to one aspect of the present disclosure, there is provided an electronic component including: one or more switches; and a switch driver circuit for driving the one or more switches, the switch driver circuit including: an input for receiving an input clock signal; an output for providing an output clock signal; a first transistor and a second transistor, each including a first terminal and a second terminal; a third transistor coupled to the first transistor in a cascode arrangement; and a level shifter circuit for level shifting the input clock signal to generate a level-shifted input clock signal, wherein: the first terminal of the first transistor is for receiving a signal indicative of the input clock signal, the first terminal of the second transistor is for receiving a signal indicative of the level-shifted input clock signal, the second terminal of the first transistor is coupled to the third terminal of the third transistor, and the second terminal of the third transistor is coupled to the output, and the second terminal of the second transistor is coupled to the output.

[0008] According to another aspect of the present disclosure, there is provided an electronic component including: one or more switches; and a switch driver circuit for driving the one or more switches, the switch driver circuit including: an input for receiving an input clock signal; an output for providing an output clock signal; a first transistor and a second transistor, each including a first terminal and a second terminal; a first level shifter circuit for level shifting the input clock signal to generate a level-shifted input clock signal; and a second level shifter circuit; wherein: the first terminal of the first transistor is for receiving a signal indicative of the input clock signal, the first terminal of the second transistor is for receiving a signal indicative of the level-shifted input clock signal, the second terminal of the second transistor is coupled to the second level shifter circuit, each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output, the first level shifter circuit is for controlling a high voltage value of the level-shifted input clock signal, and the second level shifter circuit is for controlling a high voltage level of the output clock signal.

[0009] According to another aspect of the present disclosure, there is provided a switching driver circuit, comprising: an input for receiving an input clock signal; an output for providing an output clock signal; a first transistor and a second transistor, each comprising a first terminal and a second terminal; a first level shifter circuit for level shifting the input clock signal to generate a level-shifted input clock signal; and a second level shifter circuit; wherein: the first terminal of the first transistor is for receiving a signal indicative of the input clock signal, the first terminal of the second transistor is for receiving a signal indicative of the level-shifted input clock signal, the second terminal of the second transistor is coupled to the second level shifter circuit, and each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To provide a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like components, and in the drawings:

[0011] Figure 1 A circuit diagram is provided of an example circuit in accordance with some embodiments of the present disclosure in which a boost switching driver with level shifting in a branch of a P-type transistor can be used;

[0012] Figure 2 A circuit diagram is provided of an example circuit in accordance with some embodiments of the present disclosure having a boost switching driver with level shifting in a branch of a P-type transistor;

[0013] Figure 3 A circuit diagram is provided of an example level shifter circuit in accordance with some embodiments of the present disclosure configured to perform level shifting in a situation where the maximum / high signal level is controlled;

[0014] Figure 4 A circuit diagram is provided of an example circuit in accordance with some embodiments of the present disclosure having a boost switching driver with level shifting implemented using a level shifter circuit in a branch of a P-type transistor Figure 3 in a branch of a P-type transistor;

[0015] Figure 5 A circuit diagram is provided of an example circuit in accordance with some embodiments of the present disclosure having a boost switching driver and having an additional transistor, the boost switching driver having level shifting in a branch of a P-type transistor, the additional transistor being provided as a cascode transistor to an N-type transistor;

[0016] Figure 6A circuit diagram of an example circuit having a boost switch driver and an additional level shifter in accordance with some embodiments of the present disclosure, the boost switch driver having a level shift in a branch of a P-type transistor, the additional level shifter configured to control a minimum / low signal level;

[0017] Figure 7 A circuit diagram of an example circuit in accordance with some embodiments of the present disclosure in which a boost switch driver having a level shift in a branch of an N-type transistor can be used;

[0018] Figure 8 A circuit diagram of an example circuit having a boost switch driver in accordance with some embodiments of the present disclosure, the boost switch driver having a level shift in a branch of an N-type transistor;

[0019] Figure 9 A circuit diagram of an example level shifter circuit in accordance with some embodiments of the present disclosure, the example level shifter circuit configured to perform a level shift in a situation of controlling a minimum / low signal level;

[0020] Figure 10 A circuit diagram of an example circuit having a boost switch driver in accordance with some embodiments of the present disclosure, the boost switch driver having a level shift implemented using a level shifter circuit in a branch of an N-type transistor Figure 9 ;

[0021] Figure 11 A circuit diagram of an example circuit having a boost switch driver and an additional transistor in accordance with some embodiments of the present disclosure, the boost switch driver having a level shift in a branch of an N-type transistor, the additional transistor provided as a cascode transistor to a P-type transistor;

[0022] Figure 12 A circuit diagram of an example circuit having a boost switch driver and an additional level shifter in accordance with some embodiments of the present disclosure, the boost switch driver having a level shift in a branch of an N-type transistor, the additional level shifter configured to control a minimum / low level;

[0023] Figure 13 A schematic illustration of an example component in which one or more boost switch drivers can be implemented in accordance with some embodiments of the present disclosure;

[0024] Figure 14 A block diagram of an example system that can include one or more boost switch drivers in accordance with some embodiments of the present disclosure;

[0025] Figure 15 A block diagram of an example RF device that can include one or more boost switch drivers in accordance with some embodiments of the present disclosure; and

[0026] Figure 16 Provide a block diagram showing an example data processing system according to some embodiments of the present disclosure, the example data processing system being configurable to control the operation of one or more boost switch drivers. Detailed description

[0027] Overview

[0028] The systems, methods, and apparatus of the present disclosure each have several innovative aspects, no single one of which is responsible for all of the desired attributes disclosed herein. Details of one or more implementations of the subject matter described in the present disclosure are set forth in the following description and the drawings.

[0029] Embodiments of the present disclosure relate to switch driver circuits, and to apparatuses and systems in which such circuits may be implemented. In one aspect of the present disclosure, an example switch driver circuit includes two branches. The first branch includes a first transistor (e.g., transistor m5 shown in the drawings of the present disclosure). The second branch includes a second transistor (e.g., transistor m6 shown in the drawings of the present disclosure) and a level shifter circuit. One of these transistors is an N-type transistor and the other is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch such that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level shifted by the level shifter circuit to produce a level-shifted input clock signal, and the level-shifted input clock signal is provided to the second transistor. In the context where the input clock signal has a low voltage value and a high voltage value, level shifting the input clock signal includes the level shifter circuit changing each of the low voltage value and the high voltage value of the input signal to produce a level-shifted input signal. The switch driver circuit is further configured to combine the output of the first transistor with the output of the second transistor to produce an output clock signal. Various embodiments of this circuit are described hereinafter as a "boost switch driver circuit" (or simply as a "boost switch driver") because it may allow providing an output voltage swing that exceeds the core supply rail. The boost switch drivers described herein may advantageously allow providing extremely fast boost edges in situations where high-speed signal processing requires additional swing, which may help to maximize both clock speed and dynamic range. Other aspects of the present disclosure provide systems (e.g., RF transceivers) that may include one or more boost switch drivers as described herein, and methods for providing such boost switch drivers.

[0030] The exact design of the boost switch drivers described herein may be implemented in many different ways, all of which are within the scope of the present disclosure.

[0031] In an example of a design variant according to various embodiments of the present disclosure, a selection can be made individually for each of the transistors of a boost switch driver according to any of the embodiments described herein to employ bipolar transistors (e.g., in cases where the various transistors can be NPN or PNP transistors), field effect transistors (FETs), e.g., metal oxide semiconductor (MOS) technology transistors (e.g., in cases where the various transistors can be N-type MOS (NMOS) or P-type MOS (PMOS) transistors), or a combination of one or more FETs and one or more bipolar transistors, provided that one of the transistors in the first and second branches of the boost switch driver circuit is an N-type transistor (e.g., if the transistors are bipolar transistors, then one of the transistors is an NPN transistor, or if the transistors are FETs, then one of the transistors is an NMOS transistor), and the other is a P-type transistor (e.g., if the transistors are bipolar transistors, then the other is a PNP transistor, or if the transistors are FETs, then the other is a PMOS transistor). In the figures of the present disclosure, the transistors are shown as FETs, and thus the terms for referring to their terminals are described as gate terminals, drain terminals, and source terminals. However, in further embodiments of the present disclosure, any of the FETs shown in the figures can be replaced with corresponding bipolar transistors. Thus, the descriptions provided below with reference to "gate terminals" can be considered to refer to "first terminals", where, if the transistors are FETs, the term "first terminal" of the transistor is used to refer to the gate terminal, or if the transistors are bipolar transistors, it is used to refer to the base terminal. Similarly, the descriptions provided below with reference to "drain terminals" can be considered to refer to "second terminals", where, if the transistors are FETs, the term "second terminal" of the transistor is used to refer to the drain terminal, or if the transistors are bipolar transistors, it is used to refer to the collector terminal, and the descriptions provided below with reference to "source terminals" can be considered to refer to "third terminals", where, if the transistors are FETs, the term "third terminal" of the transistor is used to refer to the source terminal, or if the transistors are bipolar transistors, it is used to refer to the emitter terminal. These terms remain the same regardless of whether the transistors of a given technology are N-type transistors or P-type transistors.

[0032] In another example, in various embodiments, a selection can be made individually for each of the transistors of any of the boost switch drivers described herein regarding what type of transistor architecture to employ. For example, any of the transistors of a boost switch driver described herein implemented as an FET can be a planar transistor or can be a non-planar transistor (some examples of the latter include FinFETs, nanowire transistors, and nanoribbon transistors).

[0033] As will be appreciated by those skilled in the art, aspects of the present disclosure, particularly aspects of the boost switch driver as presented herein, can be embodied in various ways, e.g., as a method, system, computer program product, or computer-readable storage medium. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software aspects with hardware aspects, all of which may generally be referred to herein as a "circuit," "module," or "system." The functions described in the present disclosure may be implemented as algorithms executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and portions of steps of each of the methods described herein may be executed by different processing units. Additionally, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media, preferably non-transitory, on which is embodied (e.g., stored) computer-readable program code. In various embodiments, this computer program may, for example, be downloaded (updated) to existing devices and systems (e.g., existing RF ADCs, transceivers, and / or their controllers, etc.), or stored when manufacturing these devices and systems.

[0034] The following detailed description presents various descriptions of specific certain embodiments. However, the innovations described herein can be embodied in many different ways, for example, as defined and covered by the selected examples.

[0035] In the following description, reference is made to the accompanying drawings, in which like reference numerals may indicate identical or functionally similar elements. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Moreover, some embodiments may incorporate any suitable combination of features from two or more of the drawings. Additionally, it will be understood that certain embodiments may include more elements than those shown in the drawings and / or a subset of the elements shown in the drawings. Generally, although some of the drawings provided herein illustrate various aspects of a boost switch driver and systems in which such circuits may be implemented, the details of these systems may vary in different embodiments. For example, the various components of the boost switch driver presented herein may have other components, such as logic, storage, passive elements (e.g., resistors, capacitors, inductors, etc.) or other elements (e.g., transistors, etc.), included therein or coupled thereto that are not specifically shown in the drawings. In another example, the details shown in some of the drawings, such as the specific arrangements and example implementation details of the various components of the boost switch driver presented herein (e.g., details of the level shifter circuit) and / or the specific arrangements of the coupling connections may vary in different embodiments, where the illustrations of the drawings of the present disclosure only provide some examples of how these components may be used together to implement the boost switch driver. In yet another example, although some of the embodiments shown in the drawings of the present disclosure illustrate a specific number of components (e.g., a specific number of level shifter circuits in a boost switch driver), it should be understood that, in accordance with the description provided herein, these embodiments may be implemented in a boost switch driver or any other device or system having any number of these components. Additionally, although certain elements, such as the various elements of the boost switch driver presented herein, may be depicted in the drawings as being communicatively coupled using a single depicted line, in some embodiments, any of these elements may be coupled by multiple conductive lines, such as those that may be present in a bus or when differential signals are involved.

[0036] The description may use the phrases "in one embodiment" or "in embodiments", which may each refer to one or more of the same or different embodiments. Unless otherwise specified, the use of the ordinal adjectives "first", "second", and "third", etc. to describe a common object only indicates different examples of like objects and is not intended to imply that the objects so described must be in a given sequence in time, space, rank, or in any other way. Additionally, for the purposes of the present disclosure, the phrase "A and / or B" or the symbol "A / B" means (A), (B), or (A and B), and the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the symbol "A / B / C" means (A, B, and / or C). When referring to a measurement range, the term "between" includes the endpoints of the measurement range.

[0037] Aspects of the illustrative embodiments are described using terms commonly employed by those skilled in the art to convey the substance of their work to others in the art. For example, the term "connected" means a direct electrical connection between the things being connected, without any intermediate device / component, while the term "coupled" means a direct electrical connection between the things being connected, or an indirect electrical connection through one or more passive or active intermediate device / components. In another example, the term "circuit" or "circuitry" (used interchangeably) refers to one or more passive and / or active components arranged to cooperate with each other to provide the desired function. Sometimes, in this description, the term "circuit" may be omitted (e.g., a boost switch driver circuit may be simply referred to as a "boost switch driver"; a level shifter circuit may be simply referred to as a "level shifter", etc.). If used, then based on the context of a particular value as described herein or as known in the art, terms such as "substantially", "approximately", "about", etc. may generally be used to mean within + / - 20% of the target value, e.g., within + / - 10% of the target value.

[0038] Boost Switch Driver Circuit with Two Branches and Voltage Level Shifting in One Branch

[0039] All embodiments of the boost switch driver presented herein are based on splitting an input signal to the boost switch driver circuit between two branches and then combining the outputs of the two branches to produce an output signal from the boost switch driver circuit. In addition, all embodiments include a level shifter circuit in at least one of the branches, which allows the output signal from the boost switch driver circuit to have a greater signal swing than the input signal and carefully controls the maximum / high signal level, minimum / low signal level, or both of the output signal. One of the branches includes a P-type transistor and the other branch includes an N-type transistor. When only one of the branches includes a level shifter circuit, the embodiments of the boost switch driver presented herein can be generally divided into the following two groups of embodiments: one group of embodiments has level shifting on one side of the P-type transistor (i.e., in the branch containing the P-type transistor) as Figures 1 to 6 shown, and one group of embodiments has level shifting on one side of the N-type transistor (i.e., in the branch containing the N-type transistor) as Figures 7 to 12 shown. However, further embodiments are possible and within the scope of the present disclosure, in which level shifting is performed on both one side of the P-type transistor and one side of the N-type transistor. Such embodiments can be considered as a combination of the level shifting as described with reference to Figures 1 to 6 and the level shifting as described with reference to Figures 7 to 12 all of which combinations are within the scope of the present disclosure.

[0040] Example Boost Switch Driver Circuit with Voltage Level Shifting in the Branch of P-Type Transistor

[0041] Figure 1 Provided is a circuit diagram of an example circuit 100 that may use a boost switch driver with a level shift in a branch of a P-type transistor according to some embodiments of the present disclosure. As Figure 1 shown, circuit 100 may include a series of first inverters 102 and second inverters 104 coupled to a switch 106. The first inverter 102 may be a fast inverter configured to drive the second inverter 104 (e.g., a basic dual-transistor inverter having one PMOS and one NMOS transistor, using core MOS transistors with a core supply voltage), and the second inverter may include any of the boost switch drivers described herein having a level shift performed in a branch of a P-type transistor. The first inverter 102 may be configured to receive a digital signal (e.g., a clock signal) having a series of voltage values and provide an inverted version of the signal to the second inverter 104. For example, the digital signal provided to the first inverter 102 may be a series of voltage values between a low voltage value (e.g., 0 volts (V)) and a high voltage value (e.g., 1 V), an example of which is Figure 1 shown as signal 112 (schematically shown within the dashed box labeled "112"). The output of the first inverter 102 corresponding to this input is Figure 1 shown as signal 114 (schematically shown within the dashed box labeled "114"). Thus, the output of the first inverter 102 swings by 1 V. The second inverter 104 may be a boost switch driver that is supply-boosted (i.e., configured to boost / increase the output swing). This is Figure 1 shown in that the second inverter 104 receives a signal having an output swing of 1 V (i.e., small figure 114) and outputs an inverted and boosted version of the signal, which is Figure 1 shown as signal 116 (schematically shown within the dashed box labeled "116") having a low voltage value of still 0 V but now a high voltage value of 1.4 V. The output of the second inverter 104 may then be used to drive the switch 106, which in some embodiments may be implemented as the Figure 1 transistor shown.

[0042] In various embodiments, inverter 104 may include any of the boost switch driver circuits presented herein that have a voltage level shift in the branch of the P-type transistor. In various embodiments, signals 112, 114, 116 may be different. For example, the signals may have different high and low values. Similarly, the low supply voltage and the high supply voltage coupled to each of inverter 102 and inverter 104 may be different in different embodiments where any of the boost switch driver circuits presented herein that have a voltage level shift in the branch of the P-type transistor are used to implement inverter 104. Further, in a further embodiment, inverter 104 that includes any of the boost switch driver circuits presented herein that have a voltage level shift in the branch of the P-type transistor may be included in a circuit other than circuit 100, and in particular, may not have to be implemented together with inverter 102, as Figure 1 shown.

[0043] Figure 2 A circuit diagram of an example circuit 200 having a boost switch driver according to some embodiments of the present disclosure is provided, the boost switch driver having a voltage level shift on one side of the P-type transistor. Circuit 200 may be considered an example of circuit 100, where the reference numerals of circuit 100 for Figure 1 are used to refer to elements that are the same as or functionally similar to those shown for circuit 200 for Figure 2 such that the description of these elements provided with respect to one figure is not repeated for the other figure, and only the differences are described (the same applies to other figures of the present disclosure).

[0044] As Figure 2 shown, in some embodiments, the first inverter 102 may be implemented as a pair of complementary transistors m3, m4 (i.e., one of the transistors is N-type and the other is P-type). For example, the gate terminals of transistors m3 and m4 may be coupled together and both may be coupled to the input clock signal 112, the drain terminals of transistors m3 and m4 may be coupled together and both may be coupled to the output 114, and the source terminals of transistors m3 and m4 may be coupled to the low supply voltage and the high supply voltage for the first inverter 102. For example, transistor m3 may be an N-type transistor (e.g., an NMOS transistor, as shown in the corresponding circuit diagram for transistor m3 in Figure 2 ), whose source terminal is coupled to the low supply voltage (e.g., 0V), and transistor m4 may be a P-type transistor (e.g., a PMOS transistor, as shown in Figure 2shown in the corresponding circuit diagram for transistor m4). As described above, the output clock signal 114 of the first inverter 102 can be used as the basis for the input clock signal to the second inverter 104.

[0045] Figure 2 The boost switch driver circuit 204 is further shown, which can be, for example, an example of the second inverter 104 described above. As Figure 2 shown, the circuit 204 can include an input 222, an output 224, and two branches 226 between the input 222 and the output 224. The first branch, Figure 2 schematically indicated by a dashed line 226-1, can include transistor m5. The second branch, Figure 2 schematically indicated by a dotted line 226-2, can include transistor m6 and a level shifter circuit 230. One of transistors m5 and m6 can be an N-type transistor and the other can be a P-type transistor. Since Figure 2 an embodiment with level shifting done on one side of the P-type transistor is shown, transistor m6 is a P-type transistor (e.g., a PMOS transistor) whose source terminal is coupled to a high supply voltage (e.g., 1.4V), as shown in Figure 2 the corresponding circuit diagram for transistor m6, while transistor m5 is an N-type transistor (e.g., an NMOS transistor), as shown in Figure 2 the corresponding circuit diagram for transistor m5. The circuit 204 can be configured to split the input clock signal (e.g., signal 114) between the first branch 226-1 and the second branch 226-2 such that a portion of the input clock signal 114 split to the first branch 226-1 is provided to transistor m5 of the branch, and a portion of the input clock signal split to the second branch 226-2 is level shifted by the level shifter circuit 230 to produce a level-shifted signal 214-2, and the level-shifted signal 214-2 is provided to transistor m6. Figure 2 Shown is the signal 214-1 provided to transistor m5 (i.e., the gate terminal of transistor m5), and the signal 214-2 provided to transistor m6 (i.e., the gate terminal of transistor m6). The signal 214-1 and the signal 114 have the same voltage swing (e.g., from about 0 to about 1V, as for Figure 2In terms of what is shown in the example of [], it may be substantially the same, and compared with the signal 114, the signal 214-2 can be a level-shifted signal with a voltage swing from about 0.5V to about 1.4V. The circuit 204 is further configured to combine the output of the transistor m5 (e.g., the output from the drain terminal of the transistor m5) with the output of the transistor m6 (e.g., the output from the drain terminal of the transistor m6) to generate the output clock signal 116. Thus, the gate terminals of each of the transistors m5 and m6 can be coupled to the input 222, except that the gate terminal of the transistor m6 is coupled to the input 222 via a level-shifter circuit 230 configured to perform level shifting before providing the signal to the transistor m6. Similarly, the drain terminals of each of the transistors m5 and m6 can be coupled to the output 224, and the output can be coupled to the switch 106 to be driven by the switch driver circuit 204.

[0046] In some embodiments, the level-shifter circuit 230 can include a voltage controller circuit 232, which can be configured to receive a reference signal 234 as an input and generate an output 236, as Figure 2 shown. Additionally, the level-shifter circuit 230 can further include a coupling capacitor 238 coupled to the voltage controller circuit 232. For example, the first capacitor electrode of the coupling capacitor 238 can be coupled to the input 222, while the second capacitor electrode of the coupling capacitor 238 can be coupled to each of the voltage controller circuit 232 and the gate terminal of the transistor m6. In other words, a portion of the input clock signal 114 split into the second branch 226-2 of the circuit 204 can be configured to be applied to the first capacitor electrode of the coupling capacitor 238, and the second capacitor electrode of the coupling capacitor 238 can be coupled to each of the output 236 of the voltage controller circuit 232 and the gate terminal of the transistor m6. The input 234 to the voltage controller circuit 232 can be a reference voltage or any other control signal configured to control the maximum voltage level set by the voltage controller circuit 232. The output 236 from the voltage controller circuit 232 can form the basis of the level-shifted input clock signal 214-2 to be provided to the gate terminal of the transistor m6.

[0047] When the transistor m6 is a P-type transistor (as Figure 2 shown in the embodiments of []), the voltage controller circuit 232 can be configured to control the maximum voltage value in the level-shifted input clock signal 214-2 provided to the transistor m6, and thus in the output signal 116. For this purpose, the input to the NMOS transistor m5 can directly come from the 1V domain inverter output 114 (swinging from 0V to 1V), as Figure 2Input 214-1 shown in, while the input to PMOS transistor m6 can be level-shifted via coupling capacitor 238 with voltage controller circuit 232 to provide a maximum switching voltage of, for example, 1.4V, and ideally a minimum switching voltage of 1.4V - 1V = 0.4V. Due to capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of level shifter circuit 230 can be attenuated by a ratio regarding the size of coupling capacitor 228 and the size of the capacitance on the gate of PMOS transistor m6 plus the wiring parasitic capacitance. Thus, the signal at the output Nout of level shifter circuit 230 can swing from 1.4V to 1.4V - 0.9V = 0.5V (instead of the ideal 0.4V, which would result in a 1V swing from the input Nin to the output of level shifter circuit 230), as shown by signal 214-2 shown in Figure 2 As shown in Figure 2 The voltage controller circuit 232 or level shifter circuit 230 shown in can be referred to as a "maximum level controller" because the voltage controller circuit or level shifter circuit is configured to set the maximum voltage value of the level-shifted input clock signal 214-2. The minimum voltage value of the level-shifted input clock signal 214-2 can then be automatically adjusted based on the ratio between the capacitance of coupling capacitor 238 and the capacitance of the load for voltage controller circuit 232.

[0048] In some embodiments of a level shifter circuit for a P-type transistor coupled to a boost switch driver circuit (e.g., as shown in Figure 2 ), the high supply voltage coupled to the source terminal of the P-type transistor (i.e., transistor m6 in this case) can be substantially the same as the maximum voltage value controlled by voltage controller circuit 232 (e.g., both can be 1.4V), although in other embodiments, these voltages can be different. Generally, the value of the supply voltage coupled to the source terminal of the P-type transistor (i.e., transistor m6 in this case) that is also part of a branch including a maximum level controller can correspond to (e.g., be substantially equal to) the high voltage in the level-shifted input clock signal 214-2. In some embodiments of circuit 204, the low supply voltage coupled to the source terminal of the N-type transistor (i.e., transistor m5 in this case) that is part of a branch not including a level shifter circuit can be substantially the same as the minimum voltage value in output signal 116 (e.g., both can be 0V), although in other embodiments, these voltages can be different (e.g., in the case of including a second level shifter circuit, as shown in Figure 6 )

[0049] In various embodiments, the level shifter circuit 230 can be implemented in any way that allows careful control of the maximum value of the level-shifted input clock signal 214-2 to be provided to the P-type transistor m6. One example is shown in Figure 3 However, in other embodiments of the circuit 204, the level shifter circuit 230 can be implemented in a different manner. Figure 3 A circuit diagram of an exemplary level shifter circuit 300 according to some embodiments of the present disclosure is provided. The exemplary level shifter circuit can be used with or in a boost switch driver, for example, as the level shifter circuit 230 of the boost switch driver 204, to perform level shifting in a situation where the maximum / high signal level is controlled.

[0050] As Figure 3 shown, the level shifter circuit 300 can include a pair of cross-coupled transistors m1 and m2. Transistors m1 and m2 are cross-coupled because the gate terminal of transistor m1 is coupled to the drain terminal of transistor m2 and the gate terminal of transistor m2 is coupled to the drain terminal of transistor m1. The source terminal of each of transistors m1 and m2 is coupled to a reference voltage 234, which is provided to the level shifter circuit 300 to control the maximum voltage level set by the level shifter circuit 300. When the level shifter circuit 300 is a maximum level controller ( Figure 3 the embodiment shown in), transistors m1 and m2 can be P-type transistors, for example, PMOS transistors as shown in Figure 3 and in subsequent figures of the maximum level controller. Additionally, when the level shifter circuit 300 is a maximum level controller, the value of the reference voltage 234 can be configured to correspond to the high voltage in the level-shifted input clock signal 214-2 output by the circuit. In some embodiments, the reference voltage 234 can be substantially the same as the supply voltage to which the source terminal of transistor m6 is coupled (e.g., for Figure 2 and Figure 3 the examples shown, both can be approximately 1.4V), and can be from the same voltage source.

[0051] As Figure 3As further shown in , the level shifter circuit 300 may further include a pair of capacitors C1 and C2, and an inverter Inv coupled between the capacitors, for example, by coupling the input of the inverter Inv to the first capacitor electrode of the capacitor C1 and coupling the output of the inverter Inv to the first capacitor electrode of the capacitor C2. The second capacitor electrode of the capacitor C1 may be coupled to the drain terminal of the transistor m1, and the second capacitor electrode of the capacitor C2 may be coupled to the drain terminal of the transistor m2. The input to the level shifter circuit 300 may be applied / provided to the node Nin, which is coupled to the first capacitor electrode of the capacitor C1 and the input of the inverter Inv, as Figure 3 shown in , and may be the input signal 114. The level shifter circuit 300 may generate an output signal from the output node Nout, which is coupled to one or more of the second capacitor electrode of the capacitor C1, the drain terminal of the transistor m1, and the gate terminal of the transistor m2. The output signal from the output node Nout may be the level-shifted input clock signal 214-2 as described above, and may drive a load coupled to the output node Nout (in Figure 3 represented by the capacitor C in Load ).

[0052] Since the level shifter circuit 300 is a maximum level controller, the reference voltage 234 applied to the source terminals of the transistors m1 and m2 may accurately control the maximum / high level of the output voltage of the signal 214-2 (e.g., ensuring the level is about 1.4V). The minimum / low level of the output voltage of the signal 214-2 may then be established based on the capacitor charge redistribution between the capacitor C1 and the load capacitance C Load , which is based on the ratio of these capacitances. Thus, the voltage swing of the output signal 214-2 may be based on the value of the reference voltage 234 provided to the level shifter circuit 300 and on the capacitor charge redistribution between the capacitor C1 and the load capacitance C Load .

[0053] Figure 4 A circuit diagram of an example circuit 400 having a boost switch driver according to some embodiments of the present disclosure is provided, which has a level shift implemented using the level shifter circuit 300 on one side of the transistor m6. The circuit 400 may be considered an example of the circuit 200, where the level shifter circuit 230 is implemented as the level shifter circuit 300, and thus (in the schematic illustration of Figure 3 ) is replaced by the level shifter circuit 300. In Figure 4 , the reference numbers of the circuits for Figure 4 are used to refer to those related to Figures 1 to 3 , and Figures 1 to 3The elements shown in are the same or functionally similar elements, so the description of those elements will not be repeated for Figure 4 Furthermore, Figure 3 Various components of the level shifter circuit 300 shown in and described above, such as transistors m1 and m2, capacitors C1 and C2, and inverter Inv, are also shown in Figure 4 to clearly show how the level shifter circuit 300 replaces the Figure 2 level shifter circuit 230 shown in for this embodiment. It should be noted that in the Figure 4 embodiment, the coupling capacitor 238 of the level shifter circuit 230 is implemented by the capacitor C1 of the level shifter circuit 300. In the context of the circuit 400, the input node Nin and output node Nout of the level shifter circuit 300 are also shown in Figure 4 .

[0054] Figure 5 A circuit diagram of an example circuit 500 according to some embodiments of the present disclosure is provided, which has a boost switch driver and has an additional transistor. The boost switch driver has a level shift in the branch of a P-type transistor (i.e., transistor m6 for the shown example). The additional transistor provides a cascode transistor to an N-type transistor in another branch (i.e., transistor m5 for the shown example). The circuit 500 can be regarded as a further embodiment of the circuit 400. Wherein, similar to the circuit 400, the level shifter circuit 230 is implemented as the level shifter circuit 300, and thus is replaced by the level shifter circuit 300 in the Figure 5 schematic illustration. In Figure 5 , the reference numbers for the Figures 1 to 4 circuit are used to refer to the same or functionally similar elements as those shown in Figures 1 to 4 , so that the description of those elements will not be repeated for Figure 5 , and only the differences are described. The difference between the circuit 500 and the circuit 400 is that the circuit 500 further includes an additional transistor m7 that provides a cascode transistor to the transistor m5 described above. For this purpose, the transistors m5 and m7 can be transistors of the same type (e.g., both are N-type transistors, as shown in the Figure 5 illustration). The cascode transistor m7 can be regarded as a part of the first branch 226-1. As shown in Figure 5As shown, the drain terminal of transistor m5 can be coupled to output 224 by coupling the drain terminal of transistor m5 to the source terminal of cascode transistor m7 and coupling the drain terminal of cascode transistor m7 to output 224. In various embodiments, the gate terminal (e.g., the gate terminal) of cascode transistor m7 can be coupled to a suitable reference voltage 534. For example, for an embodiment where cascode transistor m7 is an N-type transistor as shown (i.e., for an embodiment where the level shifter circuit included in circuit 500 is a maximum level controller), reference voltage 534 can be approximately 1V. However, in other embodiments, the value of reference voltage 534 can be different.

[0055] Although Figure 5 only one cascode transistor m7 is shown in Figure 5 other embodiments of the circuit shown in Figure 5 can include more than one cascode transistor m7 in the first branch 226-1. Although Figure 3 cascode transistor m7 is shown in connection with level shifter circuit 300 of Figure 2 in a further embodiment of circuit 200 shown in Figures 1 to 6 the first branch 226-1 of circuit 200 can include at least one such cascode transistor m7, where level shifter circuit 230 can but need not be implemented as level shifter circuit 300. Additionally, in any of the embodiments having a boost switch driver with level shifting in the branch of P-type transistors (e.g., any of the embodiments described in reference to Figures 1 to 6 one or more additional transistors m8 (not specifically shown in the drawings) can be provided as cascode transistors to transistor m6 (i.e., as cascode transistors to the P-type transistor of the level shifter circuit). To this end, transistors m6 and m8 can be the same type of transistor (e.g., both are P-type transistors), and one or more cascode transistors m8 can be part of the second branch 226-2. For example, the gate terminal of such a cascode transistor m8 can be coupled to ground potential; the source terminal of transistor m8 can be coupled to the drain terminal of transistor m6; and the drain terminal of cascode transistor m8 can be coupled to output 224.

[0056] Figure 6 A circuit diagram of an example circuit 600 is provided in accordance with some embodiments of the present disclosure having a boost switch driver and having an additional level shifter circuit, the boost switch driver having level shifting in the branch of P-type transistors, the additional level shifter circuit configured to control the minimum / low level. Circuit 600 can be considered a further embodiment of circuit 500, where, similar to circuit 500, level shifter circuit 230 is implemented as level shifter circuit 300, and thus (in Figure 6is schematically shown) is replaced by a level shifter circuit 300. Also similar to circuit 500, circuit 600 further includes a cascode transistor m7. In Figure 6 , the reference numerals for the Figures 1 to 5 circuits are used to refer to elements that are the same as or functionally similar to those shown in Figures 1 to 5 , such that the description of those elements is not repeated for Figure 6 and only the differences are described. Circuit 600 differs from circuit 500 in that circuit 600 further includes an additional level shifter circuit 630 configured to control the minimum / low level of the output signal from circuit 600. Thus, circuit 630 can be referred to as a "minimum level controller".

[0057] In some embodiments, the additional level shifter circuit 630 can be implemented in a manner similar to the level shifter circuit 300, except that the P-type transistors m1 and m2 of the level shifter circuit 300 are replaced by N-type transistors in the level shifter circuit 630 in order to control the minimum / low level of the output signal from the level shifter circuit 630. Refer to Figure 9 for a more detailed description of this circuit (i.e., the additional level shifter circuit 630 can be implemented as Figure 9 the level shifter circuit 900 shown in

[0058] As Figure 6 shown, the level shifter circuit 630 can include a pair of cross-coupled transistors m1 and m2. Transistors m1 and m2 are cross-coupled because the gate terminal of transistor m1 is coupled to the drain terminal of transistor m2 and the gate terminal of transistor m2 is coupled to the drain terminal of transistor m1. The source terminal of each of transistors m1 and m2 is coupled to a reference voltage 634, which is provided to the level shifter circuit 630 to control the minimum voltage level set by the level shifter circuit 630. When the level shifter circuit 630 is a minimum level controller, transistors m1 and m2 can be N-type transistors, for example, the NMOS transistors shown in Figure 6 and in the subsequent figures of the minimum level controller. Additionally, when the level shifter circuit 630 is a minimum level controller, the value of the reference voltage 634 can be configured to correspond to the low voltage in the level-shifted clock signal 616 output by circuit 630.

[0059] As Figure 6As further shown, the level shifter circuit 630 may further include a pair of capacitors C1 and C2, and an inverter Inv coupled between the capacitors, for example, by coupling the input of the inverter Inv to the first capacitor electrode of the capacitor C1 and coupling the output of the inverter Inv to the first capacitor electrode of the capacitor C2. The second capacitor electrode of the capacitor C1 may be coupled to the switch 106 to be driven by the switch driver 600, and the second capacitor electrode of the capacitor C2 may be coupled to the drain terminal of the transistor m2 (and correspondingly coupled to the gate terminal of the transistor m1 since the drain terminal of the transistor m2 is coupled to the gate terminal of the transistor m1).

[0060] The input to the level shifter circuit 630 may be applied / provided to a node Nin of the circuit 630, which is coupled to the first capacitor electrode of the capacitor C1 and, in some embodiments, to the input of the inverter Inv, as Figure 6 shown. In some embodiments, the input to the level shifter circuit 630 may be based on the output signal 116 from the boost switch driver circuit 204, i.e., for Figure 6The example shown is based on a signal from 0V to 1.4V. The level shifter circuit 630 can generate an output signal from the output node Nout of the circuit 630, which is coupled to one or more of the second capacitor electrode of the capacitor C1, the drain terminal of the transistor m1, and the gate terminal of the transistor m2. The output signal 616 from the output node Nout of the level shifter circuit 630 can be a level-shifted version of the input signal (e.g., signal 116) provided at the input node Nin of the level shifter circuit 630, where the minimum / low value of the signal is carefully controlled based on the reference signal 634. For example, if the input signal provided at the input node Nin of the level shifter circuit 630 is signal 116 having a minimum voltage value of 0V and a maximum voltage value of 1.4V as described above, then the level shifter circuit 630 can shift these values by approximately 0.5V (i.e., the value of the reference voltage 634). In particular, the level shifter circuit 630 is configured to carefully control the value by which the minimum voltage value is shifted based on the reference voltage 634, i.e., for the example shown, the minimum voltage value is shifted from 0V to 0.5V. Ideally, the maximum switching voltage would be 1.4V + 0.5V = 1.9V. However, similar to the maximum voltage controller, due to capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the level shifter circuit 630 can be attenuated by the ratio of the size of the coupling capacitor C1 of the level shifter circuit 630 to the size of the capacitance on the gate of the transistor implementing the switch 106 plus the wiring parasitic capacitance. Thus, the signal at the output Nout of the level shifter circuit 630 can swing from 0.5V to 0.5V + 1.3V = 1.8V (instead of the ideal 1.9V, which would result in a 1.4V swing from the input Nin to the output Nout of the level shifter circuit 630), as shown by the signal 616 shown in Figure 6 Thus, the level shifter circuit 630 can carefully control the minimum / low value of the level-shifted clock signal 616 based on the reference signal 634, while the maximum / high voltage value of the level-shifted clock signal 616 can then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor C1 of the level shifter circuit 630 and the capacitance of the load for the level shifter circuit 630 (including parasitic capacitance). In other words, since the level shifter circuit 630 is a minimum level controller, the reference voltage 634 applied to the source terminals of the transistors m1 and m2 of the level shifter circuit 630 can accurately control the minimum / low level of the output voltage of the signal 616 (e.g., ensuring the level is approximately 0.5V). The maximum / high level of the output voltage of the signal 616 can then be based on the capacitor C1 of the level shifter circuit 630 and the load capacitance C for the level shifter circuit 630 Loadestablished by capacitor charge redistribution between them, the capacitor charge redistribution being based on the ratio of these capacitances. Thus, the voltage swing of the output signal 616 can be based on the value of the reference voltage 234 provided to the level shifter circuit 300, the value of the reference voltage 634 provided to the level shifter circuit 630, and the capacitor C1 of the level shifter circuit 630 and the load capacitance C of the level shifter circuit 630 Load capacitor charge redistribution between them.

[0061] Although not specifically shown in Figure 6 , in other embodiments of the circuit 630, the input to the inverter Inv of the level shifter circuit 630 can be based on an inverted version of the input signal 114 provided to the input 222, rather than the output signal 116 from the output 224 as shown in Figure 6 . In such embodiments, the inverter of the level shifter circuit 630 can be decoupled from the signal 116, but instead coupled to the inverted version of the signal 114, which can be advantageous in cases where driving the inverter of the level shifter circuit 630 with a signal having a signal swing greater than about 1V may be unreliable. In such embodiments, one of the capacitor electrodes of the capacitor C1 of the level shifter circuit 630 is still driven by the signal 116, such that the level shifter circuit 630 can then produce an output signal provided at the output node Nout of the level shifter circuit 630 as a level-shifted version of the signal 116 provided at the input node Nin of the level shifter circuit 630, wherein the minimum / low value of the signal is carefully controlled based on the reference signal 634.

[0062] Figure 6 shows one way in which the level shifter circuit 630 can be implemented to provide control of the minimum / low level of the output voltage of the signal 616 as described above. In other embodiments of the circuit 600, the level shifter circuit 630 can be implemented in any other way than the way shown in Figure 6 , as long as it provides sufficiently accurate control of the minimum / low level of the output voltage of the signal 616, wherein the maximum / high level is adjusted accordingly.

[0063] Although Figure 6 in connection with Figure 3 the level shifter circuit 300 of shows an additional level shifter circuit 630, in a further embodiment of the circuit 200 shown in Figure 2 , an additional level shifter circuit 630 can be included to receive the signal 116 as an input and produce the output 616, as described with reference to Figure 6 , wherein the level shifter circuit 230 can but need not be implemented as the level shifter circuit 300. Additionally, although Figure 6 in connection with Figure 5The cascode transistor m7 shows an additional level shifter circuit 630, but in a further embodiment of the circuit 200 shown in Figure 2 , an additional level shifter circuit 630 as described with reference to Figure 6 may be included without the cascode transistor m7. Still in a further embodiment of the circuit 200 shown in Figure 2 , an additional level shifter circuit 630 as described with reference to Figure 6 may be included without the cascode transistor m7, and wherein the level shifter circuit 230 and the level shifter circuit 300 are implemented in different ways. In any of these embodiments, the level shifter circuit 630 may be implemented in any other way than the way shown in Figure 6 , as long as it provides sufficiently accurate control of the minimum / low level of the output voltage of the signal 616 as described above.

[0064] Still further, although Figure 6 shows a level shifter circuit 630 configured to provide control of the minimum / low level of the output voltage of the signal 616 as described above, in other embodiments, the level shifter circuit 630 may use a level shifter circuit 630' configured to provide control of the maximum / high level of the output voltage of the signal 616 instead ( Figure 6 not shown, but reference numerals are used here for convenience of explanation). In some such embodiments, to implement the level shifter circuit 630', Figure 6 the level shifter circuit 630 shown in may be replaced with other examples of the level shifter circuit 300, or equivalently, Figure 6 the NMOS transistors of the level shifter circuit 630 shown in may be replaced with PMOS transistors, and the reference voltage 634 may be replaced with a reference voltage 634' configured to accurately control the maximum / high level of the output voltage of the signal 616 (also not shown in Figure 6 but reference numerals are used here for convenience of explanation).

[0065] The input to the level shifter circuit 630' may be applied / provided to the node Nin of the circuit 630', which node is coupled to the first capacitor electrode of the capacitor C1 and, in some embodiments, to the input of the inverter Inv, as shown in Figure 6 . In some embodiments, the input to the level shifter circuit 630' may be based on the output signal 116 from the boost switch driver circuit 204, i.e., for Figure 6The example shown is based on a signal from 0V to 1.4V. The level shifter circuit 630’ can generate an output signal from the output node Nout of the circuit 630’, which is coupled to one or more of the second capacitor electrode of the capacitor C1, the drain terminal of the transistor m1, and the gate terminal of the transistor m2. The output signal 616 from the output node Nout of the level shifter circuit 630’ can be a level-shifted version of the input signal (e.g., signal 116) provided at the input node Nin of the level shifter circuit 630’, where the maximum / high value of the signal is carefully controlled based on the reference signal 634’. For example, if the input signal provided at the input node Nin of the level shifter circuit 630’ is the signal 116 having a minimum voltage value of 0V and a maximum voltage value of 1.4V as described above, then the level shifter circuit 630’ can shift these values such that the maximum voltage value is 1.8V, which for this example will be the value of the reference voltage 634’. In particular, the level shifter circuit 630’ is configured to carefully control the value by which the maximum voltage value is shifted based on the reference voltage 634’, i.e., for the example shown, the maximum voltage value is shifted by 0.4V, from 1.4V to 1.8V. Ideally, the minimum switching voltage would be 0V + 0.4V = 0.4V. However, as described above for the maximum voltage controller 300, due to capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the level shifter circuit 630’ can be attenuated by the ratio of the size of the coupling capacitor C1 with respect to the level shifter circuit 630’ to the size of the capacitance on the gate of the transistor implementing the switch 106 plus the wiring parasitic capacitance. Thus, the minimum voltage value at the output Nout of the level shifter circuit 630’ can be 1.8V - 1.3V = 0.5V (instead of the ideal 0.4V, which would result in a 1.4V swing from the input Nin to the output Nout of the level shifter circuit 630’), as shown in Figure 6as shown by the signal 616 shown in [reference]. Thus, the level shifter circuit 630' can carefully control the maximum / high value of the level-shifted clock signal 616 based on the reference signal 634', and the minimum / low voltage value of the level-shifted clock signal 616 can then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor C1 of the level shifter circuit 630' and the capacitance of the load (including parasitic capacitance) for the level shifter circuit 630'. In other words, since the level shifter circuit 630' is a maximum level controller, the reference voltage 634' applied to the source terminals of the transistors m1 and m2 of the level shifter circuit 630' can accurately control the maximum / high level of the output voltage of the signal 616 (e.g., ensuring the level is about 1.8V). The minimum / low level of the output voltage of the signal 616 can then be established based on the capacitor charge redistribution between the capacitor C1 of the level shifter circuit 630' and the load capacitance C of the level shifter circuit 630', and this capacitor charge redistribution is based on the ratio of these capacitances. Thus, the voltage swing of the output signal 616 can be based on the value of the reference voltage 234 provided to the level shifter circuit 300, the value of the reference voltage 634' provided to the level shifter circuit 630', and the capacitor charge redistribution between the capacitor C1 of the level shifter circuit 630' and the load capacitance C of the level shifter circuit 630'. Load between, and this capacitor charge redistribution is based on the ratio of these capacitances. Thus, the voltage swing of the output signal 616 can be based on the value of the reference voltage 234 provided to the level shifter circuit 300, the value of the reference voltage 634' provided to the level shifter circuit 630', and the capacitor charge redistribution between the capacitor C1 of the level shifter circuit 630' and the load capacitance C Load between.

[0066] Similar to the variant of the level shifter circuit 630 shown above Figure 6 in other embodiments of the circuit 630', the input to the inverter Inv of the level shifter circuit 630' can be based on the inverted version of the input signal 114 provided to the input 222, rather than the output signal 116 from the output 224 as shown in Figure 6 above. In such embodiments, the inverter of the level shifter circuit 630' can be decoupled from the signal 116 and instead coupled to the inverted version of the signal 114, which can be advantageous in cases where it may be unreliable to drive the inverter of the level shifter circuit 630' with a signal having a signal swing greater than about 1V. In such embodiments, one of the capacitor electrodes of the capacitor C1 of the level shifter circuit 630' is still driven by the signal 116, such that the level shifter circuit 630' can then generate an output signal provided at the output node Nout of the level shifter circuit 630' as a level-shifted version of the signal 116 provided at the input node Nin of the level shifter circuit 630', where the maximum / high value of the signal is carefully controlled based on the reference signal 634'.

[0067] In other embodiments of circuit 600, the level shifter circuit 630' may be implemented in any other way than the level shifter circuit 300, as long as it provides sufficiently accurate control of the maximum / high level of the output voltage of signal 616, where the minimum / low level is adjusted accordingly.

[0068] Example Boost Switch Driver Circuit with Voltage Level Shifting in the Branch of N-Type Transistor

[0069] Figure 7 Provided is a circuit diagram of an example circuit 700 according to some embodiments of the present disclosure in which a boost switch driver with level shifting in a branch of an N-type transistor can be used. As Figure 7 shown, circuit 700 may include a series of first inverters 702 and second inverters 704 coupled to switch 706. The first inverter 702 may be substantially similar to the first inverter 102, configured to receive a signal 712 (similar to signal 112) as an input and produce a signal 714 (similar to signal 714) as an output. The descriptions provided above with reference to inverter 102, input signal 112, and output signal 114 apply respectively to inverter 702, input signal 712, and output signal 714, and are thus not repeated for the sake of brevity.

[0070] The first inverter 704 may be configured to drive a second inverter 104, which may include any of the boost switch drivers described herein having level shifting performed in a branch of an N-type transistor. The second inverter 704 may be a boost switch driver for supply boosting (i.e., configured to increase the output swing). This is Figure 7 shown in that the second inverter 704 receives a signal with an output swing of 1V (i.e., small figure 714) and outputs an inverted version of the signal with a larger output swing, which is Figure 7 shown in as a signal 716 (schematically shown within the dashed box labeled "716") that still has a high voltage value of 1V but now has a low voltage value of -0.4V. The output of the second inverter 704 may then be used to drive the switch 706, which in some embodiments may be implemented as Figure 7 the transistor shown.

[0071] In various embodiments, inverter 104 may include any of the boost switch driver circuits presented herein having a voltage level shift in the branch of an N-type transistor. In various embodiments, signals 712, 714, 716 may be different. For example, the signals may have different high and low values. Similarly, the low supply voltage and the high supply voltage coupled to each of inverter 702 and inverter 704 may be different in different embodiments where any of the boost switch driver circuits presented herein having a voltage level shift in the branch of an N-type transistor are used to implement inverter 704. Additionally, in further embodiments, inverter 704 including any of the boost switch driver circuits presented herein having a voltage level shift in the branch of an N-type transistor may be included in a circuit other than circuit 700 and, in particular, may be implemented, but not necessarily, together with inverter 702, as Figure 7 shown.

[0072] Figure 8 A circuit diagram of an example circuit 800 with a boost switch driver according to some embodiments of the present disclosure is provided, the boost switch driver having a voltage level shift on one side of an N-type transistor. Circuit 800 may be considered an example of circuit 700, where the reference numbers of circuit 700 for Figure 7 are used to refer to elements that are the same as or functionally similar to those shown for circuit 800 for Figure 8 such that the descriptions of these elements provided with respect to one figure are not repeated for the other figure, and only the differences are described.

[0073] As Figure 8 shown, in some embodiments, first inverter 702 may be implemented as a pair of complementary transistors m3, m4 (i.e., one of the transistors is N-type and the other is P-type), similar to the implementation of first inverter 102 shown in Figure 2 The description of the first inverter shown in Figure 2 applies to first inverter 702 and is not repeated here for the sake of brevity. The output clock signal 714 of first inverter 702 may be used as the basis for the input clock signal to second inverter 704.

[0074] Figure 8 A boost switch driver circuit 804 is further shown, which may be, for example, an example of second inverter 704 described above. As Figure 8 shown, circuit 804 may include an input 822, an output 824, and two branches 826 between input 822 and output 824. The first branch, schematically indicated by a dotted line 826-1 in Figure 8 may include transistor m5. The second branch, in Figure 8is schematically indicated by a dashed line 826-2 and may include a transistor m6 and a level shifter circuit 830. Again, one of the transistors m5 and m6 may be an N-type transistor and the other may be a P-type transistor. Since Figure 8 an embodiment showing level shifting done on one side of an N-type transistor is shown, the transistor m6 is an N-type transistor (e.g., an NMOS transistor, as shown in the corresponding circuit diagram representation for transistor m6 in Figure 8 ), with its source terminal coupled to a low supply voltage (e.g., -0.4V), while the transistor m5 is a P-type transistor (e.g., a PMOS transistor, as shown in the corresponding circuit diagram representation for transistor m5 in Figure 8 ). The circuit 804 may be configured to divide an input clock signal (e.g., signal 714) between a first branch 826-1 and a second branch 826-2 such that a portion of the input clock signal 714 divided to the first branch 826-1 is provided to the transistor m5 of the branch and a portion of the input clock signal divided to the second branch 826-2 is level shifted by the level shifter circuit 830 to produce a level-shifted signal 814-2, and the level-shifted signal 814-2 is provided to the transistor m6. Figure 8 shows the signal 814-1 provided to the transistor m5 (i.e., the gate terminal of the transistor m5) and the signal 814-2 provided to the transistor m6 (i.e., the gate terminal of the transistor m6). The signal 814-1 and the signal 714 may be substantially the same in terms of their voltage swing (e.g., from about 0V to about 1V, as shown for the example of Figure 8 ), while the signal 814-2 may be a level-shifted signal having a voltage swing from about -0.4V to about 0.5V compared to the signal 714. The circuit 804 is further configured to combine the output of the transistor m5 (e.g., the output from the drain terminal of the transistor m5) with the output of the transistor m6 (e.g., the output from the drain terminal of the transistor m6) to produce an output clock signal 716. Thus, the gate terminal of each of the transistors m5 and m6 may be coupled to the input 822, except that the gate terminal of the transistor m6 is coupled to the input 822 via a level shifter circuit 830 configured to perform level shifting before providing the signal to the transistor m6. Similarly, the drain terminal of each of the transistors m5 and m6 may be coupled to the output 824, which may be coupled to a switch 706 to be driven by the switch driver circuit 804.

[0075] In some embodiments, the level shifter circuit 830 may include a voltage controller circuit 832, which may be configured to receive a reference signal 834 as an input and produce an output 836, as Figure 8As shown. In addition, the level shifter circuit 830 may further include a coupling capacitor 838 coupled to the voltage controller circuit 832. For example, the first capacitor electrode of the coupling capacitor 838 may be coupled to the input 822, and the second capacitor electrode of the coupling capacitor 838 may be coupled to each of the voltage controller circuit 832 and the gate terminal of the transistor m6. In other words, a portion of the input clock signal 714 that is split into the second branch 826-2 of the circuit 804 may be configured to be applied to the first capacitor electrode of the coupling capacitor 838, and the second capacitor electrode of the coupling capacitor 838 may be coupled to each of the output 836 of the voltage controller circuit 832 and the gate terminal of the transistor m6. The input 834 to the voltage controller circuit 832 may be a reference voltage or any other control signal configured to control the minimum voltage level set by the voltage controller circuit 832. The output 836 from the voltage controller circuit 832 may form the basis of the level-shifted input clock signal 814-2 to be provided to the gate terminal of the transistor m6.

[0076] When the transistor m6 is an N-type transistor, as Figure 8 shown in the embodiment of, the voltage controller circuit 832 may be configured to control the minimum voltage value in the level-shifted input clock signal 814-2 provided to the transistor m6, and thus in the output signal 716. For this purpose, the input to the PMOS transistor m5 may come directly from the 1V domain inverter output 114 (swinging from 0V to 1V), as the input 814-1 shown in Figure 8 while the input to the NMOS transistor m6 may be level-shifted via the coupling capacitor 838 with the voltage controller circuit 832 to provide a minimum switching voltage of, for example, -0.4V, and ideally a maximum switching voltage of -0.4V + 1V = 0.6V. Due to capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the level shifter circuit 830 may be attenuated by a ratio regarding the size of the coupling capacitor 828 and the size of the capacitance on the gate of the NMOS transistor m6 plus the wiring parasitic capacitance. Thus, the signal at the output Nout of the level shifter circuit 830 may swing from -0.4V to -0.4V + 0.9V = 0.5V (instead of the ideal 0.6V, which would result in a 1V swing from the input Nin to the output Nout of the level shifter circuit 830), as shown by the signal 814-2 shown in Figure 8 As shown in Figure 8The voltage controller circuit 832 or the level shifter circuit 830 shown in [Figure X] may be referred to as a "minimum level controller" because the voltage controller circuit or the level shifter circuit is configured to set the maximum voltage value of the level-shifted input clock signal 814-2. The maximum voltage value of the level-shifted input clock signal 814-2 may then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor 838 and the capacitance of the load for the voltage controller circuit 832.

[0077] In some embodiments of a level shifter circuit (e.g., as shown in [Figure N]) coupled to an N-type transistor of a boost switch driver circuit, the low supply voltage coupled to the source terminal of the N-type transistor (i.e., transistor m6 in this case) may be substantially the same as the minimum voltage value controlled by the voltage controller circuit 832 (e.g., both may be -0.4V), although in other embodiments these voltages may be different. Generally, the value of the supply voltage of the source terminal of the N-type transistor (i.e., transistor m6 in this case) coupled to the branch also including the minimum level controller may correspond to (e.g., be substantially equal to) the low voltage in the level-shifted input clock signal 814-2. In some embodiments of the circuit 804, the high supply voltage coupled to the source terminal of the P-type transistor (i.e., transistor m5 in this case) coupled to the branch not including the level shifter circuit may be substantially the same as the maximum voltage value in the output signal 716 (e.g., both may be 1V), although in other embodiments these voltages may be different (e.g., in the case of including a second level shifter circuit, e.g., as Figure 12 shown in [Figure X]).

[0078] In various embodiments, the level shifter circuit 830 may be implemented in any way that allows for careful control of the minimum value of the level-shifted input clock signal 814-2 to be provided to the N-type transistor m6. One example is shown in Figure 9 [Figure X], however, in other embodiments of the circuit 804, the level shifter circuit 830 may be implemented in a different way. Figure 9 A circuit diagram of an exemplary level shifter circuit 900 according to some embodiments of the present disclosure is provided, which exemplary level shifter circuit may be used with or in a boost switch driver, e.g., as the level shifter circuit 830 of the boost switch driver 804, to perform level shifting in the case of controlling minimum / high signal levels.

[0079] As Figure 9As shown, the level shifter circuit 900 may include a pair of cross-coupled transistors m1 and m2, a pair of capacitors C1 and C2, and an inverter Inv. The arrangement of the level shifter circuit 900 is substantially the same as that of the level shifter circuit 300, except that the transistors m1 and m2 are N-type transistors in the level shifter circuit 900, since the level shifter circuit 900 is a minimum level controller. The descriptions regarding the couplings between the various elements of the level shifter circuit 300 apply to the level shifter circuit 900 and are thus not repeated for the sake of brevity.

[0080] When the level shifter circuit 900 is a minimum level controller, the value of the reference voltage 834 may be configured to correspond to the low voltage in the level-shifted input clock signal 814-2 output by the circuit. In some embodiments, the reference voltage 834 may be substantially the same as the supply voltage coupled to the source terminal of the transistor m6 (e.g., for Figure 8 and 9 the example shown, both may be about -0.4V) and may be from the same voltage source.

[0081] Since the level shifter circuit 900 is a minimum level controller, the reference voltage 834 applied to the source terminals of the transistors m1 and m2 can accurately control the minimum / low level of the output voltage of the signal 814-2 (e.g., ensuring the level is about -0.4V). The maximum / high level of the output voltage of the signal 814-2 can then be established based on the capacitor charge redistribution between the capacitor C1 and the load capacitance C Load which is based on the ratio of these capacitances. Thus, the voltage swing of the output signal 814-2 can be based on the value of the reference voltage 834 provided to the level shifter circuit 900 and on the capacitor charge redistribution between the capacitor C1 and the load capacitance C Load

[0082] Figure 10 A circuit diagram of an example circuit 1000 having a boost switch driver according to some embodiments of the present disclosure is provided, the boost switch driver having a level shift implemented using the level shifter circuit 900 in a branch of N-type transistors. The circuit 1000 may be considered an example of the circuit 800, where the level shifter circuit 830 is implemented as the level shifter circuit 900 and is thus (in the Figure 9 schematic illustration) replaced by the level shifter circuit 900. In Figure 10 the reference numbers of the circuits for Figure 10 are used to refer to elements that are the same as or functionally similar to those shown in Figures 7 to 9 such that the descriptions of those elements are not repeated for Figures 7 to 9 In addition, Figure 10 ​​Figure 9 The various components of the level shifter circuit 900 shown in and described above, such as transistors m1 and m2, capacitors C1 and C2, and inverter Inv, are also shown in Figure 10 to clarify how the level shifter circuit 900 replaces the Figure 8 level shifter circuit 830 shown in. It should be noted that in the Figure 10 embodiment of, the coupling capacitor 838 of the level shifter circuit 830 is implemented by the capacitor C1 of the level shifter circuit 900. In the context of the circuit 1000, the input node Nin and output node Nout of the level shifter circuit 900 are also shown in Figure 10 .

[0083] Figure 11 A circuit diagram of an example circuit 1100 is provided that has a boost switch driver and an additional transistor in accordance with some embodiments of the present disclosure. The boost switch driver has a level shift in the branch of an N-type transistor (i.e., transistor m6 for the example shown). The additional transistor provides a cascode transistor to a P-type transistor in another branch (i.e., transistor m5 for the example shown). The circuit 1100 can be considered a further embodiment of the circuit 1000, where, similar to the circuit 1000, the level shifter circuit 830 is implemented as the level shifter circuit 900 and is thus replaced by the level shifter circuit 900 in the Figure 11 schematic illustration. In Figure 11 , the reference numbers for the Figures 7 to 10 circuit are used to refer to elements that are the same as or functionally similar to those shown in Figures 7 to 10 such that the description of those elements is not repeated for Figure 11 and only the differences are described. The circuit 1100 differs from the circuit 1000 in that the circuit 1100 further includes an additional transistor m7 described above that provides a cascode transistor to transistor m5. To this end, transistors m5 and m7 can be transistors of the same type (i.e., both are P-type transistors, as shown in the Figure 11 illustration). The cascode transistor m7 can be considered part of the first branch 826-1. As Figure 11As shown, the drain terminal of transistor M5 can be coupled to output 824 by coupling the drain terminal of transistor M5 to the source terminal of cascode transistor M7 and coupling the drain terminal of cascode transistor M7 to output 224. In various embodiments, the gate terminal of cascode transistor M7 can be coupled to a suitable reference voltage 1134. For example, for an embodiment where cascode transistor M7 is a P-type transistor as shown (i.e., for an embodiment where the level shifter circuit included in circuit 1100 is a minimum level controller), reference voltage 1134 can be approximately 0V. However, in other embodiments, the value of reference voltage 1134 can be different.

[0084] Although Figure 11 only one cascode transistor M7 is shown in Figure 11 other embodiments of the circuit shown in Figure 11 can include more than one cascode transistor M7 in first branch 826-1. Although Figure 9 cascode transistor M7 is shown in connection with level shifter circuit 900 of Figure 8 in a further embodiment of circuit 800 shown in Figures 7 to 12 first branch 826-1 of circuit 800 can include at least one such cascode transistor M7, where level shifter circuit 830 can, but need not, be implemented as level shifter circuit 900. Additionally, in any of the embodiments having a level-shifted boost switch driver in a branch of N-type transistors (e.g., any of the embodiments described with reference to Figures 7 to 12 ), one or more additional transistors M8 (not specifically shown in the figures) can be provided as cascode transistors to transistor M6 (i.e., as cascode transistors to the N-type transistor of the level shifter circuit). To this end, transistors M6 and M8 can be the same type of transistor (e.g., both are N-type transistors), and one or more cascode transistors M8 can be considered part of second branch 826-2. For example, the source terminal of such a cascode transistor M8 can be coupled to the drain terminal of transistor M6 and the drain terminal of cascode transistor M8 can be coupled to output 224. The gate terminal of such a cascode transistor M8 can be coupled to a suitable reference voltage, e.g., for an embodiment where cascode transistor M8 is an N-type transistor, the suitable reference voltage is approximately 1V (since for

[0085] Figure 12A circuit diagram of an example circuit 1200 is provided that has a boost switch driver and an additional level shifter circuit in accordance with some embodiments of the present disclosure. The boost switch driver has a level shift in a branch of N-type transistors, and the additional level shifter circuit is configured to control the minimum / low level of the final output signal 1216. Circuit 1200 can be considered a further embodiment of circuit 1100, where, similar to circuit 1100, the level shifter circuit 830 coupled to the input of transistor m5 is implemented as level shifter circuit 900 and is thus (in the schematic illustration of Figure 12 ) replaced by level shifter circuit 900. Also similar to circuit 1100, circuit 1200 further includes a cascode transistor m7. In Figure 12 , the reference numbers for the circuits for Figures 7 to 11 are used to refer to elements that are the same as or functionally similar to those shown in Figures 7 to 11 , such that the description of those elements is not repeated for Figure 12 and only the differences are described. Circuit 1200 differs from circuit 1100 in that circuit 1200 further includes Figure 9 another example of level shifter circuit 900, labeled in Figure 12 as level shifter circuit 1230 configured to control the minimum / low level of the output signal 1216 from circuit 1200 based on a reference signal 1234. Since the operation of level shifter circuit 900 has been described in detail above, this description is not repeated here with reference to circuit 1230. The reference signal 1234 is similar to the reference signal 834 described above, except that its value can be different for level shifter circuit 1230. For example, if the input signal provided at the input node Nin of level shifter circuit 1230 is signal 716 having a minimum voltage value and a maximum voltage value of -0.4V and 1V, respectively, as described above, then level shifter circuit 1230 can shift these values by approximately 0.9V (i.e., the value of the reference voltage 1234 can be 0.5V, as in Figure 12(as shown). In particular, the voltage shifter circuit 1230 can be configured to carefully control the value by which the minimum voltage value is shifted based on the reference voltage 1234, i.e., for the example shown, the minimum voltage value is shifted from -0.4V to 0.5V. Ideally, the maximum switching voltage would be 1V + 0.9V = 1.9V. However, as described above for circuit 900, due to capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the voltage shifter circuit 1230 can be attenuated by the ratio of the magnitude of the coupling capacitor C1 of the voltage shifter circuit 1230 to the magnitude of the capacitance on the gate of the transistor implementing the switch 706 plus the wiring parasitic capacitance. Thus, the signal at the output Nout of the voltage shifter circuit 1230 can swing from 0.5V to 0.5V + 1.3V = 1.8V (instead of the ideal 1.9V, which would result in a 1.4V swing from the input Nin to the output Nout of the voltage shifter circuit 1230), as shown by the signal 1216 in Figure 12 Thus, the voltage shifter circuit 1230 can carefully control the minimum / low value of the level-shifted clock signal 1216 based on the reference signal 1234, while the maximum / high voltage value of the level-shifted clock signal 1216 can then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor C1 of the voltage shifter circuit 1230 and the capacitance of the load (including parasitic capacitance) for the voltage shifter circuit 1230. In other words, since the voltage shifter circuit 1230 is a minimum level controller, the reference voltage 1234 applied to the source terminals of the transistors m1 and m2 of the voltage shifter circuit 630 can accurately control the minimum / low level of the output voltage of the signal 1216 (e.g., ensuring the level is approximately 0.5V). The maximum / high level of the output voltage of the signal 1216 can then be established based on the capacitor charge redistribution between the capacitor C1 of the voltage shifter circuit 1230 and the load capacitance C for the voltage shifter circuit 1230, which capacitor charge redistribution is based on the ratio of these capacitances. Thus, the voltage swing of the output signal 1216 can be based on the value of the reference voltage 834 provided to the voltage shifter circuit 900, the value of the reference voltage 1234 provided to the voltage shifter circuit 1230, and the capacitor charge redistribution between the capacitor C1 of the voltage shifter circuit 1230 and the load capacitance C of the voltage shifter circuit 1230. Load between. Load between.

[0086] Although Figure 12 not specifically shown in, in other embodiments of the circuit 1230, the input to the inverter Inv of the voltage shifter circuit 1230 can be based on the inverted version of the input signal 714 provided to the input 822, rather than from as Figure 12The output signal 716 of the output 824 shown therein. In such embodiments, the inverter of the level shifter circuit 1230 can be decoupled from the signal 716 and instead coupled to the inverted version of the signal 714, which can be advantageous in cases where driving the inverter of the level shifter circuit 1230 with a signal having a signal swing greater than about 1V may be unreliable. In such embodiments, one of the capacitor electrodes of the capacitor C1 of the level shifter circuit 1230 is still driven by the signal 716, such that the level shifter circuit 1230 can then generate an output signal provided at the output node Nout of the level shifter circuit 1230 as a level-shifted version of the signal 716 provided at the input node Nin of the level shifter circuit 1230, wherein the minimum / low value of the signal is carefully controlled based on the reference signal 1234.

[0087] Figure 12 Illustrates one way in which the level shifter circuit 1230 can be implemented to provide control over the minimum / low level of the output voltage of the signal 1216 as described above. In other embodiments of the circuit 1200, the level shifter circuit 1230 can be replaced by any circuit configured to provide sufficiently accurate control over the minimum / low level of the output voltage of the signal 1216, wherein the maximum / high level is adjusted accordingly.

[0088] Although Figure 12 in connection with Figure 9 the level shifter circuit 900 of Figure 8 illustrates an additional level shifter circuit 1230, in further embodiments of the circuit 800 shown in Figure 12 an additional level shifter circuit 1230 can be included to receive the signal 716 as an input and generate the output 1216, as described with reference to Figure 12 in connection with Figure 11 the cascode transistor m7 of Figure 8 illustrates an additional level shifter circuit 1230, in further embodiments of the circuit 800 shown in Figure 12 an additional level shifter circuit 1230 as described with reference to Figure 8 can be included without the cascode transistor m7. Still in further embodiments of the circuit 800 shown in Figure 12 an additional level shifter circuit 1230 as described with reference to Figure 12implemented in any other way than that shown, as long as it provides sufficiently accurate control of the minimum / low level of the output voltage of signal 1216 as described above.

[0089] Still further, although Figure 12 shows a level shifter circuit 1230 configured to provide control of the minimum / low level of the output voltage of signal 1216 as described above, in other embodiments, the level shifter circuit 1230 may use a level shifter circuit 1230' (not shown in Figure 12 shown, but the reference number is used here for convenience of description) configured to provide control of the maximum / high level of the output voltage of signal 1216 instead. In some such embodiments, to implement the level shifter circuit 1230', Figure 12 the level shifter circuit 1230 shown in Figure 12 may be replaced by a level shifter circuit 300, or equivalently, the NMOS transistors of the level shifter circuit 1230 shown in Figure 12 may be replaced by PMOS transistors, and the reference voltage 1234 may be replaced by a reference voltage 1234' (not shown in Figure 12 either, but the reference number is used here for convenience of description) configured to accurately control the maximum / high level of the output voltage of signal 1216.

[0090] The input to the level shifter circuit 1230' may be applied / provided to the node Nin of the circuit 1230', which node is coupled to the first capacitor electrode of the capacitor C1 and, in some embodiments, to the input of the inverter Inv, as Figure 12 shown in Figure 12The example shown is based on a signal from -0.4V to 1V. The level shifter circuit 1230’ can generate an output signal from the output node Nout of the circuit 1230’, which is coupled to one or more of the second capacitor electrode of the capacitor C1, the drain terminal of the transistor m1, and the gate terminal of the transistor m2. The output signal 1216 from the output node Nout of the level shifter circuit 1230’ can be a level-shifted version of the input signal (e.g., signal 716) provided at the input node Nin of the level shifter circuit 1230’, where the maximum / high value of the signal is carefully controlled based on the reference signal 1234’. For example, if the input signal provided at the input node Nin of the level shifter circuit 1230’ is the signal 716 having a minimum voltage value of -0.4V and a maximum voltage value of 1V as described above, then the level shifter circuit 1230’ can shift these values such that the maximum voltage value is 1.8V, which for this example will be the value of the reference voltage 1234’. In particular, the level shifter circuit 1230’ is configured to carefully control the value by which the maximum voltage value is shifted based on the reference voltage 1234’, i.e., for the example shown, the maximum voltage value is shifted by 0.8V, from 1V to 1.8V. Ideally, the minimum switching voltage would be -0.4V + 0.8V = 0.4V. However, as described above for the maximum voltage controller 300, due to capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the level shifter circuit 1230’ can be attenuated by the ratio of the size of the coupling capacitor C1 of the level shifter circuit 1230’ to the size of the capacitance on the gate of the transistor in which the switch 706 can be implemented plus the wiring parasitic capacitance. Thus, the minimum voltage value at the output Nout of the level shifter circuit 1230’ can be 1.8V - 1.3V = 0.5V (instead of the ideal 0.4V, which would result in a 1.4V swing from the input Nin to the output Nout of the level shifter circuit 1230’), as shown in Figure 12as shown by the signal 1216 shown in. Thus, the level shifter circuit 1230' can carefully control the maximum / high value of the level-shifted clock signal 1216 based on the reference signal 1234', and the minimum / low voltage value of the level-shifted clock signal 1216 can then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor C1 of the level shifter circuit 1230' and the capacitance (including parasitic capacitance) of the load for the level shifter circuit 1230'. In other words, since the level shifter circuit 1230' is a maximum level controller, the reference voltage 1234' applied to the source terminals of the transistors m1 and m2 of the level shifter circuit 1230' can accurately control the maximum / high level of the output voltage of the signal 1216 (e.g., ensuring the level is about 1.8V). The minimum / low level of the output voltage of the signal 1216 can then be established based on the capacitor charge redistribution between the capacitor C1 of the level shifter circuit 1230' and the load capacitance C of the level shifter circuit 1230', and the capacitor charge redistribution is based on the ratio of these capacitances. Therefore, the voltage swing of the output signal 1216 can be based on the value of the reference voltage 834 provided to the level shifter circuit 900, the value of the reference voltage 1234' provided to the level shifter circuit 1230', and the capacitor charge redistribution between the capacitor C1 of the level shifter circuit 1230' and the load capacitance C of the level shifter circuit 1230'. Load between to establish, and the capacitor charge redistribution is based on the ratio of these capacitances. Therefore, the voltage swing of the output signal 1216 can be based on the value of the reference voltage 834 provided to the level shifter circuit 900, the value of the reference voltage 1234' provided to the level shifter circuit 1230', and the capacitor charge redistribution between the capacitor C1 of the level shifter circuit 1230' and the load capacitance C of the level shifter circuit 1230'. Load between the capacitor charge redistribution.

[0091] Similar to the variant of the level shifter circuit 1230 described above Figure 12 shown in, in other embodiments of the circuit 1230', the input to the inverter Inv of the level shifter circuit 1230' can be based on the inverted version of the input signal 714 provided to the input 822, rather than the output signal 716 from the output 824 as shown in. Figure 12 shown in. In such embodiments, the inverter of the level shifter circuit 1230' can be decoupled from the signal 716 and instead coupled to the inverted version of the signal 714, which can be advantageous in cases where it may be unreliable to drive the inverter of the level shifter circuit 1230' with a signal having a signal swing greater than about 1V. In such embodiments, one of the capacitor electrodes of the capacitor C1 of the level shifter circuit 1230' is still driven by the signal 716, such that the level shifter circuit 1230' can then generate an output signal provided at the output node Nout of the level shifter circuit 1230' as a level-shifted version of the signal 716 provided at the input node Nin of the level shifter circuit 1230', where the maximum / high value of the signal is carefully controlled based on the reference signal 1234'.

[0092] In other embodiments of circuit 1200, the level shifter circuit 1230' may be implemented in any other way than the level shifter circuit 300, as long as it provides sufficiently accurate control of the maximum / high level of the output voltage of signal 1216, where the minimum / low level is adjusted accordingly.

[0093] Example Systems and Devices

[0094] A boost switch driver circuit or portions thereof as described herein (e.g., only portions of inverter circuits 104 and / or 704 as described herein) may be included in any suitable system, apparatus, or device. For example, in some embodiments, any one or portions of the boost switch drivers may be included in an ADC as Figure 13 shown. In other embodiments, any one or portions of the boost switch drivers may be included in a larger system or device configured to perform analog-to-digital conversion. Some examples of such systems and devices are shown in Figure 14 and 15 . Other examples of systems and devices that include one or more of the boost switch drivers as described herein are possible and within the scope of the present disclosure.

[0095] Figure 13 A schematic illustration of an example component 1300 (e.g., an ADC) in which one or more boost switch drivers 1310 may be implemented according to some embodiments of the present disclosure is provided. One or more boost switch drivers 1310 may include any of the boost switch driver circuits described above, e.g., any embodiment of the boost switch driver described with reference to Figures 1 to 12 . One or more boost switch drivers 1310 may be configured to drive one or more switches 1320. In some embodiments, there may be a one-to-one correspondence between one or more boost switch drivers 1310 and one or more switches 1320 (i.e., each boost switch driver 1310 may be configured to drive only one of the switches 1320 and each of the switches 1320 may be configured to be driven by only one of the boost switch drivers 1310). In other embodiments, a single boost switch driver 1310 may drive more than one of the switches 1320 and / or a single one of the switches 1320 may be driven by more than one of the boost switch drivers 1310.

[0096] Figure 14 is a block diagram of an example system 2100 (e.g., a computing device) that may include one or more boost switch drivers according to any of the embodiments disclosed herein. For example, any suitable components of the components of system 2100 may include one or more of the boost switch drivers disclosed herein. In Figure 14Several components are shown as being included in system 2100, but any one or more of these components may be omitted or duplicated depending on the application. In some embodiments, some or all of the components included in system 2100 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single chip system (SoC) die.

[0097] Additionally, in various embodiments, system 2100 may not include Figure 14 one or more of the components shown, but system 2100 may include interface circuitry for coupling to the one or more components. For example, system 2100 may not include display device 2106, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 2106 may be coupled. In another set of examples, system 2100 may not include audio input device 2118 or audio output device 2108, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 2118 or audio output device 2108 may be coupled.

[0098] System 2100 may include processing device 2102 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory. Processing device 2102 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), encryption processors (specialized processors that execute encryption algorithms in hardware), server processors, or any other suitable processing device. System 2100 may include memory 2104, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or hard disk drives. In some embodiments, memory 2104 may include memory that shares a die with processing device 2102. This memory may be used as a cache memory and may include embedded DRAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).

[0099] In some embodiments, system 2100 may include a communication chip 2112 (e.g., one or more communication chips). For example, communication chip 2112 may be configured to manage wireless communication for the transfer of data to and from system 2100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can convey data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated device does not contain any wires, although in some embodiments the associated device may not contain any wires.

[0100] Communication chip 2112 may implement any of several wireless standards or protocols, including but not limited to: Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) program, along with any amendments, updates, and / or revisions (e.g., LTE-Advanced program, Ultra Mobile Broadband (UMB) program (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks - an acronym representing Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass compliance and interoperability testing for the IEEE 802.16 standard. Communication chip 2112 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication chip 2112 may operate according to Enhanced Data rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 2112 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and above. In other embodiments, communication chip 2112 may operate according to other wireless protocols. System 2100 may include an antenna 2122 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0101] In some embodiments, the communication chip 2112 may manage wired communication, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2112 may include multiple communication chips. For example, a first communication chip 2112 may be dedicated to short-range wireless communication, such as Wi-Fi or Bluetooth, and a second communication chip 2112 may be dedicated to long-range wireless communication, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 2112 may be dedicated to wireless communication, and the second communication chip 2112 may be dedicated to wired communication.

[0102] System 2100 may include a battery / power circuitry 2114. The battery / power circuitry 2114 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling the components of system 2100 to an energy source (e.g., an AC line power) separate from system 2100.

[0103] System 2100 may include a display device 2106 (or the corresponding interface circuitry as discussed above). The display device 2106 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0104] System 2100 may include an audio output device 2108 (or the corresponding interface circuitry as discussed above). The audio output device 2108 may include any device that produces an audible indicator, such as a speaker, headphones, or earbuds.

[0105] System 2100 may include an audio input device 2118 (or the corresponding interface circuitry as discussed above). The audio input device 2118 may include any device that produces a signal representative of sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output).

[0106] System 2100 may include a GPS device 2116 (or the corresponding interface circuitry as discussed above). As is known in the art, the GPS device 2116 may communicate with a satellite-based system and may receive the location of system 2100.

[0107] System 2100 may include another output device 2110 (or the corresponding interface circuitry as discussed above). Examples of other output devices 2110 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0108] System 2100 may include another input device 2120 (or corresponding interface circuitry as discussed above). Examples of other input devices 2120 may include accelerometers, gyroscopes, compasses, image acquisition devices, keyboards, cursor control devices (such as mice), styli, touch pads, bar code readers, quick response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0109] System 2100 may have any desired form factor, such as a handheld or mobile electronic device (e.g., a cellular phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), a desktop electronic device, a server device, or other network-connected computing components, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, system 2100 may be any other electronic device that processes data.

[0110] Figure 15 is a block diagram of an example RF device 2200 (e.g., an RF transceiver) that may include one or more components having one or more boost switch drivers according to any of the embodiments disclosed herein. For example, any suitable component of the components of RF device 2200 may include a die that includes at least one boost switch driver or a portion thereof configured to drive one or more switches according to any of the embodiments disclosed herein. In some embodiments, RF device 2200 may be included within any component of system 2100 as described in reference Figure 16 or may be coupled to any one of the components of system 2100, e.g., coupled to the memory 2104 and / or the processing device 2102 of system 2100. In still other embodiments, RF device 2200 may further include any one of the components described in reference Figure 16 such as, but not limited to, the battery / power circuitry 2114, the memory 2104, and the various input and output devices as shown in Figure 16 .

[0111] In general, the RF device 2200 can be any device or system that can support wireless transmission and / or reception of signals in the form of electromagnetic waves in an RF range from approximately 3 kilohertz (kHz) to approximately 300 gigahertz (GHz). In some embodiments, the RF device 2200 can be used for wireless communication, for example, in a base station (BS) or user equipment (UE) device for any suitable cellular wireless communication technology such as GSM, WCDMA, or LTE. In other examples, the RF device 2200 can be used as or in, for example, a BS or UE device for millimeter-wave wireless technology such as fifth-generation (5G) wireless (i.e., high-frequency / short-wavelength spectrum, e.g., having a frequency in the range between approximately 20 GHz and 60 GHz, corresponding to a wavelength in the range between approximately 5 millimeters and 15 millimeters). In yet another example, the RF device 2200 can be used for wireless communication using Wi-Fi technology (e.g., a 2.4 GHz band, corresponding to a wavelength of approximately 12 cm; or a 5.8 GHz band, spectrum, corresponding to a wavelength of approximately 5 cm), for example, in Wi-Fi-enabled devices such as desktop computers, laptop computers, video game consoles, smartphones, tablet computers, smart TVs, digital audio players, cars, printers, etc. In some embodiments, a Wi-Fi-enabled device can be, for example, a node in a smart system configured to communicate data with other nodes (e.g., smart sensors). Still in another example, the RF device 2200 can be used for wireless communication using Bluetooth technology (e.g., a band from approximately 2.4 GHz to approximately 2.485 GHz, corresponding to a wavelength of approximately 12 cm). In other embodiments, the RF device 2200 can be used for transmitting and / or receiving RF signals for purposes other than communication, for example, in an automotive radar system or in medical applications such as magnetic resonance imaging (MRI).

[0112] In various embodiments, the RF device 2200 can be included in a frequency-division duplex (FDD) or time-division duplex (TDD) variant that can be used for frequency allocation in a cellular network. In an FDD system, the uplink (i.e., an RF signal transmitted from a UE device to a BS) and the downlink (i.e., an RF signal transmitted from a BS to a US device) can use separate frequency bands simultaneously. In a TDD system, the uplink and the downlink can use the same frequency but at different times.

[0113] In Figure 15Several components are shown as being included in the RF device 2200, but any one or more of these components may be omitted or replicated depending on the application. For example, in some embodiments, the RF device 2200 may be an RF device that supports both wireless transmission and reception of RF signals (e.g., an RF transceiver), in which case it may include components referred to herein as a transmit (TX) path and components referred to herein as a receive (RX) path. However, in other embodiments, the RF device 2200 may be an RF device that only supports wireless reception (e.g., an RF receiver), in which case it may include components of the RX path but not components of the TX path, or the RF device 2200 may be an RF device that only supports wireless transmission (e.g., an RF transmitter), in which case it may include components of the TX path but not components of the RX path.

[0114] In some embodiments, some or all of the components included in the RF device 2200 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single die, e.g., on a single SoC die.

[0115] Additionally, in various embodiments, the RF device 2200 may not include Figure 15 one or more of the components shown in, but the RF device 2200 may include interface circuitry for coupling to the one or more components. For example, the RF device 2200 may not include the antenna 2202, but may include antenna interface circuitry (e.g., matching circuitry, connectors, and driver circuitry) to which the antenna 2202 may be coupled. In another set of examples, the RF device 2200 may not include the digital processing unit 2208 or the local oscillator 2206, but may include device interface circuitry (e.g., connectors and support circuitry) to which the digital processing unit 2208 or the local oscillator 2206 may be coupled.

[0116] As Figure 15 shown, the RF device 2200 may include the antenna 2202, the duplexer 2204, the local oscillator 2206, and the digital processing unit 2208. As also shown in Figure 15 the RF device 2200 may include an RX path that may include an RX path amplifier 2212, an RX path premix filter 2214, an RX path mixer 2216, an RX path postmix filter 2218, and an ADC 2220. As Figure 15As further shown, the RF device 2200 may include a TX path, which may include a TX path amplifier 2222, a post-TX path mixer filter 2224, a TX path mixer 2226, a pre-TX path mixer filter 2228, and a DAC 2230. Still further, the RF device 2200 may further include an impedance tuner 2232, an RF switch 2234, and control logic 2236. In various embodiments, the RF device 2200 may include Figure 15 multiple examples of any of the components shown in. In some embodiments, the RX path amplifier 2212, the TX path amplifier 2222, the duplexer 2204, and the RF switch 2234 may be considered to form or be part of the RF front end (FE) of the RF device 2200. In some embodiments, the RX path amplifier 2212, the TX path amplifier 2222, the duplexer 2204, and the RF switch 2234 may be considered to form or be part of the RF FE of the RF device 2200. In some embodiments, the RX path mixer 2216 and the TX path mixer 2226 (possibly, associated with Figure 15 the pre-mix and post-mix filters shown in) may be considered to form or be part of the RF transceiver of the RF device 2200 (if only the RX path or TX path components are included in the RF device 2200 respectively, then may be considered to form or be part of the RF receiver or RF transmitter). In some embodiments, the RF device 2200 may further include one or more control logic elements / circuits shown as control logic 2236 in Figure 15 e.g., an RF FE control interface. In some embodiments, the control logic 2236 may be configured to control at least part of any of the boost switch drivers within any component of the RF device 2200 operating as described herein. In some embodiments, the control logic 2236 may be used to perform control over other functions within the RF device 2200, such as enhanced control of complex RF system environments, support for the implementation of envelope tracking techniques, reduction of dissipated power, etc.

[0117] The antenna 2202 can be configured to wirelessly transmit and / or receive RF signals according to any wireless standard or protocol (such as Wi-Fi, LTE, or GSM), as well as any other wireless protocol designated as 3G, 4G, 5G, and above. If the RF device 2200 is an FDD transceiver, then the antenna 2202 can be configured to receive and transmit communication signals in separate (i.e., non-overlapping and non-consecutive) frequency bands simultaneously (e.g., in frequency bands having an interval of, for example, 20 MHz from each other). If the RF device 2200 is a TDD transceiver, then the antenna 2202 can be configured to receive and transmit communication signals in a frequency band that can be the same or overlapping for the TX path and the RX path in sequence. In some embodiments, the RF device 2200 can be a multi-band RF device, in which case the antenna 2202 can be configured to receive signals having multiple RF components in separate frequency bands simultaneously and / or configured to transmit signals having multiple RF components in separate frequency bands simultaneously. In such embodiments, the antenna 2202 can be a single wide-band antenna or multiple band-specific antennas (i.e., multiple antennas each configured to receive and / or transmit signals in a specific frequency band). In various embodiments, the antenna 2202 can include multiple antenna elements, for example, multiple antenna elements forming a phased antenna array (i.e., a communication system or any antenna array that can use multiple antenna elements and phase shifts to transmit and receive RF signals). Compared with a single antenna system, a phased antenna array can provide advantages such as gain, direction manipulation ability, and increased simultaneous communication. In some embodiments, the RF device 2200 can include more than one antenna 2202 for implementing antenna diversity. In some such embodiments, an RF switch 2234 can be deployed to switch between different antennas.

[0118] The output of the antenna 2202 can be coupled to the input of a duplexer 2204. The duplexer 2204 can be any suitable component configured to filter multiple signals to allow two-way communication via a single path between the duplexer 2204 and the antenna 2202. The duplexer 2204 can be configured to provide an RX signal to the RX path of the RF device 2200 and receive a TX signal from the TX path of the RF device 2200.

[0119] The RF device 2200 can include one or more local oscillators 2206 configured to provide local oscillator signals, which can be used for down-conversion of RF signals received by the antenna 2202 and / or up-conversion of signals to be transmitted by the antenna 2202.

[0120] The RF device 2200 can include a digital processing unit 2208, which can include one or more processing devices. In some embodiments, the digital processing unit 2208 can be implemented as Figure 16The processing device 2102 shown in [description not provided], the description of the processing device having been provided above (when used as the digital processing unit 2208, the processing device 2102 may but need not implement any of the boost switch drivers described herein). The digital processing unit 2208 may be configured to perform various functions related to the digital processing of RX and / or TX signals. Examples of such functions include but are not limited to: decimation / downsampling, error correction, digital downconversion or upconversion, DC offset cancellation, automatic gain control, etc. Although Figure 15 not shown in [figure reference not provided], in some embodiments, the RF device 2200 may further include a memory device, e.g., the memory device 2104 described with reference to Figure 16 configured to cooperate with the digital processing unit 2208. When used within or coupled to the RF device 2200, the memory device 2104 may but need not implement any of the boost switch drivers described herein.

[0121] Returning to the details of the RX path that may be included in the RF device 2200, the RX path amplifier 2212 may include a low noise amplifier (LNA). The input of the RX path amplifier 2212 may be coupled, e.g., via a duplexer 2204, to an antenna port (not shown) of the antenna 2202. The RX path amplifier 2212 may amplify the RF signal received by the antenna 2202.

[0122] The output of the RX path amplifier 2212 may be coupled to the input of the RX path premix filter 2214, which may be a harmonic or bandpass (e.g., low pass) filter configured to filter the received RF signal that has been amplified by the RX path amplifier 2212.

[0123] The output of the RX path premix filter 2214 can be coupled to the input of the RX path mixer 2216 (also referred to as a downconverter). The RX path mixer 2216 can include two inputs and one output. The first input can be configured to receive an RX signal, which can be a current signal indicative of the signal received by the antenna 2202 (e.g., the first input can receive the output of the RX path premix filter 2214). The second input can be configured to receive a local oscillator signal from one of the local oscillators 2206. The RX path mixer 2216 can then mix the signals received at its two inputs to produce a downconverted RX signal provided at the output of the RX path mixer 2216. As used herein, downconversion refers to the process of mixing a received RF signal with a local oscillator signal to produce a lower frequency signal. In particular, when two input frequencies are provided at the two input ports, the TX path mixer (e.g., downconverter) 2216 can be configured to produce a sum frequency and / or a difference frequency at the output port. In some embodiments, the RF device 2200 can implement a direct conversion receiver (DCR), also referred to as a homodyne, synchronous, or zero IF receiver, in which case the RX path mixer 2216 can be configured to demodulate an incoming radio signal using a local oscillator signal whose frequency is equal to or very close to the carrier frequency of the radio signal. In other embodiments, the RF device 2200 can utilize downconversion to an intermediate frequency (IF). The IF can be used in a superheterodyne radio receiver, where the received RF signal is shifted to the IF before the final detection of the information in the received signal. Converting to the IF can be useful for several reasons. For example, when using several filter stages, they can all be set to a fixed frequency, which makes them easier to build and tune. In some embodiments, the RX path mixer 2216 can include several such IF conversion stages.

[0124] Although at Figure 15A single RX path mixer 2216 is shown in the RX path, but in some embodiments, the RX path mixer 2216 can be implemented as a quadrature downconverter, in which case the RX path mixer will include a first RX path mixer and a second RX path mixer. The first RX path mixer can be configured to perform downconversion to generate an in-phase (I) downconverted RX signal by mixing the RX signal received by the antenna 2202 with the in-phase component of the local oscillator signal provided by the local oscillator 2206. The second RX path mixer can be configured to perform downconversion to generate a quadrature (Q) downconverted RX signal by mixing the RX signal received by the antenna 2202 with the quadrature component of the local oscillator signal provided by the local oscillator 2206 (the quadrature component is a component that is 90 degrees out of phase with the in-phase component of the local oscillator signal). The output of the first RX path mixer can be provided to the I signal path, and the output of the second RX path mixer can be provided to the Q signal path, which can be out of phase with the I signal path by substantially 90 degrees.

[0125] The output of the RX path mixer 2216 can optionally be coupled to an RX path post-mix filter 2218, which can be a low-pass filter. In the case where the RX path mixer 2216 is a quadrature mixer implementing the first and second mixers as described above, the in-phase and quadrature components provided at the outputs of the first and second mixers respectively can be coupled to corresponding individual first path post-mix filters and second RX path post-mix filters included in the filter 2218.

[0126] The ADC 2220 can be configured to convert the mixed RX signal from the RX path mixer 2216 from the analog domain to the digital domain. The ADC 2220 can be a quadrature ADC, like the RX path quadrature mixer 2216, which can include two ADCs configured to digitize the downconverted RX path signals separated in the in-phase and quadrature components. The output of the ADC 2220 can be provided to the digital processing unit 2208, which is configured to perform various functions related to the digital processing of the RX signal so that the information encoded in the RX signal can be extracted. One or more of any of the embodiments of the boost switch driver described herein can be included within the ADC 2220.

[0127] Returning to the details of the TX path that can be included in the RF device 2200, the digital signal (TX signal) to be transmitted by the antenna 2202 at a later time can be provided from the digital processing unit 2208 to the DAC 2230. Similar to the ADC 2220, the DAC 2230 can include two DACs configured to convert the digital I path and Q path TX signal components into analog form respectively.

[0128] Optionally, the output of the DAC 2230 can be coupled to the TX path premix filter 2228, which can be a bandpass (e.g., low-pass) filter (or, in the case of quadrature processing, a pair of bandpass (e.g., low-pass) filters) configured to filter out signal components outside the desired frequency band from the analog TX signal output by the DAC 2230. The digital TX signal can then be provided to the TX path mixer 2226, which can also be referred to as an upconverter. Similar to the RX path mixer 2216, the TX path mixer 2226 can include a pair of TX path mixers for mixing in-phase and quadrature components. Similar to the first RX path mixer and the second RX path mixer that can be included in the RX path, each of the TX path mixers of the TX path mixer 2226 can include two inputs and one output. The first input can receive the TX signal component converted to analog form by the corresponding DAC 2230, which will be upconverted to generate the RF signal to be transmitted. The first TX path mixer can generate an in-phase (I) upconverted signal by mixing the TX signal component converted to analog form by the DAC 2230 with the in-phase component of the TX path local oscillator signal provided from the local oscillator 2206 (in various embodiments, the local oscillator 2206 can include multiple different local oscillators, or be configured to provide different local oscillator frequencies to the mixer 2216 in the RX path and the mixer 2226 in the TX path). The second TX path mixer can generate a quadrature-phase (Q) upconverted signal by mixing the TX signal component converted to analog form by the DAC 2230 with the quadrature component of the TX path local oscillator signal. The output of the second TX path mixer can be added to the output of the first TX path mixer to generate the real RF signal. The second input of each of the TX path mixers can be coupled to the local oscillator 2206.

[0129] Optionally, the RF device 2200 can include a TX path postmix filter 2224 configured to filter the output of the TX path mixer 2226.

[0130] The TX path amplifier 2222 can be a power amplifier (PA) configured to amplify the power of the upconverted RF signal before providing the upconverted RF signal to the antenna 2202 for transmission.

[0131] In various embodiments, any one of the RX path premix filter 2214, the RX path postmix filter 2218, the TX postmix filter 2224, and the TX premix filter 2228 may be implemented as an RF filter. In some embodiments, the RF filter may be implemented as a plurality of RF filters or a filter bank. The filter bank may include a plurality of RF filters that may be coupled to a switch (e.g., RF switch 2234), the switch configured to selectively open and close any one of the plurality of RF filters (e.g., activate any one of the plurality of RF filters) in order to achieve the desired filtering characteristics of the filter bank (i.e., in order to program the filter bank). For example, when the RF device 2200 is or is included in a BS or UE device, this filter bank may be used to switch between different RF frequency ranges. In another example, this filter bank may be programmable to suppress TX leakage at different duplex distances.

[0132] The impedance tuner 2232 may include any suitable circuitry configured to match the input impedance and the output impedance of different RF circuitry to minimize signal loss in the RF device 2200. For example, the impedance tuner 2232 may include an antenna impedance tuner. Being able to tune the impedance of the antenna 2202 may be particularly advantageous because the impedance of the antenna changes depending on the environment in which the RF device 2200 is located, e.g., the impedance of the antenna depends on, for example, whether the antenna is held in the hand, placed on the roof of a vehicle, etc.

[0133] As described above, the RF switch 2234 may be a device configured to route high-frequency signals through a transmission path, e.g., in order to Figure 15 selectively switch between multiple examples of any one of the components shown in, e.g., in order to achieve the desired behavior and characteristics of the RF device 2200. For example, in some embodiments, the RF switch may be used to switch between different antennas 2202. In other embodiments, the RF switch may be used to switch between multiple RF filters of the RF device 2200 (e.g., by selectively opening and closing RF filters). Generally, an RF system will include multiple such RF switches.

[0134] The RF device 2200 presents a simplified version and, in other embodiments, may include Figure 15Other components not specifically shown. For example, the RX path of the RF device 2200 may include a current-to-voltage amplifier between the RX path mixer 2216 and the ADC 2220, and the current-to-voltage amplifier may be configured to amplify and convert the down-converted signal into a voltage signal. In another example, the RX path of the RF device 2200 may include a balun for generating a balanced signal. In yet another example, the RF device 2200 may further include a clock generator, which may include, for example, a suitable phase-locked loop (PLL) configured to receive a reference clock signal and use it to generate different clock signals, and the different clock signals may then be used to time the operations of the ADC 2220, the DAC 2230, and / or may also be used by the local oscillator 2206 to generate local oscillator signals to be used in the RX path or the TX path.

[0135] Example Data Processing System

[0136] Figure 16 Provided is a block diagram showing an example data processing system 2300 according to some embodiments of the present disclosure, and the example data processing system may be configured to control the operation of one or more boost switch drivers as described herein. For example, the data processing system 2300 may be configured to implement or control the boost switch drivers 204, 804, or a part of any other embodiment of the boost switch driver as described herein. In another example, the data processing system 2300 may be configured to implement Figure 15 at least a part of the control logic 2236 shown in.

[0137] As Figure 16 shown, the data processing system 2300 may include at least one processor 2302 (e.g., a hardware processor 2302) coupled to a memory element 2304 via a system bus 2306. Thus, the data processing system may store program code in the memory element 2304. Further, the processor 2302 may execute the program code accessed from the memory element 2304 via the system bus 2306. In one aspect, the data processing system may be implemented as a computer suitable for storing and / or executing program code. However, it should be understood that the data processing system 2300 may be implemented in the form of any system capable of executing the functions described within the present disclosure that includes a processor and a memory.

[0138] In some embodiments, the processor 2302 may execute software or algorithms to perform activities as discussed in this disclosure, particularly, activities related to operating a boost switch driver as described herein. The processor 2302 may comprise any combination of hardware, software, or firmware that provides programmable logic, including, by way of non-limiting example, a microprocessor, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic array (PLA), an application specific IC (ASIC), or a virtual machine processor. The processor 2302 may be communicatively coupled to a memory element 2304, such as in a direct memory access (DMA) configuration, such that the processor 2302 may read from or write to the memory element 2304.

[0139] Generally, the memory element 2304 may comprise any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash, read only memory (ROM), optical media, virtual memory regions, magnetic or tape memory, or any other suitable technology. Unless otherwise specified, any of the memory elements discussed herein should be construed to be subsumed within the broad term "memory". Information that is measured, processed, tracked, or sent to or from any of the components of the data processing system 2300 may be provided in any database, register, control list, cache, or storage structure, all of which may be referenced at any suitable time frame. Any such storage option may be subsumed within the broad term "memory" as used herein. Similarly, any of the potential processing elements, modules, and machines described herein should be construed to be subsumed within the broad term "processor". Each of the elements shown in the figures of this disclosure, e.g., any element showing a boost switch driver as shown in Figures 1 to 12 may also comprise a suitable interface for receiving, transmitting, and / or otherwise communicating data or information in a network environment such that it may communicate with, e.g., the data processing system 2300.

[0140] In certain example embodiments, the mechanisms for implementing one or more boost switch drivers as outlined herein may be implemented by logic encoded in one or more tangible media that may include a non-transitory medium, e.g., embedded logic provided in an ASIC, DSP instructions, software (possibly including object code and source code) to be executed by a processor or other similar machine, etc. In some examples of these examples, memory elements, such as Figure 16The memory element 2304 shown herein can store data or information for the operations described herein. This includes memory elements capable of storing software, logic, code, or processor instructions that are executed to implement the activities described herein. The processor can execute any type of instructions associated with the data or information used to implement the operations detailed herein. In one example, a processor, such as, for example Figure 16 the processor 2302 shown herein, can transform an element or item (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein can be implemented using fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein can be some type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or an ASIC that includes digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0141] The memory element 2304 can include one or more physical memory devices, such as, for example, local memory 2308 and one or more mass storage devices 2310. Local memory can refer to RAM or other non-permanent memory devices typically used during the actual execution of program code. The mass storage device can be implemented as a hard disk drive or other permanent data storage device. The processing system 2300 can also include one or more cache memories (not shown) that provide temporary storage of at least some program code to reduce the number of times the program code must be retrieved from the mass storage device 2310 during execution.

[0142] As Figure 16 shown herein, the memory element 2304 can store the application program 2318. In various embodiments, the application program 2318 can be stored in the local memory 2308, one or more mass storage devices 2310, or spaced apart from the local memory and the mass storage device. It should be understood that the data processing system 2300 can further execute an operating system (not shown in Figure 16 herein) that can facilitate the execution of the application program 2318. The application program 2318 implemented in the form of executable program code can be executed by the data processing system 2300, for example, by the processor 2302. In response to the execution of the application program, the data processing system 2300 can be configured to perform one or more of the operations or method steps described herein.

[0143] Input / output (I / O) devices depicted as input device 2312 and output device 2314 may optionally be coupled to the data processing system. Examples of input devices may include, but are not limited to, a keyboard, a pointing device such as a mouse, and the like. Examples of output devices may include, but are not limited to, a monitor or display, a speaker, and the like. In some embodiments, output device 2314 may be any type of screen display, such as a plasma display, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator, such as a dial, a barometer, or an LED. In some implementations, the system may include a driver (not shown) for output device 2314. Input and / or output devices 2312, 2314 may be coupled to the data processing system directly or through an intervening I / O controller.

[0144] In an embodiment, the input device and the output device may be implemented as a combined input / output device (shown in Figure 16 dashed lines surrounding input device 2312 and output device 2314). An example of such a combined device is a touch-sensitive display, sometimes also referred to as a "touch screen display" or simply a "touch screen". In this embodiment, input to the device may be provided by the movement of a physical object, such as a stylus or a user's finger touching on or near the display screen.

[0145] Network adapter 2316 may also optionally be coupled to the data processing system to enable it to be coupled to other systems, computer systems, remote network devices, and / or remote storage devices through an intervening private or public network. The network adapter may include a data receiver for receiving data transmitted to the data processing system 2300 by the systems, devices, and / or networks, and a data transmitter for transmitting data from the data processing system 2300 to the systems, devices, and / or networks. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that may be used with the data processing system 2300.

[0146] Selection Instances

[0147] The following paragraphs provide various examples of the embodiments disclosed herein.

[0148] Example 1 provides a switching driver circuit, comprising: an input configured to receive an input clock signal; an output configured to provide an output clock signal; a first transistor (e.g., transistor m5 shown in the drawings of the present disclosure); a second transistor (e.g., transistor m6 shown in the drawings of the present disclosure), wherein each of the first transistor and the second transistor comprises a first terminal (e.g., a gate terminal) and a second terminal (e.g., a drain terminal), and wherein one of the first transistor and the second transistor is a P-type transistor (e.g., a PMOS transistor) and the other is an N-type transistor (e.g., an NMOS transistor); and a level shifter circuit configured to level shift the input clock signal to generate a level-shifted input clock signal. The first terminal of the first transistor is configured to receive a signal indicative of the input clock signal (e.g., the input clock signal itself or a version of the input clock signal that has been level shifted in a manner complementary to the level shift of the signal to be provided to the second transistor), the first terminal of the second transistor is configured to receive a signal indicative of the level-shifted input clock signal, and each of the second terminals of the first transistor and the second transistor is coupled to the output (i.e., the second terminal of the first transistor is coupled to the second terminal of the second transistor, and both are coupled to the output).

[0149] Example 2 provides the switching driver circuit according to Example 1, wherein the input clock signal has a low voltage value and a high voltage value, and level shifting the input clock signal comprises the level shifter circuit changing each of the low voltage value and the high voltage value of the input signal to generate the level-shifted input signal.

[0150] Example 3 provides the switching driver circuit according to Example 1 or 2, wherein the level shifter circuit comprises a coupling capacitor and a voltage controller circuit, and the first terminal of the second transistor is configured to receive the signal indicative of the level-shifted input clock signal through a first capacitor electrode coupled to the input and a second capacitor electrode coupled to each of the voltage controller circuit and the first terminal of the second transistor.

[0151] Example 4 provides the switching driver circuit according to Example 3, wherein the voltage controller circuit is configured to control the high voltage value in the level-shifted input clock signal. This voltage controller circuit may be referred to as a "maximum level controller" because it sets the maximum voltage value of the level-shifted input clock signal. The minimum voltage value is then automatically adjusted based on the ratio between the capacitance of the coupling capacitor and the capacitance of the load for the voltage controller circuit.

[0152] Example 5 provides the switch driver circuit according to Example 4, wherein a third terminal of the second transistor is coupled to a supply voltage, and a value of the supply voltage corresponds to (e.g., is substantially equal to) the high voltage in the level-shifted input clock signal.

[0153] Example 6 provides the switch driver circuit according to Example 4 or 5, wherein the voltage controller circuit includes a pair of cross-coupled transistors, each including a first terminal (e.g., a gate terminal), a second terminal (e.g., a drain terminal), and a third terminal (e.g., a source terminal), the first terminal of the first transistor of the pair of cross-coupled transistors is coupled to the second terminal of the second transistor of the pair of cross-coupled transistors, the first terminal of the second transistor of the pair of cross-coupled transistors is coupled to the second terminal of the first transistor of the pair of cross-coupled transistors, the third terminal of each of the first transistor of the pair of cross-coupled transistors and the second transistor of the pair of cross-coupled transistors is coupled to a reference voltage, and a value of the reference voltage corresponds to (e.g., is substantially equal to) the high voltage in the level-shifted input clock signal.

[0154] Example 7 provides the switch driver circuit according to any one of Examples 4 to 6, wherein the first transistor is an N-type transistor and the second transistor is a P-type transistor.

[0155] Example 8 provides the switch driver circuit according to any one of Examples 4 to 6, wherein the level shifter circuit is a first level shifter circuit, the switch driver circuit further includes a second level shifter circuit, and the second level shifter circuit is configured to control a low voltage level in the output clock signal.

[0156] Example 9 provides the switch driver circuit according to Example 3, wherein the voltage controller circuit is configured to control a low voltage value in the level-shifted input clock signal. This voltage controller circuit may be referred to as a "minimum level controller" because it sets a minimum voltage value of the level-shifted input clock signal. A maximum voltage value is then automatically adjusted based on a ratio between a capacitance of the coupling capacitor and a capacitance of a load for the voltage controller circuit.

[0157] Example 10 provides the switch driver circuit according to Example 9, wherein a third terminal of the second transistor is coupled to a supply voltage, and a value of the supply voltage corresponds to (e.g., is substantially equal to) the low voltage in the level-shifted input clock signal.

[0158] Example 11 provides a switch driver circuit according to Example 9 or 10, wherein the voltage controller circuit includes a pair of cross-coupled transistors, each of which includes a first terminal (e.g., a gate terminal), a second terminal (e.g., a drain terminal), and a third terminal (e.g., a source terminal). The first terminal of the first transistor of the pair of cross-coupled transistors is coupled to the second terminal of the second transistor of the pair of cross-coupled transistors, the first terminal of the second transistor of the pair of cross-coupled transistors is coupled to the second terminal of the first transistor of the pair of cross-coupled transistors, the third terminal of each of the first transistor of the pair of cross-coupled transistors and the second transistor of the pair of cross-coupled transistors is coupled to a supply voltage, and the value of the supply voltage corresponds to (e.g., is substantially equal to) the low voltage in the level-shifted input clock signal.

[0159] Example 12 provides a switch driver circuit according to any one of Examples 9 to 11, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0160] Example 13 provides a switch driver circuit according to any one of Examples 9 to 12, wherein the level shifter circuit is a first level shifter circuit, the switch driver circuit further includes a second level shifter circuit, and the second level shifter circuit is configured to control the high voltage level in the output clock signal.

[0161] Example 14 provides a switch driver circuit according to any one of the foregoing examples, which further includes a third transistor coupled to the first transistor in a cascode arrangement, wherein the second terminal of the first transistor is coupled to the output by coupling the second terminal of the first transistor to the third terminal (e.g., the source terminal) of the third transistor and coupling the second terminal (e.g., the drain terminal) of the third transistor to the output.

[0162] In various embodiments, the first terminal (e.g., the gate terminal) of the third transistor may be coupled to a suitable reference voltage. For example, for an embodiment in which the third transistor is an N-type transistor, the reference voltage may be approximately 1V, or for an embodiment in which the third transistor is a P-type transistor, the reference voltage may be approximately 0V (ground).

[0163] Example 15 provides a switch driver circuit according to any one of the foregoing examples, wherein each of the first transistor and the second transistor is a field effect transistor, and wherein the first terminal is a gate terminal, the second terminal is a drain terminal, and the third terminal is a source terminal.

[0164] Example 16 provides a switching driver circuit, which includes: a first branch including a first transistor (e.g., transistor m5 shown in the drawings of the present disclosure); and a second branch including a second transistor (e.g., transistor m6 shown in the drawings of the present disclosure) and a level shifter circuit. An input clock signal is split between the first branch and the second branch such that a signal indicative of a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level shifted by the level shifter circuit to generate a level-shifted input clock signal and a signal indicative of the level-shifted input clock signal is provided to the second transistor. One of the first transistor and the second transistor is an N-type transistor and the other is a P-type transistor. The output of the first transistor is combined with the output of the second transistor to generate an output clock signal.

[0165] Example 17 provides the switching driver circuit according to Example 16, wherein each of the first transistor and the second transistor includes a first terminal (e.g., a gate terminal), a second terminal (e.g., a drain terminal), and a third terminal (e.g., a source terminal), the signal indicative of the portion of the input clock signal split to the first branch is provided to the first terminal of the first transistor, and the signal indicative of the level-shifted input clock signal is provided to the first terminal of the second transistor.

[0166] Example 18 provides the switching driver circuit according to Example 17, wherein the level shifter circuit includes a capacitor and a voltage control circuit, a portion of the input clock signal split to the second branch is configured to be applied to a first capacitor electrode of the capacitor, and a second capacitor electrode of the capacitor is coupled to each of an output of the voltage control circuit and the first terminal of the second transistor.

[0167] Example 19 provides the switching driver circuit according to Example 17 or 18, wherein the second terminal of the first transistor is coupled to the second terminal of the second transistor, the third terminal of the first transistor is coupled to a first supply voltage, and the third terminal of the second transistor is coupled to a second supply voltage.

[0168] Example 20 provides a method of fabricating a switch driver circuit, the method comprising: providing an input configured to receive an input clock signal; providing an output configured to provide an output clock signal; providing a first transistor (e.g., transistor m5 as shown in the figures of the present disclosure); providing a second transistor (e.g., transistor m6 as shown in the figures of the present disclosure), wherein each of the first transistor and the second transistor includes a first terminal (e.g., a gate terminal) and a second terminal (e.g., a drain terminal), and wherein one of the first transistor and the second transistor is a P-type transistor (e.g., a PMOS transistor) and the other is an N-type transistor (e.g., an NMOS transistor); and providing a level shifter circuit configured to level shift the input clock signal to produce a level-shifted input clock signal, wherein the first terminal of the first transistor is configured to receive a signal indicative of the input clock signal, the first terminal of the second transistor is configured to receive a signal indicative of the level-shifted input clock signal, and each of the second terminals of the first transistor and the second transistor is coupled to the output (i.e., the second terminal of the first transistor is coupled to the second terminal of the second transistor, and both are coupled to the output).

[0169] Example 21 provides the method according to Example 20, wherein the switch driver circuit is the switch driver circuit according to any one of Examples 1 to 19.

[0170] Variations and Implementations

[0171] Although the embodiments of the present disclosure have been described above with reference to exemplary embodiments as shown in Figures 1 to 16 , those skilled in the art will recognize that the various teachings described above apply to a wide variety of other embodiments.

[0172] In the discussion of the above embodiments, components of the system, such as, for example, inverters, resistors, transistors, and / or other components, can be readily replaced, substituted, or otherwise modified to accommodate the requirements of a particular circuit system. Also, it should be noted that the use of complementary electronics, hardware, software, etc. provides equally viable options for implementing the teachings of the present disclosure related to implementing one or more boost switch drivers.

[0173] Components of various systems for implementing one or more boost switch drivers as presented herein may include electronic circuitry that performs the functions described herein. In some instances, one or more components of the system may be provided by a processor specifically configured to perform the functions described herein. For example, the processor may include one or more application-specific components, or may include programmable logic gates configured to perform the functions described herein. The circuitry may operate in the analog domain, digital domain, or mixed-signal domain. In some examples, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer-readable storage medium.

[0174] In some embodiments, any number of the circuits of the figures may be implemented on a board of the associated electronic device. The board may be a general-purpose circuit board that may hold various components of the internal electronic system of the electronic device and may further provide connectors for other peripheral devices. More specifically, the board may provide electrical connections through which other components of the system may communicate electrically. Any suitable processor (including DSPs, microprocessors, support chipsets, etc.), computer-readable non-transitory memory elements, etc. may be suitably coupled to the board based on configuration requirements, processing commands, computer design, etc. Other components such as external storage devices, additional sensors, controllers for audio / video displays, and peripheral devices may be attached to the board as plug-in cards via cables or integrated into the board itself. In various embodiments, the functionality described herein may be implemented in emulation form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structure that supports those functions. The software or firmware providing the emulation may be provided on a non-transitory computer-readable storage medium that includes instructions that allow a processor to implement those functions.

[0175] In some embodiments, the circuits of the figures may be implemented as a stand-alone module (e.g., a device having associated components and circuitry configured to perform a particular application or function) or as an insertion module into application-specific hardware of an electronic device. It should be noted that embodiments of the present disclosure may be readily incorporated, in part or in whole, in a system-on-chip (SOC) package. An SOC represents an IC that integrates the components of a computer or other electronic system onto a single chip. It may contain digital, analog, mixed-signal, and typically RF functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), where multiple individual ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package.

[0176] All specifications, dimensions, and relationships outlined herein (e.g., the number of components or portions thereof of the boost switch driver shown in the figures) are provided for illustrative and teaching purposes only. Such information may vary considerably without departing from the spirit of the present disclosure or the scope of the appended claims. The specifications apply to only one non-limiting example and are thus to be construed accordingly. In the foregoing description, example embodiments have been described with reference to processors and / or component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

[0177] Note that for the numerous examples provided herein, interactions may be described in terms of two, three, four, or more electrical components. However, this is done for clarity and illustrative purposes only. It should be understood that the system may be combined in any suitable manner. In accordance with similar design alternatives, any of the components, modules, and elements shown in the figures may be combined in various possible configurations, all of which are clearly within the broad scope of the present disclosure. In some cases, it may be easier to describe one or more of the functionality of a given set of processes by referring only to a limited number of electrical elements. It should be understood that the circuits of the figures and their teachings can be readily extended and can accommodate many components, as well as more complex or sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope of the circuits or inhibit the broad teachings of the circuits, as they may be applied to countless other architectures.

[0178] Furthermore, the functions associated with implementing one or more boost switch drivers as presented herein illustrate only some of the possible functions that may be performed by or within the systems shown in the figures. Some of these operations may be deleted or removed where appropriate, or may be substantially modified or changed without departing from the scope of the present disclosure. Additionally, the timing of these operations may vary considerably. The foregoing operational flows have been provided for example and discussion purposes. The embodiments described herein provide significant flexibility, as any suitable arrangement, schedule, configuration, and timing mechanism may be provided without departing from the teachings of the present disclosure.

[0179] Note that all optional features of the devices described above may also be implemented with respect to the methods or processes described herein, and the details of the examples may be used anywhere in one or more of the embodiments.

[0180] Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to those skilled in the art, and the present disclosure is intended to embrace all such changes, substitutions, variations, alterations, and modifications that fall within the scope of the appended claims.

Claims

1. A switching driver circuit, comprising: Input, for receiving an input clock signal; Output, for providing an output clock signal; A first transistor and a second transistor, each including a first terminal and a second terminal; A third transistor, coupled to the first transistor in a cascode arrangement; And A level shifter circuit, for level shifting the input clock signal to generate a level-shifted input clock signal, Wherein: The first terminal of the first transistor is for receiving a signal indicating the input clock signal, The first terminal of the second transistor is for receiving a signal indicating the level-shifted input clock signal, The second terminal of the first transistor is coupled to the third terminal of the third transistor, and the second terminal of the third transistor is coupled to the output, and The second terminal of the second transistor is coupled to the output.

2. The switching driver circuit according to claim 1, wherein: The input clock signal has a low voltage value and a high voltage value, and Level shifting the input clock signal includes the level shifter circuit changing each of the low voltage value and the high voltage value of the input clock signal to generate the level-shifted input clock signal.

3. The switching driver circuit according to claim 1, wherein: The level shifter circuit includes a coupling capacitor and a voltage controller circuit, and the first terminal of the second transistor is for receiving a signal indicating the level-shifted input clock signal by coupling to the input through a first capacitor electrode and to each of the voltage controller circuit and the first terminal of the second transistor.

4. The switching driver circuit according to claim 3, wherein: The voltage controller circuit is for controlling the high voltage value of the level-shifted input clock signal.

5. The switching driver circuit according to claim 4, wherein: The voltage controller circuit includes a pair of cross-coupled transistors, each transistor including a first terminal, a second terminal, and a third terminal, The first terminal of the first transistor in the pair of cross-coupled transistors is coupled to the second terminal of the second transistor in the pair of cross-coupled transistors, The first terminal of the second transistor in the pair of cross-coupled transistors is coupled to the second terminal of the first transistor in the pair of cross-coupled transistors, The third terminal of each of the first transistor in the pair of cross-coupled transistors and the second transistor in the pair of cross-coupled transistors is coupled to a reference voltage, and The value of the reference voltage corresponds to the high voltage of the level-shifted input clock signal.

6. The switching driver circuit according to claim 4, wherein: The first transistor is an N-type transistor and the second transistor is a P-type transistor.

7. The switching driver circuit according to claim 4, wherein: The level shifter circuit is a first level shifter circuit, The switch driver circuit further includes a second level shifter circuit, and The second level shifter circuit is for controlling the low voltage level of the output clock signal.

8. The switching driver circuit according to claim 3, wherein: The voltage controller circuit is for controlling the low voltage value of the level-shifted input clock signal.

9. The switching driver circuit according to claim 8, wherein: The voltage controller circuit includes a pair of cross-coupled transistors, each transistor including a first terminal, a second terminal, and a third terminal, The first terminal of the first transistor in the pair of cross-coupled transistors is coupled to the second terminal of the second transistor in the pair of cross-coupled transistors, The first terminal of the second transistor in the pair of cross-coupled transistors is coupled to the second terminal of the first transistor in the pair of cross-coupled transistors, the third terminal of each of the first transistor in the pair of cross-coupled transistors and the second transistor in the pair of cross-coupled transistors is coupled to a reference voltage, and the value of the reference voltage corresponds to the low voltage of the level-shifted input clock signal.

10. The switching driver circuit according to claim 8, wherein: The first transistor is a P-type transistor and the second transistor is an N-type transistor.

11. The switching driver circuit according to claim 1, wherein: Each of the first transistor and the second transistor is a field-effect transistor, and wherein the first terminal is a gate terminal, the second terminal is a drain terminal, and the third terminal is a source terminal.

12. The switching driver circuit according to claim 4, wherein: The third terminal of the second transistor is coupled to a supply voltage, and the value of the supply voltage corresponds to the high voltage of the level-shifted input clock signal.

13. The switching driver circuit according to claim 8, wherein: The third terminal of the second transistor is coupled to a supply voltage, and the value of the supply voltage corresponds to the low voltage of the level-shifted input clock signal.

14. The switching driver circuit according to claim 8, wherein: The level shifter circuit is a first level shifter circuit, the switch driver circuit further includes a second level shifter circuit, and the second level shifter circuit is used to control the high voltage level of the output clock signal.

15. A switching driver circuit, comprising: An input for receiving an input clock signal; An output for providing an output clock signal; A first transistor and a second transistor, each including a first terminal and a second terminal; A first level shifter circuit for level-shifting the input clock signal to generate a level-shifted input clock signal; and A second level shifter circuit; wherein: the first terminal of the first transistor is used to receive a signal indicating the input clock signal, the first terminal of the second transistor is used to receive a signal indicating the level-shifted input clock signal, the second terminal of the second transistor is coupled to the second level shifter circuit, each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output, the first level shifter circuit is used to control the low voltage value of the level-shifted input clock signal, and the second level shifter circuit is used to control the high voltage level of the output clock signal.

16. The switching driver circuit according to claim 15, wherein: The level shifter circuit includes a coupling capacitor and a voltage controller circuit, and the first terminal of the second transistor is used to receive a signal indicating the level-shifted input clock signal by coupling to the input through a first capacitor electrode and to each of the voltage controller circuit and the first terminal of the second transistor.

17. The switching driver circuit according to claim 16, wherein: The voltage controller circuit includes a pair of cross-coupled transistors, each transistor including a first terminal, a second terminal, and a third terminal, the first terminal of the first transistor in the pair of cross-coupled transistors is coupled to the second terminal of the second transistor in the pair of cross-coupled transistors, The first terminal of the second transistor in the pair of cross-coupled transistors is coupled to the second terminal of the first transistor in the pair of cross-coupled transistors, the third terminal of each of the first transistor in the pair of cross-coupled transistors and the second transistor in the pair of cross-coupled transistors is coupled to a reference voltage, and the value of the reference voltage corresponds to the low voltage of the level-shifted input clock signal.

18. The switching driver circuit according to claim 15, wherein: The first transistor is a P-type transistor and the second transistor is an N-type transistor.

19. The switching driver circuit according to claim 15, wherein: Each of the first transistor and the second transistor is a field effect transistor, and wherein the first terminal is the gate terminal, the second terminal is the drain terminal, and the third terminal is the source terminal.

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