Clock synchronization method and system for multi-detector system

Abstract

The invention relates to the technical field of data processing, in particular to a clock synchronization method and system for a multi-detector system. According to the scheme, after the detector receives the system clock signal, the synchronous signal in the system clock signal is detected, after the synchronous signal is detected, the synchronous counter in the detector stops timing, and after the periodic clock signal is detected, a new round of synchronous timing is restarted with the periodic clock signal as the reference. According to the scheme, only one cable is needed to transmit the system clock signal, then the synchronizing signal in the system clock signal is detected, clock synchronization of the multiple detectors can be achieved, finally the periodic clock signal is recovered, and the multiple detectors conduct time synchronization through the same periodic clock signal. Therefore, the cost and the pressure of cable arrangement are reduced, delay is avoided, and the measurement precision of the detector is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and particularly relates to a clock synchronization method and system for a multi-detector system. Background Art

[0002] In some multi-detector systems, in order to achieve picosecond-level detector time accuracy and ensure time consistency, it is necessary to align the time of the detectors. Under normal operating conditions, the times of the individual detectors do not correspond, and thus there is a problem of aligning the times, that is, time synchronization.

[0003] In the existing detector clock synchronization scheme in a multi-detector system, generally two sets of cables are used to connect the individual detectors. One set uses single pulses for counter synchronization, and the other set is for reference clock synchronization. Using two sets of cables for clock synchronization will additionally increase the wiring pressure. Summary of the Invention

[0004] The clock synchronization method and system for a multi-detector system provided by the present invention solve the problems of detector time synchronization delay and increased wiring pressure in the existing multi-detector system.

[0005] According to a first aspect, an embodiment provides a clock synchronization method for a multi-detector system, including:

[0006] Multiple detectors of the multi-detector system obtain a system clock signal, where the system clock signal includes a synchronization signal and a periodic clock signal, and the synchronization signal is used to set a synchronization counter in the detector;

[0007] The multiple detectors detect the synchronization signal in the system clock signal;

[0008] After detecting the synchronization signal, the multiple detectors stop synchronization timing and detect the periodic clock signal, and after detecting the periodic clock signal, start a new round of synchronization timing based on the periodic clock signal.

[0009] In an implementable embodiment, the synchronization signal is a synchronization level, and the synchronization level is a high level or a low level. The multiple detectors detecting the synchronization signal in the system clock signal includes:

[0010] Detecting the duration of the inverted level after the falling edge or rising edge in the system clock signal;

[0011] Judging whether the duration of the inverted level exceeds a preset duration. If so, it is determined that the synchronization signal is detected.

[0012] In an implementable embodiment, the periodic clock signal includes a high level and a low level; detecting the periodic clock signal includes:

[0013] Determine whether the synchronization level of the synchronization signal has returned to the inverted level. If so, it is determined that a periodic clock signal has been detected.

[0014] In an implementable embodiment, the low level is inverted to the high level through a rising edge, and the high level is inverted to the low level through a falling edge; a timer for judging the synchronization signal is arranged in the detector. When the synchronization level of the synchronization signal is detected, the timer exceeds the preset timing; judging whether the synchronization level of the synchronization signal has returned to the inverted level includes:

[0015] Detect the rising edge or falling edge after the synchronization level of the synchronization signal, and judge whether the timer has returned to the preset timing. If so, it is determined that the synchronization level of the synchronization signal has returned to the inverted level corresponding to the synchronization level in the periodic clock signal.

[0016] In an implementable embodiment, after detecting the synchronization signal, it further includes:

[0017] After detecting the nth rising edge or falling edge after the synchronization level of the synchronization signal, n≥1, trigger the synchronization counter in the detector to start a new round of synchronization timing based on the periodic clock signal.

[0018] In an implementable embodiment, starting a new round of synchronization timing based on the periodic clock signal includes:

[0019] After the timer returns to the preset timing, trigger the synchronization counter in the multiple detectors to be set to the preset value, and start synchronization timing based on the preset value according to the periodic clock signal.

[0020] According to a second aspect, an embodiment provides a clock synchronization system for a multi-detector system, including a plurality of detectors, and the detectors include:

[0021] An acquisition module for acquiring a system clock signal, where the system clock signal includes a synchronization signal and a periodic clock signal, and the synchronization signal is used to set a synchronization counter in the detector;

[0022] A detection module for detecting the synchronization signal in the system clock signal;

[0023] A synchronization processing module for stopping synchronization timing and detecting the periodic clock signal after detecting the synchronization signal, and starting a new round of synchronization timing based on the periodic clock signal after detecting the periodic clock signal.

[0024] In an implementable embodiment, the multi-detector system further includes a system clock module, which is configured to generate a system clock signal according to the system clock and output it to the multiple detectors.

[0025] According to a third aspect, an embodiment provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the above method is implemented.

[0026] According to a fourth aspect, an embodiment provides a computer-readable storage medium, on which a program is stored, and the program can be executed by a processor to implement the above method.

[0027] According to the clock synchronization method / system for a multi-detector system in the above embodiment, in the multi-detector system, a system clock signal is uniformly sent to multiple detectors by a clock generator, where the system clock signal includes a synchronization signal and a periodic clock signal. After receiving the system clock signal, the detector detects the synchronization signal therein. When the synchronization signal is detected, the synchronization counter in the detector stops timing until the periodic clock signal is detected, and then a new round of synchronization timing starts based on the periodic clock signal. By adopting the above solution of the present application, only one cable is needed to transmit the system clock signal, and then the synchronization signal in the system clock signal is detected, so as to achieve clock synchronization of multiple detectors, and finally the periodic clock signal is restored, enabling multiple detectors to perform time synchronization with the same periodic clock signal. In this way, the cost and pressure of arranging cables are reduced, delay is avoided, and thus the measurement accuracy of the detectors is improved. Description of the Drawings

[0028] Figure 1 It is a flowchart of the clock synchronization method for a multi-detector system provided in this embodiment;

[0029] Figure 2 It is a flowchart of detecting the synchronization signal in the system clock signal provided in this embodiment;

[0030] Figure 3 It is a signal diagram of the system clock signal provided in this embodiment;

[0031] Figure 4 It is a schematic diagram of the clock synchronization method for a multi-detector system provided in this embodiment;

[0032] Figure 5 It is a structural block diagram of a clock synchronization system for a multi-detector system provided in this embodiment;

[0033] Figure 6Another structural block diagram of the clock synchronization system for a multi-detector system provided in this embodiment.

[0034] Reference numerals: 10, synchronization signal; 20, periodic clock signal; 21, low level; 22, high level; 30, acquisition module; 40, detection module; 50, synchronization processing module; 60, system clock module. Detailed implementation manners

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings through specific implementation manners. Similar elements in different implementation manners are labeled with related similar element numbers. In the following implementation manners, many detailed descriptions are provided to enable a better understanding of the present application. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification to avoid overwhelming the core part of the present application with excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the descriptions in the specification and general technical knowledge in the art.

[0036] In addition, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various implementation manners. At the same time, the steps or actions in the method descriptions can also be reordered or adjusted in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for clearly describing a certain embodiment and do not mean that they are necessary sequences, unless it is stated that a certain sequence must be followed.

[0037] The serial numbers assigned to the components in this article, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meanings. And the "connection" and "coupling" mentioned in this application, unless otherwise specified, both include direct and indirect connections (couplings).

[0038] In a multi-detector system, it is necessary to use detectors to mark the time when data is received, and to determine the specific location where an event occurs through the time difference. Generally, this time difference is on the picosecond level. Therefore, there are high requirements for the accuracy of detector time synchronization. For example, in a PET system, radioactive glucose is injected into the human body. Because tumors have a relatively fast metabolism, the radioactive glucose will accumulate at the tumor site. When these radioactive elements decay, they emit two photons that are exactly opposite in direction. After the detectors detect the two photons, they can determine on which straight line this element decayed by connecting the lines. Each detector can obtain the time when the element decay occurs, and then the specific position on this line can be calculated through the speed of light and the time difference. If the detectors are not time-synchronized, the time analysis between the detectors will be inaccurate, and it will be even more impossible to infer the distance through the time difference. Therefore, this application proposes a clock synchronization method for a multi-detector system, which can effectively reduce the problem of time delay between detectors and reduce the wiring pressure.

[0039] Combined with Figure 1 As shown, a clock synchronization method for a multi-detector system provided in this embodiment includes the following steps:

[0040] Step 100: Multiple detectors of the multi-detector system obtain a system clock signal. The system clock signal includes a synchronization signal 10 and a periodic clock signal 20. The synchronization signal 10 is used to set a synchronization counter in the detector.

[0041] Specifically, when it is necessary to synchronize the time of multiple detectors of the multi-detector system, a system clock signal is transmitted to the detectors. Among them, the system clock signal is as Figure 3 shown. One or more synchronization signals 10 are interspersed among multiple periodic clock signals 20. The synchronization signal 10 is a synchronization level. Specifically, the synchronization level can be a high level 22 or a low level 21. When the synchronization level is the low level 21, the duration of the low level 21 of the synchronization signal 10 is greater than the duration of the low level 21 of one period of the periodic clock signal 20; when the synchronization level is the high level 22, the duration of the high level 22 of the synchronization signal 10 is greater than the duration of the high level 22 of one period of the periodic clock signal 20.

[0042] Step 200: Multiple detectors detect the synchronization signal 10 in the system clock signal. In practical applications, each detector in the multi-detector system needs to detect the synchronization signal 10 in the system clock signal respectively. Of course, it can also be that the detectors in use detect the synchronization signal 10 in the system clock signal respectively.

[0043] Refer to Figure 2 , the detection of the synchronization signal 10 is specifically implemented through the following method:

[0044] Step 201: Detect the duration of the inverted level after the falling edge or rising edge in the system clock signal.

[0045] In practical applications, detect the duration of the inverted level after the falling edge in the system clock signal, or detect the duration of the inverted level after the rising edge in the system clock signal. Specifically, for example, if the system clock signal is at a high level 22 at the current moment, then detect the duration of the adjacent low level 21 after the falling edge of the high level 22; similarly, if the system clock signal is at a low level 21 at the current moment, then detect the duration of the adjacent high level 22 after the rising edge of the low level 21.

[0046] Step 202: Determine whether the duration of the inverted level exceeds a preset duration. If so, it is determined that the synchronization signal 10 is detected; otherwise, the synchronization signal 10 is not detected.

[0047] As Figure 3 shown, the system clock signal is a plurality of periodic clock signals 20 interspersed with a synchronization signal 10. Specifically, in the periodic clock signal 20, the clock signal within one period is: it transitions from the rising edge to the high level 22, the high level 22 lasts for a certain duration, then it transitions from the falling edge to the low level 21, and the low level 21 lasts for a certain duration. Among them, in the periodic clock signal 20, the duration of the high level 22 and the duration of the low level 21 can be the same or different.

[0048] Since the synchronization signal 10 is a synchronization level, the synchronization level can be the high level 22 or the low level 21. When the synchronization level is the low level 21, the duration of the low level 21 of the synchronization signal 10 is greater than the duration of the low level 21 in one period of the periodic clock signal 20; at this time, the detector only needs to detect this low level 21. When it is detected that the duration of this low level 21 exceeds the preset duration, it is determined that the synchronization signal 10 is detected; otherwise, the synchronization signal 10 is not detected.

[0049] Similarly, when the synchronization level is the high level 22, the duration of the high level 22 of the synchronization signal 10 is greater than the duration of the high level 22 in one period of the periodic clock signal 20; at this time, the detector only needs to detect this high level 22. When it is detected that the duration of this high level 22 exceeds the preset duration, it is determined that the synchronization signal 10 is detected; otherwise, the synchronization signal 10 is not detected.

[0050] Step 300: After multiple detectors detect the synchronization signal 10, stop the synchronization timing and detect the periodic clock signal 20. After detecting the periodic clock signal 20, start a new round of synchronization timing based on the periodic clock signal 20.

[0051] After detecting the synchronization signal 10, the synchronization counter in the detector stops the synchronization timing. When the periodic clock signal 20 starts to be restored after detecting the end of the synchronization signal 10, the synchronization counter in the detector restarts a new round of synchronization timing with a set value. This set value can be 0 or any other positive integer.

[0052] In the clock synchronization method of this embodiment, after all detectors receive the system clock signal sent by the system, the synchronization signal 10 among them is detected. When the synchronization signal 10 is detected, the synchronization counter in the detector stops timing until the periodic clock signal 20 is detected, and then a new round of synchronization timing is restarted based on the periodic clock signal 20. By adopting the above solution of the present application, only a group of cables are needed to transmit the system clock signal, and then the synchronization signal 10 in the system clock signal is detected, so as to achieve clock synchronization of multiple detectors, and finally the periodic clock signal 20 is restored, so that multiple detectors perform time synchronization with the same periodic clock signal 20. In this way, the cost and pressure of arranging cables are reduced, delays are avoided, and thus the measurement accuracy of the detectors is improved.

[0053] In addition, the solution of the present application only uses a group of cables to transmit the system clock signal, and distributes the system clock signal to each detector for time synchronization of each detector in the multi-detector system. By providing a clock with a fixed frequency, it is ensured that each detector counts according to a unified reference, that is, the time error between each detector is a definite value and does not include cumulative error; and at the same time, the synchronization signal 10 is provided, which can ensure that each detector can start counting with an acceptable starting error.

[0054] In this embodiment, the periodic clock signal 20 is a high level 22 and a low level 21; detecting the periodic clock signal 20 specifically includes: determining whether the synchronization level of the synchronization signal 10 has returned to the inverted level. If so, it is determined that the periodic clock signal 20 is detected.

[0055] Specifically, after detecting the synchronization signal 10, to start synchronization timing among the detectors, it is necessary to detect the periodic clock signal 20. In this embodiment, the method for detecting the periodic clock signal 20 is that when the synchronization level of the synchronization signal 10 is the low level 21, by determining whether the low level 21 of the synchronization signal 10 has returned to the high level 22, if it is determined that it has returned to the high level 22, then it is determined that the periodic clock signal 20 is detected, and then the detector will be triggered to start a new round of synchronization timing. Similarly, when the synchronization level of the synchronization signal 10 is the high level 22, by determining whether the high level 22 of the synchronization signal 10 has returned to the low level 21, if it is determined that it has returned to the low level 21, then it is determined that the periodic clock signal 20 is detected, and then the detector will be triggered to start a new round of synchronization timing.

[0056] Regarding how to determine whether the synchronization level of the synchronization signal 10 has been restored to the inverted level corresponding to this synchronization level in the periodic clock signal 20, it is as follows:

[0057] In this embodiment, the low level 21 is converted to the high level 22 through the rising edge, and the high level 22 is converted to the low level 21 through the falling edge; a timer for determining the synchronization signal 10 is provided in the detector. When the synchronization level of the synchronization signal 10 is detected, the timer exceeds the preset timing (i.e., times out); determining whether the low level 21 of the synchronization signal 10 has been restored to the high level 22 specifically includes: detecting the rising edge or falling edge after the synchronization level of the synchronization signal 10, and determining whether the timer has restored the preset timing. If so, it is determined that the synchronization level of the synchronization signal 10 has been restored to the inverted level corresponding to this synchronization level in the periodic clock signal 20.

[0058] A timer is provided in each detector, and the timer is used for local timing of the system clock signal received by the detector. Specifically, taking the synchronization level of the synchronization signal 10 as the low level 21 as an example for illustration, as Figure 4 shown, the timer performs timing on the periodic clock signal 20 in the system clock signal according to a periodic rule. The timer can be positive timing (such as: 0, 1, 2, 3;...; 0, 1, 2, 3). When the synchronization signal 10 is detected, the timer overflows (such as showing: 4, 5----). Or, the timer can be countdown timing (such as: 5, 4, 3, 2;...; 5, 4, 3, 2). When the synchronization signal 10 is detected, the timer times out (such as showing: 1, 0----). When the situation of timer overflow or timeout occurs, it indicates that the synchronization signal 10 has been detected. Among them, in the normal periodic clock signal 20, every time a rising edge is detected, the timer will be reset (reset to the timing value). When the timer times out, it is considered that the synchronization signal has been detected. When the timer returns to zero and a rising edge is detected again, it is determined that the periodic clock signal 20 starts to return to normal, and at the same time the timer is also reset.

[0059] As a further improvement of this embodiment, after the synchronization signal 10 is detected, it further includes: after detecting the nth rising edge or falling edge after the synchronization level of the synchronization signal 10, n≥1, triggering the synchronization counter in the detector to start a new round of synchronization timing based on the periodic clock signal.

[0060] In this embodiment, metastability may occur when the synchronous counter restarts timing, which may cause the counter times for releasing the synchronization signal 10 to be inconsistent, and further cause clock synchronization delay. To ensure that metastability does not occur when the synchronous counter restarts timing, it is necessary to stagger the time of triggering the rising edge sampling at this time. Specifically, taking the low level 21 of the synchronization signal 10 as an example, the timer is triggered to set the synchronous counter to a preset value after the nth rising edge after the end of the detection of the low level 21 of the synchronization signal 10. Generally, the value of n does not exceed 5, and it is necessary to ensure that the above logic implementation should be completed within several synchronization cycles to reduce the error caused by the frequency difference between the system clock module 60 and the local clock in the detector.

[0061] In this embodiment, a new round of synchronous timing starts based on the periodic clock signal 20, specifically including:

[0062] After the timer resumes the preset timing, it triggers the synchronous counters in multiple detectors to be set to the preset value, and starts synchronous timing based on the preset value according to the periodic clock signal 20.

[0063] Taking the low level 21 of the synchronization signal 10 as an example, since multiple detectors receive the same system clock signal synchronously, each detector also detects the synchronization signal 10 simultaneously. When the duration of the synchronization signal 10 exceeds the preset value, it will overflow or time out. After receiving the signal of the timer overflow or timeout, the synchronous counter enters the pre-synchronization state, uniformly jumps to the set value, and after detecting the rising edge, releases the synchronous counter, so that it starts to synchronously time again from the set value based on the periodic clock signal 20 after the rising edge. The synchronous counter is used to timestamp the data obtained by each detector for data analysis. Only when the timing of all detectors is synchronized can the accuracy of data analysis be guaranteed.

[0064] As Figure 4 shown, a clock synchronization system for a multi-detector system provided in this embodiment includes multiple detectors, and each detector includes an acquisition module 30, a detection module 40, and a synchronization processing module 50. Among them, the acquisition module 30 is used to acquire the system clock signal, and the system clock signal includes a synchronization signal 10 and a periodic clock signal 20. The synchronization signal 10 is used to set the synchronous counter in the detector; the detection module 40 is used to detect the synchronization signal 10 in the system clock signal; the synchronization processing module 50 is used to stop synchronous timing and detect the periodic clock signal 20 after detecting the synchronization signal 10, and after detecting the periodic clock signal 20, start a new round of synchronous timing based on the periodic clock signal 20.

[0065] The detector in the clock synchronization system of this embodiment obtains the system clock signal through the acquisition module 30, then detects the synchronization signal 10 in the system clock signal through the detection module 40. After detecting the synchronization signal 10, it stops the synchronization timing of the synchronization counter in the detector through the synchronization processing module 50 and detects the periodic clock signal 20. After detecting the periodic clock signal 20, a new round of synchronization timing starts based on the periodic clock signal 20. Specifically, the functions and specific implementation manners of each module have been elaborated in detail in the above method embodiment, and this embodiment will not be elaborated too much here.

[0066] As a further improvement of this embodiment, as Figure 5 shown, the multi-detector system of this application further includes a system clock module 60, and the system clock module 60 is used to generate a system clock signal according to the system clock and output it to multiple detectors.

[0067] Specifically, the system clock module 60 is composed of a clock generator and a clock selector. Under normal circumstances, the reference periodic clock signal 20 is transmitted through the clock generator for the internal phase-locked loop to generate the clock for counting. Among them, the phase-locked loop, that is, the loop that locks the phase, is a typical feedback control circuit that uses the externally input reference signal to control the frequency and phase of the oscillation signal inside the loop, realizes the automatic tracking of the output signal frequency to the input signal frequency, and is generally used in the closed-loop tracking circuit. When time synchronization of each detector is required, the clock selector is controlled to the signal sent by the clock generator, so that the clock generator sends the system clock signal containing the synchronization signal 10 and the periodic clock signal 20 to each detector.

[0068] An embodiment provided in this embodiment provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the above method is implemented. Since the clock synchronization method for the multi-detector system has been elaborated in detail in the above embodiment, this embodiment will not be elaborated too much here.

[0069] A computer-readable storage medium provided in this embodiment has a program stored on the medium, and the program can be executed by the processor to implement the above method. Since the clock synchronization method for the multi-detector system has been elaborated in detail in the above embodiment, this embodiment will not be elaborated too much here.

[0070] Those skilled in the art can understand that all or part of the functions of the various methods in the above embodiments can be implemented in a hardware manner or in a computer program manner. When all or part of the functions in the above embodiments are implemented in a computer program manner, the program can be stored in a computer-readable storage medium, and the storage medium can include: read-only memory, random access memory, magnetic disk, optical disk, hard disk, etc. The above functions can be realized by a computer executing the program. For example, the program is stored in the memory of the device, and when the processor executes the program in the memory, the above all or part of the functions can be realized. In addition, when all or part of the functions in the above embodiments are implemented in a computer program manner, the program can also be stored in a storage medium such as a server, another computer, magnetic disk, optical disk, flash drive or mobile hard disk, and saved to the memory of the local device by downloading or copying, or the system of the local device is updated. When the processor executes the program in the memory, all or part of the functions in the above embodiments can be realized.

[0071] The above uses specific examples to elaborate on the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art of the present invention, according to the idea of the present invention, several simple deductions, deformations or substitutions can also be made.

Claims

1. A clock synchronization method for a multi-detector system, characterized in that: include: The multiple detectors of the multi-detector system acquire a system clock signal, the system clock signal includes a synchronization signal and a periodic clock signal, and the synchronization signal is used to set a synchronization counter in the detector; The plurality of detectors detect synchronization signals in the system clock signal; After detecting the synchronization signal, the multiple detectors stop synchronization timing and detect the periodic clock signal. After detecting the periodic clock signal, a new round of synchronization timing is started based on the periodic clock signal.

2. The clock synchronization method for a multi-detector system according to claim 1, characterized in that: The synchronization signal is a synchronization level, and the synchronization level is a high level or a low level. The multiple detectors detect the synchronization signal in the system clock signal, including: Detecting the duration of the inversion level after the falling edge or the rising edge of the system clock signal; It is determined whether the duration of the inversion level exceeds a preset duration, and if so, it is determined that a synchronization signal is detected.

3. The clock synchronization method for a multi-detector system according to claim 2, characterized in that: The periodic clock signal includes a high level and a low level; and detecting the periodic clock signal includes: It is determined whether the synchronization level of the synchronization signal is restored to the inversion level, and if so, it is determined that a periodic clock signal is detected.

4. The clock synchronization method for a multi-detector system according to claim 3, characterized in that: The low level is inverted to the high level through the rising edge, and the high level is inverted to the low level through the falling edge; a timer for judging the synchronization signal is provided in the detector, and when the synchronization level of the synchronization signal is detected, the timer exceeds the preset timing; the judging whether the synchronization level of the synchronization signal is restored to the inverted level includes: Detect the rising edge or falling edge after the synchronization level of the synchronization signal to determine whether the timer has restored the preset timing. If so, determine that the synchronization level of the synchronization signal has been restored to the inversion level corresponding to the synchronization level in the periodic clock signal.

5. The clock synchronization method for a multi-detector system according to claim 4, characterized in that: After detecting the synchronization signal, the method further comprises: After detecting the nth rising edge or falling edge after the synchronization level of the synchronization signal, where n≥1, the synchronization counter in the detector is triggered to start a new round of synchronization timing based on the periodic clock signal.

6. The clock synchronization method for a multi-detector system according to claim 4, characterized in that: The starting of a new round of synchronous timing based on the periodic clock signal comprises: After the timer resumes the preset timing, the synchronous counters in the plurality of detectors are triggered to be set to a preset value, and synchronous timing is started based on the preset value according to the periodic clock signal.

7. A clock synchronization system for a multi-detector system, comprising a plurality of detectors, characterized in that: The detector comprises: An acquisition module, used for acquiring a system clock signal, wherein the system clock signal includes a synchronization signal and a periodic clock signal, and the synchronization signal is used for setting a synchronization counter in the detector; A detection module, used for detecting a synchronization signal in the system clock signal; The synchronization processing module is used to stop the synchronization timing and detect the periodic clock signal after detecting the synchronization signal, and after detecting the periodic clock signal, start a new round of synchronization timing based on the periodic clock signal.

8. The clock synchronization system for a multi-detector system according to claim 7, characterized in that: The multi-detector system further comprises a system clock module, which is used to generate a system clock signal according to a system clock and output the system clock signal to the multiple detectors.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium, characterized in that: The medium stores a program, which can be executed by a processor to implement the method according to any one of claims 1 to 6.

Images