Power reduction in handling physical layers of wireless systems

Abstract

The invention relates to power reduction in processing a physical layer of a wireless system. A system includes a controller configured to receive cellular configuration data and network traffic data. The cellular configuration data is associated with a plurality of cells within the wireless network. The system includes an on-chip shared memory configured into a plurality of memory bank groups based on cellular configuration data. Each memory bank group includes a number of memory banks. A first subset of the group of memory banks is associated with an uplink slot. A second subset of the group of memory banks is associated with a downlink slot. In response to the network traffic data being associated with the downlink slot, the first subset of memory bank groups associated with the uplink slot is clocked off. In response to the network traffic data being associated with the uplink slot, a second subset of the memory bank groups associated with the downlink slot is clocked off.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 610,988, filed on December 15, 2023, the entire content of which is incorporated herein by reference. BACKGROUND OF THE DISCLOSURE

[0003] Although the power consumption of a smart phone is critical to the success of a wireless network due to the limited power of the battery, the power consumption of base stations in a wireless network (such as 4G) is generally overlooked and very little effort has been made to reduce it. However, since the emergence of 5G wireless communication systems, the power consumption of base stations has increased significantly for several different reasons, including that 5G wireless communication systems use higher frequencies compared to 4G wireless communication systems. In addition, since the higher frequencies of 5G wireless networks make it necessary to significantly increase the number of base stations to provide sufficient coverage due to the mid- to high-frequency band characteristics of the signals, the power consumption has increased since the emergence of 5G wireless communication. For example, compared to 4G wireless communication, approximately three times as many base stations are used in 5G wireless communication to achieve similar coverage. The increase in power consumption results in inefficiencies in the system and leads to higher operating costs.

[0004] The foregoing examples of the prior art and the limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the prior art will become apparent upon reading the specification and studying the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] When read in conjunction with the accompanying Figure 1 drawings, aspects of the present disclosure are best understood from the following detailed description. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 An example of a wireless network in accordance with one aspect of the present embodiment is depicted.

[0007] Figure 2 An example of a base station processing data in accordance with one aspect of the present embodiment is depicted.

[0008] Figures 3A to 3D An example of managing power associated with shared memory in a static configuration of a wireless network in accordance with one aspect of the present embodiment is depicted.

[0009] Figures 4A to 4D An example of managing power associated with shared memory in a dynamic configuration of a wireless network in accordance with one aspect of the present embodiment is depicted.

[0010] Figure 5Depicts an example of a base station with a shared memory for processing data according to an aspect of the present embodiment.

[0011] Figure 6 Depicts an example of a processing unit of a base station in a wireless network according to an aspect of the present embodiment.

[0012] Figures 7A to 7B Depicts an example of managing the power of a processing unit in a base station that manages a wireless network according to an aspect of the present embodiment.

[0013] Figure 8 Depicts an illustrative flowchart for managing power associated with a shared memory in a processor of a base station according to an aspect of the present embodiment.

[0014] Figure 9 Depicts an illustrative flowchart for managing power associated with a processor of a base station according to an aspect of the present embodiment. Detailed Description

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter. Specific examples of components and devices are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. Additionally, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0016] Before describing the various embodiments in more detail, it should be understood that the embodiments are not limiting since elements in such embodiments may vary. It should also be understood that the elements of the specific embodiments described and / or illustrated herein can be readily separated from the specific embodiments and optionally combined with or substituted for elements in any of several other embodiments. It should also be understood that the terms used herein are for the purpose of describing certain concepts and that the terms are not intended to be limiting. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood in the field to which the embodiments belong.

[0017] In a wireless network (such as 5G), given the significant increase in the number of base stations and their power consumption associated with the increase in signal frequency, it is necessary to reduce the power consumption of the base stations. Reducing the power consumption of base stations in 5G wireless networks (for macrocell, microcell, and / or small cell deployments) results in a reduction in the cost associated with operating such wireless networks.

[0018] According to some embodiments, a 5G wireless network may adapt a virtual radio access network (RAN) and / or an open radio access network (ORAN) in which higher layer stacks are processed on a cloud server and in which physical (PHY) layer processing is offloaded to hardware components such as a peripheral component interconnect (PCI) card or a PCI express (PCIe). It should be understood that PHY layer processing may be performed simultaneously for multiple cells within a wireless network that interfaces with one or more radio units.

[0019] Generally, PHY layer processing in a wireless network and radio frequency (RF) consume most of the power in a system. For example, it consumes approximately 70% of the consumed power. Therefore, efforts to reduce power consumption associated with PHY layer processing and / or RF in the system will significantly reduce the overall power consumption of the system.

[0020] Resources (e.g., physical resource blocks (PRBs), memory, buffer space, processing resources for signal processing and computational controller workloads such as accelerators and / or digital signal processors (DSPs), etc.) are typically allocated by a base station to a cell in a 5G network, for example, when configuring a specific cell. It should be understood that a 5G wireless network is a dynamic load system and supports a variety of use cases, such as broadband, Internet of Things (IoT), ultra-low latency, etc., where each use case may have its own unique data workflow. Traditionally, resources are allocated based on cell configuration (statically) and independently of the load (traffic cell), resulting in inefficient power consumption. Thus, managing power consumption associated with PHY layer processing based on the load (which can be dynamic) is an effective way to reduce power consumption in PHY layer processing. For example, putting components (e.g., memory components, processors, etc.) into a lower power mode (e.g., sleep mode, clock gating for shutdown, etc.) when not in use can be an effective tool for reducing power consumption.

[0021] A radio frame in a wireless network may be divided into a certain number of subframes, where each subframe may be divided into a certain number of time slots, and each time slot may be used to transmit a certain number of orthogonal frequency division multiplexing (OFDM) symbols (i.e., multiple symbols may be transmitted by one user or multiple symbols may be transmitted by multiple users). For a non-limiting example, in 5G wireless communication, 100 MHz may be used with a 30 KHz subcarrier spacing (SCS), the time slot duration may be 500 μs and may be used to transmit 14 OFDM symbols.

[0022] According to some embodiments, a base station may allocate (by one or more processors, one or more accelerators, and / or one or more DSPs) a certain number of uplink time slots in a shared memory for uplink data, allocate (by one or more processors, one or more accelerators, and / or one or more DSPs) a certain number of downlink time slots in the shared memory for downlink data, and allocate (by one or more processors, one or more accelerators, and / or one or more DSPs) a certain number of flexible (can be allocated to uplink or downlink) time slots in the shared memory. Generally, the allocation of the shared memory for uplink time slots, downlink time slots, or flexible time slots is based on cell configuration. For example, as opposed to upload content, most users are involved in download content, thus, the base station may allocate 7 time slots of the shared memory for downlink, allocate 2 time slots of the shared memory for uplink, and allocate 1 time slot of the shared memory as a flexible time slot. It should be understood that a 5G wireless network may be deployed in a time division duplex (TDD) mode, i.e., transmit or receive on a cell. During downlink, the time slots allocated for uplink consume power even if not being utilized, resulting in inefficient power consumption. Similarly, during uplink, the time slots allocated for downlink consume power even if not being utilized, resulting in inefficient power consumption. In other words, the time slots allocated by the base station based on a load-independent cell configuration (e.g., 7 downlink time slots, 2 uplink time slots, and 1 flexible time slot) result in power waste.

[0023] To manage power consumption and reduce waste, the shared memory (for one or more processors, one or more accelerators, and / or one or more DSPs) used in PHY layer processing may be partitioned into multiple memory banks. A certain number of memory banks may form a group (e.g., a row of memory banks, a column of memory banks, etc.) that can be allocated as uplink time slots, downlink time slots, or flexible time slots. If needed, the memory banks are formed such that the memory banks can be clocked off, thereby reducing power consumption.

[0024] In a non - limiting example, during the uplink, the base station can perform clock gating on unused memory banks (e.g., certain groups of memory banks assigned to the downlink, certain groups of memory banks assigned to the downlink and memory banks assigned to the uplink) based on the load, etc. In a non - limiting example, during the downlink, the base station can perform clock gating on unused memory banks (e.g., certain groups of memory banks assigned to the uplink, certain groups of memory banks assigned to the uplink and memory banks assigned to the downlink) based on the load, etc. In this way, the unused memory banks no longer consume power, thereby reducing the power consumption of the base station, and more particularly, reducing the power consumption of the shared memory used in PHY layer processing.

[0025] In some embodiments, one or more processors (e.g., central processing units (CPUs)) at the base station are used for PHY layer processing. One or more CPUs can process data and assign one or more jobs to one or more hardware accelerators or assign one or more jobs to one or more DSPs. In a conventional system, even during the time when one or more CPUs are not processing any data (e.g., during the time when one or more hardware accelerators are processing one or more jobs, during the time when one or more DSPs are processing one or more jobs, etc.), one or more CPUs remain in their fully - powered - on mode. This results in a waste of power. Thus, according to some embodiments, one or more CPUs transition to a lower - power mode (e.g., sleep mode) after processing is completed (e.g., after assigning jobs to one or more accelerators, after assigning jobs to one or more DSPs, etc.) in order to reduce power consumption. For example, one or more CPUs can be processing data for the duration of 2 symbols to assign jobs to one or more accelerators and / or one or more DSPs, and then transition to a lower - power mode (e.g., sleep mode) during the remaining symbols (e.g., 12 symbols, etc.) within a given time slot that includes 14 symbols. In this way, the power consumption of one or more CPUs is significantly reduced.

[0026] Figure 1 An example of a wireless network 100 according to one aspect of the present embodiment is depicted. Although the figure depicts the components as being functionally separate, such a depiction is for illustrative purposes only. It will be apparent that the components depicted in the figure can be arbitrarily combined or divided into separate software, firmware, and / or hardware components. Additionally, it will also be apparent that such components (however they are combined or divided) can be executed on the same host or multiple hosts, and multiple hosts can be connected via one or more networks.

[0027] The wireless network 100 may include multiple cells, e.g., cells 102, 104, 106, 112, 114, 116, 122, 124, and 126. Each cell may include multiple sub - cells. For example, cell 102 may include two sub - cells, three sub - cells, etc. Each of the cells 102 to 126 is wirelessly coupled to a base station 130. The base station 130 may include one or more servers of the PHY layer for processing data, one or more PCI cards, etc. The wireless network 100 is adapted to a virtual RAN and / or ORAN architecture.

[0028] It should be understood that the base station 130 includes one or more processors to process data and assign jobs to one or more DSPs and / or one or more hardware accelerators. It should be understood that the base station 130 may allocate resources (e.g., time slots) for uplink, downlink, etc. based on cell configuration data (e.g., configuration data associated with cell 102, etc.). For example, the base station 130 may allocate 7 time slots for downlink, 2 time slots for uplink, and 1 time slot as a flexible time slot to cells 102 to 126 based on the configuration data associated with the cells (e.g., received from the cells). The allocated flexible time slot can be dynamically allocated between uplink / downlink as needed. It should be understood that the higher - layer processing associated with the communication between the base station 130 and the cells (e.g., cells 102 to 126) can be offloaded to a cloud server, while the PHY - layer processing can be offloaded to a PCI card.

[0029] Figure 2 An example of a base - station processing data according to an aspect of the present embodiment is depicted. The base station includes a controller 210, a scheduler 220, a DSP 230, an accelerator 240, and a shared memory 250. In one non - limiting example, the controller 210 may include one or more processors, e.g., a CPU. Configuration data 202 associated with a given cell (e.g., cell 102, cell 104, cell 116, etc.) may be received by the controller 210. The controller 210 may configure and allocate resources in the base station based on the configuration data 202 for the cell.

[0030] Figure 2 Each of the components in is a dedicated hardware block / component including one or more processors (e.g., microprocessors) and an on - chip memory unit storing software instructions. When the software instructions are executed by the processor, each of the hardware components becomes a dedicated hardware component for managing power and for executing job commands, as discussed in detail below. In some embodiments, the system as shown in Figure 2 is on a single chip, e.g., is a system - on - chip (SOC).

[0031] The shared memory 250 (e.g., 96 MB) can be broken down into smaller memory banks (e.g., 24 memory banks of 4 MB each). In this non-limiting example, the shared memory 250 can be broken down into multiple memory banks (e.g., memory banks 222A to 222X), where the grouping of memory banks or each individual memory bank can be clock-gated to turn off when not in use, so as to reduce the power consumption of the system. According to one non-limiting example, a certain number of memory banks within the shared memory 250 can be grouped together and assigned to uplink time slots, downlink time slots, or assigned as flexible time slots that can be dynamically assigned to the uplink or downlink as needed. The controller 210 can assign a certain number of memory banks of the shared memory 250 to downlink time slots, assign a certain number of memory banks of the shared memory 250 to uplink time slots, and assign a certain number of memory banks of the shared memory 250 to flexible time slots based on the configuration data 202. The shared memory 250 can be used by one or more of the controller 210, the DSP 230, and the accelerator 240.

[0032] In this example and for illustrative purposes that should not be construed as limiting the scope of the embodiments, the controller 210 can group memory banks 222A to 222F together based on the configuration data 202 and assign them as downlink memory banks 252 to a downlink time slot. In one non-limiting example, the controller 210 can group and assign memory banks 222G to 222L to one uplink time slot based on the configuration data 202, group memory banks 222M to 222R together and assign them to another uplink time slot, and group memory banks 222S to 222X together and assign them to yet another uplink time slot, thus forming uplink memory banks 254. In other words, one row of memory banks from the shared memory 250 is assigned to a downlink time slot, while three rows of memory banks from the shared memory 250 are assigned to three uplink time slots. In this example, no memory banks are assigned to flexible time slots, but in other examples, a certain number of memory banks can be grouped and assigned to flexible time slots. In some examples, 7 groups of memory banks can be formed where each memory bank can be assigned to a downlink time slot, 2 groups of memory banks can be formed where each memory bank can be assigned to an uplink time slot, and 1 group of memory banks can be formed and assigned as a flexible time slot.

[0033] It should be understood that the number of memory banks within each group can vary. For example, the number of memory banks allocated (grouped) for one uplink time slot can be different from that of another uplink time slot. In other words, as shown, a group of memory banks allocated to an uplink time slot can include 5 memory banks, and another group of memory banks can have a different number of memory banks, such as 3 memory banks, 4 memory banks, etc. It should be understood that the number of memory banks allocated (grouped) to a downlink time slot can be different from the number of memory banks in different downlink time slots. In other words, as shown, a group of memory banks allocated to a downlink time slot can include 5 memory banks, and another group of memory banks (not shown here) allocated to another downlink time slot can have a different number of memory banks, such as 3 memory banks, 4 memory banks, etc. Additionally, it should be understood that the number of memory banks allocated (grouped) to a downlink time slot can be different from the number of memory banks in an uplink time slot. In other words, showing 5 memory banks in each group is for illustrative purposes and should not be construed as limiting the scope of the embodiments. Further, it should be understood that each memory bank can have the same capacity (e.g., 4MB), or they can have different capacities from each other. For example, one memory bank can be 4MB while another memory bank can be 16MB.

[0034] It should be understood that in one non - limiting example, each group of memory banks can have its own clock signal. For example, memory banks 222A to 222F can have their own clock signal 262, while memory banks 222G to 222L can have their own clock signal 264, while memory banks 222M to 222R can have their own clock signal 266, and while memory banks 222S to 222X can have their own clock signal 268. As described in more detail below with respect to Figures 3A to 4D which is described in more detail, each group can be clock - gated when not in use to manage its power consumption. For example, when the base station is involved in the uplink, the downlink memory banks 252 can be clock - gated by turning off clock signal 262, and when the base station is involved in the downlink, the uplink memory banks 254 can be clock - gated by turning off clock signals 264 to 268. It should be understood that in some non - limiting examples, if desired, each memory bank can be independently clock - controlled so that the power consumption of the memory banks can be controlled at a finer level. Variations for managing power are described in more detail in the following Figures 3A to 4D which is described in more detail below.

[0035] According to some embodiments, once resources (e.g., memory banks) are allocated based on the configuration data 202 (as described above), the base station can start processing data communications from cells (e.g., cells 102 to 126). The controller 210 can receive data (PHY layer data) associated with a given time slot from one or more of the cells 102 to 126. The controller 210 can process the received data (time slot) and determine whether the data is for uplink or downlink. Thus, unused memory banks can be clock-gated to reduce power consumption. For example, if the controller 210 determines that the received data is for uplink, the memory banks allocated for downlink time slots can be powered down (e.g., by clock-gating them), and if the controller 210 determines that the received data is for downlink, the memory banks allocated for uplink time slots can be powered down (e.g., by clock-gating them), thereby reducing the power consumption of the base station.

[0036] In some embodiments, the controller 210 can process the received data and generate and assign jobs to other processing components. In other words, signal processing can be offloaded from the controller 210 to other components, such as the accelerator 240, DSP 230, etc. For example, the controller 210 can assign certain jobs associated with the received time slot to the DSP 230 and assign certain jobs associated with the received time slot to the accelerator 240. It should be understood that the accelerator 240 can be one or more hardware accelerators (e.g., field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), etc.) configured to perform at least one or more operations associated with forward error correction (FEC) calculations, equalization, demapping, etc. It should be understood that the DSP 230 can include one or more DSP cores configured to perform at least one or more operations associated with channel estimation, demodulation reference (DMR) signal generation, frequency error calculation, timing estimation, etc.

[0037] It should be understood that a subset of the accelerators from the accelerator 240 can be placed in a lower power mode when they are not being utilized (when idle) to reduce power consumption. Similarly, a subset of the DSPs from the DSP 230 can be placed in a lower power mode when they are not being utilized (when idle) to reduce power consumption. The scheduler 220 is used to schedule the jobs assigned by the controller 210 for the DSP 230 and / or the accelerator 240.

[0038] It should be understood that in some embodiments, certain event data 204 can be received by the scheduler 220 and / or the controller 210. The event data 204 can be used to further manage the power consumption of the controller 210, which is described in great detail below in Figures 6 to 7B this.

[0039] It should be understood that the base station may include other components not shown for the sake of simplicity. For example, the base station may also include other memory components, such as DDR memory, one or more databases, etc.

[0040] Now referring to Figure 3A , for illustrative purposes, a non-limiting example of allocating memory banks to time slots is shown. In Figure 3A , the controller 310 may be a controller similar to the controller 210, and the on-chip shared memory 350 may be similar to the shared memory 250. The memory banks 322A to 322X are similar to Figure 2 the memory banks 222A to 222X, and the clock signals 362 to 368 are similar to the clock signals 262 to 268. The memory banks 322A to 322F may be grouped together and allocated as a downlink memory bank 352 to a downlink time slot, while the memory banks 322G to 322L, the memory banks 322M to 322R, and the memory banks 322S to 322X are all allocated as uplink memory banks 354 to uplink time slots.

[0041] Now referring to Figure 3B , the controller 310 receives data from a cell (e.g., cell 102). The controller 310 may determine that the received data is for the downlink. Since the system is deployed in a TTD system, the data is either being sent or being received, but not both. Therefore, since the received data indicates the downlink, it is determined that the memory banks 322A to 322F allocated to the downlink time slot will be utilized, while the uplink memory bank 354 will not be utilized. Thus, since the current time slot is for the downlink rather than the uplink, the memory banks 322G to 322X are clock-gated, for example, using the clock signals 364 to 368 during this time slot. Since the memory banks 322G to 322X are not being used for the current time slot being processed, clock-gating the memory banks 322G to 322X reduces the power consumption that would otherwise result in wasted power. In addition, it should be understood that generally uplink processing is more complex in nature and thus consumes more power. Thus, significant power savings are achieved by turning off the memory banks 322G to 322X when they are not being used for the uplink.

[0042] Now referring to Figure 3C, the controller 310 receives data from a cell (e.g., cell 126). The controller 310 can determine that the received data is for the uplink. Since the system is deployed in a TTD system, data is either being transmitted or being received, rather than being both transmitted and received. Thus, because the received data indicates the uplink, it is determined that the memory banks 322G to 322X assigned to the uplink time slots will be utilized, and the downlink memory bank 352 will not be utilized. Therefore, since the current time slot is for the uplink rather than the downlink, the memory banks 322A to 322F are clocked off during this time slot, for example, using the clock signal 362. Since the memory banks 322A to 322F are not being used for the current time slot being processed, clocking off the memory banks 322A to 322F reduces the power consumption that would otherwise result in wasted power.

[0043] Now refer to Figure 3D , the controller 310 receives data from a cell (e.g., cell 126). The controller 310 can determine that the received data is for the uplink. Since the system is deployed in a TTD system, data is either being transmitted or being received, rather than being both transmitted and received. Thus, because the received data indicates the uplink, it is determined that the memory banks 322G to 322X assigned to the uplink time slots will be utilized, and the downlink memory bank 352 will not be utilized. Additionally, the system can determine that not all of the memory banks in the uplink memory bank 354 will be used based on the load associated with the wireless network. For example, the controller 310 can determine that the memory banks 322M to 322X will be used for two uplink time slots. In other words, it can be determined that even though the data being processed is related to the uplink, the memory banks 322G to 322L in the uplink memory bank 354 are not needed. Thus, based on the load on the wireless network, since the current time slot is for the uplink rather than the downlink, the memory banks 322A to 322F from the downlink memory bank 352 are clocked off during this time slot, for example, using the clock signal 362, and since the memory banks 322G to 322L assigned to the uplink time slots are not in use, the memory banks 322G to 322L are clocked off. Since the memory banks 322A to 322L are not being used for the current time slot being processed, clocking off the memory banks 322A to 322F and the memory banks 322G to 322L reduces the power consumption that would otherwise result in wasted power. In other words, the power consumption is limited to the memory banks being used, thereby reducing the power consumption.

[0044] Figures 4A to 4D Depicts an example of managing power associated with shared memory in the dynamic configuration of a wireless network according to one aspect of the present embodiment.Figures 4A to 4D illustrates the power consumption of each memory bank that can be controlled in a more refined manner. In Figure 4A , the controller 410 can be similar to the controller 310, and the on-chip shared memory 450 can be similar to the on-chip shared memory 350. The memory banks 422A to 422X are similar to the memory banks 322A to 322X of FIG. 3, except that the power consumption of each memory bank is individually controlled by its corresponding clock signals 462 to 468. The memory banks 422A to 422F can be grouped together and assigned as a downlink memory bank 452 to a downlink time slot, while the memory banks 422G to 422L, the memory banks 422M to 422R, and the memory banks 422S to 422X are all assigned as uplink memory banks 454 to an uplink time slot.

[0045] In this non-limiting example, the controller 410 receives data from a cell (e.g., cell 102). The controller 410 can determine that the received data is for the uplink. Since the system is deployed in a TTD system, the data is either being transmitted or being received, but not both transmitted and received. Therefore, it is determined that the memory banks 422A to 422F assigned to the downlink time slot will not be utilized. Thus, the memory banks 422A to 422F can be clocked off using the clock signal 462. In addition, the controller 410 can determine a subset of the memory banks that may need to be assigned to the uplink time slot based on the load on the wireless network. Thus, the number of memory banks that may be needed is adjusted, and the unused memory banks are clocked off to reduce power consumption. For example, it can be determined based on the load that even the memory banks 422G to 422Q assigned to the uplink time slot are not needed, so these memory banks are clocked off to reduce power consumption. It should be understood that the clock signals 464 and 466 can be used to clock off the memory banks 422G to 422Q during the processing of the current time slot, thereby reducing power consumption. Since the memory banks 422G to 422Q are not being used for the current time slot being processed, clocking off the memory banks 422G to 422Q reduces the power consumption that would otherwise result in wasted power.

[0046] Figure 4B substantially similar to Figure 4A except that the controller 410 determines a higher load on the wireless network compared to Figure 4A . Thus, more memory banks are needed to process the current time slot associated with the uplink. In this non-limiting example, in addition to the downlink memory bank 452 being clocked off, the memory banks 422G to 422O are also clocked off to reduce power consumption because they are not needed to process the current time slot.

[0047] Figure 4CSubstantially similar to Figure 4A FIG., except that the controller 410 determines a lighter load on the wireless network compared to Figure 4A . As such, fewer memory banks are needed to process the current time slot associated with the uplink. In this non-limiting example, memory banks 422G through 422R and 422W through 422X are also clocked off to reduce power consumption because they are not needed to process the current time slot, in addition to the downlink memory bank 452 being clocked off.

[0048] Figure 4D Substantially similar to Figure 4A . In this non-limiting example, the controller 410 receives data from a cell (e.g., cell 102). The controller 410 may determine that the received data is for the downlink. Since the system is deployed in a TTD system, data is either being sent or being received, but not both. Accordingly, it is determined that memory banks 422G through 422X, which are allocated for uplink time slots, will not be utilized. As such, memory banks 422G through 422X can be clocked off using clock signals 464 through 468. Additionally, the controller 410 may determine a subset of memory banks that may be needed for downlink time slots based on the load on the wireless network. Accordingly, the number of memory banks that may be needed is adjusted, and unused memory banks are clocked off to reduce power consumption. For example, it may be determined based on the load that memory banks 422A through 422D, even though allocated for downlink time slots, are not needed, and thus these memory banks are clocked off to reduce power consumption. It should be understood that clock signal 462 can be used to clock off memory banks 422A through 422D during the processing of the current time slot, thereby reducing power consumption. Since memory banks 422A through 422D and memory banks 422G through 422X are not being used for the current time slot being processed, clocking off memory banks 422A through 422D and memory banks 422G through 422X reduces the power consumption that would otherwise result in wasted power.

[0049] It should be understood that Figures 3A to 4D for illustrative purposes that should not be construed as limiting the scope of the embodiments, the use of clock signals to control the power consumption of memory banks is described. For example, clock signals can be used in conjunction with gate logic to control the powering on or powering off of memory banks.

[0050] Figure 5Depicts an example of a base station 500 with shared memory for processing data according to an aspect of the present embodiment. The base station 500 may include one or more controllers 510A to 510N, one or more DSPs 550A to 550N, one or more accelerators 540A to 540N, and a shared memory that is decomposed into a plurality of memory banks 522A to 522K, for example, 96MB. It should be understood that one or more controllers 510A to 510N, one or more DSPs 550A to 550N, one or more accelerators 540A to 540N, and a plurality of memory banks 522A to 522K may be coupled to each other via an interconnect 540 (e.g., interconnect X). It should be understood that controller 510A may include a plurality of controllers, e.g., CPUs. Similarly, each of controllers 510B to 510N may each include a plurality of controllers. It should also be understood that DSP 550A may include a plurality of DSPs. Similarly, each of DSPs 550B to 550N may include a plurality of DSPs. In addition, it should be understood that accelerator 540A may include a plurality of accelerators, e.g., FPGAs, ASICs, etc. Similarly, each accelerator 540B to 540N may include a plurality of accelerators. It should be understood that Figure 5 the DSPs, accelerators, controllers, and memory banks may be similar to the DSPs, accelerators, controllers, and memory banks described in Figures 2 to 4D . In addition, it should be understood that, as described above, each controller, each DSP, each accelerator, and each memory bank may be clocked off (placed in a lower power mode) when not needed, thereby reducing power consumption. It should be understood that memory banks 522A to 522K may each be 4MB memories. It should also be understood that in some non-limiting examples, the sizes of at least two of the memory banks may be different from each other, e.g., one may be 4Mb and the other may be 8MB.

[0051] As described above, the shared memory utilization varies based on the number of cells and the supported bandwidth (i.e., based on the load on the wireless network). In a non-limiting example of TDD, at 20MHz bandwidth and 18 cells with 7 downlink time slots and 3 uplink time slots, the embodiments described above enable 14 uplink memory banks to be clock-gated approximately 70% of the time, thereby providing significant power savings associated with PHY layer processing. The range of power consumption reduction using the embodiments described above can range from approximately 26% savings in the uplink to approximately 62% savings in the downlink, with an average savings of approximately 52%.

[0052] It should be understood that time is critical in a 5G wireless network, and a system (e.g., a base station) may have a very limited time budget to parse the received data of the configured cell and appropriately create jobs. Thus, as described above, a combination of an accelerator and / or a DSP can be used. As a non-limiting example, a PHY configured with a 15 kHz subcarrier spacing has a 1 ms time slot for processing and the next 1 ms time slot for transmitting or receiving 14 OFDM symbols in the air. By increasing the subcarrier spacing, the allocated time slot is further reduced. For example, for a subcarrier spacing increased to 30 kHz, the time slot becomes half. To manage the limited time budget, the PHY layer processing can utilize two subsystems. As described above, the first subsystem can include a DSP, an accelerator, a shared memory, etc. The second subsystem can include a CPU subsystem as described Figure 6 in the following.

[0053] Figure 6 FIG. depicts an example of a processing unit of a base station in a wireless network according to an aspect of the present embodiment. The processing unit may include a controller 610 (CPU thread), a scheduler 620, and an event manager 630. The controller 610 can be one or more of the controllers as described Figures 2 to 5 in the following. The controller 610 receives data in the wireless network. The controller 610 is configured to process the data in a first power mode (e.g., fully powered-on mode), and based on this processing, a first set of jobs can be assigned to at least one or more accelerators and / or a second set of jobs can be assigned to at least one or more DSPs. It should be understood that the accelerators and DSPs are similar to Figures 2 to 5 the accelerators and DSPs described in the following. Once the assignment of jobs for processing is completed (i.e., once the processing of the data by the controller 610 is completed), the job assignment is sent to the scheduler 620 for scheduling to be executed by the accelerator and / or DSP.

[0054] It should be understood that since the controller 610 has completed its processing of the current data (e.g., assigning jobs to the DSP and / or accelerator), it transitions to a second power mode (e.g., sleep mode), and the second power mode is in a lower power mode than the power mode of the first power mode. According to a non-limiting example, the event manager 630 manages the power mode associated with the controller 610. In a non-limiting example, the event manager 630 transitions the controller 610 to the second power mode, and in another non-limiting example, the controller 610 automatically transitions to the second power mode. It should be understood that in a non-limiting example, the event manager 630 is also configured to transition the controller 610 from the second power mode to the first power mode (to wake up the controller 610) in response to a trigger event (e.g., an interrupt, expiration of a configurable time amount, etc.).

[0055] relative to Figure 7A A non - limiting example in [reference] describes power consumption management of controller 610 with respect to downlink processing. In [reference], data associated with downlink time slot 702 is received, and subsequently the next set of data associated with downlink time slot 705 is received. Controller 610 processes the data associated with downlink time slot 702. In a non - limiting example, when data is received, controller 610 is woken up by event manager 630 so that the data can be processed (if controller 610 is in a sleep mode). In this non - limiting example, controller 610 can process the data (e.g., parse the received data) within a time amount of two symbols (i.e., controller 610 wakes up during controller wake - up 703), and create / assign a job associated with the data in downlink time slot 702 to the DSP and / or accelerator. Figure 7A The job assignment is sent to scheduler 620 to be scheduled for execution by the DSP and / or accelerator. For example, the created / assigned job can be queued in scheduler 620. Since controller 610 has completed its processing (i.e., parsing and assigning / creating jobs for the accelerator and / or DSP), event manager 630 transitions the controller from the first power mode to the second power mode. Thus, controller 610 remains in the second power mode (i.e., controller sleep 704) until a trigger event occurs. In this non - limiting example, the trigger event is receiving data associated with downlink time slot 705 and can be an interrupt generated. Thus, event manager 630 wakes up controller 610 to process the data associated with downlink time slot 705. In this non - limiting example, controller 610 wakes up during controller wake - up 706 (i.e., the time amount it takes to assign a job associated with the data in downlink time slot 705 to the DSP and / or accelerator) for processing the data associated with downlink time slot 705. Once controller 610 determines the assignment of the job associated with the data in downlink time slot 705, event manager 630 transitions controller 610 to the second power mode, similar to above. As illustrated, controller 610 spends a large time amount (e.g., a time amount associated with 12 symbols) in the second power mode and wakes up only for a time sufficient to complete its processing (e.g., parsing and assigning / creating jobs for the DSP and / or accelerator, which may take approximately 2 symbols). Thus, the power consumption of controller 610 is significantly reduced. Since there are typically multiple controllers (e.g., 6 controllers, etc.) in the system, this results in an even more significant power reduction. It should be understood that 70% of the downlink time slots are processed at this time, so the power management of controller 610 described above results in a significant power reduction.

[0056] ​

[0057] It should be understood that the above example describes an interruption where the trigger event is generated as a result of receiving new data. However, it should be understood that the trigger event can be the expiration of a configured amount of time. For example, the controller 610 can transition to a second power mode within a configured amount of time (e.g., a configurable amount of time), and when the configured amount of time expires, the controller transitions from the second power mode to the first power mode. In a non-limiting example, the trigger event can be the expiration of a configured amount of time or a generated interruption, whichever occurs first. In other words, the controller 610 remains in the second power mode and transitions to the first power mode after the expiration of the configured amount of time in the absence of a trigger event (e.g., an interruption), or if an interruption is received before the expiration of the configured amount of time, the controller can transition to the first power mode before the expiration of the configured amount of time. In a non-limiting example, the interruption can be associated with a timing report Figure 7B described with respect to the uplink data.

[0058] Now refer to Figure 7B, the power consumption management with respect to the controller 610 for uplink processing is described. In this example, data associated with the uplink time slot 709 is received, and subsequently data associated with the uplink time slots 712 and 715 are received respectively. For illustrative purposes, each uplink time slot includes 14 symbols. It should be understood that according to a non-limiting example, the controller 610 can process uplink data that can be approximately 3 symbols (3 symbols long). For example, the controller 610 can use up to 3 symbols to parse the received data, and assign / create jobs associated with the data in the uplink time slot 709 to one or more DSPs and / or one or more accelerators (i.e., assignment 721). The assigned / created jobs can be sent to the scheduler 620 (e.g., queued in the scheduler 620) to be scheduled for execution by one or more DSPs and / or one or more accelerators. Thus, after the first 3 symbols of the data in the uplink time slot 709, the event manager 630 transitions the controller 610 from the first power mode to the second power mode. In one example, the controller 610 transitions from the first power mode to the second power mode until a trigger event occurs (e.g., the expiration of a configured amount of time, an interruption, event data, etc.). In this example, the controller 610 remains in the second power mode during the controller sleep 711 time, which in this example is a time amount equivalent to 9 symbol lengths. Event data 722 can be generated, for example, by one or more of the DSPs and / or one or more of the accelerators associated with processing their respective data, and the respective data is scheduled to be executed before the data associated with the uplink time slot 709. In a non-limiting example, the event data 722 can include a time report, and it can be a time equivalent to 2 symbol lengths.

[0059] The event data 722 causes an interruption to wake up the controller 610, for example, so as to transition the controller 610 from the second power mode to the first power mode. After the event data 722 can be the next set of data associated with the uplink time slot 712. Thus, the controller 610 spends another 3 symbol lengths to parse the data associated with the uplink time slot 712, and assigns / creates jobs for one or more accelerators and / or one or more DSPs. As described above, the assigned / created jobs are sent to the scheduler 620 (e.g., queued in its queue) to be scheduled for execution by the DSPs and / or accelerators. In a non-limiting example, the controller 610 remains in the first power mode for a time amount of the controller wake-up 713 (equivalent to 5 symbols) to process the event data 722 and the data associated with the uplink time slot 712. It should be understood that since the controller 610 has completed the processing of the data associated with the uplink time slot 712, the event manager 620 transitions the controller from the first power mode to the second power mode.

[0060] The controller 610 remains in the second power mode for the controller sleep time 714 (which is 9 symbols long in this example) until the next trigger event occurs (e.g., an interrupt, event data, new data for the next uplink time slot, expiration of a configured amount of time, etc.). In this non-limiting example, event data 724 generated by one or more of the DSPs associated with the data processing for the uplink time slot 709 and / or one or more of the accelerators can be received. Thus, an interrupt can be generated to transition the controller 610 from the second power mode to the first power mode. Similar to before receiving and parsing the next set of data associated with the uplink time slot 715 and creating / assigning jobs by the controller 610 to one or more of the accelerators and / or DSPs. In other words, the controller 610 remains in the first power mode for the controller wake-up time 716 (which is 5 symbols long in this example), after which the event manager 620 transitions the controller to the second power mode during the controller sleep time 717.

[0061] As Figure 7A and Figure 7B illustrated, the controller spends a significant amount of time in the lower power mode compared to a conventional system that is always on regardless of whether the controller is processing data. As a result, the power consumption of the controller is significantly reduced.

[0062] It should be understood that the power management associated with the controller, as Figures 6 to 7B described, can operate in a polling mode or an interrupt mode. In the polling mode, the controller 610 can call the event manager 630 to poll for events, such as expiration of a configured amount of time, time reports generated by the DSP and / or accelerator, etc. After the call to the event manager 630, the controller 610 can transition to the second power mode (e.g., sleep mode) within the configured amount of time. During the configured amount of time, if no trigger event occurs other than the expiration of the configured amount of time (at which point the controller 610 transitions back to the first power mode), the controller 610 remains in the second power mode. The controller 610 can then process any outstanding tasks and transition back to the second power mode when the processing is complete. It should be understood that if there are no outstanding tasks when the controller 610 transitions from the second power mode to the first power mode, the controller transitions back to the second power mode. This process can repeat itself. However, if a trigger event other than the expiration of the configured time occurs, the event manager 630 transitions the controller 610 to the first power mode before the expiration of the configured amount of time. When in the first power mode, the controller 610 processes any outstanding requests and transitions back to the second power mode when complete. This process repeats itself.

[0063] In contrast, in interrupt mode, when the controller completes its processing (e.g., parsing data and assigning / creating jobs for one or more of the DSP and / or accelerator), the controller 610 transitions itself from the first power mode to the second power mode. The controller 610 may remain in the second power mode until the event manager 630 receives an interrupt. The event manager 630 wakes up the controller 610 (i.e., transitions the controller 610 from the second power mode to the first power mode). The controller 610 may complete processing of any pending tasks and may transition itself back to the second power mode when the controller completes its processing. The process may repeat itself.

[0064] Figures 6 to 7B The embodiment described in results in a power consumption reduction of approximately 85% in the downlink and approximately 60% in the uplink, for an average reduction of approximately 78%.

[0065] Figure 8 An illustrative flow chart for managing power associated with a shared memory in a processor of a base station according to one aspect of the present embodiment is depicted. At step 810, cellular configuration data and network service data are received, as described above in Figures 1 to 5 The cellular configuration data is associated with a plurality of cells within a wireless network, as described in Figures 1 to 5 At step 820, based on the cellular configuration, a first subset of memory banks in a plurality of memory banks of the on-chip shared memory is allocated to the uplink time slot, such as Figures 1 to 5 At step 830, a plurality of uplink groups (e.g., a plurality of rows) are formed from the first subset of memory banks, as described above. In one non-limiting example, the uplink group may include one memory bank. At step 840, a second subset of memory banks in the plurality of memory banks of the on-chip shared memory is allocated to the downlink time slot based on the cellular configuration, as described above with respect to Figures 1 to 5 At step 850, a plurality of downlink groups are formed from the second subset of memory banks, as described above. In a non-limiting example, a downlink group may include one memory bank. At step 860, in response to the network traffic data being associated with the downlink time slot, a first subset of memory banks in the plurality of memory banks is clocked off, as described above. At step 870, in response to the network traffic data being associated with the uplink time slot, a second subset of memory banks in the plurality of memory banks is clocked off, as described above.

[0066] It should be understood that in some embodiments, based on the load associated with network traffic data and in response to the network traffic data being associated with a downlink time slot, a subset of uplink groups among multiple uplink groups is clocked off. In some embodiments, based on the load associated with network traffic data and in response to the network traffic data being associated with an uplink time slot, a subset of downlink groups among multiple downlink groups is clocked off.

[0067] In some embodiments, a third subset of memory banks among multiple memory banks is allocated as a flexible time slot, which is configured as an uplink time slot or a downlink time slot according to the load associated with network traffic. As described above, the wireless network can be deployed in TDD. It should be understood that the number of memory banks in each uplink group can be the same or different from each other. It should also be understood that the number of memory banks in each downlink group can be the same or different from each other. In addition, the number of memory banks in one uplink group can be the same or different from that in one downlink group.

[0068] It should be understood that the method can include a physical layer for processing network traffic data. In a non-limiting example, the method can also include determining whether the traffic data is associated with an uplink or a downlink. In some embodiments, the method further includes scheduling a first plurality of jobs for one or more hardware accelerators and scheduling a second plurality of jobs for one or more DSP cores, and wherein the one or more DSP cores are configured to perform at least one or more operations associated with channel estimation. The hardware accelerator can be configured to perform at least one or more operations associated with FEC calculation, equalization, and demapping. The DSP core can be configured to perform one or more of DMR signal generation, frequency error calculation, and timing estimation.

[0069] Figure 9 An illustrative flowchart for managing power associated with a processor of a base station according to an aspect of the present embodiment is depicted. At step 910, data associated with a time slot is received in the wireless network by a controller, as Figure 1 and Figures 6 to 7B described. The wireless network can be deployed in TTD. At step 920, the data is processed in a first power mode, as Figure 1 and Figures 6 to 7B described. At step 930, a plurality of jobs associated with the data are assigned to at least one or more hardware accelerators or one or more DSP cores, as Figure 1 and Figures 6 to 7B described. At step 940, after the controller completes processing the data associated with the time slot, the controller transitions from the first power mode to a second power mode, as Figure 1 and Figures 6 to 7Bas described. It should be understood that when the controller is processing data associated with a time slot, the second power mode is a lower power mode compared to the first power mode. At step 950, a plurality of jobs are scheduled for at least one or more hardware accelerators or for one or more DSP cores, as Figure 1 and Figures 6 to 7B described. At step 960, the controller transitions from the second power mode to the first power mode in response to a trigger event, as Figure 1 and Figures 6 to 7B described.

[0070] It should be understood that the data can be downlink data and that the time slot is a downlink time slot. It should be understood that the trigger event can be associated with receiving another data associated with another time slot in a wireless network, as Figure 1 and Figures 6 to 7B described.

[0071] It should be understood that the data can be uplink data and that the time slot is an uplink time slot. According to some non - limiting examples, the trigger event is receiving data associated with a subset of jobs associated with a plurality of jobs for at least one or more hardware accelerators or with another subset of jobs associated with a plurality of jobs for at least one or more DSP cores, as Figure 1 and Figures 6 to 7B described.

[0072] In some embodiments, within a configured amount of time, the controller transitions from the first power mode to the second power mode. It should be understood that transitioning the controller from the second power mode to the first power mode can be in response to the expiration of the configured amount of time and further in response to not receiving a trigger event. In one non - limiting example, the method further includes the controller requesting a poll after transitioning to the first power mode and that in the absence of a trigger event, the controller transitions from the first power mode to the second power mode. It should be understood that the controller can transition from the second power mode to the first power mode during the configured amount of time and in response to receiving a trigger event.

[0073] In some embodiments, the controller remains in a second power mode until an interruption occurs and the interruption is sent to the controller to transition the controller from the second power mode to the first power mode. In one non-limiting example, the method includes processing a subset of jobs among a plurality of jobs by at least one or more hardware accelerators and processing another subset of jobs among the plurality of jobs by one or more DSP cores. As described above, the one or more hardware accelerators are configured to perform at least one or more operations associated with FEC calculation, equalization, and demapping, and wherein the one or more DSP cores are configured to perform at least one or more operations associated with channel estimation, DMR signal generation, frequency error calculation, and timing estimation.

[0074] The foregoing description of the various embodiments of the claimed subject matter has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best describe the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the claimed subject matter, the various embodiments suitable for the particular uses contemplated, and the various modifications.

Claims

1. A system comprising: a controller configured to receive cellular configuration data and network traffic data, wherein the cellular configuration data is associated with a plurality of cells within a wireless network; as well as an on-chip shared memory configured into a plurality of memory bank groups based on the cellular configuration data, wherein each memory bank group of the plurality of memory bank groups includes a certain number of memory banks, and wherein a first subset of memory bank groups of the plurality of memory bank groups are associated with uplink time slots, and wherein a second subset of memory bank groups of the plurality of memory bank groups are associated with downlink time slots, wherein a first subset of the memory bank groups associated with the uplink time slot are clocked off in response to the network service data being associated with a downlink time slot, and wherein a second subset of the memory bank groups associated with the downlink time slot are clocked off in response to the network service data being associated with an uplink time slot.

2. The system of claim 1, wherein a third subset of the memory bank groups of the plurality of memory bank groups associated with the flexible time slots is configured as an uplink time slot or a downlink time slot according to a load associated with the network traffic. 3 . The system of claim 1 , wherein the controller and the on-chip shared memory are within a base station deployed in time division duplex (TDD). 4 . The system of claim 1 , wherein the number of the memory banks of each group within the first subset of the memory bank groups is the same.

5. The system of claim 1, wherein the number of the memory banks of each group within the second subset of the groups of memory banks is the same. 6 . The system according to claim 1 , wherein the controller and the on-chip shared memory are located in a physical card of a base station, and the physical card is configured to process a physical layer of the network service data.

7. The system of claim 6, wherein the physical card is a Peripheral Component Interconnect (PCI) card.

8. The system of claim 1 , further comprising one or more hardware accelerators and one or more digital signal processing (DSP) cores, wherein the controller is configured to schedule one or more jobs for the one or more hardware accelerators and the one or more DSP cores, wherein the one or more hardware accelerators are configured to perform at least one or more operations associated with forward error correction (FEC) calculation, equalization, and demapping, and wherein the one or more DSP cores are configured to perform at least one or more operations associated with channel estimation, demodulation reference (DMR) signal generation, frequency error calculation, and timing estimation.

9. A system comprising: a controller configured to receive cellular configuration data and network traffic data, wherein the cellular configuration data is associated with a plurality of cells within a wireless network; as well as an on-chip shared memory, the on-chip shared memory comprising a plurality of memory banks, wherein a first subset of memory banks in the plurality of memory banks are allocated to uplink time slots based on the cellular configuration, and wherein the first subset of memory banks includes a plurality of uplink groups, wherein a second subset of memory banks in the plurality of memory banks are allocated to downlink time slots based on the cellular configuration, and wherein the second subset of memory banks includes a plurality of downlink groups, wherein a first subset of the memory banks allocated to uplink time slots are clocked off in response to the network traffic data being associated with downlink time slots, and wherein a subset of the uplink groups in the plurality of uplink groups are clocked off in response to a load associated with downlink data of the network data, wherein a second subset of the memory banks allocated to downlink time slots are clocked off in response to the network service data being associated with uplink time slots, and wherein a subset of downlink groups in the plurality of downlink groups are clocked off in response to a load associated with uplink data of the network data.

10. The system of claim 9, wherein a third subset of the memory banks of the plurality of memory banks are associated with flexible time slots that are configured as uplink time slots or downlink time slots depending on a load associated with the network traffic.

11. The system of claim 9, wherein the controller and the on-chip shared memory are within a base station deployed in time division duplex (TDD).

12. The system of claim 9, wherein the number of memory banks of each group within the plurality of uplink groups is the same.

13. The system of claim 9, wherein the number of memory banks of each group within the plurality of downlink groups is the same.

14. The system according to claim 9, wherein the controller and the on-chip shared memory are located in a physical card of a base station, and the physical card is configured to process a physical layer of the network service data.

15. The system of claim 14, wherein the physical card is a Peripheral Component Interconnect (PCI) card.

16. The system of claim 9, further comprising one or more hardware accelerators and one or more digital signal processing (DSP) cores, wherein the controller is configured to schedule one or more jobs for the one or more hardware accelerators and the one or more DSP cores, wherein the one or more hardware accelerators are configured to perform at least one or more operations associated with forward error correction (FEC) calculation, equalization, and demapping, and wherein the one or more DSP cores are configured to perform at least one or more operations associated with channel estimation, demodulation reference (DMR) signal generation, frequency error calculation, and timing estimation.

17. The system of claim 9, wherein each uplink group of the plurality of uplink groups includes a number of memory banks in the first subset of the memory banks.

18. The system of claim 17, wherein the number of the memory banks is one.

19. The system of claim 9, wherein each downlink group of the plurality of downlink groups includes a number of memory banks in the second subset of the memory banks.

20. The system of claim 19, wherein the number of the memory banks is one.

21. A method comprising: receiving cellular configuration data and network service data, wherein the cellular configuration data is associated with a plurality of cells within a wireless network; allocating a first subset of memory banks of a plurality of memory banks of an on-chip shared memory to uplink time slots based on the cellular configuration; forming a plurality of uplink groups from a first subset of the memory banks; allocating a second subset of memory banks of the plurality of memory banks of the on-chip shared memory to downlink time slots based on the cellular configuration; forming a plurality of downlink groups from a second subset of the memory banks; In response to the network traffic data being associated with a downlink time slot, clocking off a first subset of the memory banks of the plurality of memory banks; as well as In response to the network traffic data being associated with an uplink time slot, a second subset of the memory banks of the plurality of memory banks are clocked off.

22. The method according to claim 21, further comprising: In response to the network traffic data being associated with a downlink time slot, a subset of the uplink groups of the plurality of uplink groups are clock-off based on a load associated with the network traffic data.

23. The method of claim 22, wherein each of the plurality of uplink groups comprises a memory bank.

24. The method according to claim 21, further comprising: In response to the network traffic data being associated with an uplink time slot, a subset of the downlink groups of the plurality of downlink groups are clocked off based on a load associated with the network traffic data.

25. The method of claim 24, wherein each of the plurality of downlink groups comprises a memory bank.

26. The method of claim 21, further comprising allocating a third subset of the plurality of memory banks as flexible time slots, the flexible time slots being configured as uplink time slots or downlink time slots depending on a load associated with the network traffic.

27. The method of claim 21, wherein the wireless network is deployed in time division duplex (TDD).

28. The method of claim 21, wherein the number of memory banks in each uplink group in the plurality of uplink groups is the same.

29. The method of claim 21, wherein a number of memory banks in one of the plurality of uplink groups is different from a number of memory banks in another of the plurality of uplink groups.

30. The method of claim 21, wherein the number of memory banks of each downlink group within the plurality of downlink groups is the same.

31. The method of claim 21, wherein a number of memory banks in one of the plurality of downlink groups is different from a number of memory banks in another of the plurality of downlink groups.

32. The method of claim 21, further comprising processing a physical layer of the network traffic data.

33. The method of claim 21, further comprising: Scheduling a first plurality of jobs for one or more hardware accelerators, wherein the one or more hardware accelerators are configured to perform at least one or more operations associated with forward error correction (FEC) calculation, equalization, and demapping; as well as A second plurality of jobs are scheduled for one or more digital signal processing (DSP) cores, and wherein the one or more DSP cores are configured to perform at least one or more operations associated with channel estimation, demodulation reference (DMR) signal generation, frequency error calculation, and timing estimation.

34. The method of claim 21, further comprising determining whether the traffic data is associated with an uplink or a downlink.

35. A system comprising: means for receiving cellular configuration data and network service data, wherein the cellular configuration data is associated with a plurality of cells within a wireless network; means for allocating a first subset of memory banks of a plurality of memory banks of an on-chip shared memory to uplink time slots based on the cellular configuration; means for forming a plurality of uplink groups from a first subset of said memory banks; means for allocating a second subset of memory banks of the plurality of memory banks of the on-chip shared memory to downlink time slots based on the cellular configuration; means for forming a plurality of downlink groups from a second subset of said memory banks; means for clocking off a first subset of the memory banks of the plurality of memory banks in response to the network traffic data being associated with a downlink time slot; as well as Means for clocking off a second subset of the memory banks of the plurality of memory banks in response to the network traffic data being associated with an uplink time slot.

36. The system of claim 35, further comprising: Means for clocking off a subset of uplink groups of the plurality of uplink groups based on a load associated with the network traffic data and in response to the network traffic data being associated with a downlink time slot.

37. The system of claim 36, wherein each of the plurality of uplink groups comprises a memory bank.

38. The system of claim 35, further comprising: Means for clocking out a subset of downlink groups of the plurality of downlink groups based on a load associated with the network traffic data and in response to the network traffic data being associated with an uplink time slot.

39. The system of claim 38, wherein each of the plurality of downlink groups comprises a memory bank.

40. The system of claim 35, further comprising means for allocating a third subset of the plurality of memory banks as flexible time slots, the flexible time slots being configured as uplink time slots or downlink time slots depending on a load associated with the network traffic.

41. The system of claim 35, wherein the wireless network is deployed in time division duplex (TDD).

42. The system of claim 35, wherein the number of memory banks in each uplink group in the plurality of uplink groups is the same.

43. The system of claim 35, wherein a number of memory banks in one of the plurality of uplink groups is different from a number of memory banks in another of the plurality of uplink groups.

44. The system of claim 35, wherein the number of memory banks of each downlink group within the plurality of downlink groups is the same.

45. The system of claim 35, wherein a number of memory banks in one of the plurality of downlink groups is different from a number of memory banks in another of the plurality of downlink groups.

46. ​​The system of claim 35, further comprising: A device for processing the physical layer of the network service data.

47. The system of claim 35, further comprising: means for scheduling a first plurality of jobs for one or more hardware accelerators, wherein the one or more hardware accelerators are configured to perform at least one or more operations associated with forward error correction (FEC) computation, equalization, and demapping; as well as Means for scheduling a second plurality of jobs for one or more digital signal processing (DSP) cores, and wherein the one or more DSP cores are configured to perform at least one or more operations associated with channel estimation, demodulation reference (DMR) signal generation, frequency error calculation, and timing estimation.

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