Semiconductor structure and method of making same, memory array structure

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure, a preparation method thereof, and a memory array structure, the semiconductor structure comprising a substrate; a write transistor and a read transistor on the substrate, the write transistor comprising a first gate, a first semiconductor layer surrounding the first gate, a write bit line extending along a first direction, and a write word line extending along a second direction, the write bit line being in electrical contact with a first end of the first semiconductor layer, and the write word line being in electrical contact with the first gate; the read transistor comprising a second semiconductor layer, a second gate, a read bit line extending along the second direction, and a read word line extending along the first direction, the second gate being in electrical contact with a second end of the first semiconductor layer, and the read bit line being in electrical contact with one end of the second semiconductor layer along the first direction; wherein the projections of the read bit line, the read word line, the write word line, and the write bit line on the substrate do not overlap with each other, and the write bit line and the read word line are located on two sides of the first semiconductor layer along a third direction.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to the semiconductor field, in particular to a semiconductor structure and a preparation method thereof, and a memory array structure. BACKGROUND

[0002] DRAM memory cells in computers are made of a single transistor and a single capacitor, a so-called 1T1C design. This memory cell opens the transistor when writing, and the charge is pushed into the capacitor or removed from the capacitor; when reading, the charge is extracted and measured (if any). The system is super fast, cheap, and has very low power consumption, but it also has some drawbacks.

[0003] First, reading consumes the charge of the capacitor, so reading means writing the bit back into the memory. Even if reading is not performed, the charge will eventually leak from the capacitor through the transistor. All cells need to be refreshed periodically to maintain data. In the current DRAM chip, this operation is performed every 64 ms. However, there are difficulties in preparing the capacitor and manufacturing the transistor with ultra-low leakage, so it is difficult to manufacture an excellent capacitor in the manufacturing process for building logic circuits.

[0004] For the above reasons, a new embedded capacitorless DRAM, simply referred to as 2T0C structure, is applied. The 2T0C embedded DRAM is composed of a read transistor and a write transistor to form a cell structure, and uses a gate capacitor to store charge and changes the transistor transconductance to store information. How to reduce the interference between transistors in the process of preparing the 2T0C structure is a problem that those skilled in the art need to consider. SUMMARY

[0005] The embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof, and a memory array structure, which at least has the advantage of reducing the interference between transistors.

[0006] According to some embodiments of the present disclosure, the semiconductor structure comprises: a substrate; a write transistor on the substrate, the write transistor comprising a first gate, a first semiconductor layer surrounding the first gate, a write bit line extending in a first direction, and a write word line extending in a second direction, the first semiconductor layer comprising a first end and a second end opposite to each other in a third direction, the write bit line being in electrical contact with the first end, and the write word line being in electrical contact with the first gate; and a read transistor, the read transistor comprising a second semiconductor layer, a second gate, a read bit line extending in the second direction, and a read word line extending in the first direction, the second gate being in electrical contact with the second end, the read bit line being in electrical contact with one end of the second semiconductor layer in the first direction, and the read word line being located on one side of the second semiconductor layer in the third direction; wherein the read bit line, the read word line, the write word line, and the write bit line do not overlap with each other in the orthographic projection of the substrate, and the write bit line and the read word line are located on two sides of the first semiconductor layer in the third direction, and the write bit line and the read word line are located on two sides of the second semiconductor layer in the third direction.

[0007] According to some embodiments of the present disclosure, the semiconductor structure comprises: a substrate; a write transistor on the substrate, the write transistor comprising a first gate, a first semiconductor layer surrounding the first gate, a write bit line extending in a first direction, and a write word line extending in a second direction, the first semiconductor layer comprising a first end and a second end opposite to each other in a third direction, the write bit line being in electrical contact with the first end, and the write word line being in electrical contact with the first gate; and a read transistor, the read transistor comprising a second semiconductor layer, a second gate, a read bit line extending in the second direction, and a read word line extending in the first direction, the second gate being in electrical contact with the second end, the read bit line being in electrical contact with one end of the second semiconductor layer in the first direction, and the read word line being located on one side of the second semiconductor layer in the third direction; wherein the read bit line, the read word line, the write word line, and the write bit line do not overlap with each other in the orthographic projection of the substrate, and the write bit line and the read word line are located on two sides of the first semiconductor layer in the third direction, and the write bit line and the read word line are located on two sides of the second semiconductor layer in the third direction.

[0008] According to some embodiments of the present disclosure, the semiconductor structure comprises: a substrate; a write transistor on the substrate, the write transistor comprising a first gate, a first semiconductor layer surrounding the first gate, a write bit line extending in a first direction, and a write word line extending in a second direction, the first semiconductor layer comprising a first end and a second end opposite to each other in a third direction, the write bit line being in electrical contact with the first end, and the write word line being in electrical contact with the first gate; and a read transistor, the read transistor comprising a second semiconductor layer, a second gate, a read bit line extending in the second direction, and a read word line extending in the first direction, the second gate being in electrical contact with the second end, the read bit line being in electrical contact with one end of the second semiconductor layer in the first direction, and the read word line being located on one side of the second semiconductor layer in the third direction; wherein the read bit line, the read word line, the write word line, and the write bit line do not overlap with each other in the orthographic projection of the substrate, and the write bit line and the read word line are located on two sides of the first semiconductor layer in the third direction, and the write bit line and the read word line are located on two sides of the second semiconductor layer in the third direction.

[0009] The technical scheme provided by the embodiments of the present disclosure has at least the following advantages:

[0010] The semiconductor structure and the preparation method thereof and the memory array structure provided by the embodiments of the present disclosure are provided. The write transistor comprises a write bit line extending in a first direction and a write word line extending in a second direction. The read transistor comprises a read bit line extending in the second direction and a read word line extending in the first direction. The read bit line, the read word line, the write word line and the write bit line do not overlap with each other in the orthographic projection of the substrate. The write bit line and the read word line are located on two sides of the first semiconductor layer along a third direction. The write bit line and the read word line are located on two sides of the second semiconductor layer along the third direction. The write bit line and the read word line can adopt the stepped structure in the conventional structure to reduce the interference between the write bit line and the write word line and the interference between the read bit line and the read word line. The read bit line, the read word line, the write word line and the write bit line do not overlap with each other in the orthographic projection of the substrate. The write bit line and the read word line are located on two sides of the first semiconductor layer along the third direction. The write bit line and the read word line are located on two sides of the second semiconductor layer along the third direction. It can be seen that the read transistor and the write transistor do not affect each other. The distance between the write bit line and the read word line is far, so as to avoid the read-write crosstalk between the units. BRIEF DESCRIPTION OF DRAWINGS

[0011] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which are illustrative of various embodiments and implementations that can be implemented in accordance with embodiments. The drawings are in no way limiting of the scope of this disclosure. One of ordinary skill in the art will readily recognize from the following description that alternative embodiments of the embodiments illustrated can be realized and are contemplated. The drawings are more fully interpreted by the descriptions of the embodiments below.

[0012] Figure 1 A structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is provided.

[0013] Figure 2 A structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is provided. Figure 1 A circuit diagram of a corresponding semiconductor structure is provided.

[0014] Figure 3 A structural schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure is provided.

[0015] Figure 4 A structural schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure is provided. Figure 3 A circuit diagram of a corresponding semiconductor structure is provided.

[0016] Figure 5 A first structural schematic diagram of a memory array structure provided by another embodiment of the present disclosure is provided.

[0017] Figure 6 A first structural schematic diagram of a memory array structure provided by another embodiment of the present disclosure is provided. Figure 5Top view of the corresponding storage array structure;

[0018] Figure 7 for Figure 5 The corresponding circuit diagram of the memory array structure;

[0019] Figure 8 This is a second structural schematic diagram of a storage array structure provided in another embodiment of the present disclosure;

[0020] Figure 9 This is a third structural schematic diagram of a storage array structure provided in another embodiment of the present disclosure;

[0021] Figure 10 This is a fourth structural diagram of a storage array structure provided in another embodiment of the present disclosure;

[0022] Figure 11 This is a fifth structural schematic diagram of a storage array structure provided in another embodiment of the present disclosure;

[0023] Figure 12 This is a sixth structural schematic diagram of a storage array structure provided in another embodiment of the present disclosure;

[0024] Figure 13 for Figure 12 A schematic diagram of the local structure corresponding to the protrusion in the diagram;

[0025] Figure 14 This is a schematic diagram of the semiconductor structure corresponding to the first film layer and the second film layer in a method for preparing a semiconductor structure according to another embodiment of the present disclosure;

[0026] Figure 15 for Figure 14 A schematic diagram of the cross-sectional structure along section A1-A2 or section B1-B2;

[0027] Figure 16 This is a schematic diagram of the semiconductor structure corresponding to the formation of the first groove in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

[0028] Figure 17 for Figure 16 A schematic diagram of the cross-sectional structure along section A1-A2;

[0029] Figure 18 for Figure 16 A schematic diagram of the cross-sectional structure along section B1-B2;

[0030] Figure 19 A cross-sectional schematic diagram of a semiconductor structure corresponding to a write transistor in a method for fabricating a semiconductor structure according to another embodiment of this disclosure;

[0031] Figure 20 Another cross-sectional structure diagram of forming the semiconductor structure corresponding to the write transistor is provided in the method for manufacturing the semiconductor structure according to another embodiment of the present disclosure;

[0032] Figure 21 A structure diagram of forming the semiconductor structure corresponding to the write bit line is provided in the method for manufacturing the semiconductor structure according to another embodiment of the present disclosure;

[0033] Figure 22 A structure diagram of removing the semiconductor structure corresponding to the second film layer is provided in the method for manufacturing the semiconductor structure according to another embodiment of the present disclosure;

[0034] Figure 23 A cross-sectional structure diagram of forming the semiconductor structure corresponding to the second semiconductor layer is provided in the method for manufacturing the semiconductor structure according to another embodiment of the present disclosure;

[0035] Figure 24 Another cross-sectional structure diagram of forming the semiconductor structure corresponding to the second semiconductor layer is provided in the method for manufacturing the semiconductor structure according to another embodiment of the present disclosure;

[0036] Figure 25 A cross-sectional structure diagram of forming the semiconductor structure corresponding to the second recess is provided in the method for manufacturing the semiconductor structure according to another embodiment of the present disclosure;

[0037] Figure 26 A cross-sectional structure diagram of forming the semiconductor structure corresponding to the read bit line is provided in the method for manufacturing the semiconductor structure according to another embodiment of the present disclosure;

[0038] Figure 27 A cross-sectional structure diagram of removing the semiconductor structure corresponding to the third film layer is provided in the method for manufacturing the semiconductor structure according to another embodiment of the present disclosure;

[0039] Figure 28 A cross-sectional structure diagram of forming the semiconductor structure corresponding to the read word line is provided in the method for manufacturing the semiconductor structure according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] As known from the background, the current semiconductor structure has the problem of interference between transistors.

[0041] The semiconductor structure and the preparation method thereof and the memory array structure provided by the embodiments of the present disclosure are provided, the write transistor comprises a write bit line extending in a first direction and a write word line extending in a second direction; the read transistor comprises a read bit line extending in the second direction and a read word line extending in the first direction, the read bit line, the read word line, the write word line and the write bit line do not overlap with each other in the orthographic projection of the substrate, and the write bit line and the read word line are located on the two sides of the first semiconductor layer along a third direction, and the write bit line and the read word line are located on the two sides of the second semiconductor layer along the third direction, wherein the write bit line and the read word line can adopt the stepped structure in the conventional structure, so as to reduce the interference between the write bit line and the write word line and the interference between the read bit line and the read word line; the read bit line, the read word line, the write word line and the write bit line do not overlap with each other in the orthographic projection of the substrate, and the write bit line and the read word line are located on the two sides of the first semiconductor layer along the third direction, and the write bit line and the read word line are located on the two sides of the second semiconductor layer along the third direction, so that the read transistor and the write transistor do not affect each other, and the distance between the write bit line and the read word line is far, thereby avoiding the read-write crosstalk between the units.

[0042] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0043] Figure 1 A structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is provided; Figure 2 A structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is provided; Figure 1 A circuit diagram of a corresponding semiconductor structure.

[0044] Reference Figure 1 The embodiments of the present disclosure provide a semiconductor structure, comprising: a substrate.

[0045] In some embodiments, the substrate is a single film layer structure, the material of the substrate is a semiconductor material, and the semiconductor material can include any one of silicon, germanium, silicon carbide or germanium silicon. The substrate has N-type doping elements or P-type doping elements. The N-type doping elements can be group V elements such as phosphorus (P) elements, bismuth (Bi) elements, antimony (Sb) elements or arsenic (As) elements, and the P-type doping elements can be group III elements such as boron (B) elements, aluminum (Al) elements, gallium (Ga) elements or indium (In) elements.

[0046] Continuing to refer to Figure 1The semiconductor structure comprises: a write transistor 10 on a substrate, the write transistor 10 comprising a first gate, a first semiconductor layer 101 surrounding the first gate, a write bit line 104 extending along a first direction Y, and a write word line 103 extending along a second direction Z, the first semiconductor layer 101 comprising a first end 106 and a second end 107 opposite to each other along a third direction X, the write bit line 104 being in electrical contact with the first end 106, and the write word line 103 being in electrical contact with the first gate; and a read transistor 11, the read transistor 11 comprising a second semiconductor layer 111, a second gate 113, a read bit line 114 extending along the second direction Z, and a read word line 116 extending along the first direction Y, the second gate 113 being in electrical contact with the second end 107, the read bit line 114 being in electrical contact with one end of the second semiconductor layer 111 along the first direction Y, and the read word line 116 being located at one side of the second semiconductor layer 111 along the third direction X; wherein the read bit line 114, the read word line 116, the write word line 103, and the write bit line 104 do not overlap with each other in the orthographic projection of the substrate, and the write bit line 104 and the read word line 116 are located at two sides of the first semiconductor layer 101 along the third direction X, and the write bit line 104 and the read word line 116 are located at two sides of the second semiconductor layer 111 along the third direction X.

[0047] Reference Figure 1 The read transistor 11 further comprises: a conductive layer 117 extending along the second direction Z, and a third gate; the third gate is located at one side of the second semiconductor layer 111 along the third direction X, and the read word line 116 is in electrical contact with the third gate; the second semiconductor layer 111 comprises a third end 121 and a fourth end 122 opposite to each other along the first direction Y, the read bit line 114 is in electrical contact with the third end 121, and the conductive layer 117 is in electrical contact with the fourth end 122.

[0048] In some embodiments, Figure 1 The semiconductor structure shown is a double-gate 2T0C structure, that is, an auxiliary gate (second gate) is added, the second gate is connected to the source-drain end of the write transistor 10, the voltage is provided by the source-drain end of the write transistor 10, and the source-drain end of the write transistor 10 is configured to store the write voltage of the write transistor 10. Due to the back gate effect of the gate of the transistor, as the write transistor 10 writes the voltage to the source-drain end of the write transistor 10, the auxiliary gate of the read transistor 11 obtains the corresponding write voltage, and according to the difference of the auxiliary gate write voltage (for example, high voltage or low voltage), the gate of the read transistor 11 will exhibit different threshold voltages (V TH ); for an N-type read transistor, when the voltage of the auxiliary gate is high voltage (for example, the write voltage is "1"), V TH will be negative; when the voltage of the auxiliary gate is low voltage (for example, the write voltage is "0"), V THWhen reading the write voltage, the positive shift transistor 11 can adjust the input voltage of the third gate according to the voltage on the second gate (i.e. the voltage of the source-drain end of the write transistor 10), so as to ensure the conduction between the source-drain of the read transistor 11, thereby avoiding the gate of the read transistor 11 from being affected by the back gate effect, and successfully reading the storage voltage of the write transistor 10.

[0049] In some embodiments, the reference voltage Vref is a voltage of the read bit line RBL. Figure 2 The write transistor 10 and the read transistor 11 form a 2T0C structure. The write transistor 10 includes a first pin W1, a second pin W2 and a third pin W3. The first pin W1 is a first source-drain end of the write transistor 10, and the first pin W1 is electrically connected with a write bit line WBL. The second pin W2 is a second source-drain end of the write transistor 10, and the second pin W2 is electrically connected with a second gate of the write transistor 10. The third pin W3 is a gate end of the write transistor 10, and the third pin W3 is electrically connected with a write word line WWL. The read transistor 11 includes a first end point R1, a second end point R2, a third end point R3 and a fourth end point R4. The first end point R1 is a third source-drain end of the read transistor 11, and the first end point R1 is electrically connected with a read bit line RBL. The second end point R2 is a fourth source-drain end of the read transistor 11, and the second end point R2 is configured to input a reference voltage Vref. The third end point R3 is a first gate control end of the read transistor 11, and the first gate control end is electrically connected with the second pin W2 of the write transistor 10. The fourth end point R4 is a second gate control end of the read transistor 11, and the second gate control end is electrically connected with a read word line RWL.

[0050] In some embodiments of the present application, the double-gate 2T0C structure, compared with the traditional 2T0C structure, maintains the advantages of the traditional 2T0C structure, and the read operation is non-destructive, has very low leakage, does not need a large-capacitance capacitor, and indium gallium zinc oxide (IGZO) transistors can be used in the structure. Therefore, the 2T0C structure of some embodiments of the present application solves the problem of the demand for a large-capacitance capacitor, and accordingly reduces the refresh frequency and power consumption.

[0051] In some embodiments, the material of the first semiconductor layer 101 includes a semiconductor material, such as silicon, germanium or silicon germanium.

[0052] In some embodiments, the material of the first semiconductor layer 101 is amorphous material, which has gaps inside, higher carrier mobility, and can reduce the thickness of the first semiconductor layer 101, reduce the line width of the semiconductor structure in a limited cell area, and further improve the storage density of the semiconductor structure. The amorphous material can include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide), or ITO (Indium Tin Oxide).

[0053] In some embodiments, the material of the first semiconductor layer 101 includes IGZO, and the carrier mobility of the IGZO is 20-50 times that of the carrier mobility of polysilicon, which is conducive to improving the carrier mobility in the first semiconductor layer 101, thereby reducing the leakage current when the semiconductor structure is working, reducing the power consumption of the semiconductor structure, and improving the working efficiency of the semiconductor structure. In addition, the thin film deposition process for preparing IGZO is simple and has low deposition temperature, which can improve the problem of thermal damage and thermal defects of the substrate and the active layer. Due to the characteristics of IGZO itself, the uniformity of the large-area first semiconductor layer 101 prepared by using IGZO is good, which can improve the electrical performance and stability of the first semiconductor layer 101.

[0054] In some embodiments, the first semiconductor layer 101 includes a first source-drain end, a first channel region, and a second source-drain end arranged in sequence. The first source-drain end is in electrical contact with the write bit line 104, the second source-drain end is in electrical contact with the second gate 113, the first gate is opposite to the first channel region, and the first gate is in electrical contact with the write word line 103. In the embodiments of the present application, the material of the first gate and the write word line is the same, and they can be prepared in the same preparation process, so Figure 1 the reference sign of the first gate is not shown in the figure.

[0055] In some embodiments, the material of the write bit line 104 includes copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W), or an alloy thereof.

[0056] In some embodiments, the material of the write word line 103 includes copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, or an alloy thereof.

[0057] In some embodiments, the material of the second semiconductor layer 111 includes semiconductor material and amorphous material.

[0058] In some embodiments, the second semiconductor layer 111 comprises a third source-drain end, a second channel region and a fourth source-drain end arranged in sequence, the third source-drain end is in electrical contact with the read bit line 114, the fourth source-drain end is in electrical contact with the conductive layer 117, the second channel region comprises a first sub-channel region and a second sub-channel region, the first sub-channel region is opposite to the second gate, and the second sub-channel region is opposite to the third gate.

[0059] In some embodiments, the material of the second gate 113 comprises a doped polysilicon, a metal material of copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten or an alloy thereof.

[0060] In some embodiments, the material of the read bit line 114 comprises a metal material of copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten or an alloy thereof.

[0061] In some embodiments, the material of the conductive layer 117 comprises a metal material of copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten or an alloy thereof.

[0062] In some embodiments, the material of the read word line 116 comprises a metal material of copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten or an alloy thereof.

[0063] In some embodiments, the material of the read word line 116 is the same as that of the third gate. The read word line 116 and the third gate are prepared in the same preparation process, so that there is no interface threshold difference between the read word line 116 and the third gate, and the current can cross between the third gate and the read word line 116 without interface, so as to improve the migration speed of the current and the response speed of the third gate.

[0064] It is worth noting that the non-overlapping orthographic projection includes that the area of the orthographic projection is completely non-overlapping, that is, the edges of the orthographic projection are not overlapping (see Figure 1 ).

[0065] With reference to Figure 1 , the semiconductor structure further comprises: a first gate dielectric layer 102 between the first semiconductor layer 101 and the first gate; a second gate dielectric layer 112 between the second gate 113 and the second semiconductor layer 111; and a third gate dielectric layer 115 between the second semiconductor layer 111 and the third gate.

[0066] In some embodiments, the material of the first gate dielectric layer 102 can comprise silicon oxide, silicon carbide, silicon nitride or other high dielectric constant materials, for suppressing short channel effects, thereby suppressing tunneling leakage current and the like.

[0067] In some embodiments, the material of the second gate dielectric layer 112 can include silicon oxide, silicon carbide, silicon nitride or other high dielectric constant material, for suppressing short channel effects, suppressing tunneling leakage current and the like.

[0068] In some embodiments, the material of the third gate dielectric layer 115 can include silicon oxide, silicon carbide, silicon nitride or other high dielectric constant material, for suppressing short channel effects, suppressing tunneling leakage current and the like.

[0069] With reference to the foregoing Figure 1 , the semiconductor structure further comprises: a first filling layer 105, the first filling layer 105 is located on the surface of the substrate, and the first filling layer 105 is located between the write bit line 104 and the read bit line 114.

[0070] In some embodiments, the write transistor 10 or the read transistor 11 can be an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or a P-type MOSFET.

[0071] The embodiments of the present disclosure provide a semiconductor structure, the write transistor 10 comprises a write bit line 104 extending in a first direction Y and a write word line 103 extending in a second direction Z; the read transistor 11 comprises a read bit line 114 extending in the second direction Z and a read word line 116 extending in the first direction Y, the read bit line 114, the read word line 116, the write word line 103 and the write bit line 104 do not overlap each other in the orthographic projection of the substrate, and the write bit line 104 and the read word line 116 are located on both sides of the first semiconductor layer 101 along a third direction X, and the write bit line 104 and the read word line 116 are located on both sides of the second semiconductor layer 111 along the third direction X, wherein the write bit line 104 and the read word line 116 can adopt a step structure in a conventional structure, to reduce the interference between the write bit line 104 and the write word line 103 and the interference between the read bit line 114 and the read word line 116; the read bit line 114, the read word line 116, the write word line 103 and the write bit line 104 do not overlap each other in the orthographic projection of the substrate, and the write bit line 104 and the read word line 116 are located on both sides of the first semiconductor layer 101 along the third direction X, and the write bit line 104 and the read word line 116 are located on both sides of the second semiconductor layer 111 along the third direction X, so that the read transistor 11 and the write transistor 10 do not affect each other, and the distance between the write bit line 104 and the read word line 116 is far, thereby avoiding read-write crosstalk between cells.

[0072] Accordingly, another aspect of the present disclosure provides a semiconductor structure according to some embodiments of the present disclosure, which is different from the semiconductor structure described in the above embodiment in that the read word line and the second semiconductor layer are in direct electrical contact, and the same or corresponding technical features of the above embodiment are not repeated here.

[0073] Figure 3 A structural schematic diagram of another semiconductor structure according to an embodiment of the present disclosure is provided. Figure 4 For Figure 3 A circuit diagram of a corresponding semiconductor structure.

[0074] Referring to Figure 3 , the present embodiment provides a semiconductor structure, comprising: a substrate; a write transistor 20 on the substrate, the write transistor 20 comprising a first gate, a first semiconductor layer 201 surrounding the first gate, a write bit line 204 extending along a first direction Y, and a write word line 203 extending along a second direction Z, the first semiconductor layer 201 comprising a first end 206 and a second end 207 opposite to each other along a third direction X, the write bit line 204 being in electrical contact with the first end 206, and the write word line 203 being in electrical contact with the first gate; and a read transistor 21, the read transistor 21 comprising a second semiconductor layer 211, a second gate 213, a read bit line 214 extending along the second direction Z, and a read word line 216 extending along the first direction Y, the second gate 213 being in electrical contact with the second end 207, and the read bit line 214 being in electrical contact with one end of the second semiconductor layer 211 along the first direction Y; wherein the read bit line 214, the read word line 216, the write word line 203, and the write bit line 204 do not overlap with each other in the orthographic projection of the substrate, and the write bit line 204 and the read word line 216 are located on two sides of the first semiconductor layer 201 along the third direction X.

[0075] Referring to Figure 3 , the read word line 216 extends along the second direction Z, and the read word line 216 is in electrical contact with a fourth end 224 of the second semiconductor layer.

[0076] In some embodiments, the read word line is located on one side of the second semiconductor layer 111 along the third direction X, and the read word line is in electrical contact with one side of the second semiconductor layer along the third direction X. The third end of the second semiconductor layer has a read bit line, and the fourth end can have another read bit line, i.e., the read transistor comprises a transistor comprising two channel regions.

[0077] In some embodiments, the material of the read word line 216 comprises a metal material of copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, or an alloy thereof.

[0078] In some embodiments, referring to Figure 4The write transistor 20 and the read transistor 21 form a 2T OC structure. The write transistor 20 includes a first pin W1, a second pin W2 and a third pin W3. The first pin W1 is a first source-drain end of the write transistor 20, and the first pin W1 is electrically connected with a write bit line WBL. The second pin W2 is a second source-drain end of the write transistor 20, and the second pin W2 is electrically connected with a second gate of the write transistor 20. The third pin W3 is a gate end of the write transistor 20, and the third pin W3 is electrically connected with a write word line WWL. The read transistor 21 includes a first end point R1, a second end point R2 and a third end point R3. The first end point R1 is a third source-drain end of the read transistor 21, and the first end point R1 is electrically connected with a read bit line RBL. The second end point R2 is a fourth source-drain end of the read transistor 21, and the second end point R2 is electrically connected with a read word line RWL. The third end point R3 is a gate control end of the read transistor 21, and the first gate control end is electrically connected with the second pin W2 of the write transistor 20.

[0079] Reference Figure 4 The working principle of the read transistor 21 and the write transistor 20 is as follows: a large voltage is applied to the gate of the write transistor 20 through the write word line WWL to turn on the write transistor 20. When "1" needs to be written, a first voltage is applied to the write bit line WBL. When "0" needs to be written, a second voltage is applied to the write bit line WBL. The first voltage and the second voltage have a certain voltage difference. Whether the read data is "1" or "0" is determined by judging whether there is current passing between the read bit line RBL and the read word line RWL.

[0080] Figure 3 The write transistor 20, the first semiconductor layer 201, the first gate, the write bit line 204, the write word line 203, the first gate dielectric layer 202, the read transistor 21, the second semiconductor layer 211, the second gate 213, the second gate dielectric layer 212, the read bit line 214 and the first filling layer 205 in the semiconductor structure shown in the figure can refer to the write transistor 10, the first semiconductor layer 101, the first gate, the write bit line 104, the write word line 103, the first gate dielectric layer 102, the read transistor 11, the second semiconductor layer 111, the second gate 113, the second gate dielectric layer 112, the read bit line 214 and the first filling layer 105 in the above-mentioned embodiments, and here will not be described in detail.

[0081] The semiconductor structure provided by the embodiments of the present disclosure includes a write transistor 20, which comprises a write bit line 204 extending in a first direction Y and a write word line 203 extending in a second direction Z; and a read transistor 21, which comprises a read bit line 214 extending in the second direction Z and a read word line 216 extending in the first direction Y. The read bit line 214, the read word line 216, the write word line 203 and the write bit line 204 do not overlap with each other in the orthographic projection of the substrate, and the write bit line 204 and the read word line 216 are located on both sides of the first semiconductor layer 201 along a third direction X, and the write bit line 204 and the read word line 216 are located on both sides of the second semiconductor layer 211 along the third direction X. The write bit line 204 and the read word line 216 can adopt a stepped structure in a conventional structure, so as to reduce the interference between the write bit line 204 and the write word line 203 and the interference between the read bit line 214 and the read word line 216. The read bit line 214, the read word line 216, the write word line 203 and the write bit line 204 do not overlap with each other in the orthographic projection of the substrate, and the write bit line 204 and the read word line 216 are located on both sides of the first semiconductor layer 201 along the third direction X, and the write bit line 204 and the read word line 116 are located on both sides of the second semiconductor layer 211 along the third direction X. It can be seen that the read transistor 21 and the write transistor 20 do not affect each other, and the distance between the write bit line 204 and the read word line 216 is far, so as to avoid the read-write crosstalk between the units.

[0082] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a storage array structure composed of the semiconductor structure shown in the above embodiments. The same or corresponding technical features as the above embodiments will not be described herein again. Figure 1 The semiconductor structure shown in the above embodiments is taken as an example.

[0083] Figure 5 A first structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure is shown in FIG. 2. Figure 6 A second structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure is shown in FIG. 3. Figure 5 A top view of the corresponding storage array structure is shown in FIG. 4. Figure 7 A circuit diagram of the corresponding storage array structure is shown in FIG. 5. Figure 5 A third structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure is shown in FIG. 6. Figure 8 A fourth structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure is shown in FIG. 7. Figure 9 A fifth structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure is shown in FIG. 8. Figure 10 A sixth structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure is shown in FIG. 9. Figure 11 A sixth structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure is shown in FIG. 9.

[0084] Figure 12 A sixth structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure is shown in FIG. 9.Figure 13 Fig. 2 is a schematic diagram of a partial structure corresponding to the protrusion in Fig. 1. Figure 12 Fig. 3 is a schematic diagram of a partial structure corresponding to the protrusion in Fig. 1.

[0085] Fig. 4 is a schematic diagram of a partial structure corresponding to the protrusion in Fig. 1. Figure 5 Referring to Fig. 4, the storage array structure includes: a plurality of semiconductor structures arranged in an array along a first direction Y and along a second direction Z, a write word line 103 electrically connected to a plurality of first gates arranged along the second direction Z, and a write bit line 104 electrically connected to a first end of a plurality of first semiconductor layers 101 arranged along the first direction Y; a read transistor 11 located on one side of the first semiconductor layer 101 of the corresponding write transistor 10 along a third direction X; a read bit line 114 electrically connected to a third end of a plurality of second semiconductor layers 111 arranged along the second direction Z, and a read word line 116 located on one side of a plurality of second semiconductor layers 111 arranged along the first direction Y; a projection of at least two write bit lines 104 on the substrate overlaps; and / or a projection of at least two read word lines 116 on the substrate overlaps, which can save the unit configuration size of the read word line 116 and the write bit line 104, i.e., there is a spatial overlap in the vertical space, so as to save the floor area and floor size in the two-dimensional space and improve the integration of the semiconductor structure in the horizontal direction.

[0086] In some embodiments, the projection overlap includes two aspects: first, the area of the projection is completely consistent with the contour, i.e., the projections completely overlap (see Fig. 2); second, the area of the projection is not completely consistent with the contour, i.e., the larger area covers the smaller area, i.e., the projections overlap each other (see Fig. 3). Figure 5 Figure 12 In some embodiments, referring to Fig. 4, the plurality of semiconductor structures arranged in an array along the first direction Y and along the second direction Z form an array structure, the array structure includes a first array structure 13 and a second array structure 14 arranged along the third direction X; the first array structure 13 and the second array structure 14 are axisymmetric along a median line M1-M2 of the read word line 116; and / or the first array structure 13 and the second array structure 14 are axisymmetric along a median line N1-N2 of the write bit line 104. In this way, the first array structure 13 and the second array structure 14 can share the read word line 116 and the write bit line 104, thereby saving the floor area and floor size in the two-dimensional space and improving the integration of the semiconductor structure in the horizontal direction.

[0087] In some embodiments, referring to Fig. 4, the plurality of semiconductor structures arranged in an array along the first direction Y and along the second direction Z form an array structure, the array structure includes a first array structure 13 and a second array structure 14 arranged along the third direction X; the first array structure 13 and the second array structure 14 are axisymmetric along a median line M1-M2 of the read word line 116; and / or the first array structure 13 and the second array structure 14 are axisymmetric along a median line N1-N2 of the write bit line 104. In this way, the first array structure 13 and the second array structure 14 can share the read word line 116 and the write bit line 104, thereby saving the floor area and floor size in the two-dimensional space and improving the integration of the semiconductor structure in the horizontal direction. Figure 6 In some embodiments, referring to Fig. 4 or Fig. 5, the array structure further includes a plurality of contact structures 108, the contact structure 108 is in electrical contact with a connection line, and the connection line is one of the read word line 116 or the write bit line 104.

[0088] Figure 7 Figure 9

[0089] ​​​​In some embodiments, the contact structure 108 is used to connect the read word line 116 or the write bit line 104 in the semiconductor structure with an external element to achieve positioning to a specific memory cell by regulating the external element to control the read word line 116 or the write bit line 104 in the semiconductor structure, thereby performing relevant reading and writing.

[0090] In some embodiments, the material of the contact structure 108 includes a metal material of copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten or an alloy thereof.

[0091] With reference to Figure 7 , the memory array structure further includes an isolation structure 109 located between the partial connection line and the contact structure 108.

[0092] With reference to Figure 7 or Figure 9 , the other of the read word line 116 or the write bit line 104 includes a body portion extending along the first direction Y, and a connection portion extending along the third direction X, the body portion being located between the first array structure 13 and the second array structure 14, the connection portion being located at one side of the body portion along the first direction Y, the connection portion being electrically connected with the plurality of body portions, and further including a selection transistor 33, one side of the selection transistor 33 being electrically connected with the connection portion, and the other side of the selection transistor 33 being electrically connected with the body portion.

[0093] In some embodiments, the selection transistor 33 includes a third semiconductor layer 331, a fourth gate dielectric layer 332 and a gate conductive layer 333.

[0094] In some embodiments, with reference to Figure 8 , the read word line 116 includes a first body portion 1161 extending along the first direction Y, and a first connection portion 1162 extending along the third direction X, the first body portion 1161 being located between the first array structure 13 and the second array structure 14, the first connection portion 1162 being located at one side of the first body portion 1161 along the first direction Y, the first connection portion 1162 being electrically connected with the plurality of first body portions 1161, and further including a selection transistor 33, one side of the selection transistor 33 being electrically connected with the first connection portion 1162, and the other side of the selection transistor 33 being electrically connected with the first body portion 1162.

[0095] In some embodiments, with reference to Figure 9The write bit line 104 includes a second body portion 1041 extending along the first direction Y, and a second connecting portion 1042 extending along the third direction X. The second body portion 1041 is electrically connected to the first ends of the plurality of first semiconductor layers 101 arranged along the first direction Y. The first connecting portion 1042 is located at one side of the second body portion 1041 along the first direction Y, and is electrically connected to the plurality of second body portions 1041. One side of the selection transistor 33 is electrically connected to the second connecting portion 1042, and the other side of the selection transistor 33 is electrically connected to the second body portion 1041.

[0096] Referring to Figure 10 In some embodiments, the read word line 116 includes a first body portion 1161 extending along the first direction Y, and a first connecting portion 1162 extending along the third direction X. The first body portion 1161 is located between the first array structure 13 and the second array structure 14. The first connecting portion 1162 is located at one side of the first body portion 1161 along the first direction Y, and is electrically connected to the plurality of first body portions 1161. The first selection transistor 35 has one side electrically connected to the first connecting portion 1162, and the other side electrically connected to the first body portion 1161. The write bit line 104 includes a second body portion 1041 extending along the first direction Y, and a second connecting portion 1042 extending along the third direction X. The second body portion 1041 is electrically connected to the first ends of the plurality of first semiconductor layers 101 arranged along the first direction Y. The first connecting portion 1042 is located at one side of the second body portion 1041 along the first direction Y, and is electrically connected to the plurality of second body portions 1041. The second selection transistor 36 has one side electrically connected to the second connecting portion 1042, and the other side electrically connected to the second body portion 1041.

[0097] Referring to Figure 11 In some embodiments, the read word line 116 includes a first body portion 1161 extending along the first direction Y, and a first connecting portion 1162 extending along the third direction X. The first body portion 1161 is located between the first array structure 13 and the second array structure 14. The first connecting portion 1162 is located at one side of the first body portion 1161 along the first direction Y, and is electrically connected to the plurality of first body portions 1161. The first selection transistor 35 has one side electrically connected to the first connecting portion 1162, and the other side electrically connected to the first body portion 1161. The write bit line 104 includes a second body portion 1041 extending along the first direction Y, and a second connecting portion 1042 extending along the third direction X. The second body portion 1041 is electrically connected to the first ends of the plurality of first semiconductor layers 101 arranged along the first direction Y. The first connecting portion 1042 is located at one side of the second body portion 1041 along the first direction Y, and is electrically connected to the plurality of second body portions 1041. The second selection transistor 36 has one side electrically connected to the second connecting portion 1042, and the other side electrically connected to the second body portion 1041.

[0098] The first selection transistor 35 includes a first active layer 351, a first gate oxide layer 352, and a first gate conductive layer 353 arranged in sequence. The second selection transistor 36 includes a second active layer 361, a second gate oxide layer 362, and a second gate conductive layer 363 arranged in sequence.

[0099] In some embodiments, the first connecting portion 1162 and the second connecting portion 1042 are located at two sides of the array structure along the first direction Y.

[0100] Referring to Figure 12 and Figure 13In some embodiments, the connection line has a protrusion 17 at one end along the first direction Y, the protrusion 17 decreasing in length along the first direction Y in a direction along the third direction X towards the substrate, each contact structure 108 being in contact with the protrusion 17; the protrusion 17 comprises adjacent first, second and third protrusions 171, 172 and 173, the length of the second protrusion 172 being greater than the length of the first protrusion 171, and the orthogonal projection of the contact structure 108 in electrical contact with the second protrusion 172 on the substrate does not overlap the orthogonal projection of the first protrusion 171 on the substrate.

[0101] The contact structure 108 comprises a first plug 161 in electrical contact with the first protrusion, a second plug 162 in electrical contact with the second protrusion, and a third plug 163 in electrical contact with the third protrusion.

[0102] Correspondingly, the disclosure also provides a method for manufacturing a semiconductor structure, which has the same or corresponding technical features as the above embodiments, and will not be described in detail here. Figures 14-28 The method for manufacturing a semiconductor structure provided by another embodiment of the disclosure comprises the steps of providing a substrate, sequentially forming a first film layer and a second film layer on the surface of the substrate, and patterning the first film layer and the second film layer to expose the substrate.

[0103] It should be noted that, Figures 14-28 The method for manufacturing a semiconductor structure provided by another embodiment of the disclosure comprises the steps of providing a substrate, sequentially forming a first film layer and a second film layer on the surface of the substrate, and patterning the first film layer and the second film layer to expose the substrate.

[0104] Referring to Figure 14 and Figure 15 , the method comprises the steps of providing a substrate, sequentially forming a first film layer and a second film layer on the surface of the substrate, and patterning the first film layer and the second film layer to expose the substrate.

[0105] In some embodiments, the first film layer and the second film layer have different etching rates in the same etching process. The material of the first film layer comprises silicon oxide, and the material of the second film layer comprises silicon nitride.

[0106] Referring to Figure 16 , the first film layer and the second film layer are patterned to form a first recess exposing the substrate.

[0107] Figure 17 For Figure 16 the cross-sectional structure along the A1-A2 section; Figure 18 For Figure 16 the cross-sectional structure along the B1-B2 section.

[0108] Referring to Figure 17 , a portion of the second film layer 182 along the first groove is etched laterally to increase the width of the first groove 183 corresponding to the second film layer 182.

[0109] Figure 19 A method for manufacturing a semiconductor structure according to another embodiment of the present disclosure includes forming a semiconductor structure corresponding to a write transistor along a cross section A1-A2 (see Figure 16 ) of a structure schematic diagram. Figure 20 A method for manufacturing a semiconductor structure according to another embodiment of the present disclosure includes forming a semiconductor structure corresponding to a write transistor along a cross section B1-B2 (see Figure 16 ) of a structure schematic diagram. Figure 21 A method for manufacturing a semiconductor structure according to another embodiment of the present disclosure includes forming a semiconductor structure corresponding to a write bit line along a cross section A1-A2 (see Figure 16 ) of a structure schematic diagram. Figure 22 A method for manufacturing a semiconductor structure according to another embodiment of the present disclosure includes removing a semiconductor structure corresponding to a second film layer along a cross section B1-B2 (see Figure 16 ) of a structure schematic diagram.

[0110] Referring to Figures 19-21 , a write transistor 10 is formed on a substrate, the write transistor 10 includes a first gate, a first semiconductor layer 101 surrounding the first gate, a write bit line 104 extending along a first direction Y, and a write word line 103 extending along a second direction Z, the first semiconductor layer 101 includes a first end and a second end opposite to each other along a third direction X, the write bit line 104 is in electrical contact with the first end, and the write word line 103 is in electrical contact with the first gate.

[0111] Referring to Figure 19 , the first semiconductor layer 101, a first gate dielectric layer 102, and the write word line 103 are sequentially formed, the first semiconductor layer 101 and the first gate dielectric layer 102 are located between the first film layer 181 and the first film layer 181, and the write word line 103 fills the first groove 183 (see Figure 18 ). In the process of forming the write word line 103, a first gate is formed, the material of the first gate is the same as that of the write word line 103, and the first gate and the write word line 103 are the same feature.

[0112] Referring to Figure 21 , a portion of the second film layer 182 is laterally removed until the side surface of the first semiconductor layer 101 is exposed.

[0113] Continuing to refer to Figure 21 , the write bit line 104 is formed, and the write bit line 104 is located between the first film layer 181 and the first film layer 181.

[0114] With reference back to Figure 21 , the second film layer 182 (refer to Figure 20 ) is removed by part of the width, but the side surface of the write bit line 104 is not exposed, that is, the second film layer still serves as the first filling layer 105 (refer to Figure 1 ) between the write bit line 104 and the subsequently formed read bit line 114.

[0115] With reference back to Figures 23-28 , the preparation method comprises: preparing a read transistor 11 located at one side of the first semiconductor layer 101 along the third direction X; the read transistor 11 comprises a second semiconductor layer 111, a second gate 113, a read bit line 114 extending along the second direction Z, and a read word line 116 extending along the first direction Y, the second gate 113 is in electrical contact with the second end, the read bit line 114 is in electrical contact with one end of the second semiconductor layer 111 along the first direction Y, and the read word line 116 is located at one side of the second semiconductor layer 111 along the third direction X; wherein the read bit line 114, the read word line 116, the write word line 103, and the write bit line 104 do not overlap each other in the orthogonal projection of the substrate.

[0116] Figure 23 A preparation method of a semiconductor structure provided by another embodiment of the present disclosure forms a semiconductor structure corresponding to the second semiconductor layer along the A1-A2 cross section (refer to Figure 16 ). Figure 24 A preparation method of a semiconductor structure provided by another embodiment of the present disclosure forms a semiconductor structure corresponding to the second semiconductor layer along the B1-B2 cross section (refer to Figure 16 ).

[0117] With reference back to Figure 23 , the second gate 113, the second gate dielectric layer 113, and the second semiconductor layer 111 are sequentially formed around the first semiconductor layer 101.

[0118] With reference back to Figure 23 , the third film layer 184 is formed between adjacent first film layers 181, the third film layer 184 surrounds the second semiconductor layer 111, and the third film layer 184 is located at the side surface of the second film layer 182.

[0119] Figure 25 A preparation method of a semiconductor structure provided by another embodiment of the present disclosure forms a semiconductor structure corresponding to the second recess along the B1-B2 cross section (refer to Figure 16 ).

[0120] With reference to 25, the second recess 185 is formed, the second recess 185 penetrates the first film layer 181 and the fourth film layer 184 until the surface of the substrate is exposed, and the second recess 185 exposes the side surface of the second semiconductor layer 111.

[0121] Figure 26 A method for manufacturing a semiconductor structure according to yet another embodiment of the present disclosure includes forming a semiconductor structure corresponding to a read bit line along a B1-B2 cross section (see FIG. 6B). Figure 16 ) structure schematic diagram.

[0122] Referring to Figure 26 , the read bit line 114 and the conductive layer 117 are formed, the conductive material filling one of the second grooves 185 as the read bit line 114, and the conductive material filling the other of the second grooves 185 as the conductive layer 117.

[0123] Figure 27 A method for manufacturing a semiconductor structure according to yet another embodiment of the present disclosure includes removing a semiconductor structure corresponding to a third film layer along an A1-A2 cross section (see FIG. 6A). Figure 16 ) structure schematic diagram.

[0124] Referring to Figure 27 , the third film layer 184 beyond the side surface of the read bit line 114 and the conductive layer 117 is removed.

[0125] Figure 28 A method for manufacturing a semiconductor structure according to yet another embodiment of the present disclosure includes forming a semiconductor structure corresponding to a read word line along an A1-A2 cross section (see FIG. 6A). Figure 16 ) structure schematic diagram.

[0126] Referring to Figure 28 , the third gate dielectric layer 115 and the read word line 116 are formed, the third gate dielectric layer 115 and the read word line 116 being between the first film layer 181 and the first film layer 181.

[0127] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present disclosure, therefore the protection scope of the present disclosure should be limited by the scope defined in the claims.

Claims

1.A semiconductor structure, comprising: a substrate; a write transistor on the substrate, the write transistor comprising a first gate, a first semiconductor layer surrounding the first gate, a write bit line extending in a first direction, and a write word line extending in a second direction, the first semiconductor layer comprising a first end and a second end opposite to each other in a third direction, the write bit line being in electrical contact with the first end, and the write word line being in electrical contact with the first gate; a read transistor, the read transistor comprising a second semiconductor layer, a second gate, a read bit line extending in the second direction, and a read word line extending in the first direction, the second gate being in electrical contact with the second end, the read bit line being in electrical contact with one end of the second semiconductor layer in the first direction, and the read word line being on one side of the second semiconductor layer in the third direction; wherein the read bit line, the read word line, the write word line, and the write bit line do not overlap with each other in a projection of the substrate, and the write bit line and the read word line are on two sides of the first semiconductor layer in the third direction, and the write bit line and the read word line are on two sides of the second semiconductor layer in the third direction; the read transistor further comprising a conductive layer extending in the second direction, and a third gate, the third gate being on one side of the second semiconductor layer in the third direction, the read word line being in electrical contact with the third gate, and the second semiconductor layer comprising a third end and a fourth end opposite to each other in the first direction, the read bit line being in electrical contact with the third end, and the conductive layer being in electrical contact with the fourth end. 2.The semiconductor structure of claim 1, wherein the read word line is in electrical contact with one side of the second semiconductor layer in the third direction. 3.A memory array structure, comprising the semiconductor structure of claim 1 or 2, wherein a plurality of the semiconductor structures are arranged in an array in the first direction and in the second direction, the write word line is electrically connected to a plurality of the first gates arranged in the second direction, and the write bit line is electrically connected to the first ends of a plurality of the first semiconductor layers arranged in the first direction; the read transistor is on one side of the first semiconductor layer of the corresponding write transistor in the third direction; the read bit line is electrically connected to the third ends of a plurality of the second semiconductor layers arranged in the second direction, and the read word line is on one side of a plurality of the second semiconductor layers arranged in the first direction; the projections of at least two of the write bit lines on the substrate overlap with each other; and / or the projections of at least two of the read word lines on the substrate overlap with each other. 4.The memory array structure of claim 3, wherein a plurality of the semiconductor structures arranged in the first direction and in the second direction form an array structure, the array structure comprising a first array structure and a second array structure arranged in the third direction; the first array structure and the second array structure are axisymmetric along a median line of the read word line; and / or the first array structure and the second array structure are axisymmetric along a median line of the write bit line. ​ ​ ​ ​ 5.The memory array structure of claim 4, wherein, further comprising: a plurality of contact structures, the contact structures in electrical contact with the connection line, the connection line being one of the read word line or the write bit line. 6.The memory array structure of claim 5, wherein, the connection line has a protrusion at one end along the first direction, the protrusion decreasing in length along the first direction towards the substrate, each contact structure in contact with the protrusion; the protrusion comprises a first protrusion and a second protrusion, the second protrusion having a length greater than the first protrusion, the contact structure in electrical contact with the second protrusion not overlapping the first protrusion in the projection on the substrate. 7.The memory array structure of claim 5, wherein, the other one of the read word line or the write bit line comprises: a body portion extending along the first direction; a connection portion extending along the third direction, the body portion between the first array structure and the second array structure, the connection portion on one side of the body portion along the first direction, the connection portion electrically connecting a plurality of the body portions; further comprising: a select transistor, one side of the select transistor in electrical contact with the connection portion, another side of the select transistor in electrical contact with the body portion. 8.The memory array structure of claim 5 or 6, wherein, comprising: a first contact structure in electrical contact with the read word line and a second contact structure in electrical contact with the write bit line. 9.The memory array structure of claim 4, wherein, the read word line comprises: a first body portion extending along the first direction; a first connection portion extending along the third direction, the first body portion between the first array structure and the second array structure, the first connection portion on one side of the first body portion along the first direction, the first connection portion electrically connecting a plurality of the first body portions; further comprising: a first select transistor, one side of the first select transistor in electrical contact with the first connection portion, another side of the first select transistor in electrical contact with the first body portion; the write bit line comprises: a second body portion extending along the first direction; a second connection portion extending along the third direction, the second body portion electrically connecting a first end of a plurality of the first semiconductor layers arranged along the first direction, the first connection portion on one side of the second body portion along the first direction, the first connection portion electrically connecting a plurality of the second body portions; further comprising: a second select transistor, one side of the second select transistor in electrical contact with the second connection portion, another side of the second select transistor in electrical contact with the second body portion. 10.The memory array structure of claim 9, wherein, the first connection portion and the second connection portion are on two sides of the array structure along the first direction. 11.A method for manufacturing a semiconductor structure, comprising: providing a substrate; ​ forming a write transistor and a read transistor, the write transistor being located on the substrate, the write transistor comprising a first gate, a first semiconductor layer surrounding the first gate, a write bit line extending along a first direction, and a write word line extending along a second direction, the first semiconductor layer comprising a first end and a second end opposite along a third direction, the write bit line being in electrical contact with the first end, the write word line being in electrical contact with the first gate; the read transistor being located on a side of the first semiconductor layer along the third direction, the read transistor comprising a second semiconductor layer, a second gate, a read bit line extending along a second direction, and a read word line extending along a first direction, the second gate being in electrical contact with the second end, the read bit line being in electrical contact with an end of the second semiconductor layer along the first direction, the read word line being located on a side of the second semiconductor layer along a third direction; wherein the read bit line, the read word line, the write word line, and the write bit line do not overlap with each other in the orthographic projection on the substrate; the read transistor further comprising a conductive layer extending along the second direction and a third gate, the third gate being located on a side of the second semiconductor layer along the third direction, the read word line being in electrical contact with the third gate, the second semiconductor layer comprising a third end and a fourth end opposite along the first direction, the read bit line being in electrical contact with the third end, the conductive layer being in electrical contact with the fourth end.

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