Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The method comprises the steps of providing a substrate; a laminated structure is formed on the substrate, the laminated structure comprises first stacking layers and second stacking layers which are alternately stacked on the substrate in the first direction, and the first direction intersects with the plane where the substrate is located; forming a first hole groove and a second hole groove which extend along the first direction in the laminated structure; forming an oxide active layer in the first hole groove; forming a gate structure in the first hole groove in which the oxide active layer is formed; and annealing the semiconductor structure in an oxygen environment, enabling oxygen to enter the first stacking layer through the second hole groove, and enabling oxygen in the first stacking layer to move into the oxide active layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a semiconductor device, a dynamic random access memory, and a manufacturing method thereof. Background Art

[0002] The development of dynamic random access memories (DRAMs) pursues performance indicators such as high speed, high integration density, and low power consumption. As the structural dimensions of semiconductor devices are scaled down, the technical barriers encountered by existing structures are becoming increasingly obvious. Therefore, developing more novel structures based on existing structures is an effective means to break through the existing technical barriers.

[0003] The emergence of three-dimensional dynamic random access memories (3D DRAMs), especially 3D DRAMs including multilayer horizontal cells (MHCs), which typically include multiple transistors stacked on a substrate, meets the above requirements.

[0004] In current 3D DRAM structures, new technical routes have been developed, and oxide semiconductor materials are applied as the active layer in transistors to prepare 3D DRAM structures. Summary of the Invention

[0005] According to a first aspect of the embodiments of the present disclosure, a method for preparing a semiconductor structure is provided, including:

[0006] Providing a substrate; the substrate has a stacked structure, the stacked structure includes a first stacked layer and a second stacked layer alternately stacked on the substrate along a first direction, and the first direction intersects the plane of the substrate;

[0007] Forming a first via trench and a second via trench extending along the first direction in the stacked structure;

[0008] Forming an oxide active layer in the first via trench;

[0009] Forming a gate structure in the first via trench where the oxide active layer is formed;

[0010] Annealing the semiconductor structure in an oxygen environment, the oxygen enters the first stacked layer through the second via trench, and oxygen in the first stacked layer moves to the oxide active layer.

[0011] In some embodiments, it further includes: filling a thermally conductive polymer in the second via trench.

[0012] In some embodiments, a bit line structure is formed in the second stacked layer, and the bit line structure is electrically connected to the oxide active layer.

[0013] In some embodiments, a storage node is formed in the second stacked layer, and the storage node is electrically connected to the oxide active layer.

[0014] In some embodiments, at least a portion of the oxide active layer corresponding to the first stacked layer is removed.

[0015] In some embodiments, titanium nitride is included in the gate structure and / or the bit line structure.

[0016] In some embodiments, the first stacked layer includes an oxide insulating material.

[0017] In some embodiments, the oxide active layer includes one or more of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, gallium oxide, or tin oxide.

[0018] In some embodiments, the temperature of the annealing step is 350 degrees Celsius to 450 degrees Celsius, and the duration is 1.5 hours to 2.5 hours.

[0019] According to a second aspect of the embodiments of the present disclosure, a semiconductor structure is provided which is prepared according to the foregoing preparation method.

[0020] On the one hand, the embodiments provided by the present disclosure can repair the oxide active layer by annealing in an oxygen environment, thereby improving the electrical performance of the device; on the other hand, filling the second via with a thermally conductive polymer can improve the heat dissipation performance of the device and improve the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of a semiconductor device shown according to an exemplary embodiment;

[0022] Figure 2a is a schematic diagram of a semiconductor device shown according to an exemplary embodiment along a plane passing through the gate structure in the D1-D2 direction;

[0023] Figure 2b is a schematic diagram of a semiconductor device shown according to an exemplary embodiment along a plane passing through the gate structure and the heat dissipation structure in the D1-D3 direction;

[0024] Figures 3 - 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 22 is a schematic diagram of a position of a gate structure along a plane passing through the D1-D2 direction in a certain step of a preparation method of a semiconductor device shown according to an exemplary embodiment;

[0025] Figure 10 ,Figure 12 , Figure 14 , Figure 16 , Figures 18 - 21 , Figures 23 - 24 is a schematic diagram of a certain step in the method for manufacturing a semiconductor device shown according to an exemplary embodiment, passing through the positions of the gate structure and the heat conduction structure along the plane where D1 - D3 are located. Detailed implementation manners

[0026] Hereinafter, the technical solutions of the present disclosure will be further elaborated in detail in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art.

[0027] In the following paragraphs, the present disclosure will be described more specifically by way of example with reference to the drawings. The advantages and features of the present disclosure will be clearer according to the following description and the claims. It should be noted that the drawings are all in a very simplified form and use non - precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present disclosure.

[0028] It can be understood that the meanings of "on...", "above...", and "over..." in the present disclosure should be interpreted in the broadest way, so that "on..." not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.

[0029] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0030] In the embodiments of the present disclosure, the term "layer" refers to a part of a material including a region having a thickness. The layer can extend over the entire structure below or above, or can have a range smaller than the range of the structure below or above. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include multiple sub - layers.

[0031] It should be noted that, without conflict, the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily.

[0032] According to the first aspect of the embodiments of the present disclosure, as Figure 1 , Figure 2aAnd Figure 2b As shown, a semiconductor structure 10 is disclosed, including a substrate 100 and a memory array structure stacked on the substrate along a first direction (D1) and arranged along a second direction (D3). The first direction (D1) intersects with the plane where the substrate is located, the second direction (D2) is parallel to the plane where the substrate is located, and the third direction (D2) intersects with the second direction and is parallel to the plane where the substrate is located.

[0033] In some embodiments, the substrate is selected from semiconductor materials such as single crystal silicon, silicon germanium, silicon carbide, or silicon on insulator.

[0034] In some embodiments, the substrate may include pre-formed structures therein, such as select transistors or connection structures disposed in substrate vias, etc.

[0035] In some embodiments, there are multiple memory array structures, which are disposed on the substrate in pairs along the second direction (D2), and a protective layer P1 is filled between the memory array structures.

[0036] In some embodiments, the protective layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and their combinations, etc.

[0037] The memory array structure includes multiple memory cells. The memory cells include transistors 800 and memory nodes 600. The transistors include oxide active layers 200 and gate structures 400. The memory nodes are electrically connected to the oxide active layers. The layers of the memory array structure are spaced apart by interlayer insulating layers S1. The gate structures of the memory cells corresponding to different layers are connected in the D1 direction, and the memory cells arranged in the same layer are electrically connected to the same bit line structure 500 extending along the D3 direction. The memory array structure further includes a heat conduction structure 300, which extends along the D1 direction and includes a material with high thermal conductivity.

[0038] In some embodiments, the heat conduction structure includes a heat-conducting polymer.

[0039] In some embodiments, the heat conduction structure is in direct contact with the bit line structure.

[0040] In some embodiments, a pseudo-oxide active layer is provided between the heat conduction structure and the bit line structure.

[0041] In some embodiments, the memory node is selected from one or more of a storage capacitor, a phase change memory, a magnetoresistive memory, or a ferroelectric memory, etc. Here, taking the memory node as a storage capacitor as an example, the storage capacitor includes a lower electrode, a capacitive dielectric layer, and an upper electrode. The lower electrode of the storage capacitor is electrically connected to the oxide active layer of the transistor, the capacitive dielectric layer covers the lower electrode, the upper electrode covers the capacitive dielectric layer, and multiple storage capacitors share the upper electrode.

[0042] In some embodiments, the capacitive dielectric layer of the storage capacitor is selected from at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate to form, or includes, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0043] In some embodiments, the lower electrode of the storage capacitor comprises a metal, metal nitride, metal oxide, metal silicide, conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or a non-metallic material such as polysilicon, indium gallium tin oxide, indium tin oxide, or a combination thereof.

[0044] In some embodiments, the lower electrode of the storage capacitor is titanium nitride.

[0045] In some embodiments, the upper electrode of the storage capacitor comprises a metal, metal nitride, metal oxide, metal silicide, conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or a non-metallic material such as polysilicon, indium gallium tin oxide, indium tin oxide, or a combination thereof.

[0046] In some embodiments, the upper electrode of the storage capacitor is a multi-layer structure of titanium nitride and polysilicon.

[0047] In some embodiments, the oxide active layer comprises one or more of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, gallium oxide, or tin oxide.

[0048] In some embodiments, the interlayer insulating layer comprises an oxide insulating material.

[0049] In some embodiments, the interlayer insulating layer comprises silicon oxide, silicon oxynitride, and combinations thereof, or a metal oxide such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof, etc.

[0050] In some embodiments, the material of the interlayer insulating layer is silicon oxide.

[0051] In some embodiments, the gate structure comprises a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or a non-metallic material such as polysilicon, indium gallium tin oxide, indium tin oxide, or a combination thereof.

[0052] In some embodiments, the gate structure comprises a gate electrode and a gate insulating layer.

[0053] In some embodiments, the gate electrode is titanium nitride.

[0054] In some embodiments, the gate electrode is a stacked structure of titanium nitride and tungsten, and the titanium nitride is disposed as a barrier layer between the tungsten and the gate insulating layer.

[0055] In some embodiments, the material of the gate insulating layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a metal oxide such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof.

[0056] In some embodiments, the bit line structure comprises a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or a non-metallic material such as polysilicon, indium gallium tin oxide, indium tin oxide, or a combination thereof.

[0057] In some embodiments, the bit line structure comprises a bit line electrode and a lead pad electrically connected thereto.

[0058] In some embodiments, the bit line electrode is titanium nitride.

[0059] In some embodiments, the semiconductor structure is a component of a three-dimensional dynamic random access memory, and the three-dimensional dynamic random access memory further includes a sense amplifier (SA) and a word line driver (WD). The gate structure is electrically connected to the word line driver, and the bit line structure is connected to the sense amplifier.

[0060] According to a second aspect of the embodiments of the present disclosure, as Figures 3 - 24 shown, a method for manufacturing a semiconductor structure is disclosed. Combining Figure 1 , Figure 2a and Figure 2bUnderstand. Provide a substrate 100; the substrate is formed with a stacked structure 700, the stacked structure includes a first stacked layer M1 and a second stacked layer M2 alternately stacked on the substrate along a first direction; a first via V1 and a second via V2 extending along the first direction are formed in the stacked structure; an oxide active layer 200 is formed in the first via; a gate structure 400 is formed in the first via where the oxide active layer is formed; the semiconductor structure is annealed T in an oxygen environment, oxygen enters the first stacked layer through the second via, and oxygen in the first stacked layer moves to the oxide active layer.

[0061] In some embodiments, as Figure 3 shown, a first stacked layer M1 and a second stacked layer M2 are alternately formed on a substrate (not shown). The first stacked layer M1 and the second stacked layer M2 respectively represent two selected different materials.

[0062] In some embodiments, after two initial material layers are alternately formed on the substrate, a stacked structure composed of the first stacked layer M1 and the second stacked layer M2 is formed by an etching process and a deposition process to replace the two initial material layers. The two initial material layers are selected from alternately deposited silicon nitride and silicon oxide, or single crystal silicon and silicon germanium made by epitaxial growth, or two different thin film materials with a high etching selectivity alternately prepared.

[0063] In some embodiments, the first stacked layer M1 is an oxide insulating material.

[0064] In some embodiments, the material of the first stacked layer is selected from silicon oxide, silicon oxynitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide and their combinations, etc.

[0065] In some embodiments, the etching process for fabricating the stacked structure includes anisotropic etching or isotropic etching, such as dry etching or wet etching.

[0066] In some embodiments, the deposition process for fabricating the stacked structure includes physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, epitaxial growth (EPI), etc.

[0067] In some embodiments, as Figure 4 shown, a first trench T1 is formed in the stacked structure.

[0068] In some embodiments, the method of forming the first trench may be prepared by a lithography process. Specifically, the lithography process includes forming a photoresist on a substrate, exposing and developing the photoresist to form a photoresist with a preset pattern, and etching the stacked structure through the patterned photoresist to form the first trench. Optionally, the etching process includes anisotropic etching or isotropic etching, such as dry etching or wet etching.

[0069] In some embodiments, the lithography process further includes forming a hard mask on the substrate, forming a photoresist on the hard mask, exposing and developing the photoresist to form a preset pattern, etching the hard mask through the patterned photoresist to transfer the preset pattern to the hard mask, stripping the photoresist, and etching the stacked structure through the patterned hard mask to form the first trench.

[0070] In some embodiments, with the development of semiconductor manufacturing processes, the integration level increases and the size shrinks. A single lithography process cannot form the preset widths required for the active region and isolation trenches, and multiple lithography processes are needed. For example, two exposure and etching processes (LELE), or self-aligned double patterning process (SADP), or self-aligned quadruple patterning process (SAQP), etc.

[0071] In some embodiments, as Figure 5 shown, a second trench T2 is formed in the second stacked layer through the first trench in the stacked structure with the first trench.

[0072] In some embodiments, a part of the second stacked layer is removed by side etching to form the second trench.

[0073] In some embodiments, the method of side etching the second stacked layer may be a liquid-phase etching process. It can be understood that the etching rate of the etching solution for the second stacked layer is greater than the etching rate of the etching solution for the first stacked layer.

[0074] In some embodiments, as Figures 6 - 7 shown, a bit line structure 500 is formed in the second trench of the stacked structure.

[0075] In some embodiments, a third material layer M3 is deposited in the first trench and the second trench of the stacked structure, and the third material layer on the sidewall of the first trench is removed, and the remaining third material layer in the second trench forms the bit line structure 500.

[0076] In some embodiments, the third material layer is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polysilicon, doped or undoped single-crystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. The method for forming the third material layer is selected from physical vapor deposition (PVD) methods, atomic layer deposition (ALD) methods, pulsed laser deposition (PLD) methods, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for forming the third material layer is the atomic layer deposition (ALD) method.

[0077] In some embodiments, the method for removing the third material layer on the sidewalls of the first trench is an anisotropic etching process including dry etching processes, plasma etching processes, etc.

[0078] In some embodiments, as Figure 8 shown, after forming the bit line structure, a protective layer P1 is formed in the first trench.

[0079] In some embodiments, the method for forming the protective layer P1 is selected from physical vapor deposition (PVD) methods, atomic layer deposition (ALD) methods, pulsed laser deposition (PLD) methods, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0080] In some embodiments, the method for forming the protective layer P1 further includes planarizing the substrate on which the protective layer is deposited by chemical mechanical polishing (CMP).

[0081] In some embodiments, in a method similar to that for forming the bit line structure, a trench is formed in the stacked structure, then a part of the second stacked layer is removed by lateral etching, and then the lower electrode 601 of the storage capacitor is formed, and a capacitor dielectric layer and an upper electrode are formed on the lower electrode.

[0082] In some embodiments, the method for forming the lower electrode of the storage capacitor is selected from physical vapor deposition (PVD) methods, atomic layer deposition (ALD) methods, pulsed laser deposition (PLD) methods, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for forming the lower electrode is the atomic layer deposition (ALD) method.

[0083] In some embodiments, the method for forming the capacitor dielectric layer of the storage capacitor is selected from physical vapor deposition (PVD) methods, atomic layer deposition (ALD) methods, pulsed laser deposition (PLD) methods, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0084] In some embodiments, the method for forming the upper electrode of the storage capacitor is selected from physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0085] In some embodiments, the upper electrode of the storage capacitor is a multi-layer structure of titanium nitride and polysilicon. The method for forming titanium nitride is atomic layer deposition (ALD) method; the method for forming polysilicon is furnace tube deposition.

[0086] In some embodiments, similar to forming the protective layer P1 in the first trench, a protective layer is formed in the trench where the storage node is fabricated.

[0087] In some embodiments, the method for forming the protective layer is selected from physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0088] In some embodiments, the method for forming the protective layer further includes planarizing the substrate on which the protective layer is deposited by chemical mechanical polishing (CMP).

[0089] In some embodiments, as Figures 9 - 10 shown, in the stacked structure where the bit line structure and the storage node are formed, a first via V1 and a second via V2 are formed.

[0090] In some embodiments, the method for forming the first via and the second via includes forming them through a patterning process, which is similar to the foregoing patterning process and will not be elaborated here.

[0091] In some embodiments, the critical dimensions of the first via and the second via are the same and are formed in the same process step.

[0092] In some embodiments, the critical dimensions of the first via and the second via are smaller than the distance between the bit line structure and the storage node. The sidewalls of the first via and the second via include a first stacked layer and a second stacked layer.

[0093] In some embodiments, as Figures 11 - 12 shown, the third trench T3 is formed by laterally etching the second stacked layer through the first via and the second via, exposing the bit line structure 500 and the storage node. Here, taking the storage capacitor as an example, the lower electrode 601 is exposed.

[0094] In some embodiments, as Figures 13 - 14As shown, a fourth material layer M4 is deposited on the sidewalls of the first and second hole grooves and the third groove, and the fourth material layer is connected to the bit line structure and the lower electrode of the storage capacitor. The material of the fourth material layer is selected from one or more of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, gallium oxide, or tin oxide. The formation method of the fourth material layer is selected from physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0095] In some embodiments, the fourth material layer is a multi-layer structure, formed by multiple depositions, and the material of each layer is respectively selected from one or more of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, gallium oxide, or tin oxide.

[0096] In some embodiments, as Figures 15 - 16 shown, the fourth material layer on the sidewalls of the first and second hole grooves is removed, and the remaining fourth material layer in the third groove forms an active layer. The active layer in the third groove in the first hole groove constitutes an oxide active layer 200, and the active layer in the third groove in the second hole groove constitutes a pseudo-oxide active layer 200'.

[0097] In some embodiments, the method for removing the fourth material layer is an anisotropic etching process including dry etching process, plasma etching process, etc.

[0098] In some embodiments, as Figures 17 - 18 shown, a gate structure 400 is formed in the first hole groove, and a pseudo-gate structure 400' is formed in the second hole groove. The gate structure and the pseudo-gate structure are formed in the same process step.

[0099] In some embodiments, both the gate structure and the pseudo-gate structure include a gate insulating layer and a gate electrode.

[0100] In some embodiments, the formation method of the gate insulating layer includes physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0101] In some embodiments, the formation method of the gate electrode includes physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0102] In some embodiments, as Figure 19 shown, the pseudo-gate structure is removed to re-expose the second hole groove V2.

[0103] In some embodiments, removing the dummy gate structure includes etching away the dummy gate structure through a patterning process to form a second via.

[0104] In some embodiments, as Figure 24 shown, the semiconductor structure having a gate structure, an oxide active layer, and a second via formed in the stacked structure is placed in an oxygen environment for annealing. Oxygen enters the first stacked layer through the second via, and the oxygen in the first stacked layer is transferred to the oxide active layer, thereby repairing the oxygen vacancies in the oxide active layer.

[0105] In some embodiments, the annealing process performed on the semiconductor structure has a temperature of 350 °C to 450 °C and a duration of 1.5 hours to 2.5 hours.

[0106] In some embodiments, as Figure 20 shown, after the annealing process of the semiconductor structure is completed, a thermally conductive polymer is filled in the second via to form a thermally conductive structure 300.

[0107] In some embodiments, as Figure 21 shown, after the first via and the second via are formed in the stacked structure and before the oxide active layer is formed, a second protective layer P2 is formed in the second via, and then subsequent preparation of the oxide active layer and the gate structure is carried out. After the preparation of the gate structure is completed, the second protective layer is removed to expose the second via again, and then an annealing process is carried out in an oxidation environment, and then a thermally conductive polymer is filled in the second via to form a thermally conductive structure 300. The thermally conductive structure of the semiconductor structure obtained by this method has no dummy oxide active layer between the bit line structure and the storage node. The second protective layer P2 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and their combinations, etc. The forming method of the second protective layer P2 includes physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0108] In some embodiments, as Figures 22 - 23As shown, in a stacked structure having a bit line structure and a storage node, a first via and a second via are formed. The critical dimensions of the first via and the second via are equal to or slightly larger than the distance between the bit line structure and the storage node. The sidewalls of the first via and the second via expose the bit line structure and the lower electrode of the storage capacitor. Then, a fourth material layer M4 and a gate structure 400 are sequentially formed in the first via, and a fourth material layer M4 and a dummy gate structure 400' are sequentially formed in the second via through the same process steps. Optionally, a second protective layer is first filled in the second via, and then a fourth material layer and a gate structure are sequentially formed in the first via. Then, the second stacked layer is removed to expose the fourth material layer corresponding to the first stacked layer, and the fourth material layer corresponding to the first stacked layer is removed by an etching process, and the remaining fourth material layer in the first via forms an oxide active layer. The stacked structure having the oxide active layer is again deposited with a third protective layer to fill the space left by the first stacked layer. The material of the third protective layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and their combinations, etc. The forming method of the third protective layer includes physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0109] In some embodiments, the material of the third protective layer is the same as that of the first stacked layer.

[0110] In some embodiments, the step of performing an annealing process in an oxygen environment is carried out after the third protective layer is fabricated.

[0111] In some embodiments, the step of performing an annealing process in an oxygen environment is completed before the first stacked layer is removed.

[0112] In some embodiments, the method of removing the second stacked layer includes wet etching.

[0113] In some embodiments, the etching process of removing the fourth material layer corresponding to the first stacked layer includes wet etching.

[0114] According to the third aspect of the embodiments of the present disclosure, a semiconductor structure fabricated by the method for fabricating a semiconductor structure as described above in the present disclosure.

[0115] In the process of manufacturing semiconductor structures, hydrogen-rich process steps are inevitably involved. For example, in the preparation of titanium nitride, after forming an oxide active layer, such hydrogen-rich process steps can cause hydrogen to diffuse in the semiconductor structure and enter the oxide active layer to combine with the oxygen contained therein. This results in an increase in oxygen vacancies in the oxide active layer. It is also known that an increase in oxygen vacancies in an oxide semiconductor material can improve the conductivity of the oxide semiconductor material. Therefore, the threshold voltage of the oxide active layer is changed, which in turn affects the performance of the transistor. Annealing the oxide active layer in an oxygen environment can repair the oxygen vacancies in the oxide active layer, thereby improving the transistor performance. However, an electrode structure is formed around the oxide active layer, especially the titanium nitride structure is dense and oxygen is difficult to penetrate. Therefore, how to anneal the oxide active layer is an urgent problem to be solved.

[0116] Through the design of the second via and the first stacked layer, the present disclosure enables oxygen to diffuse into the oxide active layer, thereby repairing the oxygen vacancies in the oxide active layer and improving the performance of the semiconductor structure.

[0117] The accumulation of thermal effects in a multi-layer stacked semiconductor structure is also an urgent problem to be solved. Forming a heat conduction structure in the second via can not only obtain a semiconductor structure with better electrical performance, but also solve the thermal effects of the device and improve the product stability.

[0118] The various semiconductor devices shown in this specific embodiment can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or can also be a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be implemented by the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).

[0119] The above is only the specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all of them should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: Providing a substrate; the substrate is formed into a stacked structure, the stacked structure includes a first stacked layer and a second stacked layer alternately stacked on the substrate along a first direction, the first direction intersecting with a plane where the substrate is located; forming a first hole slot and a second hole slot extending along the first direction in the laminated structure; forming an oxide active layer in the first hole groove; forming a gate structure in the first hole groove in which the oxide active layer is formed; The semiconductor structure is annealed in an oxygen environment, the oxygen enters the first stacked layer through the second hole groove, and the oxygen in the first stacked layer moves into the oxide active layer.

2. The preparation method according to claim 1, characterized in that: Also includes: The second holes are filled with a thermally conductive polymer.

3. The preparation method according to claim 1, characterized in that: A bit line structure is formed in the second stacked layer, the bit line structure being electrically connected to the oxide active layer.

4. The preparation method according to claim 1, characterized in that: A storage node is formed in the second stacked layer, the storage node being electrically connected to the oxide active layer.

5. The preparation method according to claim 1, characterized in that: At least a portion of the oxide active layer corresponding to the first stacked layer is removed.

6. The preparation method according to claim 3, characterized in that: The gate structure and / or the bit line structure may include titanium nitride.

7. The preparation method according to claim 1, characterized in that: The first stacked layer includes an oxide insulating material.

8. The preparation method according to claim 1, characterized in that: The oxide active layer includes one or more of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, gallium oxide or tin oxide.

9. The preparation method according to claim 1, characterized in that: The temperature of the annealing step is 350 degrees Celsius to 450 degrees Celsius, and the duration is 1.5 hours to 2.5 hours.

10. A semiconductor structure, characterized in that: Prepared according to any one of claims 1 to 9.

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