Schottky diode and preparation method thereof

Abstract

The invention discloses a Schottky diode and a preparation method thereof. The Schottky diode comprises a substrate; the heterostructure comprises a whole-surface heterojunction and a plurality of strip-shaped heterojunctions, the whole-surface heterojunction is located on the substrate, the strip-shaped heterojunctions are located on the surface, away from the substrate, of the whole-surface heterojunction, and every two adjacent strip-shaped heterojunctions are arranged at intervals; the anode is located on the surface, away from the substrate, of the whole-surface heterojunction, and the anode is located at the first ends of the strip-shaped heterojunctions; the cathode is located on the surface, away from the substrate, of the whole-face heterojunction, and the cathode is located at the second ends of the strip-shaped heterojunctions. According to the technical scheme provided by the embodiment of the invention, the 2DEG concentration and mobility at the heterojunction interface are improved, and the electrical performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a Schottky diode and a manufacturing method thereof. Background Art

[0002] The GaN-based Schottky diode includes a heterojunction formed by materials such as GaN and AlGaN. A two-dimensional electron gas (2DEG) with high concentration and high mobility is formed at the heterojunction interface, which is widely used in high-frequency and high-speed devices.

[0003] However, the current GaN-based Schottky diodes have the situation that the concentration and mobility of the 2DEG at the heterojunction interface are not high enough, which seriously affects the electrical performance of the GaN-based Schottky diodes. Summary of the Invention

[0004] The present invention provides a Schottky diode and a manufacturing method thereof to increase the concentration and mobility of the 2DEG at the heterojunction interface and improve the electrical performance of the device.

[0005] According to one aspect of the present invention, there is provided a Schottky diode, comprising:

[0006] A substrate;

[0007] A heterostructure, the heterostructure includes a full-surface heterojunction and a plurality of strip-shaped heterojunctions. The full-surface heterojunction is located on the substrate, and the plurality of strip-shaped heterojunctions are located on the surface of the full-surface heterojunction away from the substrate, and two adjacent strip-shaped heterojunctions are arranged at intervals;

[0008] An anode, the anode is located on the surface of the full-surface heterojunction away from the substrate, and the anode is located at the first end of the plurality of strip-shaped heterojunctions;

[0009] A cathode, the cathode is located on the surface of the full-surface heterojunction away from the substrate, and the cathode is located at the second end of the plurality of strip-shaped heterojunctions. The direction from the first end of the plurality of strip-shaped heterojunctions to the second end of the plurality of strip-shaped heterojunctions is the extending direction of the plurality of strip-shaped heterojunctions.

[0010] According to another aspect of the present invention, there is provided a manufacturing method of a Schottky diode, comprising:

[0011] Providing a substrate;

[0012] Forming a full-surface heterojunction on the substrate;

[0013] Forming a plurality of strip-shaped heterojunctions on the surface of the full-surface heterojunction away from the substrate; wherein, two adjacent strip-shaped heterojunctions are arranged at intervals; the full-surface heterojunction and the plurality of strip-shaped heterojunctions form a heterostructure;

[0014] An anode and a cathode are formed on the surface of the all-surface heterojunction away from the substrate. Among them, the anode is located at the first end of the plurality of strip-shaped heterojunctions, the cathode is located at the second end of the plurality of strip-shaped heterojunctions, and the direction in which the first end of the plurality of strip-shaped heterojunctions points to the second end of the plurality of strip-shaped heterojunctions is the extending direction of the plurality of strip-shaped heterojunctions.

[0015] An embodiment of the present application provides a Schottky diode and a preparation method. The Schottky diode includes: The heterostructure includes an all-surface heterojunction and a plurality of strip-shaped heterojunctions. The all-surface heterojunction forms 2DEG near the interface between its channel layer and barrier layer. The plurality of strip-shaped heterojunctions are located between the anode and the cathode, forming parallel current channels. While increasing the 2DEG concentration in the Schottky diode, the high and low 2DEG concentrations can be arranged alternately, thereby improving the mobility of 2DEG. Moreover, the 2DEG conduction paths at the heterojunction interfaces of the all-surface heterojunction and the plurality of strip-shaped heterojunctions in the heterostructure are in parallel, and the regionalization is restricted to move within the parallel current channels, making the transconductance stable period wider, thereby improving the stability of the transconductance and improving the linearity of the device. In summary, the above technical solution increases the concentration and mobility of 2DEG at the heterojunction interface and improves the electrical performance of the device. Description of the Drawings

[0016] Figure 1 is a schematic structural diagram of a Schottky diode provided according to an embodiment of the present invention;

[0017] Figure 2 is a schematic structural diagram of another Schottky diode provided according to an embodiment of the present invention;

[0018] Figure 3 is a schematic structural diagram of yet another Schottky diode provided according to an embodiment of the present invention;

[0019] Figure 4 is a schematic structural diagram of yet another Schottky diode provided according to an embodiment of the present invention;

[0020] Figure 5 is Figure 2 a schematic cross-sectional structure diagram in the A1-A2 direction in;

[0021] Figure 6 is Figure 2 a top view of;

[0022] Figure 7 is a schematic structural diagram of yet another Schottky diode provided according to an embodiment of the present invention;

[0023] Figure 8 is Figure 7 a schematic cross-sectional structure diagram in the B1-B2 direction in;

[0024] Figure 9 is Figure 7 a schematic cross-sectional structure diagram in the C1-C2 direction of

[0025] Figure 10 a schematic structure diagram of another Schottky diode provided according to an embodiment of the present invention;

[0026] Figure 11 a schematic structure diagram of another Schottky diode provided according to an embodiment of the present invention;

[0027] Figure 12 a schematic flowchart of a preparation method of a Schottky diode provided according to an embodiment of the present invention;

[0028] Figures 13 to 15 is Figure 12 a schematic structure diagram corresponding to each step in

[0029] Figure 16 is Figure 12 a schematic flowchart included in S130 of

[0030] Figures 17 to 18 is Figure 16 a schematic structure diagram corresponding to each step in

[0031] Figure 19 is Figure 12 a schematic flowchart of another process included in S130 of

[0032] Figure 20 is Figure 19 a schematic structure diagram corresponding to S1304 in

[0033] Figure 21 is Figure 12 a schematic flowchart of a process included after S130 of

[0034] Figures 22 to 23 is Figure 21 a schematic structure diagram corresponding to each step in

[0035] Figure 24 is Figure 12 a schematic flowchart of another process included after S130 of

[0036] Figures 25 to 26 is Figure 24 a schematic structure diagram corresponding to each step in

[0037] Figures 27 to 28 is Figure 24 a schematic structure diagram corresponding to each step in Detailed implementation manners

[0038] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.

[0039] In order to increase the concentration and mobility of 2DEG at the heterojunction interface, reduce the reverse leakage current, and improve the electrical performance of the device, the embodiments of the present invention provide the following technical solutions:

[0040] As Figure 1 shown, Figure 1 is a schematic structural diagram of a Schottky diode provided according to an embodiment of the present invention. The Schottky diode includes: a substrate 01; a heterostructure 02, the heterostructure 02 includes a whole-surface heterojunction 23 and a plurality of strip-shaped heterojunctions 24. The whole-surface heterojunction 23 is located on the substrate 01, and the plurality of strip-shaped heterojunctions 24 are located on the surface of the whole-surface heterojunction 23 away from the substrate 01, and two adjacent strip-shaped heterojunctions 24 are arranged at intervals; an anode 03, the anode 03 is located on the surface of the whole-surface heterojunction 23 away from the substrate 01, and the anode 03 is located at the first end of the plurality of strip-shaped heterojunctions 24; a cathode 04, the cathode 04 is located on the surface of the whole-surface heterojunction 23 away from the substrate 01, and the cathode 04 is located at the second end of the plurality of strip-shaped heterojunctions 24. The direction in which the first end of the plurality of strip-shaped heterojunctions 24 points to the second end of the plurality of strip-shaped heterojunctions 24 is the extending direction of the plurality of strip-shaped heterojunctions 24.

[0041] Specifically, the strip-shaped heterojunction 24 includes a channel layer 21 and a barrier layer 22. A high-concentration and high-mobility 2DEG is formed near the interface between the channel layer 21 and the barrier layer 22 in the strip-shaped heterojunction 24.

[0042] Optionally, the heterostructure 02 includes any one of an AlGaN / GaN heterostructure, an AlScN / GaN heterostructure, and an AlN / GaN heterostructure. The channel layer 21 includes GaN, and the barrier layer 22 includes any one of AlGaN, AlScN, and AlN.

[0043] Optionally, the plurality of strip-shaped heterojunctions 24 share the cathode 04 and also share the anode 03, which simplifies the structures of the cathode 04 and the anode 03.

[0044] Optionally, the Schottky diode further includes a buffer layer 09 located between the substrate 01 and the heterostructure 02. The buffer layer 09 is used to relieve the lattice mismatch between the substrate 01 and the heterostructure 02 to improve the film formation quality of the heterostructure 02.

[0045] In the technical solution provided by the embodiment of the present invention, the heterostructure 02 includes a full-surface heterojunction 23 and a plurality of strip-shaped heterojunctions 24. The full-surface heterojunction 23 forms 2DEG near the interface between its channel layer 21 and barrier layer 22. The plurality of strip-shaped heterojunctions 24 are located between the anode 03 and the cathode 04, forming a plurality of parallel current channels. While increasing the 2DEG concentration in the Schottky diode, the high and low 2DEG concentrations can be arranged alternately, thereby improving the mobility of 2DEG. Moreover, the 2DEG conduction paths at the heterojunction interfaces of the full-surface heterojunction 23 and the plurality of strip-shaped heterojunctions 24 in the heterostructure 02 are in parallel, and the regionalization is restricted to move within the parallel current channels, making the transconductance stable period wider, thereby improving the stability of the transconductance and improving the linearity of the device. In summary, the above technical solution increases the concentration and mobility of 2DEG at the heterojunction interface and improves the electrical performance of the device.

[0046] Optionally, the anode can also be located at the first end of the full-surface heterojunction, and the cathode can also be located at the second end of the full-surface heterojunction (not shown).

[0047] Optionally, on the basis of the above technical solution, Figure 2 is a schematic structural diagram of another Schottky diode provided by the embodiment of the present invention, Figure 3 is a schematic structural diagram of still another Schottky diode provided by the embodiment of the present invention, Figure 4 is a schematic structural diagram of still another Schottky diode provided by the embodiment of the present invention. As Figures 2 to 4 shown, the Schottky diode further includes a first p-GaN layer 05 and / or a second p-GaN layer 06; the first p-GaN layer 05 is located between two adjacent strip-shaped heterojunctions 24, and the first p-GaN layer 05 is located on the surface of the full-surface heterojunction 23 away from the substrate 01; the second p-GaN layer 06 is located on the side surface of the strip-shaped heterojunction 24.

[0048] Figure 2 shows the scheme in which the Schottky diode includes both the first p-GaN layer 05 and the second p-GaN layer 06. Figure 3 shows the technical solution in which the Schottky diode includes the first p-GaN layer 05. The first p-GaN layer 05 is located at the bottom of the groove formed between two strip-shaped heterojunctions 24; optionally, the first p-GaN layer 05 is fabricated by selective epitaxy. Figure 4 shows the scheme in which the Schottky diode includes the second p-GaN layer 06. The second p-GaN layer 06 is located on the side surface of the groove formed between two strip-shaped heterojunctions 24; optionally, the second p-GaN layer 06 is fabricated by selective epitaxy.

[0049] Optionally, as Figure 2As shown, the Schottky diode includes a first p-GaN layer 05 and a second p-GaN layer 06, and the second p-GaN layer 06 is connected to the first p-GaN layer 05.

[0050] Specifically, the first p-GaN layer 05 is located between two adjacent strip-shaped heterojunctions 24, and the first p-GaN layer 05 is located on the surface of the whole-surface heterojunction 23 away from the substrate 01, which can deplete the 2DEG in the whole-surface heterojunction 23 below the first p-GaN layer 05, redistribute the electric field of the whole-surface heterojunction 23, prevent avalanche breakdown, increase the actual breakdown voltage of the Schottky barrier diode and reduce the reverse leakage current.

[0051] The second p-GaN layer 06 is located on the side of the strip-shaped heterojunction 24. When the Schottky diode is in the off state, a PN junction depletion region will be formed between the second p-GaN layer 06 and the adjacent strip-shaped heterojunction 24. A relatively large depletion region can be obtained at a lower voltage, and the depletion region can turn off the conductive channel of the strip-shaped heterojunction, forming a large-area high-resistance region, which can effectively reduce the reverse leakage.

[0052] Optionally, on the basis of the above technical solution, as Figure 2 and Figure 3 shown, the first p-GaN layer 05 has no contact with the cathode 04, and the first p-GaN layer 05 is in contact with the anode 03.

[0053] Optionally, on the basis of the above technical solution, as Figure 2 and Figure 4 shown, the second p-GaN layer 06 has no contact with the cathode 04, and the second p-GaN layer 06 is in contact with the anode 03.

[0054] Optionally, on the basis of the above technical solution, Figure 5 is Figure 2 a schematic cross-sectional structure diagram in the A1-A2 direction in Figure 6 is Figure 2 a top view of Figure 5 and Figure 6 shown, the Schottky diode includes a first p-GaN layer 05 and a second p-GaN layer 06; the first p-GaN layer 05 and the second p-GaN layer 06 located between two strip-shaped heterojunctions 24 form a "U" - shaped structure. The first p-GaN layer 05 and the second p-GaN layer 06 located at the edge position of the whole-surface heterojunction 23 form an "L" - shaped structure.

[0055] Specifically, the Schottky diode includes a first p-GaN layer 05 and a second p-GaN layer 06. In the arrangement direction of the plurality of strip-shaped heterojunctions 24, the first p-GaN layer 05 completely covers the entire surface heterojunction 23 between two strip-shaped heterojunctions 24, and can deplete the 2DEG in the surface heterojunction 23 below the first p-GaN layer 05, so that the electric field of the entire surface heterojunction 23 between two strip-shaped heterojunctions 24 is redistributed, preventing avalanche breakdown during reverse bias, increasing the actual breakdown voltage of the Schottky barrier diode and reducing the reverse leakage current. It should be noted that in the direction perpendicular to the arrangement direction of the plurality of strip-shaped heterojunctions 24, neither the first p-GaN layer 05 nor the second p-GaN layer 06 is in contact with the cathode 04.

[0056] The first p-GaN layer 05 and the second p-GaN layer 06 located at the edge position of the surface heterojunction 23 form an "L" shape structure. In the arrangement direction of the plurality of strip-shaped heterojunctions 24, the first p-GaN layer 05 completely covers up to the edge position of the surface heterojunction 23, and can deplete the 2DEG below the first p-GaN layer 05, so that the electric field of the entire edge position of the surface heterojunction 23 is redistributed, preventing avalanche breakdown, increasing the actual breakdown voltage of the Schottky barrier diode and reducing the reverse leakage current. It should be noted that in the direction perpendicular to the arrangement direction of the plurality of strip-shaped heterojunctions 24, neither the first p-GaN layer 05 nor the second p-GaN layer 06 is in contact with the cathode 04.

[0057] Optionally, on the basis of the above technical solution, Figure 7 is a schematic structural diagram of another Schottky diode provided according to an embodiment of the present invention, Figure 8 is Figure 7 a schematic cross-sectional structure diagram in the B1-B2 direction in Figure 7 and Figure 8 shown. The Schottky diode further includes a third p-GaN layer 07, and the third p-GaN layer 07 is located on the surface of the strip-shaped heterojunction 24 away from the surface heterojunction 23.

[0058] Specifically, the third p-GaN layer 07 can deplete the 2DEG in the strip-shaped heterojunction 24 below the third p-GaN layer 07, further improving the redistribution of the electric field of the surface heterojunction 23 below the strip-shaped heterojunction 24, preventing avalanche breakdown, increasing the actual breakdown voltage of the Schottky barrier diode and reducing the reverse leakage current.

[0059] Optionally, as Figure 7 and Figure 8 shown, the third p-GaN layer 07 is also located on the surface of the second p-GaN layer 06 away from the first p-GaN layer 05, forming a structure in which the second p-GaN layer 06 and the third p-GaN layer 07 are connected to each other.

[0060] Optionally, on the basis of the above technical solution, Figure 9 is Figure 7 a schematic cross-sectional structure diagram in the C1-C2 direction of Figure 9 as shown. The Schottky diode further includes a fourth p-GaN layer 08, and the fourth p-GaN layer 08 is located between the anode 03 and the strip heterojunction 24.

[0061] Specifically, the fourth p-GaN layer 08 is located on the side of the strip heterojunction 24 and between the anode 03 and the strip heterojunction 24. When the Schottky diode is in the off state, a PN junction depletion region will be formed near the fourth p-GaN layer 08. It can obtain a larger depletion region at a lower voltage. The depletion region can turn off the conductive channel and form a large-area high-resistance region, which can effectively reduce the reverse leakage current.

[0062] Optionally, as Figure 9 shown, the fourth p-GaN layer 08 is connected to the third p-GaN layer 07; optionally, the fourth p-GaN layer 08 is connected to the second p-GaN layer 06.

[0063] Optionally, between two adjacent strip heterojunctions 24, the surface of the whole-surface heterojunction 23 away from the substrate 01 has a (1-100) crystal plane or a (11-20) crystal plane. Specifically, between two adjacent strip heterojunctions 24, the surface of the whole-surface heterojunction 23 away from the substrate 01 is used for subsequent epitaxial growth of the first p-GaN layer 05 and the strip heterojunction 24. The (1-100) crystal plane or the (11-20) crystal plane is a non-polar plane, which can reduce the formation of unstable chemical bonds by combining with oxygen atoms in the substrate or the environment, reduce the interface state density, and thus improve the device characteristics of the Schottky diode.

[0064] Optionally, the side surface of the strip heterojunction 24 is a semi-polar plane or a non-polar plane. Specifically, the semi-polar plane and the non-polar plane can reduce the formation of unstable chemical bonds by combining with oxygen atoms in the substrate or the environment, and improve the device characteristics.

[0065] Optionally, the Schottky diode includes a first p-GaN layer 05 and a second p-GaN layer 06, and the thickness of the first p-GaN layer 05 in the direction pointing from the substrate 01 to the heterostructure 02 is greater than the thickness of the second p-GaN layer 06 in the direction parallel to the plane where the substrate 01 is located.

[0066] Optionally, the Schottky diode includes the first p-GaN layer 05 and the second p-GaN layer 06, and the concentration of the P-type doping element in the first p-GaN layer 05 is higher than the concentration of the P-type doping element in the second p-GaN layer 06.

[0067] Specifically, the surface of the full-surface heterojunction 23 away from the substrate 01 has a (0001) crystal plane, which belongs to a polar plane. Compared with the polar plane, the epitaxial growth rate of the semi-polar plane or non-polar plane is slower. Therefore, the thickness of the second p-GaN layer 06 on the side of the strip-shaped heterojunction 24 is smaller; at the same time, the concentration of the P-type doping element in the second p-GaN layer 06 is lower. At this time, a PN junction depletion region can be formed between the second p-GaN layer 06 and between the second p-GaN layer 06 and the adjacent strip-shaped heterojunction 24, turning off the conductive channel of the strip-shaped heterojunction and reducing the reverse leakage current.

[0068] Optionally, on the basis of the above technical solution, Figure 10 is a schematic structural diagram of another Schottky diode provided according to an embodiment of the present invention. As Figure 10 shown, the full-surface heterojunction 23 includes a plurality of alternately arranged channel layers 21 and barrier layers 22.

[0069] Specifically, the plurality of alternately arranged channel layers 21 and barrier layers 22 can increase the 2DEG concentration in the channels at the heterojunction interface of the full-surface heterojunction 23 to improve the electrical performance of the device.

[0070] Optionally, on the basis of the above technical solution, as Figure 10 shown, the strip-shaped heterojunction 24 includes a plurality of alternately arranged channel layers 21 and barrier layers 22. Optionally, as Figure 10 shown, the second p-GaN layer 06 covers the entire side surface of the strip-shaped heterojunction 24 having multiple groups of channel layers 21 and barrier layers 22.

[0071] Specifically, the strip-shaped heterojunction 24 includes a plurality of alternately arranged channel layers 21 and barrier layers 22, which can increase the 2DEG concentration in the channels at the heterojunction interface of the strip-shaped heterojunction 24 to improve the electrical performance of the device.

[0072] It should be noted that, as Figure 10 shown, the number of groups of the channel layers and barrier layers included in the full-surface heterojunction 23 and the strip-shaped heterojunction 24 can be the same, both including three alternately arranged channel layers 21 and three barrier layers 22. Optionally, the number of groups of the channel layers and barrier layers of the full-surface heterojunction 23 and the strip-shaped heterojunction 24 can be different.

[0073] Optionally, on the basis of the above technical solution, Figure 11 is a schematic structural diagram of another Schottky diode provided according to an embodiment of the present invention. As Figure 11 shown, the anode 03 is a field plate structure, and the anode 03 extends from the first ends of a plurality of strip-shaped heterojunctions 24 to the side of the strip-shaped heterojunction 24 away from the full-surface heterojunction 23.

[0074] Specifically, the anode 03 is a field plate structure. The partial area of the anode 03 located on the third p-GaN layer 07 can reduce the turn-on voltage of the Schottky diode, has better reverse conduction ability, prevents avalanche breakdown during reverse conduction, and improves the reliability of the Schottky diode.

[0075] It should be noted that, as Figure 11 shown, the anode 03 covers the fourth p-GaN layer 08 and a partial area of the third p-GaN layer 07.

[0076] Optionally, the anode 03 also covers the first end of the entire heterojunction 23, and the cathode 04 also covers the second end of the entire heterojunction 23, which is convenient for controlling the switching of the Schottky diode. The first end of the entire heterojunction 23 and the first end of the strip-shaped heterojunction 24 are located on the same side of the heterostructure 02, and the second end of the entire heterojunction 23 and the second end of the strip-shaped heterojunction 24 are located on the same side of the heterostructure 02.

[0077] The embodiment of the present invention also provides a manufacturing method of a Schottky diode. Figure 12 It is a schematic flowchart of a manufacturing method of a Schottky diode provided according to the embodiment of the present invention, Figures 13 to 15 is Figure 12 the schematic structural diagram corresponding to each step in Figure 12 shown. The manufacturing method of this Schottky diode includes:

[0078] S110, as Figure 13 shown, provide a substrate 01. The material of the substrate 01 can be sapphire, silicon carbide, silicon, diamond, gallium nitride or other materials.

[0079] S120, as Figure 14 shown, form an entire heterojunction 23 on the substrate 01. Form a buffer layer 09 on the substrate 01, and then epitaxially form the entire heterojunction 23 on the surface of the buffer layer 09 away from the substrate 01. The buffer layer 09 is used to relieve the lattice mismatch between the substrate 01 and the heterostructure 02 to improve the film formation quality of the heterostructure 02.

[0080] S130, as Figure 15 shown, form a plurality of strip-shaped heterojunctions 24 on the surface of the entire heterojunction 23 away from the substrate 01; wherein, two adjacent strip-shaped heterojunctions 24 are arranged at intervals; the entire heterojunction 23 and the plurality of strip-shaped heterojunctions 24 constitute the heterostructure 02. Specifically, the heterostructure 02 forms a plurality of parallel current channels, which can make the 2DEG concentration arranged in a high-low alternating manner.

[0081] S140, as Figure 1As shown, an anode 03 and a cathode 04 are formed on the surface of the full-surface heterojunction 23 away from the substrate 01. Among them, the anode 03 is located at the first end of a plurality of strip-shaped heterojunctions 24, the cathode 04 is located at the second end of a plurality of strip-shaped heterojunctions 24, and the direction in which the first end of the plurality of strip-shaped heterojunctions 24 points to the second end of the plurality of strip-shaped heterojunctions 24 is the extending direction of the plurality of strip-shaped heterojunctions 24. Specifically, physical vapor deposition or chemical vapor deposition can be used to form the anode 03 and the cathode 04. The material of the anode 03 can be a metal, such as Ti / Al / Ni / Au, Ni / Au, etc., and the material of the cathode 04 can be a metal, such as Ti / Al / Ni / Au, Ni / Au, Al, Zr, Hf, etc.

[0082] In the technical solution provided by the embodiment of the present invention, the heterostructure 02 includes a full-surface heterojunction 23 and a plurality of strip-shaped heterojunctions 24. The full-surface heterojunction 23 forms 2DEG near the interface between its channel layer 21 and barrier layer 22. The plurality of strip-shaped heterojunctions 24 are located between the anode 03 and the cathode 04, forming a plurality of parallel current channels. While increasing the 2DEG concentration in the Schottky diode, the 2DEG concentration can be arranged in an alternating high and low manner, thereby improving the mobility of 2DEG. Moreover, the 2DEG conduction paths at the heterojunction interfaces of the full-surface heterojunction 23 and the plurality of strip-shaped heterojunctions 24 in the heterostructure 02 are in parallel, and the region is restricted to move within the parallel current channels, making the transconductance stable period wider, thereby improving the stability of the transconductance and improving the linearity of the device. In summary, the above technical solution increases the concentration and mobility of 2DEG at the heterojunction interface and improves the electrical performance of the device.

[0083] As Figure 16 shown, Figure 16 is Figure 12 a schematic flow diagram included in S130 in Figures 17 to 18 is Figure 16 the corresponding structural schematic diagram of each step in

[0084] S1301, as Figure 17 shown, a first mask layer 010 is formed on the surface of the full-surface heterojunction 23 away from the substrate 01. Among them, the first mask layer 010 includes a plurality of strip-shaped openings 0101 arranged at intervals. The first mask layer 010 can be any one of photoresist, silicon oxide, and silicon nitride.

[0085] S1302, as Figure 18 shown, strip-shaped heterojunctions 24 are formed at the strip-shaped openings 0101 of the first mask layer 010 through selective epitaxy.

[0086] S1303, as Figure 15As shown, the first mask layer 010 is removed by an etching process to form a plurality of strip-shaped heterojunctions 24 arranged at intervals.

[0087] Or, Figure 19 is Figure 12 Another process schematic diagram included in S130 in Figure 20 is Figure 19 The corresponding structural schematic diagram of S1304 in Figure 19 As shown, forming a plurality of strip-shaped heterojunctions 24 on the surface of the whole-surface heterojunction 23 away from the substrate 01 in S130 includes:

[0088] S1304, as Figure 20 shown, a whole-layer heterojunction 011 is formed on the surface of the whole-surface heterojunction 23 away from the substrate 01 by an epitaxial process. Specifically, the channel layer 21 and the barrier layer 22 of the whole-layer heterojunction 011 can be the same as those of the whole-surface heterojunction 23 in terms of materials and manufacturing processes.

[0089] S1305, as Figure 15 shown, the whole-layer heterojunction 011 is etched to form a plurality of strip-shaped heterojunctions 24, wherein two adjacent strip-shaped heterojunctions 24 are arranged at intervals.

[0090] As Figure 21 shown, Figure 21 is Figure 12 A process schematic diagram included after S130 in Figures 22 to 23 is Figure 21 The corresponding structural schematic diagrams of each step in

[0091] S1306, as Figure 22 shown, p-GaN 012 is formed on one side of the heterostructure 02 away from the substrate 01. Specifically, the P-type doping element in p-GaN 012 can be at least one of Mg, Zn, Ca, Sr, or Ba. It should be noted that p-GaN 012 is a P-type doped semiconductor film layer that has not yet undergone an annealing process for activation.

[0092] S1307, as Figure 23 shown, a patterned second mask layer 013 is formed on one side of p-GaN 012 away from the substrate 01, wherein the region exposed by the second mask layer 013 is located between two adjacent strip-shaped heterojunctions 24; specifically, the second mask layer 013 covers the strip-shaped heterojunctions 24. Optionally, the material of the second mask layer 013 can first cover the heterostructure 02 entirely, and then be etched by photolithography to form the patterned second mask layer 013.

[0093] S1308. Activate p-GaN012 by an annealing process in the area exposed by the second mask layer 013 to form a first p-GaN layer 05 as shown in Figure 3 . Specifically, the second mask layer 013 serves to prevent the underlying p-GaN012 from being activated. Optionally, the second mask layer 013 is AlN or SiN. Optionally, the second mask layer 013 is removed later.

[0094] Optionally, between two adjacent strip heterojunctions 24, the crystal plane of the area exposed by the second mask layer 013 is (1-100) or (11-20), which is beneficial to the electric field strength at the angle formed between the strip heterojunction and the planar heterojunction in the subsequently fabricated device.

[0095] Optionally, Figure 24 is Figure 12 another process schematic diagram included after S130. Figures 25 to 26 is Figure 24 the corresponding structural schematic diagram of each step in

[0096] After forming multiple strip heterojunctions 24 on the surface of the planar heterojunction 23 away from the substrate 01, S1309 also includes: Figure 25 As shown in

[0097] , form a patterned third mask layer 014 on the side of the heterostructure 02 away from the substrate 01, where the area exposed by the third mask layer 014 is located between two adjacent strip heterojunctions 24. Specifically, the third mask layer 014 covers the strip heterojunctions 24. Optionally, the material of the third mask layer 014 is SiO2 or SiN. Figure 26 As shown in

[0098] , form p-GaN012 by selective epitaxy in the area exposed by the third mask layer 014. Figure 3 Activate p-GaN012 by an annealing process to form a first p-GaN layer 05 as shown in

[0099] Optionally, Figures 27 to 28 is Figure 24 another corresponding structural schematic diagram of each step in Figure 27 As shown in Figure 28 , form a patterned fourth mask layer 015 on the side of the strip heterojunction 24 away from the substrate 01, where the area exposed by the fourth mask layer 015 is located between two adjacent strip heterojunctions 24 and on the side of the strip heterojunction 24. As shown inFigure 2 As shown, the p-GaN012 is then activated through an annealing process to form a first p-GaN layer 05 between two adjacent strip heterojunctions 24, and a second p-GaN layer 06 is formed on the side surface of the strip heterojunction 24. Optionally, the material of the fourth mask layer 015 is SiO2 or SiN; optionally, the fourth mask layer 015 is removed later.

[0100] It should be noted that the GaN-based material epitaxial growth process can be Metal-organic Chemical Vapor Deposition (MOCVD) technology. When growing GaN-based materials by MOCVD technology, there are a large number of H atoms in the MOCVD growth environment. Acceptor dopants in GaN-based materials, such as Mg elements, will be passivated by a large number of H atoms and no holes will be generated. In other words, the doping ions of p-GaN012 are not activated and cannot generate holes. As Figure 3 shown, the doping ions of p-GaN012 are activated through an annealing process. After the P-type doping elements in p-GaN012 are activated, H atoms can escape. For example, Mg elements can generate holes and consume 2DEG at the interface of the heterojunction structure.

[0101] It should also be particularly pointed out that when the Schottky diode further includes a third p-GaN layer 07 and a fourth p-GaN layer 08, p-GaN can also be formed first. Then, the doping ions of p-GaN are activated through an annealing process to form the third p-GaN layer 07 and the fourth p-GaN layer 08. The p-GaN for forming the third p-GaN layer 07 and the fourth p-GaN layer 08 can be prepared simultaneously with the p-GaN for forming the first p-GaN layer 05 and the second p-GaN layer 06.

[0102] It should be understood that the various forms of the processes shown above can be used, with steps reordered, added, or deleted. The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A Schottky diode, characterized in that, Comprising: A substrate (01); A heterostructure (02), the heterostructure (02) includes a planar heterojunction (23) and a plurality of strip-shaped heterojunctions (24), the planar heterojunction (23) is located on the substrate (01), and a plurality of the strip-shaped heterojunctions (24) are located on the surface of the planar heterojunction (23) away from the substrate (01), and two adjacent strip-shaped heterojunctions (24) are arranged at intervals; An anode (03), the anode (03) is located on the surface of the planar heterojunction (23) away from the substrate (01), and the anode (03) is located at the first end of a plurality of the strip-shaped heterojunctions (24); A cathode (04), the cathode (04) is located on the surface of the planar heterojunction (23) away from the substrate (01), and the cathode (04) is located at the second end of a plurality of the strip-shaped heterojunctions (24), and the direction in which the first end of a plurality of the strip-shaped heterojunctions (24) points to the second end of a plurality of the strip-shaped heterojunctions (24) is the extending direction of a plurality of the strip-shaped heterojunctions (24).

2. The Schottky diode according to claim 1, characterized in that, The heterostructure (02) includes any one of an AlGaN / GaN heterostructure, an AlScN / GaN heterostructure, and an AlN / GaN heterostructure.

3. The Schottky diode according to claim 1, characterized in that, It further includes a first p-GaN layer (05) and / or a second p-GaN layer (06); The first p-GaN layer (05) is located between two adjacent strip-shaped heterojunctions (24), and the first p-GaN layer (05) is located on the surface of the planar heterojunction (23) away from the substrate (01); The second p-GaN layer (06) is located on the side surface of the strip-shaped heterojunction (24).

4. The Schottky diode according to claim 3, characterized in that, Between two adjacent strip-shaped heterojunctions (24), the surface of the planar heterojunction (23) away from the substrate (01) has a (1-100) crystal plane or a (11-20) crystal plane.

5. The Schottky diode according to claim 3, characterized in that, The side surface of the strip-shaped heterojunction (24) is a semi-polar plane or a non-polar plane.

6. The Schottky diode according to claim 5, characterized in that, The Schottky diode includes the first p-GaN layer (05) and the second p-GaN layer (06), and the thickness of the first p-GaN layer (05) in the direction from the substrate (01) to the heterostructure (02) is greater than the thickness of the second p-GaN layer (06) in the direction parallel to the plane where the substrate (01) is located.

7. The Schottky diode according to claim 5, characterized in that, The Schottky diode includes the first p-GaN layer (05) and the second p-GaN layer (06), and the concentration of the P-type doping element in the first p-GaN layer (05) is higher than the concentration of the P-type doping element in the second p-GaN layer (06).

8. The Schottky diode according to claim 3, characterized in that, The Schottky diode includes the first p-GaN layer (05) and the second p-GaN layer (06); The first p-GaN layer (05) and the second p-GaN layer (06) located between two strip-shaped heterojunctions (24) form a "U" shaped structure.

9. The Schottky diode according to claim 3, characterized in that, It further includes a third p-GaN layer (07), and the third p-GaN layer (07) is located on the surface of the strip-shaped heterojunction (24) away from the planar heterojunction (23).

10. The Schottky diode according to claim 7, characterized in that, Further included is a fourth p-GaN layer (08), and the fourth p-GaN layer (08) is located between the anode (03) and the strip-shaped heterojunction (24).

11. The Schottky diode according to claim 1, characterized in that, The entire-surface heterojunction (23) includes multiple layers of channel layers (21) and barrier layers (22) arranged alternately; and / or, The strip-shaped heterojunction (24) includes multiple layers of channel layers (21) and barrier layers (22) arranged alternately.

12. The Schottky diode according to claim 1, characterized in that, The anode (03) is a field plate structure, and the anode (03) extends from the first end of multiple strip-shaped heterojunctions (24) to the side of the strip-shaped heterojunction (24) away from the entire-surface heterojunction (23).

13. A manufacturing method of a Schottky diode, characterized in that, Comprising: Providing a substrate (01); Forming an entire-surface heterojunction (23) on the substrate (01); Forming multiple strip-shaped heterojunctions (24) on the surface of the entire-surface heterojunction (23) away from the substrate (01); wherein, two adjacent strip-shaped heterojunctions (24) are arranged at intervals; the entire-surface heterojunction (23) and the multiple strip-shaped heterojunctions (24) constitute a heterostructure (02); Forming an anode (03) and a cathode (04) on the surface of the entire-surface heterojunction (23) away from the substrate (01), wherein, the anode (03) is located at the first end of multiple strip-shaped heterojunctions (24), the cathode (04) is located at the second end of multiple strip-shaped heterojunctions (24), and the direction in which the first end of multiple strip-shaped heterojunctions (24) points to the second end of multiple strip-shaped heterojunctions (24) is the extending direction of multiple strip-shaped heterojunctions (24).

14. The manufacturing method of the Schottky diode according to claim 13, wherein, Forming multiple strip-shaped heterojunctions (24) on the surface of the entire-surface heterojunction (23) away from the substrate (01) includes: Forming a first mask layer (010) on the surface of the entire-surface heterojunction (23) away from the substrate (01), wherein, the first mask layer (010) includes multiple strip-shaped openings (0101) arranged at intervals; Forming the strip-shaped heterojunction (24) at the strip-shaped openings (0101) of two first mask layers (010) by selective epitaxy; Removing the first mask layer (010); Or, forming multiple strip-shaped heterojunctions (24) on the surface of the entire-surface heterojunction (23) away from the substrate (01) includes: Forming an entire-layer heterojunction (011) on the surface of the entire-surface heterojunction (23) away from the substrate (01); Etching the entire-layer heterojunction (011) to form multiple strip-shaped heterojunctions (24); wherein, two adjacent strip-shaped heterojunctions (24) are arranged at intervals.

15. The manufacturing method of the Schottky diode according to claim 13, wherein, After forming multiple strip-shaped heterojunctions (24) on the surface of the entire-surface heterojunction (23) away from the substrate (01), further included is: Forming p-GaN (012) on the side of the heterostructure (02) away from the substrate (01); Forming a patterned second mask layer (013) on the side of the p-GaN (012) away from the substrate (01), wherein, the exposed area of the second mask layer (013) is located between two adjacent strip-shaped heterojunctions (24); The p-GaN (012) is activated by an annealing process in the region exposed by the second mask layer (013) to form a first p-GaN layer (05) between two adjacent strip heterojunctions (24). Alternatively, After forming a plurality of strip heterojunctions (24) on the surface of the whole heterojunction (23) away from the substrate (01), it further includes: Forming a patterned third mask layer (014) on the side of the heterostructure (02) away from the substrate (01), wherein the region exposed by the third mask layer (014) is located between two adjacent strip heterojunctions (24); Forming p-GaN (012) by selective epitaxial growth in the region exposed by the third mask layer (014); Activating the p-GaN (012) by an annealing process to form a first p-GaN layer (05) between two adjacent strip heterojunctions (24).

Images