Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a voltage withstanding part which comprises a SiC epitaxial layer, a P-type layer and an N-type layer, and the P-type layer and the SiC epitaxial layer form a PN junction and divide the SiC epitaxial layer into a drift region and a JFET region; the channel part comprises a heterostructure layer, a source electrode and an electrode, the heterostructure layer is provided with an electron gas channel, the source electrode and the electrode are electrically connected through the electron gas channel, the source electrode is in ohmic contact with the P-type layer, and the electrode and the JFET region are in ohmic contact through the N-type layer; wherein the P-type layer is provided with a shielding part, the shielding part and the N-type layer form a PN junction, and the shielding part is in short circuit with the source electrode. According to the invention, the shielding part can compensate the electric field recess caused by the existence of the N-type layer to improve the voltage resistance, and the shielding part is in short circuit with the source electrode to avoid the potential change caused by the floating of the shielding part.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a semiconductor device. Background Art

[0002] SiC / GaN hybrid field effect transistors make full use of the complementary advantages of GaN lateral structure and SiC vertical structure, so that it has the advantages of high withstand voltage and low on-resistance, thus better meeting the application scenarios with higher requirements for both withstand voltage performance and on-resistance.

[0003] When the SiC / GaN hybrid field effect transistor in the related art is subjected to high leakage voltage, the PN junction formed by the P-type layer and the SiC epitaxial layer on both sides is in a reverse-biased cut-off state, and the depletion region in the SiC epitaxial layer widens to bear most of the voltage drop until the JFET region between the two P-type layers is completely depleted, and the reverse bias voltage is mainly borne by this PN junction. However, due to the existence of the N-type layer between the two P-type layers, the high N-type doping of the N-type layer will lead to a very high space charge region concentration, which makes it difficult for the N-type layer depletion region to widen to achieve sufficient withstand voltage. Therefore, in practical applications, the existence of the N-type layer will reduce the withstand voltage performance of the device. Summary of the invention

[0004] In view of the above problems, the present application provides a semiconductor device that can compensate for the "electric field depression" caused by the existence of the N-type layer through a shielding part to improve the voltage resistance performance, and can avoid the potential change caused by the floating of the shielding part by short-circuiting the shielding part with the source.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: a voltage-resistant portion, comprising a SiC epitaxial layer, a P-type layer and an N-type layer, the P-type layer forming a PN junction with the SiC epitaxial layer and dividing the SiC epitaxial layer into a drift region and a JFET region; a channel portion, comprising a heterostructure layer, a source and an electrode, the heterostructure layer having an electron gas channel, the electron gas channel electrically connecting the source and the electrode, the source being in ohmic contact with the P-type layer, and the electrode being in ohmic contact with the JFET region via the N-type layer; wherein the P-type layer has a shielding portion, the shielding portion forming a PN junction with the N-type layer, and the shielding portion being short-circuited with the source.

[0006] When the semiconductor device in the above technical solution is in forward blocking, a high drain voltage is applied. On the one hand, the PN junction formed by the P-type layer and the SiC epitaxial layer is in a reverse-biased cut-off state, and the depletion region expands until the entire JFET region is depleted. Therefore, the reverse-biased voltage is borne by the PN junction between the P-type layer and the SiC epitaxial layer. When the N-type layer is not protected, the high N-type doping in the N-type layer will result in a high space charge region concentration, which makes it difficult for the depletion region of the N-type layer to expand to achieve sufficient breakdown voltage. Therefore, by forming a PN junction between the shielding portion and the N-type layer, the "electric field depression" caused by the presence of the N-type layer can be compensated, that is, part of the electric field lines starting from the depletion region of the N-type layer end at the space charge of the shielding portion instead of the SiC epitaxial layer, thereby improving the breakdown voltage performance of the semiconductor device. On the other hand, under a high drain voltage, holes will flow from the shielding portion with a higher potential through the depletion region to the P-type layer region connected to the source with a lower potential. When the drain voltage is removed, the depletion region disappears quickly. If the shielding portion is floating, the holes that have flowed away will not have time to return, and the shielding portion will change its potential due to a large amount of net negative charges left, which may lead to unpredictable results such as functional degradation or failure of the semiconductor device. Therefore, by short-circuiting the shielding portion and the source, the potential change caused by the floating of the shielding portion can be avoided.

[0007] In some embodiments, both the P-type layer and the N-type layer are symmetric about the symmetry plane.

[0008] In the above technical solution, setting both the P-type layer and the N-type layer to be symmetric about the symmetry plane can make the breakdown voltage of the semiconductor device uniform to avoid the reduction of the breakdown voltage of the semiconductor device caused by the short-board effect.

[0009] In some embodiments, the shielding portion is provided on the side of the N-type layer away from the channel portion.

[0010] In the above technical solution, the N-type layer is a thin N-type heavily doped region with a small side area. Even if a PN junction is formed with the shielding portion, its improvement in breakdown voltage performance is small. However, the bottom area on the side of the N-type layer away from the channel portion is large, and the bottom surface can form a PN junction with the shielding portion over a large area, so the improvement in breakdown voltage performance is high.

[0011] In some embodiments, the P-type layer includes: two first regions spaced apart to form a JFET region; a second region provided in the JFET region and connecting the two first regions; wherein, the second region has a channel filled with the JFET region.

[0012] In the above technical solution, the two first regions are spaced apart to form a JFET region and the second region has a channel filled with the JFET region. On the one hand, it can make the depletion region between the two first regions expand sufficiently. On the other hand, it can make the JFET region allow current to flow.

[0013] In some embodiments, the first region is in ohmic contact with the source electrode, the N-type layer is disposed between two first regions, and the second region includes: a sub-region that forms a PN junction with the N-type layer; and a plurality of bridges, each bridge connecting the sub-region and the first region, and the bridges are spaced apart to form a plurality of channels.

[0014] In the above technical solution, the P-type layer is in ohmic contact with the source electrode through the ohmic contact between the first region and the source electrode; the sub-region is a shielding part, and the sub-region is short-circuited to the source electrode through each bridge and the first region to prevent the shielding part from floating.

[0015] In some embodiments, the second region satisfies at least one of the following conditions: the orthographic projection of the sub-region on the channel portion coincides with the orthographic projection of the N-type layer on the channel portion; each bridge extends to connect to the surface of the N-type layer facing the first region.

[0016] In the above technical solution, on the one hand, the orthographic projection of the sub-region on the channel portion coincides with the orthographic projection of the N-type layer on the channel portion, so that the same mask can be used when the sub-region and the N-type layer are doped, which simplifies the process flow and reduces the number of masks, thereby reducing costs; on the other hand, each bridge extends to connect to the surface of the N-type layer facing the first region, that is, each bridge can also form a PN junction with the N-type layer, so that the formation process of each bridge can be simplified and the PN junction area formed by the N-type layer can be increased to further increase the breakdown voltage performance of the semiconductor device.

[0017] In some embodiments, the first region is in ohmic contact with the source electrode, the second region includes a plurality of bridges, each bridge connecting two first regions, and the bridges are spaced apart to form a plurality of channels, and the N-type layer includes: two third regions, which are spaced apart, and each third region forms a PN junction with each first region in a one-to-one correspondence; and a plurality of beams, each beam connecting two third regions, and each beam is electrically connected to the electrode, and each beam forms a PN junction with each bridge in a one-to-one correspondence.

[0018] In the above technical solution, the P-type layer is in ohmic contact with the source electrode through the ohmic contact between the first region and the source electrode; the shielding part includes each bridge and a part of each first region, and the shielding part is short-circuited to the source electrode through the first region to prevent the shielding part from floating.

[0019] In some embodiments, the N-type layer divides the surface of the JFET region facing the channel portion into a plurality of scattering effect regions, and an auxiliary layer is formed by N-type doping in each scattering effect region. Among them, the doping concentration of the auxiliary layer is less than the doping concentration of the N-type layer, and the auxiliary layer covers the scattering effect region.

[0020] In the above technical solution, compared with a semiconductor device without an auxiliary layer formed by doping, the auxiliary layer formed by N-type doping can reduce the surface scattering effect of each scattering effect region, thereby reducing the negative impact of the surface scattering effect on the on-resistance of this section of the current path.

[0021] In some embodiments, the N-type layer divides the surface of the JFET region facing the channel portion into a plurality of scattering effect regions, and an auxiliary layer is formed by P-type doping in each scattering effect region. Among them, the auxiliary layer and the N-type layer are arranged at a preset interval, and the auxiliary layer is also connected to the bridge.

[0022] In the above technical solution, the auxiliary layer formed by P-type doping and the N-type layer are arranged at a preset interval, so that the auxiliary layer blocks the flow of electron current at most positions close to the surface of the JFET region when conducting, in order to reduce the negative impact of the surface scattering effect on the on-resistance. Among them, the preset interval is the distance that minimizes the on-resistance between the auxiliary layer and the N-type layer. If the interval between the auxiliary layer and the N-type layer is too small, then the region of the SiC epitaxial layer between the auxiliary layer and the N-type layer is very narrow, resulting in a large on-resistance; while if the interval between the auxiliary layer and the N-type layer is too large, the on-resistance will increase due to the long path of the current at the surface close to the SiC epitaxial layer, that is, the effect introduced by the auxiliary layer is lost. Therefore, as the interval between the auxiliary layer and the N-type layer increases, the on-resistance will show a trend of first decreasing and then increasing. In addition, by connecting the auxiliary layer to the bridge, the auxiliary layer can also be short-circuited to the source through the P-type layer, thus avoiding potential changes caused by the floating of the auxiliary layer.

[0023] In some embodiments, the second region includes a plurality of bridges, each bridge connects two first regions, and each bridge is spaced apart to form a plurality of channels, and each bridge is in ohmic contact with the source; the N-type layer includes: two third regions, which are arranged at intervals, and each third region forms a PN junction with each first region in a one-to-one correspondence.

[0024] In the above technical solution, the P-type layer is in ohmic contact with the source through the ohmic contact between each bridge and the source; the shielding part includes each first region, and each first region is short-circuited to the source through the second region to avoid the floating of the shielding part.

[0025] In some embodiments, the orthographic projection of the first region on the channel portion coincides with the orthographic projection of the third region on the channel portion.

[0026] In the above technical solution, the orthographic projection of the first region on the channel portion coincides with the orthographic projection of the third region on the channel portion, so that the first region and the third region can use the same mask during doping to simplify the process flow and reduce the number of masks, thereby reducing costs.

[0027] The above description is only an overview of the technical solution of the present application. In order to be able to more clearly understand the technical means of the present application, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Upon reading the following detailed description of the preferred embodiments, various other advantages and benefits will become apparent to those of ordinary skill in the art. The drawings are only for the purpose of illustrating the preferred embodiments and are not considered to be a limitation of the present application. Also, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0029] Figure 1 It is a cross-sectional view of the semiconductor device along section A-A of the first embodiment of the present application;

[0030] Figure 2 It is a cross-sectional view of the semiconductor device along section B-B of the first embodiment of the present application;

[0031] Figure 3 It is a top view of the semiconductor device along section V-V of the first embodiment of the present application;

[0032] Figure 4 It is a top view of the semiconductor device along section M-M of the first embodiment of the present application;

[0033] Figure 5 It is a top view of the P-type layer in the semiconductor device of the first embodiment of the present application;

[0034] Figure 6 It is a cross-sectional view of the semiconductor device along section A-A of the second embodiment of the present application;

[0035] Figure 7 It is a cross-sectional view of the semiconductor device along section B-B of the second embodiment of the present application;

[0036] Figure 8 It is a top view of the semiconductor device along section M-M of the second embodiment of the present application;

[0037] Figure 9 It is a top view of the P-type layer in the semiconductor device of the second embodiment of the present application;

[0038] Figure 10 It is a cross-sectional view of the semiconductor device along section A-A of the third embodiment of the present application;

[0039] Figure 11 It is a cross-sectional view of the semiconductor device along section B-B of the third embodiment of the present application;

[0040] Figure 12 It is a top view of the semiconductor device along section M-M of the third embodiment of the present application;

[0041] Figure 13 It is a top view of the P-type layer in the semiconductor device of the third embodiment of the present application;

[0042] Figure 14 It is a cross-sectional view of the semiconductor device along section A-A of the fourth embodiment of the present application;

[0043] Figure 15 Top view of cross-section M-M of the semiconductor device according to the fourth embodiment of the present application;

[0044] Figure 16 Cross-sectional view of cross-section A-A of the semiconductor device according to the fifth embodiment of the present application;

[0045] Figure 17 Top view of cross-section M-M of the semiconductor device according to the fifth embodiment of the present application;

[0046] Figure 18 Top view of the P-type layer in the semiconductor device according to the fifth embodiment of the present application;

[0047] Figure 19 Cross-sectional view of cross-section A-A of the semiconductor device according to the sixth embodiment of the present application;

[0048] Figure 20 Cross-sectional view of cross-section B-B of the semiconductor device according to the sixth embodiment of the present application;

[0049] Figure 21 Top view of cross-section M-M of the semiconductor device according to the sixth embodiment of the present application;

[0050] Figure 22 Top view of the P-type layer in the semiconductor device according to the sixth embodiment of the present application;

[0051] Figure 23 Cross-sectional view of cross-section A-A of the semiconductor device according to the seventh embodiment of the present application;

[0052] Figure 24 Cross-sectional view of cross-section B-B of the semiconductor device according to the eighth embodiment of the present application;

[0053] Figure 25 Top view of cross-section V-V of the semiconductor device according to the eighth embodiment of the present application;

[0054] Figure 26 Cross-sectional view of cross-section A-A of the semiconductor device according to the ninth embodiment of the present application.

[0055] The reference numerals in the specific embodiments are as follows:

[0056] 1. Voltage withstand portion; 10. SiC epitaxial layer; 101. Drift region; 103. JFET region; 105. Scattering effect region; 107. Auxiliary layer; 11. P-type layer; 111. First region; 113. Second region; 114. Channel; 115. Sub-region; 116. Bridge; 118. Ohmic region; 12. N-type layer; 121. Third region; 123. Beam; 13. SiC substrate; 14. Drain;

[0057] 3. Channel portion; 15. Heterostructure layer; 15A. Electron gas channel; 151. Buffer layer; 153. GaN layer; 155. AlGaN layer; 16. Source electrode; 161. Conductive portion; 17. Electrode; 171. Conductive unit; 18. Isolation layer; 19. Gate electrode;

[0058] 5. First symmetry plane; 6. Second symmetry plane; X. First direction; Y. Second direction. Detailed implementation manners

[0059] To make the objectives, technical solutions and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are part of rather than all of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the scope of protection of this application.

[0060] Unless otherwise defined, all technical and scientific terms used in this application have the same meanings as those commonly understood by those skilled in the technical field to which this application belongs; the terms used in the description of this application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the description and claims of this application and the above accompanying drawings are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the description and claims of this application or the above accompanying drawings are used to distinguish different objects and not to describe a specific order or primary-secondary relationship.

[0061] Referring to "embodiments" in this application means that specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various positions in the description does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments.

[0062] In the description of this application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", "connected to", and "attached to" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0063] In this application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, in this application, the character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0064] In the embodiments of this application, the same reference numerals represent the same components, and for the sake of brevity, in different embodiments, the detailed description of the same components is omitted. It should be understood that the thickness, length, width, etc. of various components shown in the drawings of the embodiments of this application, as well as the overall thickness, length, width, etc. of the integrated device, are only for illustrative purposes and should not constitute any limitation to this application.

[0065] The term "plurality" as used in this application refers to two or more (including two).

[0066] The term "parallel" in this application includes not only the case of absolute parallelism but also the case of approximately parallelism as conventionally understood in engineering; at the same time, "perpendicular" also includes not only the case of absolute perpendicularity but also the case of approximately perpendicularity as conventionally understood in engineering.

[0067] In the related art, when the SiC / GaN hybrid field-effect transistor is in the forward blocking state, a forward high voltage is applied to the drain to make the device withstand a high drain voltage. At this time, the PN junctions formed by the P-type layers on both sides and the SiC epitaxial layer are in the reverse-biased cut-off state, and the depletion region in the SiC epitaxial layer widens to withstand most of the voltage drop until the entire JFET region between the two P-type layers is depleted, and then the reverse-biased voltage is mainly borne by this PN junction. However, due to the existence of the N-type layer between the two P-type layers, the high N-type doping in the N-type layer will result in a very high space charge region concentration, thereby making it difficult for the depletion region of the N-type layer to widen to achieve sufficient breakdown voltage. Because when the position of the PN junction reaches the same critical breakdown electric field, the N-type layer forms a very thin depletion region with a large electric field slope, thus blocking the penetration of the electric field lines of the built-in electric field in the N-type layer, which is intuitively reflected as a "depression" region in the electric field distribution diagram. Therefore, in practical applications, the existence of the N-type layer will reduce the breakdown voltage performance of the device.

[0068] Based on the above considerations, this application designs a semiconductor device.

[0069] The semiconductor device of this application includes but is not limited to being applied in fields such as electric vehicles, electronic devices, and power management systems, and is especially suitable for application scenarios with high requirements for both breakdown voltage performance and on-resistance.

[0070] Please refer to Figures 1 to 26 , Figure 1 is a cross-sectional view of the semiconductor device along section A-A of the first embodiment of this application; Figure 2Cross-sectional view of the semiconductor device taken along line B-B of the first embodiment of the present application; Figure 3 Top view of the semiconductor device taken along line V-V of the first embodiment of the present application; Figure 4 Top view of the semiconductor device taken along line M-M of the first embodiment of the present application; Figure 5 Top view of the P-type layer in the semiconductor device of the first embodiment of the present application; Figure 6 Cross-sectional view of the semiconductor device taken along line A-A of the second embodiment of the present application; Figure 7 Cross-sectional view of the semiconductor device taken along line B-B of the second embodiment of the present application;

[0071] Figure 8 Top view of the semiconductor device taken along line M-M of the second embodiment of the present application; Figure 9 Top view of the P-type layer in the semiconductor device of the second embodiment of the present application; Figure 10 Cross-sectional view of the semiconductor device taken along line A-A of the third embodiment of the present application; Figure 11 Cross-sectional view of the semiconductor device taken along line B-B of the third embodiment of the present application; Figure 12 Top view of the semiconductor device taken along line M-M of the third embodiment of the present application; Figure 13 Top view of the P-type layer in the semiconductor device of the third embodiment of the present application; Figure 14 Cross-sectional view of the semiconductor device taken along line A-A of the fourth embodiment of the present application; Figure 15 Top view of the semiconductor device taken along line M-M of the fourth embodiment of the present application; Figure 16 Cross-sectional view of the semiconductor device taken along line A-A of the fifth embodiment of the present application; Figure 17 Top view of the semiconductor device taken along line M-M of the fifth embodiment of the present application; Figure 18 Top view of the P-type layer in the semiconductor device of the fifth embodiment of the present application; Figure 19 Cross-sectional view of the semiconductor device taken along line A-A of the sixth embodiment of the present application; Figure 20 Cross-sectional view of the semiconductor device taken along line B-B of the sixth embodiment of the present application; Figure 21 Top view of the semiconductor device taken along line M-M of the sixth embodiment of the present application; Figure 22 Top view of the P-type layer in the semiconductor device of the sixth embodiment of the present application; Figure 23 Cross-sectional view of the semiconductor device taken along line A-A of the seventh embodiment of the present application; Figure 24 Cross-sectional view of the semiconductor device taken along line B-B of the eighth embodiment of the present application; Figure 25 Top view of the semiconductor device taken along line V-V of the eighth embodiment of the present application; Figure 26 Cross-sectional view of the semiconductor device taken along line A-A of the ninth embodiment of the present application.

[0072] As Figures 1 to 26As shown, the semiconductor device provided by an embodiment of the present application includes a breakdown voltage portion 1 and a channel portion 3. Among them, the breakdown voltage portion 1 and the channel portion 3 are demarcated by a cross-section M-M. The breakdown voltage portion 1 is used to achieve the breakdown voltage of the semiconductor device, and the channel portion 3 is used to control the on-off of the electron gas channel of the semiconductor device.

[0073] The channel portion 3 includes a heterostructure layer 15, a source electrode 16, and an electrode 17. The heterostructure layer 15 has an electron gas channel 15A. The electron gas channel 15A electrically connects the source electrode 16 and the electrode 17. The source electrode 16 is in ohmic contact with the P-type layer 11, and the electrode 17 and the JFET region 103 are in ohmic contact through the N-type layer 12. Thus, the source electrode 16 electrically connects the P-type layer 11 and the electron gas channel 15A, and the electrode 17 electrically connects the JFET region 103 and the electron gas channel 15A.

[0074] As Figure 19 、 Figure 20 、 Figure 23 and Figure 25 shown, in some embodiments, the source electrode 16 is disposed between the two electrodes 17.

[0075] As Figure 1 、 Figure 2 、 Figure 6 、 Figure 7 、 Figure 10 、 Figure 11 、 Figure 14 and Figure 16 shown, in some embodiments, the electrode 17 is disposed between the two source electrodes 16.

[0076] In some embodiments, the heterostructure layer 15 includes a buffer layer 151, a GaN layer 153, and an AlGaN layer 155 stacked in sequence. The buffer layer 151 is disposed on the breakdown voltage portion 1. Among them, the connection interface between the GaN layer 153 and the AlGaN layer 155 is the electron gas channel 15A.

[0077] In some embodiments, both the source electrode 16 and the electrode 17 are conductive metal layers. Among them, the conductive metal layer that electrically connects the P-type layer 11 and the electron gas channel 15A is used as the source electrode 16, and the conductive metal layer that electrically connects the JFET region 103 and the electron gas channel 15A is used as the electrode 17.

[0078] In some embodiments, the channel portion 3 further includes an isolation layer 18 and a gate 19. The isolation layer 18 is disposed on the heterostructure layer 15, and the gate 19 is disposed on a side of the isolation layer 18 away from the heterostructure layer 15.

[0079] In the channel portion 3, applying a voltage on the gate 19 can adjust the electron concentration in the electron gas channel 15A to control the on-off of the electron gas channel 15A.

[0080] Specifically, when the voltage of the gate 19 is less than the threshold voltage, the electrons in the electron gas channel 15A are depleted and no current flows, so that the electron gas channel 15A is non-conductive; when the voltage of the gate 19 is greater than the threshold voltage, the electric field of the gate 19 attracts electrons and increases the electron concentration in the electron gas channel 15A, so that the electron gas channel 15A is conductive, thus allowing current to pass through the electron gas channel 15A.

[0081] In some embodiments, the isolation layer 18 is a dielectric layer.

[0082] In some embodiments, the isolation layer 18 is a capping layer.

[0083] The capping layer can be any one or a combination of several of InN, GaN, AlN, AlGaN, InGaN, InAlN, InAlGaN, etc., can also be a ferroelectric material or a polarization material, and can also be a P-type semiconductor material doped or unintentionally doped.

[0084] It can be understood that in some embodiments, the gate can also be in Schottky contact with the heterostructure layer directly.

[0085] The voltage withstand portion 1 includes an SiC epitaxial layer 10, a P-type layer 11 and an N-type layer 12. The P-type layer 11 forms a PN junction with the SiC epitaxial layer 10 and divides the SiC epitaxial layer 10 into a drift region 101 and a JFET region 103. The source electrode 16 is in ohmic contact with the P-type layer 11, and the electrode 17 and the N-type layer 12 are in ohmic contact through the JFET region 103. When the semiconductor device is conducting forward, that is, when the electron gas channel 15A is conductive, the drift region 101, the JFET region 103, the N-type layer 12, the electrode 17, the electron gas channel 15A and the source electrode 16 form a current path.

[0086] Among them, the P-type layer 11 and the SiC epitaxial layer 10 have different conduction types; the N-type layer 12 and the SiC epitaxial layer 10 have the same conduction type, and the doping concentration of the N-type layer 12 is greater than that of the JFET region 103.

[0087] Among them, the drift region 101 and the JFET region 103 constitute the depletion region of the PN junction.

[0088] Among them, the SiC epitaxial layer 10 is used for voltage withstand; the SiC epitaxial layer 10 is formed by doping an N-type semiconductor material with an SiC material as a skeleton.

[0089] In some embodiments, the SiC epitaxial layer 10 is formed by directly doping the required N-type semiconductor material as a dopant during the epitaxial growth process of the SiC material.

[0090] In some embodiments, the voltage withstand portion 1 is a vertical structure, and in this vertical structure, the drain is located on the back of the SiC substrate of the semiconductor device. As Figures 1 to 25As shown, the voltage withstand portion 1 further includes a SiC substrate 13 and a drain 14. The SiC epitaxial layer 10 is disposed on the SiC substrate 13, and the drain 14 is disposed on a side of the SiC substrate 13 facing away from the SiC epitaxial layer 10.

[0091] In some embodiments, the voltage withstand portion 1 has a lateral structure. In this lateral structure, the voltage withstand is achieved by the lateral expansion of the PN junction depletion region formed by the P-type layer 11 and the SiC epitaxial layer 10. As Figure 26 shown, the voltage withstand portion 1 further includes a SiC substrate 13 and a drain 14. The drain 14 and the channel portion 3 are disposed on the same side of the SiC epitaxial layer 10, and the SiC substrate 13 connects the drain 14 and the SiC epitaxial layer 10.

[0092] Among them, the lateral expansion of the PN junction depletion region actually refers to the lateral expansion of the drift region 101.

[0093] In some embodiments, the SiC substrate 13 is formed by doping the surface of the SiC epitaxial layer 10 facing the channel portion 3.

[0094] It can be understood that, in some embodiments, the SiC substrate can also be formed by depositing on the surface of the SiC epitaxial layer facing the channel portion.

[0095] In some embodiments, the SiC substrate 13 and the SiC epitaxial layer 10 have the same conductivity type. At this time, the semiconductor device is a unipolar device, similar to a power MOSFET.

[0096] In some embodiments, the SiC substrate 13 and the SiC epitaxial layer 10 can also have different conductivity types. At this time, the semiconductor device is a bipolar device, similar to an IGBT.

[0097] The P-type layer 11 has a shielding portion. The shielding portion forms a PN junction with the N-type layer 12, and the shielding portion is short-circuited with the source 16.

[0098] In some embodiments, both the P-type layer 11 and the N-type layer 12 are symmetric about a symmetry plane. As Figure 4 、 Figure 5 、 Figure 8 、 Figure 9 、 Figure 12 、 Figure 13 、 Figure 15 、 Figure 17 、 Figure 18 、 Figure 21 、 Figure 22 shown, both the P-type layer 11 and the N-type layer 12 are symmetric about the first symmetry plane 5 left and right, and both the P-type layer 11 and the N-type layer 12 are symmetric about the second symmetry plane 6 up and down. Among them, both the first symmetry plane 5 and the second symmetry plane 6 are perpendicular to the plane where the first direction X and the second direction Y are located, and the cross-section M-M is parallel to the plane where the first direction X and the second direction Y are located.

[0099] In some embodiments, the shielding portion is disposed on a side of the N-type layer 12 away from the channel portion 3.

[0100] In some embodiments, the P-type layer 11 includes two first regions 111 and a second region 113. The two first regions 111 are spaced apart to form a JFET region 103, the second region 113 is disposed within the JFET region 103 and connects the two first regions 111, and the second region 113 has a channel 114 filled with the JFET region 103.

[0101] Wherein, the two first regions 111 are spaced along a first direction X.

[0102] As Figures 1 to 9 and Figures 24 to 26 shown, in some embodiments, the first region 111 is in ohmic contact with the source electrode 16, the N-type layer 12 is disposed between the two first regions 111, the second region 113 includes a sub-region 115 and a plurality of bridges 116, the sub-region 115 forms a PN junction with the N-type layer 12, each bridge 116 connects the sub-region 115 and the first region 111, and between the sub-region 115 and the first region 111, the bridges 116 are spaced apart to form a plurality of channels 114. That is to say, the sub-region 115 is the shielding portion, and the shielding portion is short-circuited to the source electrode 16 through the first region 111 and each bridge 116.

[0103] Wherein, the bridges 116 are spaced along a second direction Y, the first direction X is perpendicular to the second direction Y, and both the first direction X and the second direction Y are parallel to the cross-section M-M.

[0104] In some embodiments, the orthographic projection of the sub-region 115 on the channel portion 3 coincides with the orthographic projection of the N-type layer 12 on the channel portion 3.

[0105] In some embodiments, each bridge 116 extends to connect to the surface of the N-type layer 12 facing the first region 111. That is to say, each bridge 116 forms a PN junction with the side surface of the N-type layer 12.

[0106] In some embodiments, two first regions 111, a plurality of bridges 116, and a prefabricated region are formed by ion implantation doping of P-type semiconductor material in a local area of the SiC epitaxial layer 10; N-type semiconductor material is doped in a local area of the prefabricated region by ion implantation to form the N-type layer 12, and the doping concentration of the N-type layer 12 is greater than the doping concentration of the SiC epitaxial layer 10, and the portion of the prefabricated region not doped with N-type semiconductor material forms the sub-region 115. Wherein, the direction of ion implantation is perpendicular to the cross-section M-M. This ion implantation doping method can precisely control the doping dose, depth, and distribution.

[0107] It should be noted that the P-type layer 11 has a different conduction type from the SiC epitaxial layer 10 through the effect of "impurity compensation". Specifically, the local part of the SiC epitaxial layer 10 formed by doping the SiC material skeleton with an N-type semiconductor material is doped with a P-type semiconductor material. The electrons and holes ionized from the two semiconductor materials will cancel each other out, and the extra P-type semiconductor material will form the doping concentration of the P-type semiconductor material locally in the SiC epitaxial layer 10, that is, the first region 111, multiple bridges 116 and a prefabricated region are formed.

[0108] It should also be noted that the N-type layer 12 also has the same conduction type as the SiC epitaxial layer 10 through the effect of "impurity compensation". Specifically, the local part of the prefabricated region formed by doping with a P-type semiconductor material is further doped with an N-type semiconductor material. The electrons and holes ionized from the two semiconductor materials will also cancel each other out, and the extra N-type semiconductor material will form the doping concentration of the N-type semiconductor material locally in the prefabricated region, that is, the N-type layer 12 is formed, and the part of the prefabricated region that is not doped with the N-type semiconductor material forms the sub-region 115.

[0109] It should be noted that, as Figures 1 to 5 shown in the first embodiment and Figures 6 to 9 the difference between the second embodiment shown is only that: the mask plates used in the forming processes of the P-type layer 11 and the N-type layer 12 are different, resulting in different layouts of the formed P-type layer 11 and N-type layer 12.

[0110] As Figures 10 to 18 shown, in some embodiments, the first region 111 is in ohmic contact with the source electrode 16. The second region 113 includes multiple bridges 116. Each bridge 116 connects two first regions 111, and each bridge 116 is spaced apart to form multiple channels 114. The N-type layer 12 includes two third regions 121 and multiple beams 123. The two third regions 121 are arranged at intervals. Each third region 121 forms a PN junction with each first region 111 in a one-to-one correspondence; each beam 123 connects two third regions 121, and each beam 123 is electrically connected to the electrode 17. Each beam 123 forms a PN junction with each bridge 116 in a one-to-one correspondence.

[0111] Among them, the two third regions 121 are arranged at intervals along the first direction X, and each bridge 116 is arranged at intervals along the second direction Y.

[0112] It should be noted that in order to make the first region 111 in ohmic contact with the source electrode 16 and each third region 121 form a PN junction with each first region 111 in a one-to-one correspondence, only the facing ends of each third region 121 extend in the first direction X to cover the first region 111, while the opposite ends of each third region 121 are covered by the first region 111. That is to say, the local part of each first region 111 and each bridge 116 constitute a shielding part, and the shielding part is short-circuited to the source electrode 16 through the first region 111.

[0113] In some embodiments, in the first direction X, a part of the third region 121 protrudes locally from the first region 111. Thus, while the third region 121 is protected by the first region 111, a small part thereof extends into the JFET region 103 to connect with the JFET region 103.

[0114] In some embodiments, P-type semiconductor material doping is performed locally on the SiC epitaxial layer 10 by ion implantation to form two first prefabricated regions and multiple second prefabricated regions; N-type semiconductor material doping is performed locally on each part of the two first prefabricated regions, each part of the multiple second prefabricated regions, and the JFET region 103. Among them, the parts of the two first prefabricated regions that are not doped with N-type semiconductor material form the first regions 111, the parts of the multiple second prefabricated regions that are not doped with N-type semiconductor material form the multiple bridges 116, the third region 121 is formed by doping N-type semiconductor material on each part of the two first prefabricated regions, each part of the multiple second prefabricated regions, and the JFET region 103, and the multiple beams 123 are formed by doping N-type semiconductor material on each second prefabricated region. That is to say, each second prefabricated region can be divided into a first part, a second part, and a third part. The part of the first part that is not doped with N-type semiconductor material forms the bridge 116, the second part is doped with N-type semiconductor material to form a part of the third region 121, and the third part is doped with N-type semiconductor material to form the multiple beams 123.

[0115] Among them, the doping concentration of the third region 121 and the multiple beams 123 is greater than the doping concentration of the SiC epitaxial layer 10.

[0116] It should be noted that in some embodiments, the opposite ends of each third region can also be aligned with the boundary of the first region in the direction perpendicular to the cross-section M-M. Correspondingly, the third region is formed by doping N-type semiconductor material locally on each first prefabricated region, and the part of each first prefabricated region that is not doped with N-type semiconductor material forms the first region; the beam is formed by doping N-type semiconductor material locally on each second prefabricated region, and the part of each second prefabricated region that is not doped with N-type semiconductor material forms the bridge.

[0117] In some embodiments, the electrode 17 is composed of a plurality of spaced conductive units 171, and each conductive unit 171 is electrically connected to each beam 123 one by one. Among them, the plurality of conductive units 171 are spaced along the second direction Y.

[0118] Such as Figures 10 to 15As shown, in some embodiments, the N-type layer 12 divides the surface of the JFET region 103 facing the channel portion 3 into multiple scattering effect regions 105. An auxiliary layer 107 is formed by N-type doping in each scattering effect region 105. The doping concentration of the auxiliary layer 107 is less than that of the N-type layer 12, and the auxiliary layer 107 covers the scattering effect region 105.

[0119] In some embodiments, the auxiliary layer 107 is formed by doping an N-type semiconductor material through ion implantation.

[0120] As Figures 10 to 13 and Figures 16 to 18 shown, in some embodiments, the N-type layer 12 divides the surface of the JFET region 103 facing the channel portion 3 into multiple scattering effect regions 105. An auxiliary layer 107 is formed by P-type doping in each scattering effect region 105. The auxiliary layer 107 and the N-type layer 12 are spaced apart by a preset distance, and the auxiliary layer 107 is also connected to the bridge 116. It should be noted that, relative to Figures 10 to 13 the embodiments shown, Figures 16 to 18 the masks used in the formation of the bridges in the embodiments shown are different, resulting in different layouts of the formed bridges, so that the auxiliary layer 107 is also connected to the bridge 116.

[0121] As Figures 19 to 23 shown, in some embodiments, the second region 113 includes multiple bridges 116. Each bridge 116 connects two first regions 111, and each bridge 116 is spaced apart to form multiple channels 114. The bridge 116 is in ohmic contact with the source electrode 16. The N-type layer 12 includes two third regions 121, which are spaced apart. Each third region 121 forms a PN junction with each first region 111 in a one-to-one correspondence. That is to say, each first region 111 constitutes a shielding part, and the shielding part is short-circuited to the source electrode 16 through the second region 113 to maintain the potential of the shielding part.

[0122] Among them, each bridge 116 is heavily doped to form an ohmic region 118, so that the bridge 116 is in ohmic contact with the source electrode 16 through the ohmic region 118. That is to say, the ohmic region 118 and the bridge 116 have the same conduction type, and the doping concentration of the ohmic region 118 is greater than that of the bridge 116.

[0123] In some embodiments, the orthographic projection of the first region 111 on the channel portion 3 does not exceed the range of the orthographic projection of the third region 121 on the channel portion 3. That is to say, both sides of each third region 121 extend along the first direction X to completely cover each first region 111.

[0124] As Figure 23As shown, in some embodiments, the orthographic projection of the first region 111 on the channel portion 3 coincides with the orthographic projection of the third region 121 on the channel portion 3. When doping the N-type semiconductor material to form the third region 121 by ion implantation, the same mask plate as that of the first region 111 can be used to reduce the number of mask plates and simplify the process steps, thereby reducing costs.

[0125] As Figures 19 to 23 shown, in some embodiments, the source electrode 16 includes a plurality of spaced-apart conductive portions 161, and each conductive portion 161 is connected to the ohmic region 118 on each bridge 116 in a one-to-one correspondence.

[0126] It should be noted that Figures 19 to 22 the difference between the embodiment shown and Figure 23 the embodiment shown lies only in that: the mask plates for forming the third region 121 are different, resulting in different dimensions of the formed third region 121 in the first direction X.

[0127] As Figures 1 to 23 and Figure 26 shown, in some embodiments, the arrangement direction of the source electrode 16 and the electrode 17 is the first direction X, that is, the extending direction of the electron gas channel 15A is the first direction X.

[0128] As Figure 24 and Figure 25 shown, in some embodiments, the arrangement direction of the source electrode 16 and the electrode 17 is the second direction Y, that is, relative to the embodiment shown in Figures 1 to 23 and Figure 26 shown, the arrangement direction of the source electrode 16 and the electrode 17 is rotated by 90°, resulting in the extending direction of the electron gas channel 15A being rotated by 90° to become the second direction Y. In this state, the source electrode 16 and the first region 111 form the first ohmic contact position 7, the electrode 17 and the N-type layer 12 form the second ohmic contact position 8, and the first ohmic contact position 7 and the second ohmic contact position 8 are located at the diagonal positions of a cell.

[0129] When the above semiconductor device is conducting in the forward direction, the voltage of the gate 19 is greater than the threshold voltage to make the electron gas channel 15A conductive. In this state, the current starts from the drain 14 and sequentially passes through the SiC substrate 13, the SiC epitaxial layer 10, the N-type layer 12, the electrode 17, the electron gas channel 15A to reach the source electrode 16.

[0130] When the above semiconductor device is in forward blocking, the voltage of gate 19 is less than the threshold voltage so that the electron gas channel 15A is non-conductive. In this state, a high drain voltage is applied to drain 14. On the one hand, the PN junction formed by the P-type layer 11 and the SiC epitaxial layer 10 is in a reverse-biased cut-off state, and the depletion region expands until the entire JFET region is depleted. Therefore, the reverse-biased voltage is borne by the PN junction between the P-type layer 11 and the SiC epitaxial layer 10. When the N-type layer 12 is in an unprotected state, the high N-type doping of the N-type layer 12 will result in a very high space charge region concentration, which will make it difficult for the depletion region of the N-type layer to widen to achieve sufficient breakdown voltage. Therefore, by forming a PN junction between the shielding part and the N-type layer 12, the "electric field depression" caused by the presence of the N-type layer 12 can be compensated, that is, part of the electric field lines starting from the depletion region of the N-type layer 12 end at the space charge of the shielding part instead of the SiC epitaxial layer, thereby improving the breakdown voltage performance of the semiconductor device. On the other hand, under a high drain voltage, holes will flow from the shielding part with a higher potential through the depletion region to the region of the P-type layer 11 connected to the source with a lower potential. When the drain voltage is removed, the depletion region disappears quickly. If the shielding part is floating, the holes that have flowed away will not have time to return, and the shielding part will change its potential due to a large amount of net negative charge remaining, which may lead to unpredictable results such as functional degradation or failure of the semiconductor device. Therefore, by short-circuiting the shielding part and the source 16, the potential change caused by the floating of the shielding part can be avoided.

[0131] When the above semiconductor device operates in reverse, the PN junction between the P-type layer 11 and the SiC epitaxial layer 10 can be used as a freewheeling diode. Therefore, the semiconductor device is equivalent to an anti-parallel connection of a power switch device and a power rectifier, and this connection method is widely used in power switch circuits.

[0132] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other.

[0133] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of this application, rather than to limit it; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered by the scope of the claims and the description of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in each embodiment can be combined in any way. This application is not limited to the specific embodiments disclosed in the text, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A voltage-resistant part, comprising a SiC epitaxial layer, a P-type layer and an N-type layer, wherein the P-type layer forms a PN junction with the SiC epitaxial layer and divides the SiC epitaxial layer into a drift region and a JFET region; A channel portion, comprising a heterostructure layer, a source electrode and an electrode, wherein the heterostructure layer has an electron gas channel, the electron gas channel electrically connects the source electrode and the electrode, the source electrode is in ohmic contact with the P-type layer, and the electrode is in ohmic contact with the JFET region via the N-type layer; The P-type layer has a shielding portion, the shielding portion forms a PN junction with the N-type layer, and the shielding portion is short-circuited with the source.

2. The semiconductor device according to claim 1, wherein: The P-type layer and the N-type layer are symmetrical about a symmetry plane.

3. The semiconductor device according to claim 1 or 2, characterized in that: The shielding portion is disposed on a side of the N-type layer away from the channel portion.

4. The semiconductor device according to claim 3, characterized in that The P-type layer comprises: two first regions spaced apart to form the JFET region; A second region is provided in the JFET region and connects the two first regions; The second region has a channel filled by the JFET region.

5. The semiconductor device according to claim 4, characterized in that The first region is in ohmic contact with the source electrode, the N-type layer is disposed between two of the first regions, and the second region includes: A sub-region, forming a PN junction with the N-type layer; A plurality of bridges are provided, each of the bridges connecting the sub-regions and the first region, and each of the bridges is spaced apart between the sub-regions and the first region to form a plurality of the channels.

6. The semiconductor device according to claim 5, characterized in that The second zone satisfies at least one of the following conditions: The orthographic projection of the sub-region on the channel portion coincides with the orthographic projection of the N-type layer on the channel portion; Each of the bridges extends to connect with a surface of the N-type layer facing the first region.

7. The semiconductor device according to claim 4, characterized in that The first region is in ohmic contact with the source electrode, the second region includes a plurality of bridges, each of the bridges connects two of the first regions, and each of the bridges is spaced to form a plurality of channels, and the N-type layer includes: Two third regions are arranged at intervals, and each of the third regions forms a PN junction with each of the first regions in a one-to-one correspondence; A plurality of beams are provided, each of the beams connects two of the third regions, each of the beams is electrically connected to the electrode, and each of the beams forms a PN junction with each of the bridges in a one-to-one correspondence.

8. The semiconductor device according to claim 7, characterized in that The N-type layer separates the surface of the JFET region facing the channel portion into a plurality of scattering effect regions, each of the scattering effect regions is N-type doped to form an auxiliary layer, wherein the doping concentration of the auxiliary layer is less than the doping concentration of the N-type layer, and the auxiliary layer covers the scattering effect region.

9. The semiconductor device according to claim 7, characterized in that The N-type layer separates the surface of the JFET region facing the channel portion into a plurality of scattering effect regions, each of the scattering effect regions is P-type doped to form an auxiliary layer, wherein the auxiliary layer and the N-type layer are arranged at a preset interval, and the auxiliary layer is also connected to the bridge.

10. The semiconductor device according to claim 4, characterized in that The second region includes a plurality of bridges, each of the bridges connects two of the first regions, and each of the bridges is spaced apart to form a plurality of channels, and each of the bridges is in ohmic contact with the source electrode; The N-type layer comprises: Two third regions are arranged at intervals, and each of the third regions forms a PN junction with each of the first regions in a one-to-one correspondence.

11. The semiconductor device according to claim 10, characterized in that An orthographic projection of the first region on the channel portion coincides with an orthographic projection of the third region on the channel portion.

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