Groove type MOSFET device structure and manufacturing method thereof

Abstract

The invention provides a groove type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure and a manufacturing method thereof, and the structure comprises a semiconductor layer which comprises a substrate and an epitaxial layer located at one side of the substrate; the cellular groove is formed in the epitaxial layer at one side far away from the substrate from top to bottom; the terminal groove and the cellular groove are arranged in the epitaxial layer on one side far away from the substrate in parallel from top to bottom, a source terminal and a terminal field plate are arranged in the terminal groove in an up-down spaced mode, and an intermediate dielectric layer is arranged between the source terminal and the terminal field plate. By adjusting the length of the source terminal and the thickness of the intermediate dielectric layer, the potential of the electric field in the terminal area can be gradually transited from high potential to low potential.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and more particularly, to a trench MOSFET device structure and a manufacturing method thereof. Background Art

[0002] In the field of semiconductor devices, trench MOSFETs (metal-oxide-semiconductor field-effect transistors) are widely used in various electronic devices due to their superior performance. However, in the prior art, the terminal structure design of trench MOSFET devices aims to balance the electric field to improve the breakdown voltage of the device. Appropriately increasing the doping concentration of the epitaxial layer helps to reduce the specific on-resistance of the device and improve the overall performance of the device. However, this solution also faces certain challenges. Specifically, in the terminal region, multiple trenches are usually connected by grounding or floating, and the epitaxial layer between adjacent trenches can be depleted, thereby effectively balancing the electric field and increasing the breakdown voltage of the device. However, outside the terminal region, the outermost single trench needs to independently deplete the epitaxial layer outside it. At this time, if the doping concentration of the epitaxial layer is too high, the depletion ability of the outermost trench may be limited, resulting in its inability to normally deplete the epitaxial layer, thereby reducing the breakdown voltage of the terminal. This shortcoming is particularly prominent in high-voltage applications because high-voltage applications have higher requirements for the voltage withstand performance of the device. If the voltage withstand performance of the terminal is insufficient, it may cause the device to break down in a high-voltage environment, thereby affecting the reliability and stability of the device.

[0003] Therefore, how to ensure that the breakdown voltage of the device is not affected while increasing the doping concentration of the epitaxial layer has become an important research issue in the terminal structure design of trench MOSFET devices. Summary of the Invention

[0004] In view of the problems existing in the trench MOSFET devices in the prior art described above, the present application provides a trench MOSFET device structure and a manufacturing method thereof. The trench MOSFET device structure of the present invention includes a cell region and a terminal region;

[0005] Comprising

[0006] a semiconductor layer, the semiconductor layer including a substrate and an epitaxial layer located on one side of the substrate;

[0007] a trench structure, including cell trenches and terminal trenches, the trench structure being located in the epitaxial layer and extending from the surface of the epitaxial layer downward into the interior of the epitaxial layer, the cell trenches and the terminal trenches being arranged in parallel;

[0008] at least part of the terminal trenches are provided with a source terminal and a terminal field plate at intervals up and down, and an intermediate dielectric layer is provided between the source terminal and the terminal field plate.

[0009] Optionally, the cell trench is a split gate, and the cell trench includes a shielding gate and a gate conductive region located above the shielding gate, and the shielding gate and the gate conductive region are isolated by an insulating layer.

[0010] Optionally, a first gate oxide layer and a second field oxide layer are formed on the sidewall of the cell trench, the first gate oxide layer is located around the gate conductive region, and the second field oxide layer is located around the shielding gate.

[0011] Optionally, the cell trench is a standard trench gate, a second gate oxide layer is formed in the cell trench, and a polysilicon layer is deposited in the second gate oxide layer.

[0012] Optionally, at least part of the intermediate dielectric layer has different thicknesses.

[0013] Optionally, along the direction away from the cell trench, the thickness of the intermediate dielectric layer gradually increases.

[0014] Optionally, at least part of the terminal field plate has different lengths.

[0015] Optionally, along the direction away from the cell trench, the length of the terminal field plate gradually increases.

[0016] Optionally, along the direction away from the cell trench, the length of the middle terminal field plate gradually increases.

[0017] Optionally, it further includes:

[0018] A first field oxide layer, formed on the sidewall of the terminal trench;

[0019] An insulating dielectric layer, located on the side of the epitaxial layer away from the substrate to cover the cell trench and the terminal trench;

[0020] A source metal region, located above the insulating dielectric layer;

[0021] A connection structure, penetrating through the insulating dielectric layer to electrically connect the trench structure and the source metal region.

[0022] Optionally, it further includes:

[0023] A body region, formed between the cell trenches and between the adjacent cell trench and the terminal trench;

[0024] A heavily doped region, the heavily doped region is formed in the body region between the cell trenches, the depth of the heavily doped region is less than the depth of the body region, and the connection structure penetrates through the heavily doped region.

[0025] The present invention provides a method for fabricating a trench MOSFET device, comprising the following steps:

[0026] Provide a heavily doped substrate, and form a lightly doped epitaxial layer of the same type on the heavily doped substrate;

[0027] Etch the lightly doped epitaxial layer to form a terminal trench in the terminal region and a cell trench in the cell region;

[0028] Form a first field oxide layer on the inner surface of the terminal trench;

[0029] Deposit polysilicon in the terminal trench and the cell trench;

[0030] Etch the polysilicon in the terminal trench to form a terminal field plate in the first field oxide layer;

[0031] Form an intermediate dielectric layer in the terminal trench;

[0032] Deposit polysilicon in the terminal trench to form a source terminal;

[0033] Deposit an insulating layer on the lightly doped epitaxial layer to form an insulating dielectric layer;

[0034] Form a source metal region above the insulating dielectric layer.

[0035] Optionally, form a second gate oxide layer in the cell trench, and fill polysilicon in the second gate oxide layer to form a polysilicon layer.

[0036] Optionally, the method further comprises the following steps:

[0037] Form a second field oxide layer in the cell trench;

[0038] Etch the polysilicon in the cell trench to form a shielding gate in the second field oxide layer;

[0039] Grow an oxide layer above the shielding gate as a shielding oxide layer;

[0040] Form a first gate oxide layer on the inner surface of the cell trench above the shielding gate;

[0041] Deposit polysilicon in the cell trench to form a gate conductive region;

[0042] Form a body region between the cell trench and the terminal trench closest to the cell trench.

[0043] Optionally, the second field oxide layer and the first field oxide layer can be formed synchronously;

[0044] The intermediate dielectric layer and the first gate oxide layer can be formed synchronously;

[0045] The source terminal and the gate conductive region can be formed synchronously.

[0046] Optionally, it further includes forming a heavily doped region on one side of the body region close to the insulating dielectric layer, and the heavily doped region is connected to the first gate oxide layer and the connection structure.

[0047] As described above, the trench MOSFET device structure and its manufacturing method provided by the present invention at least have the following beneficial technical effects:

[0048] In the trench MOSFET device structure of the present invention, a hierarchical terminal trench structure is designed. Through the intermediate dielectric layer, the terminal trench is divided into a source terminal and a terminal field plate. Under the condition that the length of the terminal field plate remains unchanged, the thicker the intermediate dielectric layer, the higher the potential on the buried field plate; under the condition that the thickness of the intermediate dielectric layer is the same, the longer the length of the terminal field plate, the higher the potential on the buried field plate. Therefore, by adjusting the lengths of the source terminal and the terminal field plate, and the thickness of the intermediate dielectric layer, the electric field distribution can be gradually adjusted, and the electric field potential in the terminal region can be gradually transitioned from a high potential to a low potential, which can significantly improve the breakdown voltage of the device.

[0049] The process steps are simple and the design is flexible, not restricted by the traditional cell region structure. The structure forming the split gate structure in the terminal region provided by the present invention does not depend on the cell region, and the cell region can be a split gate or a conventional trench structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It shows a schematic structural diagram of the trench MOSFET device provided in Embodiment 1.

[0051] Figure 2 It shows a schematic structural diagram of the trench MOSFET device provided in Embodiment 2.

[0052] Figure 3 It shows a flowchart of the manufacturing method of the trench MOSFET device provided in Embodiment 3.

[0053] Figures 4 - 18 It is a schematic diagram of the manufacturing method of the trench MOSFET device provided in Embodiment 2.

[0054] Figure 19 It shows a flowchart of the manufacturing method of the trench MOSFET device provided in Embodiment 3.

[0055] Figures 20 - 21 It is a schematic structural diagram of the manufacturing method of the trench MOSFET device provided in Embodiment 4.

[0056] Figure 22 It shows a schematic structural diagram of the trench MOSFET device provided in the fifth embodiment.

[0057] Figure 23 It shows a schematic structural diagram of the trench MOSFET device provided in the sixth embodiment.

[0058] Reference numerals

[0059] 11. Substrate; 12. Epitaxial layer; 13. Connection structure; 14. Insulating dielectric layer; 15. Source metal region; 2. Terminal trench; 20. First field oxide layer; 21. Terminal field plate; 211. First terminal field plate; 212. Second terminal field plate; 213. Third terminal field plate; 22. Intermediate dielectric layer; 221. First intermediate dielectric layer; 222. Second intermediate dielectric layer; 223. Third intermediate dielectric layer; 23. Source terminal; 3. Cell trench; 30. Second field oxide layer; 31. Shielding gate; 32. Shielding oxide layer; 33. Gate conductive region; 34. First gate oxide layer; 35. Body region; 36. Heavily doped region; 37. Second gate oxide layer; 38. Polysilicon layer. Detailed implementation manners

[0060] The following uses specific specific examples to illustrate the implementation manners of the present invention. It should be understood that although terms such as "first" and "second" may be used here to describe each structure, these structures should not be limited by these terms. These terms are only used to distinguish one structure from another. Without departing from the scope of the exemplary embodiments, the first structure may be referred to as the second structure, and similarly, the second structure may be referred to as the first structure. The term "and / or" used here includes any and all combinations of one or more of the listed related items.

[0061] In the present invention, it should be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated thereby is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application.

[0062] Embodiment 1

[0063] This embodiment provides a trench MOSFET device structure, as Figure 1As shown in the figure, the trench MOSFET device structure provided in this embodiment includes a cell region (Ⅰ) and a termination region (Ⅱ); the trench MOSFET device structure specifically includes: a semiconductor layer, the semiconductor layer includes a substrate 11 and an epitaxial layer 12 located on the upper surface of the substrate 11; a trench structure, including a cell trench 3 and a termination trench 2, which are arranged side by side from top to bottom inside the epitaxial layer 12. Among them, the termination trench 2 is a split-gate structure, and a first field oxide layer 20 is formed on the inner surface of the termination trench 2. An anode terminal 23 and a termination field plate 21 are arranged at intervals up and down in the first field oxide layer 20 in the termination trench 2, and the anode terminal 23 and the termination field plate 21 are spaced apart by an intermediate dielectric layer 22. The main function of the termination trench 2 is to optimize the electric field distribution in the termination region and improve the breakdown voltage.

[0064] Generally, the number of termination trenches 2 is adjusted according to specific layout and circuit design requirements. If the number of chips is large, more termination trenches 2 may be required to adapt to more power and signal ports. Specifically, in this embodiment, 5 termination trenches 2 are set as an example, and some of the termination trenches 2 are split-gate structures. Specifically, in this embodiment, 3 termination trenches 2 are set as split-gate structures. Generally speaking, the avalanche breakdown point of the device occurs where the potential changes most violently. Especially for high-voltage devices, breakdown is very likely to occur prematurely at the outermost part of the termination. In this embodiment, by setting the termination trench 2 as a split-gate structure, when the device withstands voltage, the floating termination field plate 21 can provide potential, thereby optimizing the electric field distribution outside the termination and improving the voltage withstand performance of the termination. Optionally, the length of the termination field plate 21, the spacing between adjacent termination field plates 21, and the thickness of the intermediate dielectric layer 22 can all be adjusted. Single adjustment or combined adjustment can be carried out to improve the voltage withstand performance of the device.

[0065] Generally, the substrate 11 is a heavily doped semiconductor, and the epitaxial layer 12 is a lightly doped semiconductor. The substrate 11 provides a low-resistance current path, supports the epitaxial layer 12, and serves as the contact area for the drain metal; the epitaxial layer 12 reduces the electric field intensity through light doping, bears the main voltage withstand, and balances the voltage withstand and on-resistance. Optionally, the material of the substrate 11 includes: silicon, gallium arsenide, silicon carbide, germanium and other materials. In this embodiment, silicon is used as the substrate 11, and the doping concentration is between 1e 18 cm -3 -1e 20 cm -3 . The doping concentration and thickness of the epitaxial layer 12 are adjusted according to the actual target voltage withstand level. For example, for a 600V device, the thickness of the epitaxial layer 12 is 50μm, and the doping concentration is 1e 16 cm -3 ; for a 200V device, the thickness of the epitaxial layer 12 is 15μm, and the doping concentration is 2e 15 cm -3 .

[0066] Specifically, the cell trench 3 includes a gate structure to implement a main current channel. The cell trench 3 is located in the cell region (I) of the trench MOSFET device, and the terminal trench 2 is located in the terminal region (II) of the trench MOSFET device. Generally, several cell trenches 3 are included in the cell region (I), and the number of cell trenches 3 is adjusted according to the specific chip resistance. If a smaller on-resistance of the chip is required, the number of cell trenches 3 will increase accordingly. In particular, this embodiment focuses on the terminal trench 2 in the terminal region (II), so only 1 cell trench 3 is used as an example to illustrate the principle and efficacy of the present invention, rather than to limit the present invention.

[0067] Specifically, the cell trench 3 provided in this embodiment is a split-gate structure. Specifically, as Figure 1 shown, the cell trench 3 includes a shielding gate 31 and a gate conductive region 33 located above the shielding gate 31. The shielding gate 31 and the gate conductive region 33 are isolated by a shielding oxide layer 32. Optionally, a second field oxide layer 30 and a first gate oxide layer 34 are formed on the inner surface of the cell trench 3. The second field oxide layer 30 is located around the shielding gate 31, and the first gate oxide layer 34 is located around the gate conductive region 33. The split-gate structure can balance the internal electric field and improve the device breakdown voltage while shielding the capacitance between the gate conductive region 33 and the substrate 11, effectively reducing the input capacitance and output capacitance of the device and increasing the switching speed.

[0068] Specifically, the trench MOSFET device provided in this embodiment further includes an insulating dielectric layer 14 located on the side of the epitaxial layer 12 away from the substrate 11 to cover the cell trench 3 and the terminal trench 2, for providing electrical insulation to prevent a short circuit between the source metal region 15 and the epitaxial layer 12; a source metal region 15 located above the insulating dielectric layer 14, serving as a signal input terminal, a current output terminal, and also as a pin control terminal of the device to implement the control of the circuit; and a connection structure 13 penetrating through the insulating dielectric layer 14 to provide a conductive path for electrically connecting the trench structure and the source metal region 15.

[0069] In addition, the schematic structural diagram of the trench MOSFET device provided in this embodiment is a cross-sectional view of the trench MOSFET device, so the electrode lead-out structures such as the gate and the drain are not specifically shown. For example, the gate is connected to the gate trace through contact holes at the head and tail in the trench direction. This is well known to those skilled in the art, so it will not be elaborated here.

[0070] Specifically, the trench MOSFET device provided in this embodiment further includes a body region 35 formed between the first gate oxide layer 34 and the first field oxide layer 20; a heavily doped region 36 formed on one side of the body region 35 close to the insulating dielectric layer 14, and the heavily doped region 36 connects the first gate oxide layer 34 and the connection structure 13. Optionally, the substrate 11, the epitaxial layer 12, and the heavily doped region 36 are N-type conductive, and the body region 35 is P-type conductive. Optionally, the substrate 11, the epitaxial layer 12, and the heavily doped region 36 are P-type conductive, and the body region 35 is N-type conductive. Specifically, in this embodiment, the substrate 11, the epitaxial layer 12, and the heavily doped region 36 are N-type conductive, and the body region 35 is P-type conductive. When a positive voltage is applied to the gate, the gate power supply forms a strong electric field on the surface of the body region 35 through the first gate oxide layer 34, attracting minority carriers in the body region 35 to the surface to form an inversion layer. The inversion layer serves as a conductive channel to realize the current conduction between the source (source metal region 15) and the drain (epitaxial layer 12); when the device is in the off state, the PN junction structure formed by the body region 35 and the epitaxial layer 12 and the shielding gate 31 jointly achieve voltage resistance. Specifically, the structure and the function are well known to those skilled in the art and will not be elaborated here.

[0071] Optionally, the present invention does not limit and describe the active regions other than the terminal regions. The active regions are also provided with other functional structures including but not limited to cell regions.

[0072] Particularly, in the trench MOSFET device of the present invention, the trench structure 2 in the terminal region (II) is a split gate structure, which is divided into a source terminal 23 and a terminal field plate 21 by an intermediate dielectric layer 22 up and down. By adjusting the depth of the source terminal 23 in the epitaxial layer 12 and / or the thickness of the intermediate dielectric layer 22, the potential of the terminal field plate 21 can be adjusted, so as to achieve the effect of gradual transition of the terminal potential, avoiding electric field concentration in the region outside the last terminal and causing local breakdown.

[0073] Embodiment 2

[0074] This embodiment also provides a trench MOSFET device structure, as Figure 2 shown. The trench MOSFET device structure provided in this embodiment adopts basically the same technical solution as that in Embodiment 1. The difference is that in this embodiment, the cell trench 3 is a conventional trench structure, rather than the split gate structure adopted in Embodiment 1.

[0075] Please refer to Figure 2, the trench MOSFET device structure provided in this embodiment includes: a heavily doped substrate 11 and a lightly doped epitaxial layer 12 on the upper surface of the substrate 11; a cell trench 3 and a terminal trench 2. The terminal trench 2 is a split structure. A first field oxide layer 20 is formed on the inner surface of the terminal trench 2. An anode terminal 23 and a terminal field plate 21 are arranged at intervals up and down in the first field oxide layer 20 in the terminal trench 2. The anode terminal 23 and the terminal field plate 21 are spaced apart by an intermediate dielectric layer 22. The cell trench 3 includes a second gate oxide layer 37 and a polysilicon layer 38 filled in the cell trench 3.

[0076] In this embodiment, the rest of the trench MOSFET device structure is basically the same as that in Embodiment 1, and the specific structure will not be described in detail.

[0077] Embodiment 3

[0078] This embodiment provides a method for manufacturing a trench MOSFET device. As Figure 3 shown, it shows a flowchart of the method for manufacturing a trench MOSFET device provided in this embodiment, including the following steps:

[0079] S1: Provide a heavily doped substrate 11, and form a lightly doped epitaxial layer 12 of the same type on the heavily doped substrate 11;

[0080] S2: Etch the lightly doped epitaxial layer 12 to form a terminal trench 2 in the terminal area and a cell trench 3 in the cell area;

[0081] S3: Form a first field oxide layer 20 on the inner surface of the terminal trench 2;

[0082] S4: Deposit polysilicon in the terminal trench 2 and the cell trench 3;

[0083] S5: Etch the polysilicon in the terminal trench to form a terminal field plate 21 in the first field oxide layer 20;

[0084] S6: Form an intermediate dielectric layer 22 in the terminal trench 2;

[0085] S7: Deposit polysilicon in the terminal trench to form an anode terminal 23;

[0086] S8: Deposit an insulating layer on the lightly doped epitaxial layer 12 to form an insulating dielectric layer 14;

[0087] S9: Form a source metal region 15 above the insulating dielectric layer 14.

[0088] As Figures 4 - 18 shown, it shows a schematic diagram of the preparation method of the trench MOSFET device structure provided in this embodiment, including the following steps:

[0089] As Figure 4 shown, S1: Provide a semiconductor substrate 11, and form a lightly doped epitaxial layer 12 of the same type on the substrate 11.

[0090] Generally, the material of the substrate 11 includes: materials such as silicon, gallium arsenide, silicon carbide, germanium, etc. Specifically, in this embodiment, a heavily doped silicon substrate 11 is provided, and a lightly doped silicon epitaxial layer 12 is grown on the silicon substrate 11. Optionally, the substrate 11 is a heavily doped N-type silicon, and the epitaxial layer 12 is a lightly doped N-type silicon; the substrate 11 is a heavily doped P-type silicon, and the epitaxial layer 12 is a lightly doped P-type silicon. The doping gases include N-type dopants such as phosphine (PH3), ammonia gas (NH3), etc.; P-type dopants such as boron trifluoride (BF3), trimethylboron (B(CH3)3), etc. Generally, the epitaxial layer is a thin layer of material deposited on the substrate through an epitaxial growth process such as CVD chemical vapor deposition, molecular beam epitaxy, etc. Specifically, the thickness and doping concentration of the epitaxial layer 12 can be precisely controlled by CVD to meet the requirements of breakdown voltage and on-resistance.

[0091] Specifically, in this embodiment, a heavily doped N-type silicon substrate is used, and the doping concentration is 1e 19 cm -3 ; A lightly doped N-type epitaxial layer 12 is grown on the substrate 11 by chemical vapor deposition. The epitaxial growth temperature is between 1050 - 1150 °C, and the doping gas is phosphine (PH3).

[0092] As Figure 5 shown, S2: Etch the lightly doped epitaxial layer 12 to form a plurality of terminal trenches 2 in the terminal region and cell trenches 3 in the cell region.

[0093] Generally, the trench etching methods include deep reactive ion etching process, wet etching, plasma etching, reactive ion etching and other etching methods. Specifically, in this embodiment, the deep reactive ion etching process is used. Photoresist is applied on the lightly doped epitaxial layer 12 to form terminal trenches 2 in the terminal region and cell trenches 3 in the cell region. Generally, the number of terminal trenches 2 and cell trenches 3 can be adjusted according to the actual functions of the device. Generally, the spacing between adjacent cell trenches 3 is between 2 - 5 μm, and the spacing between adjacent terminal trenches 2 is between 5 - 10 μm. Specifically, in this embodiment, one cell trench 3 and five terminal trenches 2 are designed, the etching depth is between 5 - 10 μm, and the trench width is between 0.5 - 3 μm.

[0094] As Figure 6 shown, S3: Form a first field oxide layer 20 on the inner surface of the terminal trench 2;

[0095] Optionally, a second field oxide layer 30 is simultaneously formed on the inner surface of the cell trench 3.

[0096] Generally, the process methods for forming an oxide layer in a trench include thermal oxidation, CVD, HDP, wet oxidation, dry oxidation, etc. Specifically, in this embodiment, a thermal oxidation process is adopted to form a first field oxide layer 20 in the terminal trench 2 for terminal insulation; a second field oxide layer 30 is formed in the cell trench 3 for shielding the isolation of the gate 31. Generally, the oxidation temperature ranges from 950 to 1100 °C, and the oxidation rate ranges from 10 to 50 nm / h.

[0097] Particularly, the first field oxide layer 20 and the second field oxide layer 30 need to cover the bottom and side walls of the corresponding trenches.

[0098] As Figure 7 shown, S4: Deposit polysilicon 40 in the terminal trench 2 and the cell trench 3.

[0099] Generally, CVD is used to deposit polysilicon 40 in the trench to fill the terminal trench and the cell trench, and chemical mechanical polishing and other methods are used to remove the excess polysilicon on the surface. The specific filling process is common knowledge in the art, and the specific process method is not limited and will not be elaborated here.

[0100] Optionally, a layer of insulating layer is deposited on the surface of the epitaxial layer 12.

[0101] As Figure 8 shown, after step S4, it further includes etching the polysilicon in the cell trench 3 to form a shielding gate 31 in the second field oxide layer 30.

[0102] Specifically, a photomask is provided to cover the terminal region (II) and only expose the cell region (I), and the polysilicon in the cell trench 3 is etched to retain the shielding gate 31. Generally, the depth of the shielding gate 31 is adjusted according to the actual function of the device. In this embodiment, the depth of the shielding gate 31 is preferably between 3 and 5 μm.

[0103] As Figure 9 shown, it shows filling an insulating layer in the cell trench 3.

[0104] Specifically, the cell trench 3 is filled with an insulating layer to isolate the shielding gate 31 and the subsequent formed gate conductive region 33. Generally, HDP, CVD and other processes are used to fill SiO2, Si3N4, etc. The thickness of the insulating layer ranges from 0.5 to 3.0 μm, and then the excess insulating material on the surface is removed. Particularly, the insulating layer needs to completely cover the top of the shielding gate 31.

[0105] As Figure 10 shown, S5: Etch the polysilicon in the terminal trench 2 to form a terminal field plate 21 in the first field oxide layer 20.

[0106] Specifically, a photomask is provided to cover the cell region (Ⅰ), only exposing the terminal region (Ⅱ). The polysilicon in the terminal trench 2 within the terminal region is etched, leaving a certain length of polysilicon suspended in the epitaxial layer 12. This suspended polysilicon can be regarded as the terminal field plate 21. In a power device, the terminal region is the transition area between the cell region and the chip edge. If the electric field is unevenly distributed in the terminal region, it will lead to electric field concentration and cause breakdown. The terminal field plate 21 is formed in the epitaxial layer 12 and acts as a deeply buried field plate. Through the capacitive coupling effect, it expands the depletion region, reduces the potential gradient in the epitaxial layer 12, and makes the electric field distribution more uniform.

[0107] Optionally, through a single etching process, the depth of the terminal field plate 21 in each terminal trench 2 can be kept the same.

[0108] Optionally, a multiple etching process can also be adopted. Provide multiple photomasks to etch each terminal trench 2 separately, and optimize the depth of the terminal field plate 21 in each terminal trench 2 individually to achieve different depths of the terminal field plate 21.

[0109] As Figure 11 shown, S6: Form an intermediate dielectric layer 22 in the terminal trench 2.

[0110] Specifically, an intermediate dielectric layer 22 is formed in the terminal trench 2 to isolate the terminal field plate 21 and the subsequent source terminal 23. Generally, processes such as HDP and CVD can be used to fill SiO2 or Si3N4, etc. The thickness of the intermediate dielectric layer 22 is related to the breakdown voltage performance of the device. Therefore, the thickness of the intermediate dielectric layer 22 needs to be filled according to actual requirements. Generally, different thicknesses of the intermediate dielectric layer can be formed by distributed deposition or adjusted depending on the oxidation rate ratio.

[0111] Optionally, a single filling or oxidation process can be adopted to make the thickness of the intermediate dielectric layer 22 in each terminal trench the same.

[0112] Optionally, multiple or distributed filling can be used to optimize the thickness of the intermediate dielectric layer 22 in each terminal trench and change the thickness of the intermediate dielectric layer 22 in each terminal trench 2. Specifically, in this embodiment, the thickness of the intermediate dielectric layer 22 gradually increases from the cell region to the edge of the terminal region. On the side close to the cell region, the intermediate dielectric layer 22 is thinner to enhance the field plate coupling to achieve a rapid potential transition; on the side close to the edge of the terminal region, the intermediate dielectric layer 22 is thicker to slow down the potential change and avoid electric field concentration to achieve a smooth electric field transition.

[0113] As Figure 12 shown, S7: Deposit polysilicon above the intermediate dielectric layer 22 in the terminal trench 2 to form the source terminal 23.

[0114] Specifically, polysilicon is deposited above the intermediate dielectric layer 22 to fill the terminal trench, and the excess polysilicon on the surface is removed by methods such as chemical mechanical polishing. The specific filling process is common general knowledge in the art, and the specific process method is not limited and will not be elaborated herein.

[0115] As Figure 13 shown, it shows etching the insulating layer in the cell trench 3 to form a shielding oxide layer 32 in the cell trench 3.

[0116] Specifically, as Figure 13 shown, the insulating layer at the top of the cell trench 3 is etched, and an insulating layer with a certain thickness above the shielding gate 31 is retained for isolating the shielding gate 31 and the subsequent formed gate conductive region 33. Particularly, the insulating layer above the shielding gate 31 and on the inner sidewall of the cell trench 3 is removed.

[0117] Optionally, the etching of the insulating layer in the cell trench 3 can be carried out before, after, or synchronously with the etching of the polysilicon in the terminal trench 2 in step S7.

[0118] As Figure 14 shown, it shows forming a first gate oxide layer 34 on the inner surface of the cell trench 3 above the shielding gate 31, and depositing polysilicon in the cell trench 3 to form a gate conductive region 33.

[0119] Specifically, the process steps of forming the oxide layer are similar to the foregoing and will not be elaborated herein. Particularly, the thickness of the first gate oxide layer 34 is less than that of the field oxide layer (including the first field oxide layer 20 and the second field oxide layer 30). Optionally, the first gate oxide layer 34 can be formed synchronously with the intermediate dielectric layer 22 in step S8.

[0120] Specifically, the process steps of depositing polysilicon in the cell trench 3 to form a gate conductive region 33 are similar to the foregoing and will not be elaborated. Particularly, the gate conductive region 33 needs to be completely isolated from the shielding gate 31.

[0121] Optionally, the gate conductive region 33 and the source terminal 23 in step S9 can be formed synchronously.

[0122] As Figure 15 described, it shows providing a photomask and performing implantation between the cell trench 3 and the terminal trench 2 to form a body region 35.

[0123] Specifically, the body region 35 is formed between the cell trenches 3, as well as between the adjacent cell trenches 3 and the terminal trench 2. In this embodiment, that is, between the first gate oxide layer 34 and the first field oxide layer 20. The doping type of the body region 35 is opposite to that of the substrate 11 and the epitaxial layer 12. Optionally, the substrate 11 and the epitaxial layer 12 are N-doped and conductive, and the body region 35 is P-doped and conductive; the substrate 11 and the epitaxial layer 12 are P-doped and conductive, and the body region 35 is N-doped and conductive. The doping concentration of the body region 35 needs to be appropriate. Generally, the doping concentration is 1e 13 cm -3 -1e 16 cm -3 , and the junction depth is between 0.5 - 2 μm

[0124] As Figure 16 shown, it is shown that a heavily doped region 36 is formed by implantation in the body region 35.

[0125] The heavily doped region 36 is formed in the body region 35 between the cell trenches 3, on the side away from the substrate 11, and the depth of the heavily doped region 36 is less than the depth of the body region 35. The heavily doped region 36 is used to reduce the contact resistance of the body region 35 and the subsequent formed connection structure 13.

[0126] As Figure 17 shown, S8: Deposit an insulating layer on the surface of the epitaxial layer 12 to form an insulating dielectric layer 14.

[0127] Specifically, processes such as CVD and thermal oxidation are used to deposit an insulating layer (such as SiO2, Si3N4, etc.) to form the insulating dielectric layer 14, which is used to provide electrical insulation and prevent short circuits between the subsequent formed source metal region and the semiconductor region. Generally, the thickness of the insulating dielectric layer 14 is between several micrometers and several hundred micrometers, and its thickness specifically depends on the breakdown voltage requirements and process requirements. Specifically, the thickness of the insulating dielectric layer 14 is between 1 - 2 μm. Provide a photomask, etch the insulating dielectric layer 14 to form metal etch holes, and fill the metal etch holes with metal to form the connection structure 13. The connection structure 13 penetrates through the insulating dielectric layer and the heavily doped region 36, with one end connected to the source metal region 15 and the other end located in the body region 35. The connection structure 13 is used to realize the electrical connection between the trench structure and the source metal region 15. Optionally, common metal materials include: aluminum, copper, tungsten, polysilicon, and other materials with good conductivity. In particular, forming the insulating dielectric layer 14 on the surface of the epitaxial layer 12 is not limited to the method provided by the present invention, and other processes can be used according to the actual application requirements.

[0128] As Figure 18 shown, S9: Form a source metal region 15 above the insulating dielectric layer 14.

[0129] Specifically, the source metal region 15 is located on the upper surface of the insulating dielectric layer 14, and is used to collect the source current and provide an external contact point. Generally, the material includes aluminum, copper, alloy, etc., and the thickness is usually between several hundred nanometers and several micrometers, and the specific thickness depends on the current-carrying capacity.

[0130] Specifically, subsequent conventional process steps are used to fabricate the channel region, source region, etc. of the trench MOSFET device to obtain the final trench MOSFET device. The above is the manufacturing method of the trench MOSFET device provided by this embodiment. Of course, the above step sequence can be flexibly adjusted according to actual needs, and the protection scope of the present invention should not be overly limited here. For example, process technologies such as depositing insulating layers and connecting structures are already very mature and are not limited to the steps provided in this application. Specifically, in the present invention, the source terminal 23 and the terminal field plate 21 in the terminal trench need to be isolated by an intermediate dielectric layer 22 through a multi-layer filling process (depositing field oxide layer - etching - filling field plate - depositing dielectric layer - secondary filling field plate). There are many process steps, which can be preferentially realized by mask optimization, but the method steps are not limited to this.

[0131] Specifically, the number of segmented terminal trenches provided in the terminal region can be increased or decreased according to the actual device function. Specifically, the mutual cooperation of the length of the terminal field plate 21 and the thickness of the intermediate dielectric layer 22 can flexibly optimize the electric field distribution in the terminal region. Specifically, the terminal field plate 21 is a deeply buried field plate. If the electric field distribution here is uneven, it will cause electric field concentration and trigger breakdown. Therefore, the terminal field plate 21 needs to form a stepped electric field modulation with the source terminal 23 to gradually reduce the electric field intensity, reduce the electric field gradient in the epitaxial layer 12, make the electric field distribution flatter, and thus avoid the edge electric field spike.

[0132] Specifically, in a single process step, the length of the terminal trench 2 formed is fixed, so the sum of the length of the terminal field plate 21 and the length of the source terminal 23 (i.e., the depth of the intermediate dielectric layer 22 in the terminal trench 2) is fixed. For the convenience of representation, the length of the source terminal 23 is used to reflect the length of the terminal field plate 21. The longer the length of the source terminal 23 (the deeper the depth of the intermediate dielectric layer 22 in the terminal trench 2), the smaller the length of the terminal field plate 21; conversely, the shorter the length of the source terminal 23 (the shallower the depth of the intermediate dielectric layer 22 in the terminal trench 2), the longer the length of the terminal field plate 21.

[0133] Specifically, the influence of the thickness of the intermediate dielectric layer in the terminal trench and the length of the source terminal 23 on the potential of the deeply buried field plate is shown in Table 1 below. Lp represents the length of the source terminal 23, Δd represents the thickness of the intermediate dielectric layer, and Vf represents the potential carried on the deeply buried field plate (terminal field plate 21).

[0134] Table 1 Influence of the length of the source terminal and the thickness of the intermediate dielectric layer on the potential of the deeply buried field plate

[0135]

[0136] Specifically, the data in this table can represent the influence of the change in the intermediate dielectric layer and the terminal field plate length on the potential of the deeply buried field plate for the same terminal trench 2. In addition, the data in Table 1 also indicates the influence of the change trend of the intermediate dielectric layer and the terminal field plate length on the change trend of the potential of the deeply buried field plate for different terminal trenches.

[0137] It can be seen from the data in the table that: under the condition that the thickness of the intermediate dielectric layer 22 is constant, as the length of the source terminal 23 increases, that is, the length of the terminal field plate 21 decreases, the potential on the deeply buried field plate becomes lower; under the condition that the length depth of the source terminal 23 is constant (the length of the terminal field plate 21 is constant), as the thickness of the intermediate dielectric layer 22 increases, the potential on the deeply buried field plate becomes higher.

[0138] Therefore, in practical applications, by designing the terminal trench in layers and combining with adjusting the thickness of the intermediate dielectric layer, the distribution of the electric field can be gradually adjusted to achieve a gradual transition of the potential in the terminal area from a high potential to a low potential. On the side close to the cell area, the intermediate dielectric layer is designed to be thinner and the source terminal depth is deeper (the terminal field plate length is smaller), which is convenient for achieving a rapid transition of the potential; on the side close to the edge of the terminal area, the intermediate dielectric layer is designed to be thicker and the source terminal depth is deeper (the terminal field plate length is longer) to slow down the change of the potential and avoid electric field concentration. In short, the trench-type MOSFET device structure provided by the present invention can achieve a uniform distribution of the electric field in the terminal area.

[0139] Embodiment 4

[0140] This embodiment provides a method for manufacturing a trench-type MOSFET device, as Figure 19 shown, which shows the flow chart of the method for manufacturing a trench-type MOSFET device provided by this embodiment, including the following steps:

[0141] S1: Provide a heavily doped substrate 11, and form a lightly doped epitaxial layer 12 of the same type on the heavily doped substrate 11;

[0142] S2: Etch the lightly doped epitaxial layer 12 to form a terminal trench 2 in the terminal area and a cell trench 3 in the cell area;

[0143] S3: Form a first field oxide layer 20 on the inner surface of the terminal trench 2 and a second gate oxide layer 37 in the cell trench 3;

[0144] S4: Deposit polysilicon in the terminal trench 2 and the cell trench 3, and form a polysilicon layer 38 in the cell trench 3;

[0145] S5: Etch the polysilicon in the terminal trench 2 to form a terminal field plate 21 in the first field oxide layer 20.

[0146] S6: Form an intermediate dielectric layer 22 in the terminal trench 2.

[0147] S7: Deposit polysilicon above the terminal trench 2 and the intermediate dielectric layer 22 to form a source terminal 23.

[0148] S8: Provide a photomask and perform implantation between the cell trench 3 and the terminal trench 2 to form a body region 35.

[0149] S9: Perform implantation in the body region 35 to form a heavily doped region 36.

[0150] S10: Deposit an insulating layer on the lightly doped epitaxial layer 12 to form an insulating dielectric layer 14.

[0151] S11: Form a source metal region 15 above the insulating dielectric layer 14.

[0152] Specifically, please continue to refer to Figures 4 - 5 , and perform steps S1 - S2 that are basically the same as those in Embodiment 3. Provide a heavily doped substrate 11, and form a lightly doped epitaxial layer 12 on the substrate 11; etch on the epitaxial layer 12 to form a terminal trench 2 in the terminal region and a cell trench 3 in the cell region.

[0153] As Figure 20 shown, according to the aforementioned process, form a first field oxide layer 20 on the inner surface of the terminal trench 2 and form a second gate oxide layer on the inner surface of the cell trench 3.

[0154] As Figure 21 shown, deposit polysilicon in the cell trench and the terminal trench to form a polysilicon layer 38 in the cell trench 3.

[0155] Subsequently, perform steps that are basically the same as those in Embodiment 3, and perform etching - filling and other processes on the terminal trench in the terminal region to form a trench - type MOSFET device structure as Figure 2 shown.

[0156] Embodiment 5

[0157] This embodiment also provides a trench - type MOSFET device structure. As Figure 22 shown, the trench - type MOSFET device structure provided in this embodiment adopts basically the same technical solution as that in Embodiment 1. In particular, in this embodiment, the thickness of some of the intermediate dielectric layers 22 is different.

[0158] Specifically, as Figure 19As shown, in this embodiment, three terminal trenches 2 are provided, and the intermediate dielectric layers 22 are respectively a first intermediate dielectric layer 221, a second intermediate dielectric layer 222, and a third intermediate dielectric layer 223. The thickness of the first intermediate dielectric layer 221 is 0.05 μm, and the electric potential on the buried field plate is 50% BV; when the thickness of the second intermediate dielectric layer 222 is 0.20 μm, the electric potential on the buried field plate is 60% BV; when the thickness of the third intermediate dielectric layer 223 is 0.40 μm, the electric potential on the buried field plate is 90% BV. It can be seen that under the condition that the length of the terminal field plate 21 remains unchanged, the thicker the thickness of the intermediate dielectric layer 22, the higher the electric potential on the buried field plate. Therefore, optionally, in order to make the gradient of the electric field change from the cell region to the terminal region, the thickness of the intermediate dielectric layer 22 can gradually increase from the cell region to the edge of the terminal region.

[0159] In this embodiment, the remaining parts of the trench MOSFET device structure are basically the same as those in the first embodiment, and the specific structure will not be described in detail.

[0160] Embodiment Six

[0161] This embodiment also provides a trench MOSFET device structure, as Figure 23 shown, the trench MOSFET device structure provided in this embodiment adopts basically the same technical solution as that in the first embodiment. In particular, in this embodiment, the length of the terminal field plate 21 is different, that is, the length of the source terminal 23 is different (the depth of the intermediate dielectric layer 22 in the terminal trench 3 is different).

[0162] Specifically, as Figure 20As shown, in this embodiment, three terminal trenches 2 are provided, and the terminal field plate 21 includes a first terminal field plate 211, a second terminal field plate 212, and a third terminal field plate 213. To facilitate the representation of the depth of the terminal field plate 21, it is defined that for the same etching process, the depth of each terminal trench 2 obtained is the same. Specifically, in this embodiment, under the condition that the thickness of the intermediate dielectric layer 22 is the same, the length of the terminal field plate 21 is 6 μm, the length of the first terminal field plate 211 is 1 μm (the length of the terminal field plate 21 accounts for 1 / 6 of the length of the entire terminal trench 2), and the electric potential on the buried field plate is 50% BV; the length of the second terminal field plate 212 is 3 μm (the length of the terminal field plate 21 accounts for 1 / 2 of the length of the entire terminal trench 2), and the electric potential on the buried field plate is 70% BV; the length of the third terminal field plate 211 is 4 μm (the depth of the terminal field plate 21 accounts for 2 / 3 of the depth of the entire terminal trench 2), and the electric potential on the buried field plate is 90% BV. It can be seen that the longer the length of the terminal field plate 21, the higher the electric potential of the buried field plate. Therefore, optionally, in order to make the gradient of the electric field change from the cell region to the terminal region, the depth of the intermediate dielectric layer 22 in the terminal trench 3 (the length of the terminal field plate 21) can gradually become shallower (longer) from the cell region to the edge of the terminal region.

[0163] In summary, in Embodiment 5 and Embodiment 6, by adjusting the thickness of the intermediate dielectric layer 22 and the depth of the intermediate dielectric layer 22 in the terminal trench 3, the electric field distribution can be gradually modulated, the depletion region can be effectively extended, the electric field distribution in the terminal region is more uniform, and the breakdown voltage of the device can be effectively improved.

[0164] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A trench MOSFET device structure, comprising a cell region and a terminal region, characterized in that: include: A semiconductor layer, the semiconductor layer comprising a substrate and an epitaxial layer located on one side of the substrate; A groove structure, including a cell groove and a terminal groove, wherein the groove structure is located in the epitaxial layer and extends from the surface of the epitaxial layer to the inside of the epitaxial layer from top to bottom, and the cell groove and the terminal groove are arranged in parallel; A source terminal and a terminal field plate are arranged in at least part of the terminal grooves at intervals, and an intermediate dielectric layer is arranged between the source terminal and the terminal field plate.

2. The trench MOSFET device structure according to claim 1, characterized in that: The cell trench is a split gate, and the cell trench comprises a shielding gate and a gate conductive region located above the shielding gate, and the shielding gate and the gate conductive region are isolated by an insulating layer.

3. The trench MOSFET device structure according to claim 2, characterized in that: A first gate oxide layer and a second field oxide layer are formed on the sidewalls of the cell trench, wherein the first gate oxide layer is located around the gate conductive region, and the second field oxide layer is located around the shielding gate.

4. The trench MOSFET device structure according to claim 1, characterized in that: The cell trench is a standard trench gate, a second gate oxide layer is formed in the cell trench, and a polysilicon layer is deposited in the second gate oxide layer.

5. The trench MOSFET device structure according to claim 1, characterized in that: At least some of the intermediate dielectric layers have different thicknesses.

6. The trench MOSFET device structure according to claim 5, characterized in that: The thickness of the intermediate dielectric layer gradually increases in a direction away from the cell trench.

7. The trench MOSFET device structure according to claim 1 or 5, characterized in that: At least some of the terminal field plates have different lengths.

8. The trench MOSFET device structure according to claim 7, characterized in that: Along the direction away from the cell trench, the length of the terminal field plate gradually increases.

9. The trench MOSFET device structure according to claim 6, characterized in that: Along the direction away from the cell trench, the length of the terminal field plate gradually increases.

10. The trench MOSFET device structure according to claim 1, characterized in that: Also includes: A first field oxide layer formed on a sidewall of the terminal trench; An insulating dielectric layer, located on a side of the epitaxial layer away from the substrate, so as to cover the cell trench and the terminal trench; A source metal region, located above the insulating dielectric layer; A connecting structure penetrates the insulating dielectric layer to electrically connect the trench structure and the source metal region.

11. The trench MOSFET device structure according to claim 11, characterized in that: Also includes: A body region formed between the cell grooves and between the adjacent cell grooves and the terminal groove; A heavily doped region is formed in the body region between the cell trenches, the depth of the heavily doped region is less than the depth of the body region, and the connection structure passes through the heavily doped region.

12. A method for manufacturing a trench MOSFET device, characterized in that: The following steps are involved: Providing a heavily doped substrate, and forming a lightly doped epitaxial layer of the same type on the heavily doped substrate; Etching the lightly doped epitaxial layer to form a terminal trench in the terminal region and a cell trench in the cell region; forming a first field oxide layer on the inner surface of the terminal trench; Depositing polysilicon in the terminal trench and the cell trench; Etching the polysilicon in the terminal trench to form a terminal field plate in the first field oxide layer; forming an intermediate dielectric layer in the terminal trench; depositing polysilicon in the terminal trench to form a source terminal; Depositing an insulating layer on the lightly doped epitaxial layer to form an insulating dielectric layer; A source metal region is formed above the insulating dielectric layer.

13. The method for manufacturing a trench MOSFET device according to claim 12, characterized in that: The following steps are also included: A second gate oxide layer is formed in the cell trench, and polysilicon is filled in the second gate oxide layer to form a polysilicon layer.

14. The method for manufacturing a trench MOSFET device according to claim 12, characterized in that: The following steps are also included: forming a second field oxide layer in the cell trench; Etching the polysilicon in the cell trench to form a shielding gate in the second field oxide layer; growing an oxide layer on the shielding gate as a shielding oxide layer; forming a first gate oxide layer on the inner surface of the cell trench above the shielding gate; Depositing polysilicon in the cell trench to form a gate conductive region; A body region is formed between the cell trench and the terminal trench that is most adjacent to the cell trench.

15. The method for manufacturing a trench MOSFET device according to claim 14, characterized in that: The second field oxide layer and the first field oxide layer may be formed simultaneously; The intermediate dielectric layer and the first gate oxide layer can be formed simultaneously; The source terminal and the gate conductive region may be formed simultaneously.

16. The method for manufacturing a trench MOSFET device according to claim 14, characterized in that: The method further includes forming a heavily doped region in the body region on one side close to the insulating dielectric layer, wherein the heavily doped region connects the first gate oxide layer and the connection structure.

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