Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The semiconductor device comprises a plurality of nanowire structures, a first source / drain structure, a second source / drain structure, a gate structure and a gate dielectric layer. The nanowire structures extend in a vertical direction. The first source / drain structure and the second source / drain structure are sequentially stacked in the vertical direction. The grid electrode structure is arranged between the first source electrode / drain electrode structure and the second source electrode / drain electrode structure in the vertical direction, and the first source electrode / drain electrode structure, the grid electrode structure and the second source electrode / drain electrode structure respectively wrap a part of each nanowire structure. The gate dielectric layer is disposed between the gate structure and each nanowire structure, and between the gate structure and the first source / drain structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device having a nanowire structure and a method for forming the same. Background Art

[0002] When semiconductor components have advanced to the 65-nanometer technology generation, it has become difficult to continuously miniaturize using the traditional planar metal-oxide-semiconductor (MOS) transistor manufacturing process. Therefore, the prior art has proposed a solution to replace planar transistors with non-planar multi-gate transistor components. For example, dual-gate fin field effect transistor (FinFET) components, tri-gate fin field effect transistor components, and omega fin field effect transistor components have all been proposed. Now, a gate-all-around (GAAFET) transistor component using a nanowire structure as the channel has been developed as a solution to further improve component integration and component performance. Summary of the Invention

[0003] An object of the present invention is to provide a semiconductor device and a method for forming the same. The semiconductor device has a vertically disposed nanowire structure for forming a gate-all-around (GAAFET) transistor with a vertical channel. Thus, the semiconductor device of the present invention can effectively increase its carrier channel width, improve the reliability and integration of electron transport, reduce current leakage, and provide improved performance and reduced power consumption by adjusting the channel thickness, thereby enabling the semiconductor device to achieve better operating performance.

[0004] An embodiment of the present invention provides a semiconductor device, including a plurality of nanowire structures, a first source / drain structure and a second source / drain structure, a gate structure, and a gate dielectric layer. The nanowire structures extend along a vertical direction. The first source / drain structure and the second source / drain structure are stacked in sequence in the vertical direction. The gate structure is disposed between the first source / drain structure and the second source / drain structure in the vertical direction, wherein the first source / drain structure, the gate structure, and the second source / drain structure respectively cover a part of each of the nanowire structures. The gate dielectric layer is disposed between the gate structure and each of the nanowire structures, and between the gate structure and the first source / drain structure.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor device, including the following steps. Form a plurality of nanowire structures extending along a vertical direction. Form a first source / drain structure and a second source / drain structure stacked in sequence in the vertical direction. In the vertical direction, form a gate structure located between the first source / drain structure and the second source / drain structure, wherein the first source / drain structure, the gate structure, and the second source / drain structure respectively cover a part of each nanowire structure. Form a gate dielectric layer between the gate structure and each nanowire structure, and between the gate structure and the first source / drain structure.

[0006] Overall, the semiconductor device of the present invention is composed of two source / drain structures and a gate structure stacked in sequence in the vertical direction and respectively covering part of the nanowire structures to jointly form a gate-all-around field-effect transistor with a vertical channel. Thus, the semiconductor device of the present invention can effectively increase its carrier channel width under the same floor area, improve the reliability and integration of electron transmission, and thus achieve better operating performance. Moreover, the semiconductor device can further be applied to a three-dimensional stacked structure (3D stacked chip), and the semiconductor device is electrically connected to other functional devices or components, such as a memory device, a logic device, a central processing unit (CPU), or an analogue device, etc., by simultaneously performing the bonding method of metal material to metal material and dielectric material to dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 2 It is a schematic cross-sectional view of a semiconductor device in a preferred embodiment of the present invention, wherein:

[0008] Figure 1 It is a schematic perspective view of a semiconductor device in a first embodiment of the present invention; and

[0009] Figure 2 It is a schematic cross-sectional view of a semiconductor device in a first embodiment of the present invention;

[0010] Figures 3 to 11 It is a schematic view of a method for forming a semiconductor device in a preferred embodiment of the present invention, wherein:

[0011] Figure 3 It is a schematic cross-sectional view of the semiconductor device after forming the nanowire structures;

[0012] Figure 4 It is a schematic cross-sectional view of the semiconductor device after trimming the nanowire structures;

[0013] Figure 5 It is a schematic cross-sectional view of the semiconductor device after forming the dielectric material layer;

[0014] Figure 6 is a cross-sectional schematic view of a semiconductor device after forming a metal material;

[0015] Figure 7 is a cross-sectional schematic view of a semiconductor device after forming a spacer;

[0016] Figure 8 is a cross-sectional schematic view of a semiconductor device after forming a conductive material layer;

[0017] Figure 9 is a cross-sectional schematic view of a semiconductor device after forming an interconnect layer;

[0018] Figure 10 is a cross-sectional schematic view of a semiconductor device after performing a substrate thinning process; and

[0019] Figure 11 is a cross-sectional schematic view of a semiconductor device after forming another interconnect layer.

[0020] Symbol Description

[0021] 10: Semiconductor device

[0022] 20: Chip

[0023] 30: Bonding structure

[0024] 110: Nanowire structure

[0025] 110a: Top surface

[0026] 112: Nanowire structure

[0027] 114: First source / drain structure

[0028] 116: Dielectric material layer

[0029] 118: Metal layer

[0030] 118a: Etch stop layer

[0031] 120: Gate dielectric layer

[0032] 120a: First part

[0033] 120b: Second part

[0034] 122: Gate structure

[0035] 124: Spacer

[0036] 126: Conductive material layer

[0037] 128: Second source / drain structure

[0038] 130: Second internal wiring layer

[0039] 132: Carrier substrate

[0040] 134: Bubble

[0041] 136: Insulating layer

[0042] 138: First internal wiring layer

[0043] 140: Conductive structure

[0044] 142: Conductive structure

[0045] 144: Encapsulation layer

[0046] 150: Dielectric layer

[0047] 152: Conductive structure

[0048] D1: Vertical and horizontal

[0049] P1: First planarization process

[0050] P2: Second planarization process

[0051] W1: Line width

[0052] W2: Line width

[0053] X: Horizontal direction

[0054] Y: Direction Detailed implementation manners

[0055] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, several preferred embodiments of the present invention are specifically listed below, and in conjunction with the accompanying drawings, the composition and the desired effects of the present invention are described in detail. And, without departing from the spirit of the present invention, the technical features in the different embodiments described below can be replaced, recombined, and mixed with each other to form other embodiments.

[0056] Please refer to Figure 1 and Figure 2 as shown, what is illustrated is a schematic diagram of a semiconductor device 10 in a preferred embodiment of the present invention. Among them, Figure 1 is a three-dimensional schematic diagram of the semiconductor device 10, Figure 2 is Figure 1 a schematic cross-sectional view along the tangent A - A'. The semiconductor device 10 includes a plurality of nanowire structures 112, a first source / drain structure 114 and a second source / drain structure 128, a gate structure 122, and a gate dielectric layer 120. The nanowire structures 112 respectively extend along the vertical direction D1, presenting as Figure 1The cylindrical structures shown are arranged in an array, but not limited thereto. In one embodiment, the nanowire structure 112 includes, for example, a single-crystalline material, such as silicon (Si), epitaxial silicon, silicon germanium (SiGe), or silicon carbide (SiC), etc., but not limited thereto. The first source / drain structure 114, the gate structure 122, and the second source / drain structure 128 are stacked in sequence in the vertical direction D1 and respectively surround a part of the nanowire structure 112. And a gate dielectric layer 120 is further disposed between the gate structure 122, the nanowire structure 112, and the first source / drain structure 114 to electrically isolate them from each other. In this setting, the gate structure 122 is disposed between the first source / drain structure 114 and the second source / drain structure 128, and each nanowire structure 112 is respectively covered by the first source / drain structure 114, the gate structure 122, and the second source / drain structure 128, jointly forming a transistor having a vertical channel. Among them, the first source / drain structure 114 and the second source / drain structure 128 respectively serve as the two source / drains of the transistor, and the nanowire structure 112 covered by the gate structure 122 serves as the vertical channel of the transistor, so that the gate structure 122 surrounding the outside of the vertical channel can achieve the effect of a gate-all-around (GAA).

[0057] In one embodiment, the first source / drain structure 114, the gate structure 122, and the second source / drain structure 128 include, for example, a doped semiconductor material or a metal material with a low resistance value, including but not limited to silicon, silicon germanium, titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), tungsten (W), or any combination thereof. Among them, the first source / drain structure 114 and the second source / drain structure 128 preferably include the same conductive material, and the gate structure 122 preferably includes a metal material, but not limited thereto.

[0058] In detail, the gate dielectric layer 120 further includes a first portion 120a disposed between the gate structure 122 and the first source / drain structure 114 therebelow, and a second portion 120b disposed between the gate structure 122 and each nanowire structure 122. In one embodiment, the first portion 120a and the second portion 120b of the gate dielectric layer 120 are, for example, formed by the same deposition process and include the same dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a suitable low dielectric constant (low-k) material, but not limited thereto. In another embodiment, the first portion 120a and the second portion 120b of the gate dielectric layer 120 can also be selectively formed by a thermal oxidation process, such that the first portion 120a and the second portion 120b can further include different dielectric materials. In addition, the semiconductor device 10 further includes a spacer 124 covering the gate structure 122 and disposed between the second source / drain structure 128 and the gate structure 122 to electrically isolate the second source / drain structure 128 from the gate structure 122 therebelow. In one embodiment, the spacer 124, for example, also includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a suitable low dielectric constant material, but not limited thereto. It should be noted that, in this embodiment, Figure 1 in order to clearly show the vertical channel and the surrounding gate of the transistor, the illustration of elements such as the spacer 124 and the gate dielectric layer 120 is omitted, but those skilled in the art should be able to clearly infer the positions of these elements in Figure 2 from the cross-sectional schematic diagram shown. Figure 1 on.

[0059] For another example, Figure 1 and Figure 2 as shown, the semiconductor device 10 further includes a first interconnect layer 138 and a second interconnect layer 130 respectively stacked in the vertical direction D1 below and above the transistor. The first interconnect layer 138 and the second interconnect layer 130 are both disposed in an insulating layer 136, surrounded by the insulating layer 136, and respectively contact the first source / drain structure 114 and the second source / drain structure 128 of the transistor. In one embodiment, the first interconnect layer 138 and the second interconnect layer 130, for example, both include a metal material with a low resistance value, such as titanium, tantalum, aluminum, copper, tungsten, or any combination of the foregoing materials, to electrically connect the first source / drain structure 114 and the second source / drain structure 128. Thus, the first source / drain structure 114 and the second source / drain structure 128 of the transistor can be connected to other functional devices or components, such as memory devices, logic devices, central processing units, or analog devices, through the first interconnect layer 138 and the second interconnect layer 130.

[0060] For example, in this embodiment, an encapsulation layer ( Figure 1 and Figure 2 not shown) may be further disposed above the second inner wiring layer 130 to cover and enclose one side of the transistor (the side where the second source / drain structure 128 is located). The second source / drain structure 128 and the gate structure 122 of the transistor may be respectively connected to the side where the first source / drain structure 114 of the transistor is located through conductive structures 140 and 142 that electrically connect the second inner wiring layer 130 and the gate structure 122. The conductive structures 140 and 142 are, for example, also disposed in the insulating layer 136, respectively located in the horizontal direction X of the first inner wiring layer 138 and the other direction Y perpendicular to the horizontal direction X, and coplanar with a plane (such as Figure 1 the top surface shown or Figure 2 the bottom surface shown) of the first inner wiring layer 138, as shown in Figure 1 . In one embodiment, the conductive structures 140 and 142 include, for example, suitable plugs and / or conductive layers, which, for example, have low-resistance metal materials such as titanium, tantalum, aluminum, copper, tungsten, etc., but are not limited thereto. Thus, the first source / drain structure 114, the second source / drain structure 128, and the gate structure 122 of the transistor can be electrically connected to the aforementioned functional device or element through the first inner wiring layer 138 and the conductive structures 140 and 142 disposed on the same side (the side where the first source / drain structure 114 is located) of the transistor, but are not limited thereto. In another embodiment, it is also possible to choose to connect the first source / drain structure 114 and the second source / drain structure 128 of the transistor to different sides of the transistor respectively, and then connect them to the aforementioned functional device or element respectively.

[0061] According to the semiconductor device 10 of the present invention, a first source / drain structure 114, a gate structure 122, and a second source / drain structure 128 that respectively cover a part of each nanowire structure 112 are sequentially disposed in the vertical direction D1, so that the nanowire structure 112, the gate structure 122, the first source / drain structure 114, and the second source / drain structure 128 can jointly form the transistor with a vertical channel, effectively increasing the carrier channel width of the semiconductor device 10 under the same floor area, and improving the reliability and integration of electron transmission. It can not only reduce current leakage, but also provide improved performance and reduce power consumption by adjusting the channel thickness, thereby enabling the semiconductor device 10 to achieve better operating performance.

[0062] To enable those of ordinary skill in the art to which the present invention pertains to easily understand the semiconductor device 10 of the present invention, the manufacturing method of the semiconductor device 10 of the present invention will be further described below.

[0063] Please refer to Figures 3 to 11As shown, it is a cross-sectional schematic diagram of a method for forming a semiconductor device 10 in a preferred embodiment of the present invention. Although only the cross-sectional schematic diagrams of the semiconductor device 10 in each step are drawn in this embodiment, those skilled in the art should be able to clearly understand the top-view patterns of the semiconductor device 10 in each step with reference to the top-view of the semiconductor device 10 shown in Figure 1 above.

[0064] First, as Figure 3 shown, a plurality of nanowire structures 110 extending along the vertical direction D1 are formed on a top surface 100a of a substrate 100. Each nanowire structure 110 has, for example, a line width W1 of about 1 nanometer to 1000 nanometers, but is not limited thereto. Those skilled in the art should be able to easily understand that the nanowire structures 110 can also be formed into N-type channels or P-type channels according to the actual manufacturing process requirements, and selectively have different materials to provide corresponding stresses. In one embodiment, the method for forming the nanowire structures 110 includes, but is not limited to, the following steps: first, providing a bulk substrate (not shown), preferably including a single-crystalline material such as silicon, epitaxial silicon, silicon germanium, or silicon carbide, etc., and then forming a mask layer (not shown) on the bulk substrate and performing at least one patterning process through the mask layer to etch the bulk substrate to form the nanowire structures 110. However, in another embodiment, it is also possible to selectively perform an epitaxial growth process through a mask layer (not shown) formed on the substrate 100, such that an epitaxial layer (not shown, which may include a single-crystalline material different from the bulk substrate) formed on the top surface 100 of the substrate 100 becomes the nanowire structures 110. Then, after the nanowire structures 110 are formed, the aforementioned mask layer is completely removed. It should be noted that the aforementioned at least one patterning process or epitaxial growth process can be selectively performed along specific grain boundaries, such that each nanowire structure 110 presents a square or hexagonal cross-sectional shape in a top view (not shown) as Figure 1 shown, but is not limited thereto.

[0065] As Figure 4 shown, a trimming process is performed on the nanowire structures 110 to further etch each nanowire structure 110 to form nanowire structures 112 with a smaller line width W2. On the other hand, the cross-sectional shape of each nanowire structure 110 can also change from the original square or hexagonal shape to a circular or approximately circular cross-sectional shape after the trimming process, but is not limited thereto. Those skilled in the art should be able to easily understand that in one embodiment, it is also possible to directly form nanowire structures 112 with a smaller line width W2 and a circular or approximately circular cross-sectional shape through the aforementioned at least one patterning process or the aforementioned epitaxial growth process. In this way, the trimming process can be omitted on the premise of simplifying the manufacturing process.

[0066] As Figure 5As shown, a first selective deposition process, preferably an epitaxial growth process, is performed on the substrate 100 to form a low-resistance doped semiconductor material or a metal material on the top surface 100a of the substrate 100 as the first source / drain structure 114. In one embodiment, the doped semiconductor material or the metal material includes, for example, silicon, silicon germanium, titanium, tantalum, aluminum, copper, tungsten, or any combination thereof, but is not limited thereto. Then, according to the process requirements, a back-etching process is selectively performed using the difference in etching rates between the first source / drain structure 114 and the nanowire structure 112, such that the first source / drain structure 114 only surrounds the lower half of the nanowire structure 112. Next, a dielectric material layer 116 is formed to conformally cover the nanowire structure 112 and the first source / drain structure 114. The formation of the dielectric material layer 116 is, for example, by performing a deposition process, such as atomic layer deposition (ALD), such that the dielectric material layer 116 includes a single dielectric material or a composite dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a suitable low-k material, etc. Alternatively, a thermal oxidation process can also be performed to form a dielectric material layer 116 on the surfaces of the nanowire structure 112 and the first source / drain structure 114, which can include different dielectric materials, but is not limited thereto.

[0067] As Figure 6 shown, a metal deposition process, such as a chemical vapor deposition process or a physical vapor deposition process, is performed on the substrate 100 to form a metal layer 118 on the dielectric material layer 116, filling the space between the nanowire structures 112, entirely covering the nanowire structures 112, and covering the top surface of the nanowire structures 112. It should be noted that the aforementioned metal deposition process preferably includes a two-stage deposition process to pre-define an etch stop layer 118a in the metal layer 118. Those skilled in the art should easily understand that the formation height of the etch stop layer 118a can be adjusted according to the channel width required for the transistors to be formed subsequently, not limited to Figure 6 that shown.

[0068] As Figure 7As shown, at least one etching process is performed to remove the metal layer 118 and the dielectric material layer 116 above the etch stop layer 118a, exposing the top surface and the upper half of each nanowire structure 112. And simultaneously, the gate structure 122 and the gate dielectric layer 120 are formed. The gate structure 122 surrounds a part of each nanowire structure 112 and is located above the gate dielectric layer 120 and the first source / drain structure 114. Among them, the gate dielectric layer 120 specifically includes a first part 120a horizontally extending between the gate structure 122 and the first source / drain structure 114, and a second part 120b vertically extending between the gate structure 122 and each nanowire structure 122. Then, a deposition process and an etching process are performed again to form a spacer 124 on the gate structure 122. Alternatively, in another embodiment, an oxidation (or nitridation) process can also be selectively performed, and then an etching process is performed using the difference in etching rates between the oxide (or nitride) formed on the surface of the nanowire structure 112 and the oxide (or nitride) formed on the surface of the gate structure 122 to completely remove the oxide (or nitride) formed on the surface of the nanowire structure 112, and only the oxide (or nitride) formed on the surface of the gate structure 122 is retained as the spacer 124. In one embodiment, the spacer 124 also includes a dielectric material, such as including silicon oxide, silicon nitride, silicon oxynitride, or a suitable low-k material, but not limited thereto.

[0069] As Figure 8 shown, a second selective deposition process, preferably an epitaxial growth process, is performed to deposit a conductive material layer 126 on the spacer 124, covering the top surface and the upper half of each nanowire structure 112 again. In one embodiment, the conductive material layer 126 includes, for example, a doped semiconductor material with a low resistance value or a metal material, such as including silicon, silicon germanium, titanium, tantalum, aluminum, copper, tungsten, or any combination thereof, preferably including the same conductive material as the first source / drain structure 114, but not limited thereto. Then, a first planarization process P1, such as a chemical mechanical polishing process, is performed to remove a part of the conductive material layer 126 and a part of each nanowire structure 112 downward from the top surface of the conductive material layer 126, forming the second source / drain structure 128 as Figure 9 shown.

[0070] As Figure 9As shown, a second interconnection layer 130 is formed in direct contact with the second source / drain structure 128 and each nanowire structure 112. The second interconnection layer 130 includes, for example, a metal material with a low resistance value, including but not limited to titanium, tantalum, aluminum, copper, tungsten, or any combination of the foregoing materials, to electrically connect the second source / drain structure 128. In addition, in one embodiment, before forming the second interconnection layer 130, a metal silicide (not shown) may be selectively formed on the top surfaces of each nanowire structure 112 and the second source / drain structure 128 to reduce sheet resistance and contact resistance.

[0071] Then, as Figure 10 shown, a second planarization process P2 is performed, for example, by sequentially performing an ion implantation process and a chemical mechanical polishing process to completely remove the substrate 100. First, a carrier substrate 132 is disposed on the second interconnection layer 130, and the entire structure is inverted through the carrier substrate 132 so that the bottom surface of the substrate 100 faces upward. Then, the ion implantation process is performed from the bottom surface. The ion implantation process includes, for example, but is not limited to the following steps: uniformly doping a high dose of multiple ions (such as hydrogen ions or oxygen ions, not shown) from the bottom surface, and then performing a heat treatment on these ions to generate multiple bubbles 134, thereby separating a part of the substrate 100 to achieve the effect of thinning the substrate 100. Then, the remaining part of the substrate 100 is removed through the chemical mechanical polishing process.

[0072] Subsequently, please refer to Figure 11 shown, a first interconnection layer 138 is formed in direct contact with and electrically connected to the first source / drain structure 114. Along with the manufacturing process of the first interconnection layer 138, conductive structures 140 and 142 that are in direct contact with and electrically connected to the second interconnection layer 130 and the gate structure 122 may also be formed below the second interconnection layer 130 and the gate structure 122, so that the second source / drain structure 128 and the gate structure 122 can be synchronously connected to the side where the first source / drain structure 114 is located through the conductive structures 140 and 142 that electrically connect the second interconnection layer 130 and the gate structure 122 (as Figure 11The bottom side shown). Under this operation, the first source / drain structure 114, the gate structure 122, and the second source / drain structure 128 of the partial nanowire structure 112 are sequentially stacked and respectively coated, and a transistor with a vertical channel can be jointly formed to achieve the effect of a surround gate. Moreover, the first source / drain structure 114, the second source / drain structure 128, and the gate structure 122 of the transistor can further be connected to other functional devices or components, such as memory devices, logic devices, central processing units, or analog devices, etc., but not limited thereto, by the first interconnect layer 138, the second interconnect layer 130, and the conductive structures 140, 142.

[0073] Thus, the fabrication of the semiconductor device 10 in the preferred embodiment of the present invention is completed. According to the formation method of this embodiment, forming the transistor with a vertical channel can not only improve the bottleneck of the etching fabrication process, but also effectively increase the carrier channel width of the formed semiconductor device 10, enhance the reliability and integration of electron transmission, reduce current leakage, and provide improved performance and reduced power consumption by adjusting the channel thickness on the same floor area, thereby enabling the semiconductor device 10 to achieve better operating performance.

[0074] As described above, the semiconductor device 10 of the present invention includes a gate-all-around field-effect transistor with a vertical channel, which can be integrated into the current semiconductor fabrication process. For example, it can be used to replace elements such as general metal-oxide-semiconductor field-effect transistors (MOSFETs) and fin field-effect transistors (FinFETs) to fabricate various functional chips and system-on-chip (SoC). Alternatively, a chip (not shown) is also provided, and the chip has hundreds of millions of surround gate transistors as described above. Figure 1 、 Figure 2 shown to be further used to integrate with other functional chips, non-functional chips, or system-on-a-chip (SoC) such as memory chips, logic chips, and central processing unit chips to form a three-dimensional integrated circuit.

[0075] For example, again Figure 11As shown, a package layer 144 is further disposed above the second interconnect layer 130 of the semiconductor device 10, covering and enclosing one side of the transistor (the side where the second source / drain structure 128 is located). The first interconnect layer 138 and the conductive structures 140, 142 of the semiconductor device 10 are additionally connected to a plurality of conductive structures 152 on a chip 20. Among them, the conductive structures 152 are, for example, disposed in a dielectric layer 150, which can be an interposer, a functional chip, a system-on-chip (SoC), etc., and thus may include suitable plugs and / or conductive layers, which, for example, have low-resistance metal materials such as titanium, tantalum, aluminum, copper, tungsten, etc., but are not limited thereto. Subsequently, the conductive structures 152 of the chip 20 can be selectively connected to the bonding structure 30 disposed below, such as including a package substrate or a printed circuit board (PCB), but is not limited thereto. In this way, the semiconductor device 10 can be applied to the three-dimensional stacked structure. For example, by using the copper-copper hybrid bonding technology, through the bonding method of metal material to metal material and dielectric material to dielectric material simultaneously, the first interconnect layer 138 and the conductive structures 140, 142 of the semiconductor device 10 are directly connected to other functional devices or components.

[0076] Generally speaking, the semiconductor device of the present invention is composed of sequentially stacking two source / drain structures and a gate structure in the vertical direction and respectively covering part of the nanowire structure to jointly form a gate-all-around field-effect transistor with a vertical channel. Thus, the semiconductor device of the present invention can effectively increase its carrier channel width under the same floor area, improve the reliability and integration of electron transmission, and thus achieve better operating performance. Moreover, the semiconductor device can be further applied to a three-dimensional stacked structure, electrically connecting the semiconductor device to other functional devices or components, such as memory devices, logic devices, central processing units, or analog devices.

[0077] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A semiconductor device, comprising: A plurality of nanowire structures extending along a vertical direction; A first source / drain structure and a second source / drain structure stacked in sequence in the vertical direction; A gate structure disposed between the first source / drain structure and the second source / drain structure in the vertical direction, wherein the first source / drain structure, the gate structure, and the second source / drain structure respectively cover a part of each nanowire structure; And A gate dielectric layer disposed between the gate structure and each nanowire structure, and between the gate structure and the first source / drain structure.

2. The semiconductor device according to claim 1, further comprising a spacer disposed between the second source / drain structure and the gate structure.

3. The semiconductor device according to claim 1, wherein, The gate dielectric layer further includes a first part and a second part of different materials, the first part is disposed between the first source / drain structure and the gate structure, and the second part is disposed on each nanowire structure.

4. The semiconductor device according to claim 1, further comprising: A first interconnect layer surrounded by an insulating layer; And A second interconnect layer surrounded by the insulating layer, wherein the first interconnect layer and the second interconnect layer are stacked on top of each other in the vertical direction and are respectively electrically connected to the first source / drain structure and the second source / drain structure.

5. The semiconductor device according to claim 4, further comprising: A packaging layer covering the second interconnect layer; And A first conductive structure electrically connected to the second interconnect layer, and the bottom surface of the first conductive structure is coplanar with the bottom surface of the first interconnect layer.

6. The semiconductor device according to claim 5, further comprising: A chip including a plurality of second conductive structures respectively electrically connected to the first conductive structure and the first interconnect layer; And A bonding structure disposed under the chip and electrically connected to the chip.

7. The semiconductor device according to claim 6, wherein, The bonding structure includes a packaging substrate or a printed circuit board.

8. A method of forming a semiconductor device, comprising: Forming a plurality of nanowire structures extending along a vertical direction; Forming a first source / drain structure and a second source / drain structure stacked in sequence in the vertical direction; In the vertical direction, forming a gate structure between the first source / drain structure and the second source / drain structure, wherein the first source / drain structure, the gate structure, and the second source / drain structure respectively cover a part of each nanowire structure; And Forming a gate dielectric layer between the gate structure and each nanowire structure, and between the gate structure and the first source / drain structure.

9. The method of forming a semiconductor device according to claim 8, further comprising: Providing a bulk substrate; Performing a patterning process on the bulk substrate to form the nanowire structures on the substrate; And Performing a first selective deposition process to form the first source / drain structure.

10. The method of forming a semiconductor device according to claim 9, wherein, After the first source / drain structure is formed, the gate dielectric layer is formed by performing a thermal oxidation process or a deposition process.

11. The method of forming a semiconductor device according to claim 9, further comprising: Before the first source / drain structure is formed, trimming the nanowire structures.

12. The method for forming a semiconductor device according to claim 9, wherein, After the gate dielectric layer is formed, it further includes: Performing a metal deposition process on the substrate to form the gate structure; and Performing a second selective deposition process on the substrate to form the second source / drain structure.

13. The method for forming a semiconductor device according to claim 12, wherein, Forming the gate structure further includes: Forming a metal layer on the first source / drain structure to cover the top surfaces of the nanowire structures; and Partially removing the metal layer to expose the top surfaces of the nanowire structures.

14. The method for forming a semiconductor device according to claim 12 further includes: Before the second source / drain structure is formed, forming a spacer on the gate structure.

15. The method for forming a semiconductor device according to claim 9 further includes: Form a first interconnect layer on the first source / drain structure; And Form a second interconnect layer on the second source / drain structure, wherein the first interconnect layer and the second interconnect layer are stacked on top of each other in the vertical direction and are electrically connected to the first source / drain structure and the second source / drain structure respectively.

16. The method for forming a semiconductor device according to claim 15, before forming the second interconnection layer, further includes: Completely remove the substrate.

17. The method for forming a semiconductor device according to claim 16, wherein, Removing the substrate further includes: Doping a plurality of ions in the substrate; Performing a heat treatment on the ions; and Separating a part of the substrate through the ions.

18. The method for forming a semiconductor device according to claim 15 further includes: Form an encapsulation layer on the second interconnect layer; And When forming the first interconnect layer, form a first conductive structure under the second interconnect layer, the first conductive structure being electrically connected to the second interconnect layer and coplanar with the bottom surface of the first interconnect layer.

19. The method for forming a semiconductor device according to claim 18 further includes: Form a chip, the chip including a plurality of second conductive structures electrically connected to the first conductive structure and the first interconnect layer respectively; And Form a bonding structure on the chip.

20. The method for forming a semiconductor device according to claim 19, wherein, The bonding structure includes an encapsulation substrate or a printed circuit board.

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