Display device

Abstract

A display device of one embodiment includes: a substrate on which a plurality of sub-pixels and one or more repair sub-pixels are disposed; a high potential power line disposed in the plurality of sub-pixels and the repair sub-pixel; a driving transistor disposed in each of the plurality of sub-pixels and each of the repair sub-pixels; a sensing layer disposed on a high potential power line in each of the plurality of sub-pixels and each of the repair sub-pixels; an insulating layer disposed on the sensing layer in the plurality of sub-pixels and the repair sub-pixels; a light emitting element disposed between the sensing layer and the insulating layer in each of the plurality of sub-pixels; and an additional light emitting element disposed on the insulating layer in the repair sub-pixel.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0182651, filed with the Korean Intellectual Property Office on December 15, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device using light - emitting diodes (LEDs). Background Art

[0004] Display devices for computer monitors or TVs, mobile phones, etc. include self - emissive organic light - emitting display (OLED) devices, etc., and liquid crystal display (LCD) devices, etc. that require a separate light source.

[0005] Display devices have been widely used in various fields ranging from computer monitors and TVs to personal mobile devices, and research has been conducted on display devices having a wide display surface area and having a reduced volume and weight.

[0006] Additionally, in recent years, display devices including LEDs have drawn attention as next - generation display devices. LEDs are made of inorganic materials instead of organic materials, thus ensuring excellent reliability and a longer lifespan than liquid crystal display devices or organic light - emitting display devices. In addition, LEDs can ensure a fast lighting speed, excellent luminous efficiency, and excellent impact resistance and high reliability, and display high - brightness images. Summary of the Invention

[0007] An object to be achieved by the present disclosure is to provide a display device that can easily sense defective sub - pixels to which a light - emitting element has not been transferred.

[0008] Another object to be achieved by the present disclosure is to provide a display device that can easily sense defective sub - pixels to which a light - emitting element has not been transferred by using a sensing transistor.

[0009] Still another object to be achieved by the present disclosure is to provide a display device that can sense a non - transfer failure by short - circuiting a sensing layer and a first connection electrode in a defective sub - pixel to which a light - emitting element has not been transferred.

[0010] Still another object to be achieved by the present disclosure is to provide a display device that can repair defective sub - pixels to which a light - emitting element has not been transferred.

[0011] Still another object to be achieved by the present disclosure is to provide a display device that can perform repair by transferring an additional light - emitting element to a defective sub - pixel.

[0012] Another object to be achieved by the present disclosure is to provide a display device that can repair defective sub-pixels and ensure an increase in yield.

[0013] The objects of the present disclosure are not limited to the above-mentioned objects, and those skilled in the art can clearly understand other objects not mentioned above from the following description.

[0014] A display device according to an embodiment includes: a substrate on which a plurality of sub-pixels and one or more repair sub-pixels are provided; a high-potential power line provided in the plurality of sub-pixels and the repair sub-pixels; a driving transistor provided in each of the plurality of sub-pixels and each of the repair sub-pixels; a sensing layer provided on the high-potential power line in each of the plurality of sub-pixels and each of the repair sub-pixels; an insulating layer provided on the sensing layer in the plurality of sub-pixels and the repair sub-pixels; a light-emitting element provided between the sensing layer and the insulating layer in each of the plurality of sub-pixels; and an additional light-emitting element provided on the insulating layer in the repair sub-pixels.

[0015] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0016] According to the present disclosure, the light-emitting element can easily sense defective sub-pixels.

[0017] According to the present disclosure, a defective sub-pixel to which the light-emitting element is not transmitted can be easily detected by using a sensing transistor instead of an illumination test.

[0018] According to the present disclosure, in a sub-pixel in which a non-transmission failure occurs, the sensing layer and the first connection electrode can be short-circuited to sense the non-transmission failure.

[0019] According to the present disclosure, the light-emitting element can repair a defective sub-pixel to which the light-emitting element is not transmitted.

[0020] According to the present disclosure, an additional light-emitting element can be transmitted to a defective sub-pixel to repair the defective sub-pixel.

[0021] According to the present disclosure, the yield can be increased by repairing defective sub-pixels.

[0022] The effects according to the present disclosure are not limited to the above-exemplified contents, and more different effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0024] Figure 1 is a schematic diagram of a display device according to an embodiment;

[0025] Figure 2A is a partial cross-sectional view of a display device according to an embodiment;

[0026] Figure 2B is a perspective view of a tiled display device according to an embodiment;

[0027] Figure 3 is an enlarged schematic plan view of an active area of a display device according to an embodiment;

[0028] Figure 4 is a circuit diagram of a sub-pixel and a repair sub-pixel of a display device according to an embodiment;

[0029] Figure 5 is Figure 3 an enlarged plan view of region A of

[0030] Figure 6 and Figure 7 is a cross-sectional view of a sub-pixel of a display device according to an embodiment;

[0031] Figure 8 and Figure 9 is a cross-sectional view of a repair sub-pixel of a display device according to an embodiment;

[0032] Figure 10 is a circuit diagram of a repair sub-pixel of a display device according to an embodiment before a repair process; and

[0033] Figure 11 is a cross-sectional view of a repair sub-pixel of a display device according to an embodiment. DETAILED DESCRIPTION

[0034] Advantages and features of the present disclosure, and methods for achieving these advantages and features, will be apparent by referring to the following exemplary embodiments described in detail in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples, so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0035] The shapes, dimensions, ratios, angles, numbers, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, like reference numerals generally denote like elements. In addition, in the following description of the present disclosure, detailed descriptions of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Any reference to the singular may include the plural unless otherwise explicitly stated.

[0036] Even if not explicitly stated, components are interpreted to include a normal error range.

[0037] When terms such as "on," "above," "below," and "next to" are used to describe the positional relationship between two parts, one or more parts may be located between these two parts, unless these terms are used together with the terms "immediately" or "directly."

[0038] When an element or layer is disposed "on" another element or layer, another layer or another element may be directly interposed between other elements or between them.

[0039] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0040] Throughout the specification, like reference numerals generally denote like elements.

[0041] For ease of description, the dimensions and thicknesses of each component shown in the drawings are shown, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0042] The features of the various embodiments of the present disclosure may be partially or completely attached to or combined with each other and may be interlocked and operated in technically different ways, and the embodiments may be executed independently of each other or in association with each other.

[0043] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the drawings.

[0044] Figure 1 is a schematic diagram of a display device of an embodiment. In Figure 1 for ease of description, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC among the various components of the display device 100 are shown.

[0045] Reference Figure 1 , the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various types of signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0046] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL according to a plurality of gate control signals provided by the timing controller TC. In Figure 1 , one gate driver GD is disposed on one side of the display panel PN in a manner that the gate driver GD is spaced apart from the display panel PN, but the number and position of the gate driver GD are not limited thereto.

[0047] The data driver DD supplies data voltages to a plurality of data lines DL according to a plurality of data control signals and image data provided by the timing controller TC. The data driver DD can convert the image data into data voltages by using a reference gamma voltage, and supply the converted data voltages to the plurality of data lines DL.

[0048] The timing controller TC aligns the image data input from the outside, and supplies the aligned image data to the data driver DD. The timing controller TC can generate gate control signals and data control signals by using the synchronization signals input from the outside (for example, dot clock signals, data enable signals, and horizontal / vertical synchronization signals). Additionally, the timing controller TC supplies the generated gate control signals and the generated data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0049] As a component for displaying an image to a user, the display panel PN includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL may cross each other, and at the points where the scan lines SL and the data lines DL cross each other, a plurality of sub-pixels SP may be formed.

[0050] In the display panel PN, an active area AA and a non-active area NA may be defined.

[0051] The active region AA is the region where an image is displayed in the display device 100. In the active region AA, a plurality of sub-pixels SP that constitute a plurality of pixels PX and a pixel circuit for driving the plurality of sub-pixels SP can be provided. The plurality of sub-pixels SP are the minimum units that constitute the active region AA, and n number of sub-pixels SP can form one pixel PX. In each of the plurality of sub-pixels SP, a thin film transistor for driving a plurality of light emitting elements 120 or the like can be provided. Depending on the type of the display panel PN, the plurality of light emitting elements 120 can be defined in different ways. For example, in the case where the display panel PN is an inorganic light emitting display panel PN, the light emitting element 120 can be a light emitting diode (LED) or a micro light emitting diode (LED).

[0052] In the active region AA, a plurality of signal lines for transmitting various types of signals to the plurality of sub-pixels SP are provided. For example, the plurality of signal lines can include a plurality of data lines DL that supply data voltages to each of the plurality of sub-pixels SP, a plurality of scan lines SL that supply scan signals to each of the plurality of sub-pixels SP, and the like. The plurality of scan lines SL can be connected to the plurality of sub-pixels SP when extending from the active region AA in one direction, and the plurality of data lines DL can be connected to the plurality of sub-pixels SP when extending from the active region AA in a direction different from the one direction. In addition, a low potential power line VSS, a high potential power line VDD, etc. can be further provided in the active region AA, and it is not limited thereto.

[0053] As a region where an image is not displayed, the non-active region NA can be defined as a region extending from the active region AA. In the non-active region NA, a link line and a pad electrode for transmitting signals to the sub-pixels SP in the active region AA, or a driving IC such as a gate driver IC, a data driver IC, etc. can be provided.

[0054] Additionally, the non-active region NA can be placed on the rear surface of the display panel PN, that is, the surface without sub-pixels SP, or can be omitted, and it is not limited to that shown in the figure.

[0055] Furthermore, a driving unit such as a gate driver GD, a data driver DD, and a timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the non-active region NA based on the gate-in-panel (GIP) method, or can be installed between the plurality of sub-pixels SP in the active region AA based on the gate-in-active-region (GIA) method.

[0056] For example, the data driver DD and the timing controller TC can be formed on separate flexible films and printed circuit boards 110, and are electrically connected to the display panel PN, the data driver DD, and the timing controller TC in such a way that the flexible films and the printed circuit boards 110 are joined to pad electrodes formed in the non-active area NA of the display panel PN.

[0057] In another example, in the case where the gate driver GD is mounted in the active area AA based on the GIA method, and by forming side lines SRL that connect signal lines on the front surface of the display panel PN to pad electrodes on the rear surface of the display panel PN, the flexible films and the printed circuit board 110 can be joined to the rear surface of the display panel PN, minimizing the non-active area NA on the front surface of the display panel PN as much as possible. Thus, the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN based on the above method, enabling a zero bezel with substantially no bezel, and reference Figure 2A and Figure 2B provides a detailed description thereof.

[0058] Figure 2A is a partial cross-sectional view of a display device according to an embodiment. Figure 2B is a perspective view of a tiled display device according to an embodiment.

[0059] In the non-active area NA of the display panel PN, a plurality of pad electrodes for transmitting various types of signals to the plurality of sub-pixels SP are provided. For example, a first pad electrode PAD1 for transmitting signals to the plurality of sub-pixels SP is provided in the non-active area NA on the front surface of the display panel PN, and a second pad electrode PAD2 electrically connected to a driving component such as a flexible film and a printed circuit board 110 is provided in the non-active area NA on the rear surface of the display panel PN.

[0060] At this time, although not shown in the figure, various types of signal lines (e.g., scan lines SL or data lines DL, etc.) connected to the plurality of sub-pixels SP can extend from the active area AA to the non-active area NA to be electrically connected to the first pad electrode PAD1.

[0061] Additionally, a side line SRL is disposed along a side surface of the display panel PN. The side line SRL can be electrically connected to a first pad electrode PAD1 on a front surface of the display panel PN and a second pad electrode PAD2 on a rear surface of the display panel PN. Accordingly, signals from a driving component on the rear surface of the display panel PN can be transmitted to the plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Accordingly, the driving component is disposed on the rear surface of the display panel PN, and a signal transmission path between the front surface and the rear surface of the display panel PN is formed to minimize a surface area of a non-active region NA on the front surface of the display panel PN.

[0062] Referring to Figure 2B , a plurality of display devices 100 are connected to implement a tiled display device TD having a large screen. At this time, when the tiled display device TD is implemented as a display device 100 having a minimized bezel as shown in Figure 2A , a seam region where no image is displayed between the display devices 100 is minimized, thereby improving the display quality.

[0063] For example, a plurality of sub-pixels SP can form one pixel PX, and an interval D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device 100 can be the same as an interval D1 between pixels PX in one display device 100. Accordingly, when a constant interval of the pixels PX is implemented between the display devices 100, the seam region can be minimized.

[0064] However, Figure 2A and Figure 2B show examples, and the display device 100 of one embodiment can be a general display device having a bezel and is not limited thereto.

[0065] Hereinafter, a display panel PN of the display device 100 of one embodiment is specifically described.

[0066] Figure 3 is an enlarged schematic plan view of an active region of a display device of one embodiment. Figure 4 is a circuit diagram of a sub-pixel and a repair sub-pixel of a display device of one embodiment. Figure 5 is Figure 3 an enlarged plan view of region A of Figure 6 and Figure 7 are cross-sectional views of a sub-pixel of a display device of one embodiment. Figure 8 and Figure 9 are cross-sectional views of a repair sub-pixel of a display device of one embodiment. In Figure 3In [the figure], only a plurality of light-emitting elements 120, a plurality of first connection electrodes CE1, and a plurality of second connection electrodes CE2 are shown, and in Figure 5 In [the figure], for ease of description, the first connection electrodes CE1 and the second connection electrodes CE2 are shown as thick lines, and the hatching is omitted.

[0067] Referring to Figure 3 , the active region AA includes a plurality of pixel regions UPA and a plurality of transmissive regions TA.

[0068] In the active region AA, a plurality of pixel regions UPA are formed. In the plurality of pixel regions UPA, pixels PX are provided and an image is displayed. The plurality of pixel regions UPA can be arranged such that the plurality of pixel regions UPA are spaced apart from each other, and the plurality of transmissive regions TA are located between the plurality of pixel regions UPA. For example, the plurality of pixel regions UPA can be arranged while forming multiple rows and multiple columns.

[0069] A plurality of sub-pixels SP constituting the pixel PX are provided in each of the plurality of pixel regions UPA. Each of the plurality of sub-pixels SP can include a light-emitting element 120 and a pixel PX circuit, and emits light independently. For example, the plurality of sub-pixels SP can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 that emit light of different colors. For example, the first sub-pixel SP1 can be a red sub-pixel SP, the second sub-pixel SP2 can be a green sub-pixel SP, and the third sub-pixel SP3 can be a blue sub-pixel SP, but is not limited thereto.

[0070] Hereinafter, it is assumed that one pixel PX includes two first sub-pixels SP1, two second sub-pixels SP2, and two third sub-pixels SP3, that is, two red sub-pixels SP, two green sub-pixels SP, and two blue sub-pixels SP, but the configuration of the pixel PX is not limited thereto.

[0071] Multiple sub-pixels SP that make up a pixel PX may be arranged linearly in the column direction. The multiple sub-pixels SP may be arranged in the column direction and overlap with lines extending in the column direction. For example, the multiple sub-pixels SP may overlap with data lines DL, reference lines RL, high-potential power lines VDD, low-potential power lines VSS, etc. that extend in the column direction. A pixel region UPA is formed in a region where multiple opaque lines are provided to ensure the surface area of the transmissive region TA in the entire active region AA. The pixel region UPA in which the multiple sub-pixels SP are provided may be a region with a low transmittance and substantially opaque due to components such as a pixel PX circuit and a light-emitting element 120 provided in the multiple sub-pixels SP. Therefore, the multiple sub-pixels SP in the pixel region UPA may be arranged to overlap with opaque lines extending in the column direction, such as data lines DL, reference lines RL, low-potential power lines VSS, and high-potential power lines VDD. Therefore, the multiple sub-pixels SP in the pixel region UPA are arranged to overlap with multiple lines such that the surface area of the opaque region in the entire active region AA can be minimized while the surface area of the transmissive region TA can be maximized.

[0072] Multiple sub-pixels SP that form a pixel PX may be arranged linearly in the column direction. For example, in the column direction, a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 are arranged continuously. However, the order of arranging the sub-pixels SP is described as an example and is not limited thereto.

[0073] Additionally, an undelivered failure of the light-emitting element 120 may occur in at least a part of the multiple sub-pixels SP. At this time, in a display device 100 according to an embodiment, an additional light-emitting element 130 is delivered to the defective sub-pixel SP to repair the defective sub-pixel SP, thereby ensuring an increase in the yield of the display device 100. For this purpose, the multiple sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a repaired sub-pixel SP' that operates normally through a repair process. For example, in the case where the third sub-pixel SP3 among the multiple sub-pixels SP in region A fails, the third sub-pixel SP3 may be repaired to form a third repaired sub-pixel SP3'. Therefore, the pixel PX in region A may include a pair of first sub-pixels SP1, a pair of second sub-pixels SP2, a third sub-pixel SP3, and a third repaired sub-pixel SP3'.

[0074] The multiple transmissive regions TA are regions within the active region AA other than the regions where multiple lines and multiple pixel regions UPA are provided, and have a relatively high transmittance. In the transmissive regions TA, light is transmitted, and the background on the rear surface of the display device 100 can be seen from the front surface of the display device 100. The multiple transmissive regions TA can be arranged in such a way that the multiple transmissive regions TA are spaced apart from each other, with multiple lines and multiple pixel regions UPA located between the multiple transmissive regions TA. The multiple transmissive regions TA can be arranged to surround the multiple pixel regions UPA. Accordingly, the display device 100 of one embodiment can include multiple transmissive regions TA and be implemented as a transparent display device 100.

[0075] Referring to Figures 4 to 6 , each of the multiple sub-pixels SP includes a pixel PX circuit and a light-emitting element 120. The pixel PX circuit can include multiple transistors T1, T2, DT, and a storage capacitor Cst to drive the light-emitting element 120. For example, the pixel PX circuit can include a first transistor T1, a second transistor T2, a driving transistor DT, and a storage capacitor Cst. Additionally, the multiple sub-pixels SP provided in one pixel region UPA can be connected to a scan line SL, multiple data lines DL, multiple reference lines RL, multiple high-potential power lines VDD, and multiple low-potential power lines VSS to receive various types of signals.

[0076] The substrate 110, which is a component for supporting various components included in the display device 100, can be formed of an insulating material. For example, the substrate 110 can be made of glass, resin, or the like. Additionally, the substrate 110 can include a polymer or plastic or a material having flexibility.

[0077] On the substrate 110, a light-shielding layer LS is provided in each of the multiple sub-pixels SP. The light-shielding layer LS shields the light input to the driving active layer DACT of the driving transistor DT described below from the lower part of the substrate 110. Since the light input to the driving active layer DACT of the driving transistor DT from the light-shielding layer LS is shielded, current leakage is minimized.

[0078] A buffer layer 111 is provided on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be formed, for example, of a single-layer silicon oxide (SiOx) or silicon nitride (SiNx) or a multi-layer silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of the substrate 110 or the transistor, the buffer layer 111 can be omitted, and this is not limited either.

[0079] On the buffer layer 111, a driving transistor DT, a first transistor T1, and a second transistor T2 are provided in each of the plurality of sub-pixels SP.

[0080] The driving transistor DT, the first transistor T1, and the second transistor T2 in each of the plurality of sub-pixels SP can be P-type thin film transistors or N-type thin film transistors. For example, in the case of P-type thin film transistors, since holes move from the source electrode to the drain electrode, current can flow from the source electrode to the drain electrode. In the case of N-type thin film transistors, since electrons move from the source electrode to the drain electrode, current can flow from the drain electrode to the source electrode. Hereinafter, it is assumed that the driving transistor DT, the first transistor T1, and the second transistor T2 are P-type thin film transistors in which current flows from the source electrode to the drain electrode, but it is not limited thereto.

[0081] On the buffer layer 111, a driving transistor DT is provided in each of the plurality of sub-pixels SP. The driving transistor DT is a transistor for controlling the driving current supplied to the light-emitting element 120. In one pixel region UPA, the driving transistors DT in each of the plurality of sub-pixels SP can be linearly arranged in the column direction. The plurality of driving transistors DT of the plurality of sub-pixels SP can be linearly arranged while overlapping the regions where the setting reference line RL and the data line DL are provided.

[0082] The driving transistor DT includes a driving active layer DACT, a driving gate electrode DGE, a driving source electrode DSE, and a driving drain electrode DDE.

[0083] The driving active layer DACT is provided on the buffer layer 111. The driving active layer DACT can be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but it is not limited thereto.

[0084] A gate insulating layer 112 is provided on the driving active layer DACT. The gate insulating layer 112, which is an insulating layer for insulating the driving active layer DACT and the driving gate electrode DGE, can be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx) or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but it is not limited thereto.

[0085] The driving gate electrode DGE is provided on the gate insulating layer 112. The driving gate electrode DGE can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but it is not limited thereto.

[0086] A first interlayer insulating layer 113a is provided on the driving gate electrode DGE. The first interlayer insulating layer 113a has contact holes for connecting the driving source electrode DSE to the driving active layer DACT. The first interlayer insulating layer 113a, as an insulating layer for protecting the components thereunder, may be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx), or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0087] The driving source electrode DSE is provided on the first interlayer insulating layer 113a. The driving source electrode DSE is electrically connected to the driving active layer DACT through the contact holes formed at the first interlayer insulating layer 113a and the gate insulating layer 112. Additionally, the driving source electrode DSE may be electrically connected to the second transistor T2. The driving source electrode DSE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0088] On the first interlayer insulating layer 113a, a second interlayer insulating layer 113b and a first passivation layer 114a are provided, and on the first passivation layer 114a, a driving drain electrode DDE is provided. The driving drain electrode DDE can be electrically connected to the driving active layer DACT through the contact holes formed at the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. Additionally, the driving drain electrode DDE can be electrically connected to the low-potential power line VSS through the contact hole formed at the first passivation layer 114a. The driving drain electrode DDE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0089] Then, on the buffer layer 111, the first transistor T1 is provided in each of the plurality of sub-pixels SP. The first transistor T1, as a transistor for transmitting a data voltage to the driving gate electrode DGE of the driving transistor DT, may be referred to as a switching transistor. At this time, in one pixel region UPA, the plurality of first transistors T1 of the plurality of sub-pixels SP may overlap with the scanning line SL and be arranged linearly in the row direction.

[0090] Specifically, the scan line SL can be set across multiple pixel regions UPA while extending in the row direction on the gate insulating layer 112. Additionally, starting from the left side, the first transistors T1 of the first sub-pixels SP1 on the other side of the scan line SL, the first transistors T1 of the first sub-pixels SP1 on one side of the scan line SL, the first transistors T1 of the second sub-pixels SP2 on the other side of the scan line SL, the first transistors T1 of the second sub-pixels SP2 on one side of the scan line SL, the first transistors T1 of the third sub-pixels SP3 on the other side of the scan line SL, and the first transistors T1 of the third sub-pixels SP3 on one side of the scan line SL can be continuously set.

[0091] At this time, the first transistors T1 of a pair of first sub-pixels SP1 can be set adjacent to each other and share a data line DL. In addition, the first transistors T1 of a pair of second sub-pixels SP2 can be set adjacent to each other and share a data line DL. In addition, the first transistors T1 of a pair of third sub-pixels SP3 can also be set adjacent to each other and share a data line DL.

[0092] The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0093] The first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0094] The first gate electrode GE1 is disposed on the gate insulating layer 112. The first gate electrode GE1 can be electrically connected to the scan line SL. For example, the first gate electrode GE1 can be integrated with the scan line SL. The first gate electrode GE1 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0095] The first drain electrode DE1 is disposed on the first interlayer insulating layer 113a. The first drain electrode DE1 can be electrically connected to the first active layer ACT1 through a contact hole formed at the first interlayer insulating layer 113a and the gate insulating layer 112. Additionally, the first drain electrode DE1 can also be electrically connected to the second gate electrode GE2 of the second transistor T2 through a contact hole of the first interlayer insulating layer 113a. The first drain electrode DE1 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0096] The second interlayer insulating layer 113b is disposed on the first drain electrode DE1. The second interlayer insulating layer 113b, as an insulating layer for protecting the components thereunder, may be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx), or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0097] The first passivation layer 114a is disposed on the second interlayer insulating layer 113b. The first passivation layer 114a, as an insulating layer for protecting the components thereunder, may be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx), or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0098] The first source electrode SE1 is disposed on the first passivation layer 114a. The first source electrode SE1 can be electrically connected to the first active layer ACT1 through the contact holes of the first passivation layer 114a, the second interlayer insulating layer 113b, and the first interlayer insulating layer 113a. Additionally, the first source electrode SE1 can be electrically connected to the data line DL. For example, the first source electrode SE1 can be integrated with the data line DL. The first source electrode SE1 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0099] Then, on the buffer layer 111, the second transistor T2 is disposed in each of the plurality of sub-pixels SP. The second transistor T2, as a transistor for compensating the threshold voltage of the driving transistor DT, can be referred to as a sensing transistor. The second transistors T2 of the plurality of sub-pixels SP can be disposed on the left side of each of the plurality of sub-pixels SP and arranged linearly in the column direction.

[0100] For example, the scan line SL may include a portion that protrudes in the column direction from a portion extending in the row direction. The portion of the scan line SL that protrudes in the column direction can be disposed near the left side of the plurality of sub-pixels SP and overlap with the plurality of second transistors T2. The portion of the scan line SL that protrudes in the column direction can be used as the second gate electrode GE2 of the second transistors T2 of the plurality of sub-pixels SP. Therefore, the second transistors T2 of the plurality of sub-pixels SP can be disposed on the protruding portion of the scan line SL and arranged linearly in the column direction.

[0101] The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0102] The second active layer ACT2 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer ACT2 can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0103] At this time, the second active layers ACT2 of adjacent sub-pixels SP can be connected to each other. For example, the second active layers ACT2 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 disposed on one side of the scan line SL can be connected to each other while extending in the column direction, and are collectively connected to the second drain electrode DE2 disposed in the first sub-pixel SP1. Additionally, the second active layers ACT2 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 disposed on the other side of the scan line SL can also be connected to each other while extending in the column direction, and are collectively connected to the second drain electrode DE2 disposed in the first sub-pixel SP1.

[0104] That is, the portion where the channel regions of the second active layers ACT2 of the plurality of sub-pixels SP are connected to the reference line RL is made of the material of the transparent second active layer ACT2 instead of an opaque conductive material, so that the transmittance in the outermost side of the pixel region UPA can be increased. Additionally, the portion where the channel regions of the second active layers ACT2 of the plurality of sub-pixels SP are connected to the reference line RL is made of the material of the second active layer ACT2 to remove contact holes and simplify the structure of the pixel region UPA.

[0105] The gate electrode GE2 is disposed between the gate insulating layer 112 and the first interlayer insulating layer 113a. The second gate electrode GE2 can be electrically connected to the scan line SL. For example, the second gate electrode GE2 can be integrated with the protruding portion of the scan line SL and electrically connected to the protruding portion of the scan line SL. The second gate electrode GE2 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0106] The second source electrode SE2 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The second source electrode SE2 can be electrically connected to the second active layer ACT2 through the contact holes of the first interlayer insulating layer 113a and the gate insulating layer 112. Additionally, the second source electrode SE2 can be electrically connected to the driving source electrode DSE. The second source electrode SE2 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0107] The second drain electrode DE2 is disposed between the first passivation layer 114a and the second passivation layer 114b. The second drain electrode DE2 can be electrically connected to the second active layer ACT2 through a contact hole formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. The second drain electrode DE2 can be integrated with the reference line RL and electrically connected to the reference line RL. The second drain electrode DE2 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0108] Then, a storage capacitor Cst is disposed on the gate insulating layer 112. The storage capacitor Cst can store the potential difference between the driving gate electrode DGE and the driving source electrode DSE of the driving transistor DT when the light-emitting element 120 emits light, so that a constant driving current can be supplied to the light-emitting element 120. The storage capacitor Cst can include a first capacitor electrode C1 electrically connected to the driving gate electrode DGE and a second capacitor electrode C2 electrically connected to the driving source electrode DSE to keep the voltages of the driving gate electrode DGE and the driving source electrode DSE constant.

[0109] Specifically, the first capacitor electrode C1 is disposed on the gate insulating layer 112. The first capacitor electrode C1 can be integrated with the driving gate electrode DGE. The second capacitor electrode C2 is disposed on the first interlayer insulating layer 113a. The first capacitor electrode C1 and the second capacitor electrode C2 can be arranged to overlap each other, with the first interlayer insulating layer 113a between the first capacitor electrode C1 and the second capacitor electrode C2. At this time, the second capacitor electrode C2 can be integrated with the driving source electrode DSE. The first capacitor electrode C1 and the second capacitor electrode C2 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0110] Then, an auxiliary electrode AE is disposed on the first passivation layer 114a. The auxiliary electrode AE is an electrode for electrically connecting the driving source electrode DSE and the first reflective electrode RE1. The driving source electrode DSE and the first reflective electrode RE1 can be electrically connected to each other through the auxiliary electrode AE. The auxiliary electrode AE can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0111] The low-potential power line VSS is disposed on the second interlayer insulating layer 113b. The low-potential power line VSS is disposed in the column direction and overlaps with a plurality of pixel regions UPA. The low-potential power line VSS may be electrically connected to the driving drain electrode DDE. The low-potential power line VSS may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0112] The reference line RL is disposed on the first passivation layer 114a. The reference line RL may be disposed in the column direction and overlaps with a plurality of pixel regions UPA. The reference line RL may be disposed near a plurality of second transistors T2 and is electrically connected to the plurality of second transistors T2. The reference line RL may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0113] A plurality of data lines DL are disposed on the first passivation layer 114a. The plurality of data lines DL may overlap with a plurality of pixel regions UPA while extending in the column direction. The plurality of data lines DL may include data lines DL connected to the first transistors T1 of the plurality of first sub-pixels SP1, data lines DL connected to the first transistors T1 of the plurality of second sub-pixels SP2, and data lines DL connected to the first transistors T1 of the plurality of third sub-pixels SP3. For example, starting from the left, the reference line RL, the data line DL connected to the first sub-pixel SP1, the data line DL connected to the second sub-pixel SP2, and the data line DL connected to the third sub-pixel SP3 may be continuously disposed.

[0114] Then, the second passivation layer 114b is disposed on the driving transistor DT, the first transistor T1, the second transistor T2, the storage capacitor Cst, the reference line RL, and the data line DL. The second passivation layer 114b, as an insulating layer for protecting the components thereunder, may be composed of a single-layer silicon oxide (SiOx) or silicon nitride (SiNx) or a multi-layer silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0115] The first planarization layer 115a is disposed on the second passivation layer 114b. The first planarization layer 115a may planarize the upper portion of the substrate 110 on which a plurality of transistors and the storage capacitor Cst are disposed. The first planarization layer 115a may be composed of a single layer or multiple layers and may be made of, for example, photoresist or an acrylic-based organic material, but is not limited thereto.

[0116] In addition, although not shown in the figures, an additional passivation layer may be provided on the first planarization layer 115a. For example, a passivation layer composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx), or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx) is formed on the first planarization layer 115a to protect the components thereunder.

[0117] Then, a plurality of first reflective electrodes RE1 are provided on the first planarization layer 115a. The plurality of first reflective electrodes RE1 may be provided in each of the plurality of sub-pixels SP, and while the plurality of first reflective electrodes RE1 are electrically connected to the driving transistor DT and the light-emitting element 120, the light emitted from the light-emitting element 120 is reflected to the outside of the display device 100. In each of the plurality of sub-pixels SP, the plurality of first reflective electrodes RE1 may be provided near the driving source electrode DSE. The plurality of first reflective electrodes RE1 may be made of a conductive opaque material having a high reflection efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0118] On the first planarization layer 115a, a high-potential power line VDD serving as the second reflective electrode RE2 is provided. The second reflective electrode RE2 and the high-potential power line VDD may be integrated, and while reflecting the light emitted from the light-emitting element 120 to the outside of the display device 100, a high-potential power voltage is supplied to the light-emitting element 120. The second reflective electrodes RE2 of each of the plurality of sub-pixels SP may be connected to each other and integrally formed. The second reflective electrode RE2 and the high-potential power line VDD may extend in the column direction and be provided to overlap the light-emitting element 120. The second reflective electrode RE2 and the high-potential power line VDD may be provided to overlap the plurality of data lines DL, reference lines RL, and low-potential power line VSS. The second reflective electrode RE2 and the high-potential power line VDD may be made of a conductive opaque material having a high reflection efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0119] In addition, in each of the plurality of sub-pixels SP, the second reflective electrode RE2 may protrude toward the first region SA. The second reflective electrode RE2 may include a portion protruding toward the right side of each of the plurality of sub-pixels SP. The protruding portion of the second reflective electrode RE2 may overlap the first region SA on the right side of the plurality of sub-pixels SP.

[0120] Then, a third passivation layer 114c is provided on the plurality of first reflective electrodes RE1 and the plurality of second reflective electrodes RE2. The third passivation layer 114c, which serves as an insulating layer for protecting the components thereunder, may be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx), or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0121] Referring Figure 6 and Figure 7 , in each of the plurality of sub-pixels SP, a sensing layer TL is provided on the third passivation layer 114c. The sensing layer TL may overlap with the region where the plurality of light-emitting elements 120 are provided. The sensing layer TL may overlap with the plurality of light-emitting elements 120. The sensing layer TL is a layer for sensing the untransmitted faults of the plurality of light-emitting elements 120.

[0122] The sensing layer TL may protrude from the region where the plurality of light-emitting elements 120 are provided toward the first region SA on one side of each of the plurality of sub-pixels SP. For example, the sensing layer TL may include a portion protruding toward the right side of the plurality of sub-pixels SP. Additionally, the protruding portion of the sensing layer TL may overlap with the first region SA. In the first region SA, the protruding portion of the sensing layer TL and the protruding portion of the second reflective electrode RE2 may be electrically connected to each other through a contact hole formed in the third passivation layer 114c. Therefore, since in a normal sub-pixel SP, the sensing layer TL is connected to the high-potential power line VDD which is the second reflective electrode RE2, the sensing layer TL may be in a state of being supplied with a high-potential power voltage.

[0123] The sensing layer TL may be made of any one of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or their alloys, or conductive transparent materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), etc., but is not limited thereto.

[0124] An adhesive layer AD is provided on the third passivation layer 114c and the sensing layer TL. The adhesive layer AD may be formed on the front surface of the substrate 110 and fixes the light-emitting element 120 provided on the adhesive layer AD. The adhesive layer AD may be made of a photocurable adhesive material that can be cured by light. For example, the adhesive layer AD may be selected from any one of adhesive polymers, epoxy resists, UV resins, polyimide-based adhesive layers, acrylate-based adhesive layers, polyurethane-based adhesive layers, and polydimethylsiloxane (PDMS), but is not limited thereto.

[0125] On the adhesive layer AD, a plurality of light-emitting elements 120 are disposed in each of the plurality of sub-pixels SP. Additionally, additional light-emitting elements 130 are disposed in the repair sub-pixel SP'. As elements that emit light using current, the light-emitting elements 120 may include a red light-emitting element 120R that emits red light, a green light-emitting element 120G that emits green light, and a blue light-emitting element 120B that emits blue light, and combinations of the light-emitting elements 120 can achieve various colors including white. The additional light-emitting elements 130 may also be elements substantially the same as the light-emitting elements 120 and include various additional light-emitting elements 130 that emit red, green, and blue light. For example, the light-emitting elements 120 and the additional light-emitting elements 130 may be light-emitting diodes (LEDs) or micro-LEDs, but are not limited thereto.

[0126] The red light-emitting element 120R may be disposed in the first sub-pixel SP1, the green light-emitting element 120G may be disposed in the second sub-pixel SP2, and the blue light-emitting element 120B may be disposed in the third sub-pixel SP3. The plurality of light-emitting elements 120 disposed in one pixel area UPA may be linearly arranged in the column direction. Additionally, in each of the plurality of sub-pixels SP, the plurality of light-emitting elements 120 may be disposed to overlap with the second reflective electrode RE2.

[0127] Referring to Figure 6 and Figure 7 each of the plurality of light-emitting elements 120 includes a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a encapsulation film 126.

[0128] The first semiconductor layer 121 is disposed on the adhesive layer AD, and the second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be formed by doping n-type and p-type impurities on a specific material. For example, each of the first semiconductor layer 121 and the second semiconductor layer 123 may be a layer doped with n-type and p-type impurities on materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. Additionally, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto.

[0129] The light-emitting layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 may receive holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light. The light-emitting layer 122 may be configured as a single layer or a multi-quantum well (MQW), and is made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), etc., but is not limited thereto.

[0130] The first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 is an electrode for electrically connecting the driving transistor DT and the first semiconductor layer 121. At this time, the first semiconductor layer 121 may be a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on the upper surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material such as a conductive transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a conductive opaque material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0131] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 is an electrode for electrically connecting the high-potential power line VDD and the second semiconductor layer 123. At this time, the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material such as a conductive transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a conductive opaque material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0132] Then, a packaging film 126 is disposed around the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The packaging film 126 may be made of an insulating material and protects the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Additionally, the packaging film 126 has contact holes exposing the first electrode 124 and the second electrode 125, such that the first connection electrode CE1 and the second connection electrode CE2 can be electrically connected to the first electrode 124 and the second electrode 125, respectively.

[0133] In addition, a part of the side surface of the first semiconductor layer 121 may be exposed from the packaging film 126. The light-emitting element 120 manufactured on the wafer may be separated from the wafer and transferred to the display panel PN. However, in the process of separating the light-emitting element 120 from the wafer, a part of the packaging film 126 may be torn off. For example, in the process of separating the light-emitting element 120 from the wafer, a part of the packaging film 126 adjacent to the lower edge of the first semiconductor layer 121 of the light-emitting element 120 may be torn off, and a part of the lower side surface of the first semiconductor layer 121 may be exposed to the outside. Since the second planarization layer 115b and the third planarization layer 115c covering the side surface of the first semiconductor layer 121 are formed, and then the first connection electrode CE1 and the second connection electrode CE2 are formed, even if a part of the lower side of the light-emitting element 120 is exposed from the packaging film 126, a short-circuit failure can be reduced.

[0134] Then, a second planarization layer 115b and a third planarization layer 115c are disposed on the adhesive layer AD and the light-emitting elements 120.

[0135] The second planarization layer 115b may overlap a part of the sides of the plurality of light-emitting elements 120, and fix and protect the plurality of light-emitting elements 120. A torn portion of the encapsulation film 126 that protects the side surface of the first semiconductor layer 121 of the light-emitting element 120 may be covered by the second planarization layer 115b. Accordingly, contact and short-circuit failures between the connection electrodes and the first semiconductor layer 121 can be prevented.

[0136] The second planarization layer 115b may include openings. The openings of the second planarization layer 115b may overlap the light-emitting elements 120. The light-emitting elements 120 may be disposed in the openings of the second planarization layer 115b. The openings of the second planarization layer 115b may overlap the regions where the first contact hole CH1 and the second contact hole CH2 are formed. For example, referring to Figure 6 , the first electrode 124 and the second electrode 125 of the light-emitting element 120 may overlap the openings of the second planarization layer 115b. Additionally, referring to Figure 8 , in a repair sub-pixel SP' in which the light-emitting element 120 is not provided, the third planarization layer 115c may be alternatively disposed in the openings of the second planarization layer 115b. Accordingly, in a normal sub-pixel SP, the light-emitting element 120 is disposed in the openings of the second planarization layer 115b, and the third planarization layer 115c and the adhesive layer do not contact each other in the openings, but in the case of the repair sub-pixel SP', the light-emitting element 120 is not disposed in the openings, and the third planarization layer 115c and the adhesive layer AD may contact each other in the openings of the second planarization layer 115b.

[0137] The third planarization layer 115c is formed to cover the upper side portions of the second planarization layer 115b and the light-emitting elements 120. The third planarization layer 115c may have contact holes through which the first electrode 124 and the second electrode 125 of the light-emitting element 120 are exposed. The first electrode 124 and the second electrode 125 of the light-emitting element 120 are exposed from the third planarization layer 115c, but the third planarization layer 115c is partially disposed in the region between the first electrode 124 and the second electrode 125 to prevent short-circuit failures. The second planarization layer 115b and the third planarization layer 115c may be composed of a single layer or multiple layers, and are made of, for example, a photoresist or an acrylic-based organic material, but are not limited thereto.

[0138] A first connection electrode CE1 and a second connection electrode CE2 are disposed on the third planarization layer 115c.

[0139] The first connection electrode CE1 is an electrode for electrically connecting the first electrode 124 of the light-emitting element 120 and the electrode of the driving transistor DT. The first connection electrode CE1 can be electrically connected to the first reflective electrode RE1 through contact holes formed in the third planarization layer 115c, the second planarization layer 115b, and the third passivation layer 114c. At the same time, the first connection electrode CE1 can be electrically connected to the first electrode 124 in the first contact hole CH1 of the third planarization layer 115c. Therefore, the first electrode 124 and the driving source electrode DSE can be electrically connected to each other through the first connection electrode CE1, the first reflective electrode RE1, and the auxiliary electrode AE.

[0140] The second connection electrode CE2 can be an electrode for electrically connecting the second electrode 125 of the light-emitting element 120 and the high-potential power line VDD. The second connection electrode CE2 can be electrically connected to the high-potential power line VDD, which serves as the second reflective electrode RE2, through contact holes formed in the third planarization layer 115c, the second planarization layer 115b, and the third passivation layer 114c. In addition, the second connection electrode CE2 can be electrically connected to the second electrode 125 in the second contact hole CH2 of the third planarization layer 115c. Therefore, the second electrode 125 and the high-potential power line VDD can be electrically connected to each other through the second connection electrode CE2.

[0141] The first connection electrode CE1 and the second connection electrode CE2 can be made of a conductive transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited thereto.

[0142] In addition, in the drawings, the driving source electrode DSE of the driving transistor DT and the first electrode 124 of the light-emitting element 120 are electrically connected to each other. However, depending on the type of the driving transistor DT and the design of the pixel PX circuit, the driving drain electrode DDE of the driving transistor DT and the second electrode 125 of the light-emitting element 120 can be electrically connected to each other, but are not limited thereto.

[0143] Then, in the pixel region UPA, a bank BB is provided on the third planarization layer 115c, the first connection electrode CE1, and the second connection electrode CE2. The bank BB can be spaced apart from the light-emitting element 120 by a predetermined distance. The bank BB can be provided at the boundary between a plurality of sub-pixels SP and cover a part of the first connection electrode CE1 and the second connection electrode CE2. The bank BB can be spaced apart from the transmissive region TA. The bank BB can be made of a material including an opaque material or a black component to reduce color mixing among the plurality of sub-pixels SP, and is made of, for example, a black resin, but is not limited thereto.

[0144] A protective layer 116 is provided on the first connection electrode CE1, the second connection electrode CE2, and the bank BB. The protective layer 116 is a layer for protecting the components thereunder. The protective layer 116 may be composed of a single layer or multiple layers, and is made of, for example, benzocyclobutene, translucent epoxy resin, photoresist, or acrylic-based organic materials, or inorganic materials such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0145] Referring Figure 8 , in the repaired sub-pixel SP’, an additional light-emitting element 130 is provided instead of the light-emitting element 120. During the process of manufacturing the display device 100, the lighting test process of the sub-pixel SP can be performed until after the formation of the first connection electrode CE1 and the second connection electrode CE2. At this time, in the defective sub-pixel SP to which the light-emitting element 120 is not transferred, the additional light-emitting element 130 is transferred onto the first connection electrode CE1 and the second connection electrode CE2 to repair the defective sub-pixel SP. For example, the additional light-emitting element 130 that emits red light can be transferred to the defective sub-pixel SP to which the red light-emitting element 120R is not transferred, the additional light-emitting element 130 that emits green light can be transferred to the defective sub-pixel SPG to which the green light-emitting element 120G is not transferred, and the additional light-emitting element 130 that emits blue light can be transferred to the defective sub-pixel SP to which the blue light-emitting element 120B is not transferred.

[0146] First, in the repaired sub-pixel SP’, a first bonding electrode BE1 is provided on the first connection electrode CE1. The first bonding electrode BE1 is an electrode for electrically connecting the additional light-emitting element 130 and the first connection electrode CE1. The first bonding electrode BE1 can be provided in the first contact hole CH1 formed for the first connection electrode CE1. The first bonding electrode BE1 can be provided to fill the first contact hole CH1 and protrude upward toward the first connection electrode CE1.

[0147] In the repaired sub-pixel SP’, a second bonding electrode BE2 is provided on the second connection electrode CE2. The second bonding electrode BE2 is an electrode for electrically connecting the additional light-emitting element 130 and the second connection electrode CE2. The second bonding electrode BE2 can be provided in the second contact hole CH2 formed for the second connection electrode CE2. The second bonding electrode BE2 can be provided to fill the second contact hole CH2 and protrude upward toward the second connection electrode CE2.

[0148] The first bonding electrode BE1 and the second bonding electrode BE2 can be made of a conductive material that adhesively bonds the additional light-emitting element 130 to the first connection electrode CE1 and the second connection electrode CE2 and has a high reflectivity. For example, the first bonding electrode BE1 and the second bonding electrode BE2 can be made of silver paste (Ag paste) or indium, etc.

[0149] In addition, while the first bonding electrode BE1 and the second bonding electrode BE2 are respectively configured to fill the air gaps of the first contact hole CH1 and the second contact hole CH2, the first bonding electrode BE1 and the second bonding electrode BE2 can connect the additional light-emitting element 130 to the first connection electrode CE1 and the second connection electrode CE2. Specifically, when manufacturing the display device 100, in the process of forming the first contact hole CH1 and the second contact hole CH2 at the third planarization layer 115c to expose the first electrode 124 and the second electrode 125 of the light-emitting element 120, the defective sub-pixel SP to which the light-emitting element 120 is not transferred also has the first contact hole CH1 and the second contact hole CH2. Therefore, in the defective sub-pixel SP, grooves can be formed by the first contact hole CH1 and the second contact hole CH2 at the third planarization layer 115c.

[0150] In addition, after forming the first contact hole CH1 and the second contact hole CH2, a conductive layer can be formed on the front surface of the substrate 110 and patterned to form the first connection electrode CE1 and the second connection electrode CE2. In the defective sub-pixel SP, the first connection electrode CE1 and the second connection electrode CE2 are respectively shaped to correspond to the shapes of the first contact hole CH1 and the second contact hole CH2, such that the first connection electrode CE1 and the second connection electrode CE2 are formed recessedly.

[0151] However, in the case where the additional light-emitting element 130 is directly disposed on the first connection electrode CE1 and the second connection electrode CE2 formed recessedly by the grooves, air gaps can be formed in the recessed portions of the first connection electrode CE1 and the second connection electrode CE2. Since the first connection electrode CE1 and the second connection electrode CE2 are not formed in a planar manner, the first additional electrode 134 and the second additional electrode 135 of the additional light-emitting element 130 may not be correctly connected to the first connection electrode CE1 and the second connection electrode CE2, and air gaps in which oxygen or moisture exists may be formed in the grooves, resulting in a failure in which various metal layers in the display panel PN are oxidized.

[0152] Thus, in the display device 100 of one embodiment, first bonding electrodes BE1 and second bonding electrodes BE2 are formed to fill recessed portions that respectively set first connection electrodes CE1 and second connection electrodes CE2 in the first contact hole CH1 and the second contact hole CH2, so as to remove air gaps. Additionally, the additional light-emitting element 130 can be easily attached and fixed to the first bonding electrodes BE1 and second bonding electrodes BE2 having a flat upper surface, and electrically connected to the first connection electrodes CE1 and second connection electrodes CE2, thereby minimizing lighting failures of the additional light-emitting element 130. Furthermore, the first bonding electrodes BE1 and second bonding electrodes BE2 can be formed of a conductive material having a high reflectivity, and reflect light emitted from the additional light-emitting element 130 to the upper part of the display panel PN. Therefore, the first bonding electrodes BE1 and second bonding electrodes BE2 can serve as a reflective layer, thereby improving the light efficiency of the display device 100.

[0153] The additional light-emitting element 130 is disposed on the first bonding electrodes BE1 and second bonding electrodes BE2. The additional light-emitting element 130 includes a first additional semiconductor layer 131, an additional light-emitting layer 132, a second additional semiconductor layer 133, a first additional electrode 134, a second additional electrode 135, and an additional encapsulation film 136.

[0154] The second additional semiconductor layer 133 is disposed on the first bonding electrodes BE1 and second bonding electrodes BE2, and the first additional semiconductor layer 131 is disposed on the second additional semiconductor layer 133. A part of the lower surface of the first additional semiconductor layer 131 may protrude to the outside of the second additional semiconductor layer 133 such that a part of the lower surface of the first additional semiconductor layer 131 can be exposed from the second additional semiconductor layer 133. The first additional semiconductor layer 131 and the second additional semiconductor layer 133 may be layers formed by doping n-type and p-type impurities on a specific material. For example, each of the first additional semiconductor layer 131 and the second additional semiconductor layer 133 may be a layer formed by doping n-type and p-type impurities on a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. Additionally, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium (Ge), tin (Sn), etc., but is not limited thereto.

[0155] The additional light-emitting layer 132 is disposed between the first additional semiconductor layer 131 and the second additional semiconductor layer 133. The additional light-emitting layer 132 can receive holes and electrons from the first additional semiconductor layer 131 and the second additional semiconductor layer 133 to emit light. The additional light-emitting layer 132 may be configured as a single layer or a multi-quantum well (MQW), and is made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), etc., but is not limited thereto.

[0156] The first additional electrode 134 is disposed on the lower surface of the first additional semiconductor layer 131 and is exposed from the second additional semiconductor layer 133. The first additional electrode 134 may be disposed on the lower surface of the first additional semiconductor layer 131 and be exposed from the additional light-emitting layer 132 and the second additional semiconductor layer 133. The first additional electrode 134 is an electrode for electrically connecting the driving transistor DT and the first additional semiconductor layer 131. The first additional electrode 134 may be made of a conductive material such as a conductive transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a conductive opaque material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0157] The second additional electrode 135 is disposed on the lower surface of the second additional semiconductor layer 133. The second additional electrode 135 is an electrode for electrically connecting the power line and the second additional semiconductor layer 133. The second additional electrode 135 may be made of a conductive material such as a conductive transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a conductive opaque material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0158] Therefore, although the light-emitting element 120 is a lateral-structured LED chip in which a pair of electrodes are disposed on the light-emitting layer 122, the additional light-emitting element 130 is a flipchip-structure LED chip in which a pair of electrodes are disposed under the additional light-emitting layer 132, and the light-emitting element 120 and the additional light-emitting element 130 may be composed of different types of light-emitting elements 120.

[0159] Then, a packaging film 126 is disposed to surround the first additional semiconductor layer 131, the additional light-emitting layer 132, the second additional semiconductor layer 133, the first additional electrode 134, and the second additional electrode 135. The packaging film 126 may be made of an insulating material and protects the first additional semiconductor layer 131, the additional light-emitting layer 132, and the second additional semiconductor layer 133. Additionally, the additional packaging film 136 may have contact holes exposing the first additional electrode 134 and the second additional electrode 135 such that the first bonding electrode BE1 and the second bonding electrode BE2 can be electrically connected to the first additional electrode 134 and the second additional electrode 135, respectively.

[0160] Additionally, a part of the rear surface of the first additional semiconductor layer 131 may be exposed from the encapsulation film 136. As described above, in the process of separating the light-emitting element 120 fabricated on the wafer from the wafer, a part of the additional encapsulation film 136 may be torn off. For example, in the process of separating the light-emitting element 120 from the wafer, a part of the additional encapsulation film 136 adjacent to the edge on the upper side of the first additional semiconductor layer 131 of the additional light-emitting element 130 may be torn off, and a part of the upper side of the side surface of the first additional semiconductor layer 131 may be exposed to the outside. However, since the additional light-emitting element 130 is connected to the pixel circuit PX and the high-potential power line VDD in such a manner that the first additional electrode 134 and the second additional electrode 135 are bonded to the first bonding electrode BE1 and the second bonding electrode BE2 provided below the additional light-emitting element 130, a short-circuit failure caused by the first additional semiconductor layer 131 exposed from the additional encapsulation film 136 can be minimized.

[0161] In addition, the first contact hole CH1 for placing the first bonding electrode BE1 may be formed down to the third planarization layer 115c, the second planarization layer 115b, and the adhesive layer AD. Thus, in the first contact hole CH1 of the repaired sub-pixel SP’, the first connection electrode CE1 may be electrically connected to the sensing layer TL, and the first bonding electrode BE1 may be electrically connected to the sensing layer TL through the first connection electrode CE1. Specifically, the light-emitting element 120 may be transferred onto the adhesive layer AD, and before forming the second planarization layer 115b, a plurality of contact holes including the first contact hole CH1 may be first formed on the adhesive layer AD. At this time, in the sub-pixel SP onto which the light-emitting element 120 is transferred, due to the light-emitting element 120, the first contact hole CH1 may not be formed on the adhesive layer AD, and in the repaired sub-pixel SP’ onto which the light-emitting element 120 is not transferred, the adhesive layer AD at the position where the first contact hole CH1 is formed may be exposed to the outside, and thus, the first contact hole CH1 may be formed at the adhesive layer AD of the repaired sub-pixel SP’. The first contact hole CH1 formed in the adhesive layer AD of the repaired sub-pixel SP’ may be connected to the first contact hole CH1 to be formed later at the second planarization layer 115b and the third planarization layer 115c to form one first contact hole CH1. Additionally, in a state where the first contact hole CH1 is formed at the adhesive layer AD, the second planarization layer 115b and the third planarization layer 115c may be formed, and the process of forming the first contact hole CH1 and the second contact hole CH2 may be performed. At this time, in the repaired sub-pixel SP’ onto which the light-emitting element 120 is not transferred, the light-emitting element 120 is not disposed at the positions where the first contact hole CH1 and the second contact hole CH2 are formed. Therefore, the first contact hole CH1 and the second contact hole CH2 of the repaired sub-pixel SP’ may each have a greater depth than the first contact hole CH1 and the second contact hole CH2 of the normal sub-pixel SP. In the normal sub-pixel SP, the first contact hole CH1 and the second contact hole CH2 may be formed to a depth up to the positions of the first electrode 124 and the second electrode 125 of the light-emitting element 120. For example, they may be formed up to the upper surfaces of each of the first electrode 124 and the second electrode 125 on the upper surface of the third planarization layer 115c. However, in the repaired sub-pixel SP’, the first contact hole CH1 may be formed from the third planarization layer 115c down to the second planarization layer 115b and the adhesive layer AD such that the sensing layer TL is exposed at the first contact hole CH1, and the second contact hole CH2 may be formed down to the third planarization layer 115c and the second planarization layer 115b. Since the second electrode 125 is disposed higher than the first electrode 124, the depth of the second contact hole CH2 is less than the depth of the first contact hole CH1, and thus, even in the repaired sub-pixel SP’, the second contact hole CH2 may be formed to have a depth less than the depth of the first contact hole CH1.

[0162] Refer toFigure 9 , the first bonding electrode BE1 and the first connection electrode CE1 are electrodes for electrically connecting the additional light-emitting element 130 and the driving transistor DT. However, in the first contact hole CH1 of the repaired sub-pixel SP', the first bonding electrode BE1 and the first connection electrode CE1 are in a state of being connected to the sensing layer TL, and in the first region SA, the existing sensing layer TL may be in a state of being connected to the second reflective electrode RE2 serving as the high-potential power line VDD. Therefore, when the additional light-emitting element 130 is directly connected to the first bonding electrode BE1 and the first connection electrode CE1, a failure may occur in which the first additional electrode 134 of the additional light-emitting element 130 is connected to the high-potential power line VDD and the driving transistor DT through the sensing layer TL. Therefore, in the repaired sub-pixel SP', the first region SA may be in a damaged state to separate the first additional electrode 134 of the additional light-emitting element 130 and the high-potential power line VDD.

[0163] The first region SA is a region where the second reflective electrode RE2 and the sensing layer TL are electrically connected to each other. Additionally, in the repaired sub-pixel SP' to which the light-emitting element 120 is not transferred, a part of the second reflective electrode RE2 and a part of the sensing layer TL provided in the first region SA may be in a damaged state, or the sensing layer TL may be in a disconnected state, and the sensing layer TL and the second reflective electrode RE2 may be in an insulated state. Therefore, in the repaired sub-pixel SP' for repairing the defective sub-pixel SP, the sensing layer TL and the second reflective electrode RE2 are insulated so that the first additional electrode 134 of the additional light-emitting element 130 is only connected to the driving transistor DT, and the additional light-emitting element 130 is normally driven.

[0164] Hereinafter, with reference to Figure 10 and Figure 11 a process of repairing the defective sub-pixel SP to form the repaired sub-pixel SP' in the display device 100 according to an embodiment will be described.

[0165] Figure 10 is a circuit diagram of the repaired sub-pixel of the display device according to an embodiment before the repair process. Figure 11 is a cross-sectional view of the repaired sub-pixel of the display device according to an embodiment. Figure 10 is a circuit diagram of the repaired sub-pixel SP' before transferring the additional light-emitting element 130, and Figure 11 is a cross-sectional view of the repaired sub-pixel SP' before transferring the additional light-emitting element 130.

[0166] First, in the process of manufacturing the display device 100, an inspection of the sub-pixel SP for detecting a non-transfer failure of the light-emitting element 120 can be performed. For example, a plurality of light-emitting elements 120 are transferred, and in a state where the first connection electrode CE1 and the second connection electrode CE2 are formed, the plurality of light-emitting elements 120 are driven to detect the sub-pixel SP in which a non-transfer failure occurs.

[0167] Referring to Figure 10 and Figure 11 , as described above, in the defective sub-pixel SP to which the light-emitting element 120 is not transferred, since the light-emitting element 120 is not provided in the first contact hole CH1 and the second contact hole CH2, the first contact hole CH1 and the second contact hole CH2 can have a relatively large depth. Additionally, the sensing layer TL can be exposed at the first contact hole CH1 formed to have a depth greater than the depth of the second contact hole CH2. Therefore, a short-circuit failure between the sensing layer TL and the first connection electrode CE1 may occur in the first contact hole CH1. Accordingly, in the first contact hole CH1 of the defective sub-pixel SP, the driving source electrode DSE of the driving transistor DT and the high-potential power line VDD may be connected to each other through the first connection electrode CE1.

[0168] Furthermore, the voltage of the first node N1, that is, the voltage of the driving source electrode DSE of the driving transistor DT, can be sensed through the second transistor T2. The second transistor T2 can be turned on to transfer the voltage of the driving source electrode DSE to the reference line RL, and the data driver DD can sense the voltage of the first node N1 transferred to the reference line RL.

[0169] At this time, in the sub-pixel SP in which the light-emitting element 120 is provided, for example, in the Figure 4 circuit structure shown, the light-emitting element 120 is in a state of being connected to the first node N1, and in the sub-pixel SP to which the light-emitting element 120 is not transferred, for example, in the Figure 10 circuit structure shown, the high-potential power line VDD is in a state of being directly connected to the first node N1. Therefore, the voltage of the first node N1 can vary according to the presence or absence of the light-emitting element 120, and based on the result of sensing the voltage of the first node N1, a non-transfer failure of the light-emitting element 120 can be detected. Accordingly, the voltage of the first node N1 can be sensed to easily detect a non-transfer failure of the light-emitting element 120.

[0170] Then, referring to Figure 11, among the sub-pixels SP where no transmission failure is detected, the laser is transmitted to the first region SA to insulate the sensing layer TL from the high-potential power line VDD. As described above, the first bonding electrode BE1 and the first connection electrode CE1 for connecting the driving transistor DT and the additional light-emitting element 130 can be connected to the sensing layer TL in the repaired sub-pixel SP'. At this time, since the additional light-emitting element 130 is immediately transmitted without disconnecting the sensing layer TL, the first additional electrode 134 of the additional light-emitting element 130 can be electrically connected to both the driving transistor DT and the high-potential power line VDD through the first bonding electrode BE1, the first connection electrode CE1, and the sensing layer TL, thereby preventing failure.

[0171] Therefore, after the process of checking for non-transmission failures is completed, a laser is irradiated onto the first region SA of the defective sub-pixel SP to insulate the sensing layer TL from the high-potential power line VDD. For example, the laser can be irradiated onto the first region SA of the sub-pixel SP where a non-transmission failure is sensed to damage the connection hole portion to which the high-potential power line VDD and the sensing layer Tl are connected. In another example, the laser can be irradiated onto the first region SA to disconnect a part of the sensing layer TL placed in the first region SA, and the remaining part of the sensing layer TL not placed in the first region SA can also be disconnected. Additionally, in the drawings, only the disconnection of the sensing layer TL is shown, but depending on the intensity of the laser, both the sensing layer TL and the high-potential power line VDD placed in the first region SA can be disconnected. Therefore, in the first region SA, the process of insulating the sensing layer TL from the high-potential power line VDD can be performed to connect the sensing layer TL, the first bonding electrode BE1, and the first connection electrode CE1 only to the driving transistor DT in the repaired sub-pixel SP'.

[0172] After the process of insulating the sensing layer TL from the high-potential power line VDD is completed, the first bonding electrode BE1 and the second bonding electrode BE2 can be formed in the first contact hole CH1 and the second contact hole CH2, respectively. Then, the additional light-emitting element 130 is transferred onto the first bonding electrode BE1 and the second bonding electrode BE2 to form the repaired sub-pixel SP'.

[0173] In a display device 100 according to an embodiment, an undelivered failure of a light-emitting element 120 can be detected without performing an illumination test. A sensing layer TL can be disposed in an area to which the light-emitting element 120 is delivered and is electrically connected to a high-potential power line VDD. Then, when forming a first contact hole CH1 and a second contact hole CH2, the first contact hole CH1 and the second contact hole CH2 can be formed relatively deeply in a sub-pixel SP to which the light-emitting element 120 is not delivered, and the sensing layer TL can be exposed at the first contact hole CH1. Additionally, in the following process, when a first connection electrode CE1 is connected to the sensing layer TL, a short-circuit failure may occur in which the sensing layer TL, the high-potential power line VDD, and a driving transistor DT are electrically connected. Then, the voltage of a first node N1, i.e., the voltage of a driving source electrode DSE, can be sensed by a second transistor T2, such that it is easy to detect the sub-pixel SP to which the light-emitting element 120 is not delivered.

[0174] In a display device 100 according to an embodiment, an additional light-emitting element 130 can be delivered to a defective sub-pixel SP to which the light-emitting element 120 is not delivered to form a repaired sub-pixel SP' that is normally driven. After first detecting the defective sub-pixel SP to which the light-emitting element 120 is not delivered in the above inspection process, a first bonding electrode BE1 and a second bonding electrode BE2 can be formed to bond the additional light-emitting element 130 to the defective sub-pixel SP. The first bonding electrode BE1 and the second bonding electrode BE2 can have a flat upper surface, such that the additional light-emitting element 130 can be easily bonded to the first bonding electrode BE1 and the second bonding electrode BE2. Additionally, the first bonding electrode BE1 and the second bonding electrode BE2 can be respectively configured to fill a space formed by the first contact hole CH1 and the second contact hole CH2, such that an air gap between the additional light-emitting element 130 and the first connection electrode CE1 and the second connection electrode CE2 is removed. Therefore, the additional light-emitting element 130 can be stably disposed in the repaired sub-pixel SP', and the removal of the air gap can help prevent moisture and oxygen in the air gap from damaging components in the display device 100.

[0175] In a display device 100 according to an embodiment, a sensing layer TL of a repaired sub-pixel SP' may be insulated from a high-potential power line VDD to normally drive an additional light-emitting element 130. The sensing layer TL may be disposed to overlap with a first contact hole CH1 while being electrically connected to the high-potential power line VDD to detect a non-transfer failure of the light-emitting element 120. Additionally, in a sub-pixel SP to which the light-emitting element 120 is not transferred, the sensing layer TL may be electrically connected to a first connection electrode CE1, a driving transistor DT, and the high-potential power line VDD, and the voltage of a driving source electrode DSE may be sensed to detect a non-transfer failure. A first additional electrode 134 of the additional light-emitting element 130 needs to be electrically connected to the driving transistor DT through the first connection electrode CE1. However, in a state where the sensing layer TL is continuously electrically connected to the high-potential power line VDD, a failure in which the first additional electrode 134 connects both the driving source electrode DSE and the high-potential power line VDD may occur. Therefore, before transferring the additional light-emitting element 130, a laser may be irradiated onto a first region SA to insulate the sensing layer TL from the high-potential power line VDD. For example, the sensing layer TL and the high-potential power line VDD disposed in the first region SA may be disconnected from the sensing layer TL and the high-potential power line VDD not disposed in the first region SA, or the contact holes of the sensing layer TL and the high-potential power line VDD may be damaged. Accordingly, in the repaired sub-pixel SP', the sensing layer TL may be separated from the high-potential power line VDD, and the first additional electrode 134 of the additional light-emitting element 130 may be electrically connected only to the driving transistor DT and operate normally.

[0176] Exemplary embodiments of the present disclosure may also be described as follows:

[0177] According to an aspect of the present disclosure, a display device includes: a substrate on which a plurality of sub-pixels and one or more repaired sub-pixels are disposed; a high-potential power line disposed in each of the plurality of sub-pixels and the repaired sub-pixels; a driving transistor disposed in each of the plurality of sub-pixels and the repaired sub-pixels; a sensing layer disposed on the high-potential power line in each of the plurality of sub-pixels and the repaired sub-pixels; an insulating layer disposed on the sensing layer in the plurality of sub-pixels and the repaired sub-pixels; a light-emitting element disposed between the sensing layer and the insulating layer in each of the plurality of sub-pixels; and an additional light-emitting element disposed on the insulating layer in the repaired sub-pixel.

[0178] The display device may further include an adhesive layer disposed between the sensing layer and the light-emitting element below the insulating layer. In each of the plurality of sub-pixels, the sensing layer may be electrically connected to the high-potential power line through a contact hole of the adhesive layer, and in the repaired sub-pixel, the sensing layer may be insulated from the high-potential power line.

[0179] The display device may further include a first connection electrode, which is disposed on a light-emitting element in each of the plurality of sub-pixels, under an additional light-emitting element in the repair sub-pixel, and is electrically connected to the driving transistor, and the first connection electrode may be disposed on the insulating layer.

[0180] In the repair sub-pixel, the additional light-emitting element may be disposed on the first connection electrode and the insulating layer.

[0181] The first connection electrode of the repair sub-pixel may be electrically connected to the sensing layer through a first contact hole in the insulating layer, and the first connection electrodes of the plurality of sub-pixels may be electrically connected to the light-emitting elements through the first contact holes in the insulating layer.

[0182] In each of the plurality of sub-pixels, the sensing layer may be spaced apart from the first connection electrode, and the light-emitting element is interposed between the sensing layer and the first connection electrode.

[0183] The depth of the first contact holes of the plurality of sub-pixels may be less than the depth of the first contact hole of the repair sub-pixel.

[0184] The display device may further include a second connection electrode, which is disposed on a light-emitting element in each of the plurality of sub-pixels, under an additional light-emitting element in the repair sub-pixel, and is electrically connected to the high-potential power line, and the second connection electrodes of the plurality of sub-pixels may be electrically connected to the light-emitting elements through second contact holes in the insulating layer.

[0185] The depth of the second contact holes of the plurality of sub-pixels may be less than the depth of the second contact hole of the repair sub-pixel.

[0186] The second connection electrode of the repair sub-pixel may be electrically connected to the additional light-emitting element and the high-potential power line.

[0187] The display device may further include: a first bonding electrode disposed between the first connection electrode and the additional light-emitting element in the repair sub-pixel; and a second bonding electrode disposed between the second connection electrode and the additional light-emitting element in the repair sub-pixel, and the first bonding electrode and the second bonding electrode may be respectively configured to fill the first contact hole and the second contact hole.

[0188] The light-emitting element may be a light-emitting diode (LED) having a lateral structure, and the additional light-emitting element may be an LED having a flip-chip structure.

[0189] The display device may further include a first planarization layer disposed on the driving transistor. The insulating layer may include: a second planarization layer disposed on the sensing layer and having an opening configured to overlap with the first contact hole and the second contact hole; and a third planarization layer disposed on the second planarization layer. In each of the plurality of sub-pixels, the light-emitting element may be disposed in the opening of the second planarization layer, and in the repair sub-pixel, the third planarization layer may be disposed in the opening of the second planarization layer.

[0190] The depth of the first contact hole of the plurality of sub-pixels may be greater than the depth of the second contact hole of the plurality of sub-pixels, and the depth of the first contact hole of the repair sub-pixel may be greater than the depth of the second contact hole of the repair sub-pixel.

[0191] Although the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and can be implemented in a variety of different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a substrate on which a plurality of sub-pixels and one or more repair sub-pixels are disposed; a high potential power line, wherein the high potential power line is arranged in the plurality of sub-pixels and the repair sub-pixel; a driving transistor disposed in each of the plurality of sub-pixels and each of the repairing sub-pixels; a sensing layer disposed on the high potential power line in each of the plurality of sub-pixels and each of the repair sub-pixels; an insulating layer, the insulating layer being disposed on the sensing layer in the plurality of sub-pixels and the repairing sub-pixel; a light emitting element, the light emitting element being disposed between the sensing layer and the insulating layer in each of the plurality of sub-pixels; as well as An additional light emitting element is disposed on the insulating layer in the repair sub-pixel.

2. The display device according to claim 1, further comprising: an adhesive layer disposed between the sensing layer and the light emitting element below the insulating layer, wherein, in each of the plurality of sub-pixels, the sensing layer is electrically connected to the high potential power line through a contact hole of the adhesive layer, and Wherein, in the repair sub-pixel, the sensing layer is insulated from the high-potential power line.

3. The display device according to claim 1, further comprising: a first connection electrode, the first connection electrode being disposed on the light emitting element in each of the plurality of sub-pixels, being disposed below the additional light emitting element in the repair sub-pixel, and being electrically connected to the driving transistor, and Wherein, the first connecting electrode is arranged on the insulating layer.

4. The display device according to claim 3, wherein: In the repair sub-pixel, the additional light-emitting element is disposed on the first connecting electrode and the insulating layer.

5. The display device according to claim 4, wherein: The first connection electrode of the repair sub-pixel is electrically connected to the sensing layer through the first contact hole of the insulating layer, and The first connection electrodes of the plurality of sub-pixels are electrically connected to the light-emitting element through the first contact holes of the insulating layer.

6. The display device according to claim 5, wherein: In each of the plurality of sub-pixels, the sensing layer is spaced apart from the first connecting electrode, wherein the light emitting element is interposed between the sensing layer and the first connecting electrode.

7. The display device according to claim 5, wherein: A depth of the first contact hole of the plurality of sub-pixels is smaller than a depth of the first contact hole of the repair sub-pixel.

8. The display device according to claim 5, further comprising: a second connection electrode, which is disposed on the light emitting element in each of the plurality of sub-pixels, is disposed below the additional light emitting element in the repair sub-pixel, and is electrically connected to the high potential power line, and The second connection electrodes of the plurality of sub-pixels are electrically connected to the light-emitting element through the second contact holes of the insulating layer.

9. The display device according to claim 8, wherein: A depth of the second contact holes of the plurality of sub-pixels is smaller than a depth of the second contact hole of the repair sub-pixel.

10. The display device according to claim 8, wherein: The second connection electrode of the repair sub-pixel is electrically connected to the additional light-emitting element and the high-potential power line.

11. The display device according to claim 8, further comprising: a first bonding electrode, the first bonding electrode being disposed between the first connection electrode and the additional light-emitting element in the repair sub-pixel; as well as a second bonding electrode, the second bonding electrode being arranged between the second connection electrode in the repair sub-pixel and the additional light-emitting element, The first bonding electrode and the second bonding electrode are configured to fill the first contact hole and the second contact hole, respectively.

12. The display device according to claim 1, wherein: The light emitting element is a light emitting diode (LED) having a lateral structure, and The additional light emitting element is an LED having a flip chip structure.

13. The display device according to claim 8, further comprising: A first planarization layer is provided on the driving transistor, Wherein, the insulating layer comprises: a second planarization layer disposed on the sensing layer and having an opening configured to overlap the first contact hole and the second contact hole; and a third planarization layer disposed on the second planarization layer, wherein, in each of the plurality of sub-pixels, the light emitting element is disposed in the opening of the second planarization layer, and Wherein, in the repair sub-pixel, the third planarization layer is arranged in the opening of the second planarization layer.

14. The display device according to claim 8, wherein: The depth of the first contact holes of the plurality of sub-pixels is greater than the depth of the second contact holes of the plurality of sub-pixels, and Wherein, a depth of the first contact hole of the repair sub-pixel is greater than a depth of the second contact hole of the repair sub-pixel.

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