Display substrate and display panel

Abstract

The invention relates to a display substrate and a display panel. The display substrate comprises a plurality of pixel circuits arranged on a substrate, each pixel circuit comprises a driving transistor, a first light-emitting control transistor, a first reset transistor and a third reset transistor, a grid electrode of the first light-emitting control transistor is connected with a light-emitting control signal line, and a grid electrode of the third light-emitting control transistor is connected with a light-emitting control signal line; the first electrode of the third reset transistor is connected with a third initialization signal line; the first electrodes of the two first reset transistors in the same pixel circuit group are connected into an integrated structure, the integrated structure is connected with the first initialization signal line, the first reset control signal line is electrically connected with the first auxiliary signal line, and the light-emitting control signal lines extend in the first direction and are arranged on the same layer; the first auxiliary signal lines extend in the second direction, the second direction intersects with the first direction, the third initialization signal lines extend in the first direction, and the orthographic projection of the third initialization signal lines on the substrate and the orthographic projection of the light-emitting control signal lines on the substrate are not overlapped.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display substrate and a display panel. Background Art

[0002] With the continuous development of display technologies, display devices have gradually become ubiquitous in people's lives. Among them, Organic Light-Emitting Diode (OLED) display panels are widely used in intelligent products such as mobile phones, televisions, and laptop computers due to their advantages of self-luminescence, low power consumption, wide viewing angles, fast response speeds, and high contrast ratios. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate and a display panel.

[0004] To achieve the above object, the present disclosure provides a display substrate, including:

[0005] A substrate;

[0006] Multiple rows of pixel circuit rows extending in a first direction, the multiple rows of pixel circuit rows being arranged in a second direction, the second direction intersecting the first direction, each pixel circuit row including a plurality of pixel circuit groups arranged in the first direction, each pixel circuit group including two pixel circuits arranged in the first direction, each pixel circuit including: a driving transistor, a first light-emitting control transistor, a first reset transistor, and a third reset transistor, the gate of the first light-emitting control transistor being connected to a light-emitting control signal line, the first pole of the first light-emitting control transistor being connected to a first voltage signal line; the gate of the third reset transistor being connected to a second reset control signal line, the first pole of the third reset transistor being connected to a third initialization signal line, the second pole of the third reset transistor being electrically connected to the first pole of the driving transistor and the second pole of the first light-emitting control transistor, the gate of the first reset transistor being connected to a first reset control signal line, the first poles of two first reset transistors in the same pixel circuit group being connected as an integrated structure, the integrated structure being connected to a first initialization signal line, and the second pole of the first reset transistor being connected to the second pole of the driving transistor;

[0007] Wherein, the second reset control signal line and the light emission control signal line both extend along a first direction and are arranged in the same layer. The first auxiliary signal line extends along the second direction and is arranged in a different layer from the first initialization signal line. The first initialization signal line is electrically connected to the first auxiliary signal line. The third initialization signal line is located on a side of the layer where the second reset control signal line is located away from the substrate and extends along the first direction. A positive projection of the third initialization signal line on the substrate does not overlap with a positive projection of the light emission control signal line on the substrate.

[0008] In some embodiments, the pixel circuit further includes: a second reset transistor. A gate of the second reset transistor is connected to the second reset control signal line. A first pole of the second reset transistor is connected to the second reset control signal line. A second pole of the second reset transistor is connected to the light emitting device. The first initialization signal line and the second initialization signal line both extend along the first direction.

[0009] Wherein, at least two of the first initialization signal line, the second initialization signal line, and the third initialization signal line are located in different layers.

[0010] In some embodiments, a positive projection of the first pole of the third reset transistor on the substrate is located on a side of a positive projection of the first initialization signal line on the substrate away from the light emission control signal line. A positive projection of the third initialization signal line on the substrate is located on a side of a positive projection of the third initialization signal line on the substrate away from the light emission control signal line.

[0011] In some embodiments, at least one of the third initialization signal line and the second initialization signal line is located in a different layer from the first initialization signal line, and a positive projection of at least one of the third initialization signal line and the second initialization signal line on the substrate does not overlap with a positive projection of the first initialization signal line on the substrate.

[0012] And / or, a positive projection of the first reset control signal line on the substrate does not overlap with a positive projection of the second initialization signal line on the substrate.

[0013] In some embodiments, the light emission control signal line, the first reset control signal line, and the second reset control signal line are located in a first gate metal layer.

[0014] The third initialization signal line is located in a second gate metal layer.

[0015] The first initialization signal line and the second initialization signal line are located in a third gate metal layer.

[0016] The first gate metal layer, the second gate metal layer and the third gate metal layer are sequentially arranged in a direction away from the substrate.

[0017] In some embodiments, the orthographic projection of the third initialization signal line on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the second initialization signal line on the substrate;

[0018] The display substrate also includes a first source-drain metal layer located on a side of the third gate metal layer away from the substrate, the first source-drain metal layer includes a first transfer portion, an orthographic projection of the first transfer portion on the substrate overlaps with an orthographic projection of any one of the third initialization signal line and the first electrode of the third reset transistor on the substrate, and the first transfer portion is electrically connected to the third initialization signal line and the first electrode of the third reset transistor through vias, respectively, and an orthographic projection of the first transfer portion on the substrate is located between an orthographic projection of the first initialization signal line on the substrate and an orthographic projection of the second initialization signal line on the substrate, and has no overlap with an orthographic projection of the first initialization signal line on the substrate.

[0019] In some embodiments, the display substrate further comprises a first source-drain metal layer located on a side of the third gate metal layer away from the substrate, the first source-drain metal layer comprising at least one third auxiliary signal line extending along the second direction and at least one second transfer portion;

[0020] Any one of the orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the third auxiliary signal line on the substrate overlaps with the orthographic projection of the second transfer portion on the substrate, and the second transfer portion is electrically connected to the third auxiliary signal line and is electrically connected to the third initialization signal line through a via hole;

[0021] Furthermore, the orthographic projection of the second adapter on the substrate does not overlap with the orthographic projection of the first initialization signal line on the substrate, and / or the orthographic projection of the second adapter on the substrate does not overlap with the orthographic projection of the second initialization signal line on the substrate.

[0022] In some embodiments, the first source-drain metal layer further includes at least one first auxiliary signal line extending along the second direction and at least one second auxiliary signal line extending along the second direction;

[0023] The first source-drain metal layer further includes:

[0024] At least one first redundant transfer portion, a positive projection of the first redundant transfer portion on the substrate overlaps a positive projection of the third initialization signal line on the substrate, and a direction from the first redundant transfer portion to the first auxiliary signal line is the same as a direction from the second transfer portion to the third auxiliary signal line. The first redundant transfer portion is electrically insulated from the first auxiliary signal line, and the first redundant transfer portion is electrically connected to the third initialization signal line through a via hole;

[0025] And / or, at least one second redundant transfer portion, a positive projection of the second redundant transfer portion on the substrate overlaps a positive projection of the third initialization signal line on the substrate, and a direction from the second redundant transfer portion to the second auxiliary signal line is the same as a direction from the second transfer portion to the third auxiliary signal line. The second redundant transfer portion is electrically insulated from the second auxiliary signal line, and the second redundant transfer portion is electrically connected to the third initialization signal line through a via hole.

[0026] In some embodiments, a distance between an edge of the second transfer portion away from the third auxiliary signal line and the third auxiliary signal line is a first distance;

[0027] The first source-drain metal layer includes at least one first redundant transfer portion and at least one second redundant transfer portion;

[0028] A distance between an edge of the first redundant transfer portion away from the first auxiliary signal line and the first auxiliary signal line is a second distance;

[0029] A distance between an edge of the second redundant transfer portion away from the second auxiliary signal line and the second auxiliary signal line is a third distance;

[0030] A ratio of any one of the second distance and the third distance to the first distance is 0.5 to 1.5.

[0031] In some embodiments, a positive projection of a second pole of the second reset transistor on the substrate is located on a side of a positive projection of the third initialization signal line on the substrate away from the first initialization signal line;

[0032] The display substrate further includes a first source-drain metal layer on a side of the third gate metal layer away from the substrate. The first source-drain metal layer includes a third transfer portion. A positive projection of the second pole of the second reset transistor on the substrate and a positive projection of the second reset control signal line on the substrate, either one of them, overlaps with a positive projection of the third transfer portion on the substrate. The third transfer portion is electrically connected to the second pole of the second reset transistor and the second reset control signal line through vias respectively. The positive projection of the third transfer portion on the substrate also overlaps with a positive projection of the third reset control signal line on the substrate.

[0033] In some embodiments, the light-emitting control signal line, the first reset control signal line, and the second reset control signal line are located in a first gate metal layer;

[0034] The second initialization signal line is located in a second gate metal layer;

[0035] The first initialization signal line and the third initialization signal line are located in a third gate metal layer;

[0036] Wherein, the first gate metal layer, the second gate metal layer, and the third gate metal layer are sequentially arranged in a direction away from the substrate.

[0037] In some embodiments, a positive projection of the second initialization signal line on the substrate is located between a positive projection of the first initialization signal line on the substrate and a positive projection of the third initialization signal line on the substrate, and a positive projection of the first reset control signal line on the substrate is located on a side of the positive projection of the second initialization signal line away from the positive projection of the first initialization signal line on the substrate.

[0038] In some embodiments, the display substrate further includes a first source-drain metal layer on a side of the third gate metal layer away from the substrate. The first source-drain metal layer includes a first transfer portion. A positive projection of the third initialization signal line on the substrate and a positive projection of the first pole of the third reset transistor on the substrate, either one of them, overlaps with a positive projection of the first transfer portion on the substrate. And the first transfer portion is electrically connected to the third initialization signal line and the first pole of the third reset transistor through vias respectively. The positive projection of the first transfer portion on the substrate also overlaps with a positive projection of the second initialization signal line on the substrate, and the positive projection of the first transfer portion on the substrate does not overlap with a positive projection of the first initialization signal line on the substrate.

[0039] In some embodiments, the display substrate further includes a first source-drain metal layer located on a side of the third gate metal layer away from the substrate. The first source-drain metal layer includes a third transfer portion. Any one of a positive projection of the second initialization signal line on the substrate and a positive projection of a second pole of the second reset transistor on the substrate overlaps with a positive projection of the third transfer portion on the substrate. The third transfer portion is electrically connected to the second initialization signal line and the second pole of the second reset transistor through vias respectively. The positive projection of the third transfer portion on the substrate does not overlap with the positive projection of the first reset control signal line on the substrate.

[0040] In some embodiments, the first source-drain metal layer further includes at least one second auxiliary signal line extending along a second direction and at least one first connection portion. The first connection portions are electrically connected to the second auxiliary signal line and the third transfer portion respectively.

[0041] In some embodiments, the display substrate further includes a first source-drain metal layer located on a side of the third gate metal layer away from the substrate. The first source-drain metal layer includes at least one third auxiliary signal line extending along a second direction;

[0042] A positive projection of the third initialization signal line on the substrate and a positive projection of the third auxiliary signal line on the substrate have a first overlapping region. The third auxiliary signal line is electrically connected to the third initialization signal line through a via. A positive projection of the via on the substrate is within a range of a positive projection of the first overlapping region on the substrate. The first overlapping region overlaps with a positive projection of the first reset control signal line on the substrate.

[0043] In some embodiments, a first pole of the first reset transistor is located in a first semiconductor layer. The first semiconductor layer is located between the first gate metal layer and the substrate;

[0044] The display substrate further includes a first source-drain metal layer located on a side of the third gate metal layer away from the substrate. The first source-drain metal layer further includes a fourth transfer portion. The fourth transfer portion is electrically connected to the first initialization signal line and the integrated structure through vias respectively.

[0045] In some embodiments, a shape of a positive projection of the integrated structure on the substrate is an asymmetric figure.

[0046] In some embodiments, the first auxiliary signal line is located in the first source-drain metal layer. The first source-drain metal layer further includes at least one second connection portion. The second connection portions are electrically connected to the first auxiliary signal line and the fourth transfer portion respectively.

[0047] The present disclosure also provides a display panel, which is characterized by including the display substrate described in any one of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:

[0049] Figure 1 is a schematic equivalent circuit diagram of a pixel circuit in some embodiments;

[0050] Figure 2A is a schematic plan view of a plurality of pixel circuits in a display substrate in some embodiments;

[0051] Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、 Figure 2F and Figure 2G are respectively Figure 2A schematic plan views of each single-layer film in;

[0052] Figure 2H is along Figure 2A schematic cross-sectional structure diagram of the cutting line AA' in;

[0053] Figure 3A is a schematic plan view of a plurality of pixel circuits in a display substrate in some embodiments of the present disclosure;

[0054] Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F and Figure 3G are respectively Figure 3A schematic plan views of each single-layer film in;

[0055] Figure 3H is along Figure 3A schematic cross-sectional structure diagram of the cutting line BB' in the display substrate shown;

[0056] Figure 3I is Figure 3A schematic partial cross-sectional structure diagram of the display substrate shown;

[0057] Figure 4A is a schematic plan view of a plurality of pixel circuits in a display substrate in some other embodiments of the present disclosure;

[0058] Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4Fand Figure 4G are respectively Figure 4A the schematic plan views of the single-layer film layers in

[0059] Figure 4H is the schematic cross-sectional view along the Figure 4A cutting line CC’ of the display substrate shown in Detailed implementation manners

[0060] The following will describe in detail the detailed implementation manners of the present disclosure with reference to the accompanying drawings. It should be understood that the detailed implementation manners described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure.

[0061] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0062] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure belongs. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. "Connection" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0063] As used herein, "parallel" and "perpendicular" include the described situations and situations similar to the described situations, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range of approximate parallelism may be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range of approximate perpendicularity may also be, for example, within 5° deviation.

[0064] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0065] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0066] In the related art, an OLED display substrate generally includes a substrate, a driving circuit layer on one side of the substrate, and a light-emitting device layer on the side of the driving circuit layer away from the substrate. Among them, the driving circuit layer includes a plurality of pixel circuits, the light-emitting device layer includes a plurality of light-emitting devices, the pixel circuits are electrically connected to the light-emitting devices, and can provide driving signals for the light-emitting devices to cause the light-emitting devices to emit light.

[0067] Figure 1 is a schematic equivalent circuit diagram of a pixel circuit in some embodiments.

[0068] Specifically, as Figure 1 shown, the pixel circuit includes eight transistors and one storage capacitor Cst. Among them, the eight transistors are respectively a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a third reset transistor T8.

[0069] It should be noted that each of these eight transistors can be a P-type transistor or an N-type transistor, and the present disclosure does not limit this. The embodiments of the present disclosure are described by taking the threshold compensation transistor T2 as an N-type transistor, and the first reset transistor T1, the third reset transistor T8, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 as P-type transistors as examples.

[0070] Optionally, some of the eight transistors may be made of low-temperature polysilicon thin-film transistors, and the other part may be made of oxide thin-film transistors. Further optionally, the active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). The low-temperature polysilicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor on a pixel circuit to form a low-temperature polycrystalline oxide (LTPO) display panel can switch the refresh rate of the display panel to achieve low-frequency driving, which is beneficial to reducing power consumption and improving display quality.

[0071] As Figure 1 shown, the pixel circuit may further include a first node N1, a second node N2, a third node N3, and a fourth node N4. It should be noted that in the pixel circuit 9a provided in the embodiments of the present disclosure, the nodes do not represent actual existing components, but represent the convergence points of relevant electrical connections in the equivalent circuit schematic diagram of the pixel circuit. That is to say, these nodes are equivalent nodes formed by the convergence points of relevant electrical connections in the equivalent circuit schematic diagram of the pixel circuit.

[0072] Among them, the first node N1 is respectively connected to the gate of the driving transistor T3, the first electrode plate of the storage capacitor Cst, and the first pole of the threshold compensation transistor T2. The second node N2 is respectively connected to the first pole of the driving transistor T3, the second pole of the first light-emitting control transistor T5, the second pole of the data writing transistor T4, and the second pole of the third reset transistor T8. The third node N3 is respectively connected to the second pole of the first reset transistor T1, the second pole of the threshold compensation transistor T2, the first pole of the second light-emitting control transistor T6, and the second pole of the driving transistor T3. The fourth node N4 is respectively connected to the second pole of the second light-emitting control transistor T6, the second pole of the second reset transistor T7, and the light-emitting device L.

[0073] It should be noted that in the embodiments of the present disclosure, the first pole of the transistor may be the source or the drain. Correspondingly, the second pole may be the drain or the source. For example, in one example, the first pole of the threshold compensation transistor T2 is the source of the threshold compensation transistor T2, and the second pole of the threshold compensation transistor T2 is the drain of the threshold compensation transistor T2. In another example, the first pole of the driving transistor T3 is the second pole of the driving transistor T3, and the second pole of the driving transistor T3 is the first pole of the driving transistor T3.

[0074] The second electrode of the storage capacitor Cst is electrically connected to the first voltage signal line VDD, and the first electrode of the storage capacitor Cst is connected to the first node N1, that is, the first electrode of the storage capacitor Cst is connected to the gate of the driving transistor T3.

[0075] The first pole of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1 and is configured to receive the first initialization signal. The second pole of the first reset transistor T1 is electrically connected to the second pole of the driving transistor T3. The gate of the first reset transistor T1 is electrically connected to the first reset control signal line Reset_P(n) and is configured to receive the first reset control signal.

[0076] The first pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3. The second pole of the threshold compensation transistor T2 is electrically connected to the second pole of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the first scan signal line Gate_N(n) and is configured to receive the compensation control signal.

[0077] The gate of the driving transistor T3 is connected to the first electrode of the storage capacitor Cst. The first pole of the driving transistor T3 is connected to the second node N2. The second pole of the driving transistor T3 is connected to the third node N3. The driving transistor T3 determines the magnitude of the driving current flowing between the first voltage signal line VDD and the second voltage signal line VSS according to the potential difference between its gate and first pole.

[0078] The second pole of the data writing transistor T4 is electrically connected to the first pole of the driving transistor T3. The first pole of the data writing transistor T4 is electrically connected to the data signal line Data and is configured to receive the data signal. The gate of the data writing transistor T4 is electrically connected to the second scan signal line Gate_P(n) and is configured to receive the scan signal.

[0079] The first pole of the first light emission control transistor T5 is electrically connected to the first voltage signal line VDD. The second pole of the first light emission control transistor T5 is electrically connected to the first pole of the driving transistor T3. The gate of the first light emission control transistor T5 is electrically connected to the light emission control signal line EM and is configured to receive the light emission control signal.

[0080] The first pole of the second light emission control transistor T6 is electrically connected to the second pole of the driving transistor T3. The second pole of the second light emission control transistor T6 is electrically connected to the first electrode of the light emitting device L. The gate of the second light emission control transistor T6 is electrically connected to the light emission control signal line EM and is configured to receive the light emission control signal.

[0081] The first pole of the second reset transistor T7 is configured to be electrically connected to the second initialization signal line Vinit2 and is configured to receive a second initialization signal. The second pole of the second reset transistor T7 is electrically connected to the first electrode of the light-emitting device L. The gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Reset_H(n) to receive a reset control signal.

[0082] The first pole of the third reset transistor T8 is electrically connected to the third initialization signal line Vinit3 and is configured to receive a third initialization signal. The second pole of the third reset transistor T8 is electrically connected to the first pole of the driving transistor T3. The gate of the third reset transistor T8 is electrically connected to the second reset control signal line Reset_H(n) and is configured to receive a second reset control signal.

[0083] The second electrode of the light-emitting device L is electrically connected to the second voltage signal line VSS.

[0084] Wherein, the first voltage signal transmitted by the first voltage signal line VDD is, for example, a high-voltage DC signal, and the second voltage signal transmitted by the second voltage signal line VSS is, for example, a low-voltage DC signal.

[0085] Specifically, Figure 1 The driving process of the pixel circuit for driving the light-emitting device L to emit light may include a first reset stage t1, a data refresh and compensation stage t2, a second reset stage t3, and a light-emitting stage t4.

[0086] Wherein, in the first reset stage t1, the threshold compensation transistor T2 is turned on under the control of the first scan signal transmitted by the first scan signal line Gate_N(n), and the first reset transistor T1 is turned on under the control of the first reset control signal transmitted by the first reset control signal line Reset_P(n), so that the first initialization signal transmitted by the first initialization signal line Vinit1 is written into the first node N1, and then the first node N1 is reset.

[0087] At this time, the driving transistor T3 is turned on, the writing transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all in an off state, and the light-emitting device L does not emit light.

[0088] During the data refresh and compensation stage t2, the first reset transistor T1 is turned off under the control of the first reset control signal transmitted on the first reset control signal line Reset_P(n). The threshold compensation transistor T2 remains conducting. The write transistor T4 is turned on under the control of the second scan signal transmitted on the second scan signal line Gate_P(n). The driving transistor T3 maintains the conducting state during the first reset stage t1. Therefore, the data signal transmitted on the data signal line Data can sequentially pass through the write transistor T4, the driving transistor T3, and the threshold compensation transistor T2 and be transmitted to the first node N1, causing the voltage of the first node N1 to change until the voltage of the first node N1 reaches the sum of the threshold voltage of the driving transistor T3 and the voltage of the data signal line Data, causing the driving transistor T3 to turn off. During the data refresh and compensation stage t2, the threshold voltage of the driving transistor T3 can be written into the first node N1 to compensate for the threshold voltage drift of the driving transistor T3, avoid changes in the driving signal generated by the driving transistor T3, and avoid the impact on the light emission intensity of the light-emitting device L. During this stage, the first light-emission control transistor T5 and the second light-emission control transistor T6 are in the off state under the control of the light-emission control signal transmitted on the light-emission control signal line EM.

[0089] During the second reset stage t3, the threshold compensation transistor T2 is turned off under the control of the first scan signal transmitted on the first scan signal line Gate_N(n). The write transistor T4 is turned off under the control of the second scan signal transmitted on the second scan signal line Gate_P(n). The second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal transmitted on the second reset control signal line Reset_H(n), thereby writing the third initialization signal transmitted on the third initialization signal line Vinit3 into the second node N2 and writing the second initialization signal transmitted on the second initialization signal line Vinit2 into the fourth node N4, that is, writing into the first electrode (for example, specifically the anode) of the light-emitting device L, thereby resetting the second node N2 and the anode of the light-emitting device L.

[0090] During the light-emission stage t4, the second reset transistor T7 and the third reset transistor T8 are turned off under the control of the second reset control signal transmitted on the second reset control signal line Reset_H(n). The first light-emission control transistor T5 and the second light-emission control transistor T6 are turned on under the control of the light-emission control signal transmitted on the light-emission control signal line EM, thereby writing the first voltage signal transmitted on the first voltage signal line VDD into the first pole region of the driving transistor T3 and writing the anode voltage of the light-emitting device L into the second pole region of the driving transistor T3, thereby causing the driving transistor T3 to turn on, thereby forming a path between the first voltage signal line VDD and the light-emitting device L, causing the light-emitting device L to emit light.

[0091] In some display substrates, in order to meet the growing demand for high PPI (pixels per inch, also known as pixel density), the design of the pixel circuit planar structure is limited by the pixel space size, resulting in some poor technical problems in the related display substrates. Specifically, Figure 2A is a schematic diagram of the planar structure of multiple pixel circuits in a display substrate in some embodiments. Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、 Figure 2F and Figure 2G are respectively Figure 2A schematic diagrams of the planar structure of each single-layer film layer in. Figure 2H is a schematic cross-sectional structure diagram along the cutting line AA' in Figure 2A 。

[0092] Among them, Figure 2A only shows the schematic diagram of the planar structure of some of the film layers, specifically including a first semiconductor layer Poly1, a first gate metal layer Gate1, a second gate metal layer Gate2, a third gate metal layer Gate3, and a first source-drain metal layer SD1 stacked in sequence along the direction away from the substrate. More specifically, Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E and Figure 2F are respectively schematic diagrams of the planar structure of the first semiconductor layer Poly1, the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer Gate3, and the first source-drain metal layer SD1.

[0093] In addition, those skilled in the art can understand that Figure 2A in the shown embodiments, there are also a second semiconductor layer Poly2, a second source-drain metal layer SD2, etc. that are not shown. For example, as Figure 2G shown, the first pole and the second pole of the threshold compensation transistor T2 are located in the second semiconductor layer Poly2. For example, the data signal line Data and the first voltage signal line VDD may be located in the second source-drain metal layer SD2 (not shown in the embodiments of the present disclosure).

[0094] As Figure 2A shown, in combination with Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E and Figure 2FAs can be seen, the light-emitting control signal line EM, the second scan signal line Gate_P(n), the first reset control signal line Reset_P(n), the second reset control signal line Reset_H(n), and the first electrode plate C1 of the storage capacitor Cst are located in the first gate metal layer Gate1. The first gate metal layer Gate1 further includes the gate of the first reset transistor T1, the gate of the data writing transistor T4, the gate of the first light-emitting control transistor T5, the gate of the second light-emitting control transistor T6, the gate of the second reset transistor T7, and the gate of the third reset transistor T8. Among them, the gate of the first reset transistor T1 is connected to the first reset control signal line Reset_P(n) to form an integral structure, the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control signal line EM to form an integral structure, and the gates of the second reset transistor T7 and the third reset transistor T8 are connected to the second reset control signal line Reset_H(n) to form an integral structure.

[0095] The first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3 are located in the third gate metal layer Gate3. The third gate metal layer further includes the gate of the threshold compensation transistor T2.

[0096] The first scan signal line Gate_N(n) and the second electrode plate C2 of the storage capacitor Cst are located in the second gate metal layer Gate2.

[0097] Among them, the light-emitting control signal line EM, the second scan signal line Gate_P(n), the first reset control signal line Reset_P(n), the second reset control signal line Reset_H(n), the first initialization signal line Vinit1, the second initialization signal line Vinit2, the third initialization signal line Vinit3, and the first scan signal line Gate_N(n) all extend in the first direction. Among them, the first electrode plate C1 of the storage capacitor Cst is also the gate of the driving transistor T3.

[0098] As Figure 2B shown, the active layers of the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8 are located in the first semiconductor layer Poly1. In addition, the two sides of the active layer of each transistor are made conductive, so that the first pole and the second pole of each transistor can be formed. That is, the first pole and the second pole of each transistor can be formed as an integral structure with the active layer.

[0099] Obviously, in Figure 2AIn the illustrated embodiment, the orthographic projection of the light-emitting control signal line EM on the substrate and the orthographic projection of the third initialization signal line Vinit3 on the substrate mostly overlap. Therefore, in the display area of ​​the display substrate, the parasitic capacitance between the light-emitting control signal line EM and the third initialization signal line Vinit3 is relatively large, which will cause the display substrate to consume relatively large power when a driving signal with a frequency of 1 Hz is used.

[0100] like Figure 2F As shown, the first source-drain metal layer SD1 includes a plurality of transition portions, which are used to realize electrical connection between each gate metal layer, the first semiconductor layer Poly1, etc. Specifically, the first source-drain metal layer SD1 includes a first transition portion 10, a third transition portion 30, a fourth transition portion 40, a fifth transition portion 70, a sixth transition portion 80, a seventh transition portion 90, an eighth transition portion 100, a ninth transition portion 110, and a tenth transition portion 120.

[0101] Among them, Figure 2A and Figure 2H As shown, the orthographic projection of the first adapter 10 on the substrate overlaps with the first electrode of the third reset transistor T8 and the third initialization signal line Vinit3, and is electrically connected to the first electrode of the third reset transistor T8 and the third initialization signal line Vinit3 through vias, thereby realizing the electrical connection between the first electrode of the third reset transistor T8 and the third initialization signal line Vinit3. It can be understood that in the embodiment of the present disclosure, the via refers to a via that penetrates the insulating layer between two metal layers. For example, the display substrate also includes an interlayer dielectric layer between the third gate metal layer Gate3 and the first source and drain metal layer SD1. When realizing the electrical connection between the first adapter 10 located in the first source and drain metal layer SD1 and the third initialization signal line Vinit3 located in the third gate metal layer Gate3, the via refers to a via that penetrates the interlayer dielectric layer, that is, the first adapter 10 is electrically connected to the third initialization signal line Vinit3 through the via that penetrates the interlayer dielectric layer.

[0102] For example, Figure 2H As shown, the display substrate also includes a first gate insulating layer GI1 located between the first semiconductor layer Poly1 and the first gate metal layer Gate1, a second gate insulating layer GI2 located between the first gate metal layer Gate1 and the second gate metal layer Gate2, a third gate insulating layer GI3 located between the second gate metal layer Gate2 and the third metal layer, and an interlayer dielectric layer ILD located between the third gate metal layer Gate3 and the first source and drain metal layer SD1, and the first transfer portion 10 is electrically connected to the first electrode of the third reset transistor through a via hole penetrating the first gate insulating layer GI1, the second gate insulating layer GI2, the third gate metal layer Gate3 and the interlayer dielectric layer ILD.

[0103] Further, the multiple pixel circuits include multiple rows of pixel circuit rows. Each pixel circuit row includes multiple pixel circuit groups arranged along a first direction. Each pixel circuit group includes two pixel circuits arranged along the first direction. The first poles of adjacent two third reset transistors T8 in different pixel circuit groups are connected to form a first integrated structure. Moreover, the first transfer portion 10 corresponding to the first poles of these two third reset transistors T8 is connected to form a second integrated structure. The second integrated structure is electrically connected to the first integrated structure through a via hole penetrating through the first gate insulating layer GI1, the second gate insulating layer GI2, the third gate metal layer Gate3, and the interlayer dielectric layer ILD.

[0104] The positive projection of the third transfer portion 30 on the substrate SUB overlaps with the positive projection on the substrate SUB of either the first pole of the second reset transistor T7 or the second initialization signal line Vinit2. And the third transfer portion 30 is electrically connected to the first pole of the second reset transistor T7 and the second initialization signal line Vinit2 respectively through via holes. Specifically, the third transfer portion 30 is electrically connected to the second initialization signal line Vinit2 through a via hole penetrating through the interlayer dielectric layer ILD. The third transfer portion 30 is electrically connected to the first pole of the second reset transistor T7 through a via hole penetrating through the first gate insulating layer GI1, the second gate insulating layer GI2, the third gate insulating layer GI3, and the interlayer dielectric layer ILD.

[0105] The positive projection of the fourth transfer portion 40 on the substrate SUB overlaps with the positive projection on the substrate SUB of either the first pole of the first reset transistor T1 or the first initialization signal line Vinit1. And the fourth transfer portion 40 is electrically connected to the first pole of the first reset transistor T1 and the first initialization signal line Vinit1 respectively through via holes. Specifically, the fourth transfer portion 40 is electrically connected to the first initialization signal line Vinit1 through a via hole penetrating through the interlayer dielectric layer ILD. The fourth transfer portion 40 is electrically connected to the first pole of the first reset transistor T1 through a via hole penetrating through the first gate insulating layer GI1, the second gate insulating layer GI2, the third gate metal layer Gate3, and the interlayer dielectric layer ILD.

[0106] The orthographic projection of the fifth transfer portion 70 on the substrate SUB overlaps with the orthographic projection of any one of the first pole of the writing transistor T4 and the data signal line Data on the substrate SUB, and the fifth transfer portion 70 is electrically connected to the first pole of the writing transistor T4 and the data signal line Data through vias respectively. For example, the fifth transfer portion 70 is electrically connected to the first pole of the writing transistor T4 through a via penetrating through the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1. In one example, the data signal line Data is located in the second source / drain metal layer, and the display substrate further includes a passivation layer located between the first source / drain metal layer SD1 and the second source / drain metal layer, then the data signal line Data is electrically connected to the fifth connection portion 70 through a via penetrating through the passivation layer.

[0107] The orthographic projection of the sixth transfer portion 80 on the substrate SUB overlaps with the orthographic projection of any one of the first pole of the first light-emitting control transistor T5, the second electrode plate C2 of the storage capacitor Cst, and the first voltage signal line VDD on the substrate SUB, and the sixth transfer portion 80 is electrically connected to the first pole of the first light-emitting control transistor T5, the second electrode plate C2 of the storage capacitor Cst, and the first voltage signal line VDD through vias respectively. For example, the sixth transfer portion 80 is electrically connected to the first pole of the first light-emitting control transistor T5 (the first pole of the writing transistor T4) through a via penetrating through the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1. The sixth transfer portion 80 is electrically connected to the second electrode plate C2 of the storage capacitor Cst through a via penetrating through the interlayer dielectric layer ILD and the third gate insulating layer GI3. In one example, the first voltage signal line VDD is located in the second source / drain metal layer, and the first voltage signal line VDD is electrically connected to the sixth transfer portion 80 through a via penetrating through the passivation layer.

[0108] The orthographic projection of the seventh transfer portion 90 on the substrate SUB overlaps with the orthographic projection of any one of the second pole of the first light-emitting control transistor T5 and the second pole of the third reset transistor T8 on the substrate SUB, and the seventh transfer portion 90 is electrically connected to the second pole of the first light-emitting control transistor T5 and the second pole of the third reset transistor T8 through vias respectively. For example, the seventh transfer portion 90 is electrically connected to the second pole of the first light-emitting control transistor T5 through a via penetrating through the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1. The seventh transfer portion 90 is electrically connected to the second pole of the third reset transistor T8 through a via penetrating through the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1. Among them, as Figure 2B shown, the second pole of the data writing transistor T4, the first pole of the driving transistor T3, and the second pole of the first light-emitting control transistor T5 are connected as an integrated structure.

[0109] The orthographic projection of the eighth transfer portion 100 on the substrate SUB overlaps with the orthographic projection of any one of the second pole of the first light-emitting control transistor T5, the second pole of the driving transistor T3, and the first pole of the second light-emitting control transistor T6 on the substrate SUB, and the eighth transfer portion 100 is electrically connected to the second pole of the first light-emitting control transistor T5, the second pole of the driving transistor T3, and the first pole of the second light-emitting control transistor T6 through vias respectively. For example, the eighth transfer portion 100 is electrically connected to the second pole of the first light-emitting control transistor T5, the second pole of the driving transistor T3, and the first pole of the second light-emitting control transistor T6 through different vias penetrating through the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1 respectively.

[0110] The orthographic projection of the ninth transfer portion 110 on the substrate SUB overlaps with the orthographic projection of any one of the first pole of the threshold compensation transistor T2 and the first electrode plate C1 of the storage capacitor Cst (the gate of the driving transistor T3) on the substrate SUB, and the ninth transfer portion 110 is electrically connected to the gate of the driving transistor T3, the first pole of the threshold compensation transistor T2, and the first electrode plate C1 of the storage capacitor C through vias respectively. For example, the ninth transfer portion 110 is electrically connected to the first electrode plate C1 of the storage capacitor C (the gate of the driving transistor T3) through a via penetrating through the interlayer dielectric layer ILD, the third gate insulating layer GI3, and the second gate insulating layer GI2. In one example, the second semiconductor layer is located between the second gate metal layer Gate2 and the third gate metal layer Gate3, then the third gate insulating layer GI3 includes a first sub-gate insulating layer located between the second semiconductor layer and the second gate metal layer Gate2 and a second sub-gate insulating layer located between the second semiconductor layer and the third gate metal layer Gate3, and the ninth transfer portion 110 is electrically connected to the first pole of the threshold compensation transistor T2 through a via penetrating through the interlayer dielectric layer ILD and the second sub-gate insulating layer.

[0111] The orthographic projection of the tenth transfer portion 120 on the substrate SUB overlaps with the orthographic projection of any one of the first pole of the second light-emitting control transistor T6 and the second pole of the second reset transistor T7 on the substrate SUB, and the tenth transfer portion 120 is electrically connected to the first pole of the second light-emitting control transistor T6 and the second pole of the second reset transistor T7 through vias respectively. For example, the tenth transfer portion 120 is connected to the first pole of the second light-emitting control transistor T6 and the second pole of the second reset transistor T7 through vias penetrating through the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1 respectively.

[0112] In addition, the first source-drain metal layer SD1 further includes at least one first auxiliary signal line Vinit1' extending in the second direction, at least one second auxiliary signal line Vinit2' extending in the second direction, and at least one third auxiliary signal line Vinit3' extending in the second direction.

[0113] Among them, part of the fourth transfer portion 40 is electrically connected to the first auxiliary signal line Vinit1'. For example, the first source-drain metal layer SD1 further includes a second connection portion 2. The fourth transfer portion 40 is electrically connected to the first auxiliary signal line Vinit1' through the second connection portion 2.

[0114] Meanwhile, the orthographic projection of this part of the fourth transfer portion 40 on the substrate SUB overlaps with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB and is electrically connected through a via. For example, the fourth transfer portion 40 is electrically connected to the first initialization signal line Vinit1 through a via penetrating the interlayer dielectric layer ILD. Obviously, the first auxiliary signal line Vinit1' and the first initialization signal line Vinit1 are electrically connected through part of the fourth transfer portion 40.

[0115] The orthographic projection of the second auxiliary signal line Vinit2' on the substrate SUB overlaps with the orthographic projection of the second initialization signal line Vinit2 on the substrate SUB, and the second auxiliary signal line Vinit2' is electrically connected to the second initialization signal line Vinit2 through a via. For example, the second auxiliary signal line Vinit2' is electrically connected to the second initialization signal line Vinit2 through a via penetrating the interlayer dielectric layer ILD. Specifically, the specific position of this via is located at Figure 2E and Figure 2F the corresponding position of the middle wireframe a.

[0116] The orthographic projection of the third auxiliary signal line Vinit3' on the substrate SUB overlaps with the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB, and the third auxiliary signal line Vinit3' is electrically connected to the third initialization signal line Vinit3 through a via. For example, the third auxiliary signal line Vinit3' is electrically connected to the third initialization signal line Vinit3 through a via penetrating the interlayer dielectric layer ILD.

[0117] In some embodiments, the electrical connection between the third auxiliary signal line Vinit3' and the third initialization signal line Vinit3 can be similar to the electrical connection between the second auxiliary signal line Vinit2' and the second initialization signal line Vinit2, by providing another connecting portion to be electrically connected to a portion of the first transfer portion 10. In other embodiments, the electrical connection between the third auxiliary signal line Vinit3' and the third initialization signal line Vinit3 can be similar to the electrical connection between the first auxiliary signal line Vinit1' and the first initialization signal line Vinit1, and the first auxiliary signal line Vinit1' is directly electrically connected to the first initialization signal line Vinit1 through a via penetrating the interlayer dielectric layer ILD.

[0118] Obviously, the first initialization signal line Vinit1 extending along the first direction and the first auxiliary signal line Vinit1' extending along the second direction cross to form a "grid" signal transmission line, the second initialization signal line Vinit2 extending along the first direction and the second auxiliary signal line Vinit2' extending along the second direction cross to form a "grid" signal transmission line, and the third initialization signal line Vinit3 extending along the first direction and the third auxiliary signal line Vinit3' extending along the second direction cross to form a "grid" signal transmission line.

[0119] according to Figure 2A , Figure 2E and Figure 2F It can be seen from the structural schematic diagram that the positive projection of the first adapter 10 on the substrate SUB overlaps with the first initialization signal line Vinit1, and the signal voltage difference between the third initialization signal transmitted by the first adapter 10 and the first initialization signal line Vinit1 is large. For example, in one example, the third initialization signal transmitted in the first adapter 10 is a positive potential, usually 4.5V to 7V, and the first initialization signal transmitted in the first initialization signal line Vinit1 is a negative potential, usually -2.5V to -5V. As the product is used continuously, the large voltage difference between the first initialization signal line Vinit1 and the signal transmitted by the first adapter 10 can easily cause problems such as burning of the display substrate.

[0120] In order to at least alleviate or solve one of the above-mentioned technical problems, the present disclosure provides a display substrate and a display panel.

[0121] Figure 3A It is a schematic diagram of the planar structure of multiple pixel circuits in a display substrate in some embodiments of the present disclosure.

[0122] in, Figure 3AA schematic plan view showing only some of the film layers is presented, specifically including a first semiconductor layer Poly1, a first gate metal layer Gate1, a second gate metal layer Gate2, a third gate metal layer Gate3, and a first source / drain metal layer SD1, which are stacked in sequence along the direction away from the substrate SUB. Figure 3B and Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F and Figure 3G are respectively Figure 3A schematic plan views of each single-layer film layer in Figure 3B 、 Figure 3C 、 Figure 3D and Figure 3E are respectively schematic plan views of the first semiconductor layer Poly1, the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer Gate3, and the first source / drain metal layer SD1 in sequence. Figure 3F and Figure 3G are schematic plan views of the first source / drain metal layer SD1. Figure 3H is a schematic cross-sectional view along the Figure 3A cutting line BB’ in the display substrate shown. Figure 3I is Figure 3A a partial cross-sectional view of the display substrate shown.

[0123] As shown in Figure 3A 、 Figure 3C 、 Figure 3D and Figure 3H in some embodiments, for a display substrate of the present disclosure, the positive projection of the third initialization signal line Vinit3 on the substrate SUB does not overlap with the positive projection of the emission control signal line EM on the substrate SUB.

[0124] In the embodiments of the present disclosure, the non-overlap of the positive projection of the third initialization signal line Vinit3 on the substrate SUB and the positive projection of the emission control signal line EM on the substrate SUB can prevent the total capacitance of the emission control signal line EM in the display area from being too large, thereby reducing the power consumption of the display substrate.

[0125] As shown in Figure 3A 、 Figure 3D and Figure 3E in some embodiments, at least two of the first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3 are located in different layers.

[0126] Compared with Figure 2AIn the display substrate, the first initialization signal line Vinit1, the second initialization signal line Vinit2 and the third initialization signal line Vinit3 are all arranged on the third gate metal layer Gate3. Due to the connection relationship between the transistors, the spatial distribution of the third gate metal layer Gate3 is limited, so that the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB overlaps with the orthographic projection of the light-emitting control signal line EM on the substrate SUB for the most part. In the embodiment of the present disclosure, at least two of the first initialization signal line Vinit1, the second initialization signal line Vinit2 and the third initialization signal line Vinit3 are located in different layers. For example, the first initialization signal line Vinit1 and the second initialization signal line Vinit2 can be both located in the third gate metal layer Gate3, and the third initialization signal line Vinit3 is located in the first gate metal layer Gate1 or the second gate metal layer Gate2. For another example, the first initialization signal line Vinit1 and the third initialization signal line Vinit3 are both located in the third gate metal layer Gate3, and the second initialization signal line Vinit2 is located in the first gate metal layer Gate1 or the second gate metal layer Gate2.

[0127] That is to say, the embodiment of the present disclosure arranges the first initialization signal line Vinit1, the second initialization signal line Vinit2 and the third initialization signal line Vinit3 in at least two layers, which can avoid the overlap of the positive projection of the third initialization signal line Vinit3 on the substrate SUB and the positive projection of the light emitting control signal line EM on the substrate SUB, thereby avoiding excessive power consumption. At the same time, it can also avoid the problem of burning caused by the overlap of the positive projection of the first adapter 10 on the substrate SUB and the positive projection of the first initialization signal line Vinit1 on the substrate SUB in order to realize the connection of the third reset transistor.

[0128] like Figure 3A , Figure 3D , Figure 3E and Figure 3H As shown, the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB and the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB do not overlap.

[0129] In the disclosed embodiment, since the first initialization signal line Vinit1 and the third initialization signal line Vinit3 can be located in different layers, further making the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB and the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB non-overlapping can avoid burning of the display area caused by excessive voltage.

[0130] like Figure 3A , Figure 3D , Figure 3E andFigure 3H As shown, specifically, the third initialization signal line Vinit3 is located in the second gate metal layer Gate2. The first initialization signal line Vinit1 and the second initialization signal line Vinit2 are located in the third gate metal layer Gate3.

[0131] Considering the high PPI demand, compared to Figure 2A In order to at least not increase the planar space occupied by the pixel circuit, the pixel circuit shown in the embodiment of the present disclosure sets the third initialization signal line Vinit3 on the second gate metal layer Gate2, and sets the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the third gate metal layer Gate3, so that the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB and the orthographic projection of the light-emitting control signal line EM on the substrate SUB do not overlap, and at the same time, the orthographic projection of the first adapter 10 on the substrate SUB and the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB do not overlap.

[0132] Specifically, Figure 3A , Figure 3D , Figure 3E and Figure 3H As shown, the positive projection of the third initialization signal line Vinit3 on the substrate SUB is located between the positive projection of the first initialization signal line Vinit1 on the substrate SUB and the positive projection of the second initialization signal line Vinit2 on the substrate SUB. Figure 3A and Figure 3F , Figure 3G As shown, in the embodiment of the present disclosure, the orthographic projection of the first adapter 10 on the substrate SUB overlaps with the orthographic projection of any one of the third initialization signal line Vinit3 and the first electrode of the third reset transistor on the substrate SUB, and the first adapter 10 is electrically connected to the third initialization signal line Vinit3 and the first electrode of the third reset transistor through vias, respectively, and the orthographic projection of the first adapter 10 on the substrate SUB is located between the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB and the orthographic projection of the second initialization signal line Vinit2 on the substrate SUB, and has no overlap with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB.

[0133] Compared to Figure 2AIn the display substrate, the orthographic projection of the first transfer portion 10 on the substrate SUB overlaps with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB. In the embodiments of the present disclosure, by moving the film layer where the third initialization signal line Vinit3 is located and setting the specific position of the third initialization signal line Vinit3 in this film layer, it is possible to ensure that the orthographic projection of the light-emitting control signal line EM on the substrate SUB and the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB do not overlap, while also achieving that the orthographic projection of the first transfer portion 10 on the substrate SUB and the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB do not overlap.

[0134] As Figure 3G and Figure 3H shown, the first source-drain metal layer SD1 includes at least one third auxiliary signal line Vinit3' extending along the second direction and at least one second transfer portion 20, where the second direction intersects the first direction. For example, the second direction may be perpendicular to the first direction.

[0135] Any one of the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB and the orthographic projection of the third auxiliary signal line Vinit3' on the substrate SUB overlaps with the orthographic projection of the second transfer portion 20 on the substrate SUB. The second transfer portion 20 is electrically connected to the third auxiliary signal line Vinit3'. For example, specifically, as Figure 2H and Figure 2H shown, the first source-drain metal layer SD1 includes at least one third connection portion 3, and the third connection portion 3 is electrically connected to the third auxiliary signal line Vinit3' and the second transfer portion 20 respectively.

[0136] And the second transfer portion 20 is electrically connected to the third initialization signal line Vinit3 through a via. For example, the second transfer portion 20 is electrically connected to the third initialization signal line Vinit3 through a via penetrating the interlayer dielectric layer ILD.

[0137] In the embodiments of the present disclosure, by electrically connecting the third auxiliary signal line Vinit3' and the third initialization signal line Vinit3 through the second transfer portion 20, it is possible to transmit the third initialization signal to the third initialization signal line Vinit3 through the third auxiliary signal line Vinit3' and transmit it to the driving circuit through the third initialization signal line Vinit3. Obviously, the third initialization signal line Vinit3 extending along the first direction and the third auxiliary signal line Vinit3' extending along the second direction make the line for transmitting the third initialization signal form a "grid" shape, which can ensure the uniformity of the third initialization signal in the entire display area, and further ensure the uniformity of the light-emitting effect of the entire display substrate.

[0138] Moreover, the orthographic projection of the second transfer portion 20 on the substrate SUB does not overlap with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB, and / or the orthographic projection of the second transfer portion 20 on the substrate SUB does not overlap with the orthographic projection of the second initialization signal line Vinit2 on the substrate SUB.

[0139] In the embodiment of the present disclosure, the specific position of the second transfer portion 20 is set on the first source-drain metal layer SD1 according to the position of the third initialization signal line Vinit3, so as to avoid the orthographic projection of the second transfer portion 20 on the substrate SUB from overlapping with the orthographic projection of at least one of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate SUB, which can prevent the third initialization signal transmitted in the second transfer portion 20 from overlapping with the first initialization signal and the second initialization signal in the display area, thereby avoiding mutual influence between them.

[0140] As Figure 3A 、 Figure 3F 、 Figure 3G and Figure 3H shown, the first source-drain metal layer SD1 further includes at least one first auxiliary signal line Vinit1' extending in the second direction and at least one second auxiliary signal line Vinit2' extending in the second direction. On this basis, the first source-drain metal layer SD1 further includes: at least one first redundant transfer portion 50, and / or at least one second redundant transfer portion 60.

[0141] Among them, the orthographic projection of the first redundant transfer portion 50 on the substrate SUB overlaps with the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB, and the direction from the first redundant transfer portion 50 to the first auxiliary signal line Vinit1' is the same as the direction from the second transfer portion 20 to the third auxiliary signal line Vinit3'. The first redundant transfer portion 50 is electrically insulated from the first auxiliary signal line Vinit1'. The first redundant transfer portion 50 is electrically connected to the third initialization signal line Vinit3 through a via. For example, similar to the second transfer portion 20, the first redundant transfer portion 50 is electrically connected to the third initialization signal line Vinit3 through a via penetrating the interlayer dielectric layer ILD.

[0142] The orthographic projection of the second redundant connection part 60 on the substrate SUB overlaps with the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB, and the direction from the second redundant connection part 60 to the second auxiliary signal line Vinit2' is the same as the direction from the second connection part 20 to the third auxiliary signal line Vinit3'. The second redundant connection part 60 is electrically insulated from the second auxiliary signal line Vinit2'. The second redundant connection part 60 is electrically connected to the third initialization signal line Vinit3 through a via. For example, similarly, the second redundant connection part 60 is electrically connected to the third initialization signal line Vinit3 through a via penetrating the interlayer dielectric layer ILD.

[0143] In the embodiment of the present disclosure, by respectively arranging the first redundant connection part 50 and the second redundant connection part 60, which are similar in position to the second connection part 20, beside the first auxiliary signal line Vinit1' and the second auxiliary signal line Vinit2', it is possible to further ensure the avoidance of related defective problems such as vertical stripes.

[0144] As Figure 3G and Figure 3H shown, the distance between the edge of the second connection part 20 far from the third auxiliary signal line Vinit3' and the third auxiliary signal line Vinit3' is the first distance D1; the distance between the edge of the first redundant connection part 50 far from the first auxiliary signal line Vinit1' and the first auxiliary signal line Vinit1' is the second distance D2; the distance between the edge of the second redundant connection part 60 far from the second auxiliary signal line Vinit2' and the second auxiliary signal line Vinit2' is the third distance D3; wherein, the ratio of either the second distance D2 or the third distance D3 to the first distance D1 is 0.5 to 1.5.

[0145] For example, in one example, the ratio of either the second distance D2 or the third distance D3 to the first distance D1 is 1. That is, in this case, the first distance D1, the second distance D2, and the third distance D3 are all equal.

[0146] It can be understood that the positions of the first redundant connection part 50 relative to the first auxiliary signal line Vinit1', the second redundant connection part 60 relative to the second auxiliary signal line Vinit2', and the second connection part 20 relative to the third auxiliary signal line Vinit3' are the same.

[0147] That is to say, in the embodiment of the present disclosure, the first redundant connection part 50, the second redundant connection part 60, and the second connection part 20 are respectively arranged at the same positions of the first auxiliary signal line Vinit1', the second auxiliary signal line Vinit2', and the third auxiliary signal line Vinit3'. Based on this design, the embodiment of the present disclosure can further ensure the avoidance of related defective problems such as vertical stripes.

[0148] As Figure 3A 、 Figure 3B and Figure 3D shown, the positive projection of the second pole of the second reset transistor on the substrate SUB is located on the side of the positive projection of the third initialization signal line Vinit3 on the substrate SUB that is far from the first initialization signal line Vinit1.

[0149] As Figure 3F and Figure 3G shown, the first source-drain metal layer SD1 includes a third transfer portion 30. Combining Figure 3A it can be known that either the positive projection of the second pole of the second reset transistor on the substrate SUB or the positive projection of the second reset control signal line Reset_H(n) on the substrate SUB overlaps with the positive projection of the third transfer portion 30 on the substrate SUB. The third transfer portion 30 is electrically connected to the second pole of the second reset transistor and the second reset control signal line Reset_H(n) through vias respectively. For example, the third transfer portion 30 is electrically connected to the second pole of the second reset transistor through a via that penetrates the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1. The third transfer portion 30 is electrically connected to the second reset control signal line Reset_H(n) through a via that penetrates the interlayer dielectric layer ILD, the third gate insulating layer GI3, and the second gate insulating layer GI2.

[0150] Among them, the positive projection of the third transfer portion 30 on the substrate SUB also overlaps with the positive projection of the third reset control signal line on the substrate SUB.

[0151] Figure 4A is a schematic plan view showing a plurality of pixel circuits in a display substrate in some other embodiments of the present disclosure. Among them, Figure 4A only the schematic plan view of some of the film layers is shown, specifically including a first semiconductor layer Poly1, a first gate metal layer Gate1, a second gate metal layer Gate2, a third gate metal layer Gate3, and a first source-drain metal layer SD1 stacked in sequence along the direction away from the substrate SUB. Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4F and Figure 4G are respectively Figure 4A the schematic plan views of each single film layer in Figure 4B 、 Figure 4C 、 Figure 4D and Figure 4E are respectively the schematic plan views of the first semiconductor layer Poly1, the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer Gate3, and the first source-drain metal layer SD1 in sequence.Figure 4F and Figure 4G is a schematic diagram of the planar structure of the first source-drain metal layer SD1. Figure 4H is along Figure 4A The cross-sectional structure diagram of the cutting line CC' in the display substrate is shown.

[0152] like Figure 4A , Figure 4D and Figure 4E As shown, in some other embodiments, the second initialization signal line Vinit2 is located in the second gate metal layer Gate2. The first initialization signal line Vinit1 and the third initialization signal line Vinit3 are located in the third gate metal layer Gate3.

[0153] Similarly, considering the high PPI demand, compared to Figure 2A For the pixel circuit shown, in order to at least not increase the planar space occupied by the pixel circuit, the present disclosure provides another possible embodiment, specifically setting the second initialization signal line Vinit2 on the second gate metal layer Gate2, and setting the first initialization signal line Vinit1 and the third initialization signal line Vinit3 on the third gate metal layer Gate3, so that the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB and the orthographic projection of the light-emitting control signal line EM on the substrate SUB do not overlap, and at the same time, the orthographic projection of the first adapter 10 on the substrate SUB and the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB do not overlap.

[0154] like Figure 4A , Figure 4D , Figure 4E and Figure 4H As shown, the orthographic projection of the first reset control signal line Reset_P(n) on the substrate SUB does not overlap with the orthographic projection of the second initialization signal line Vinit2 on the substrate SUB.

[0155] In the disclosed embodiment, the orthographic projection of the first reset control signal line Reset_P(n) on the substrate SUB does not overlap with the orthographic projection of the second initialization signal line Vinit2 on the substrate SUB, which can significantly reduce the total capacitance of the second initialization signal line Vinit2 in the display area and help avoid the three-screen problem.

[0156] Specifically, Figure 4A , Figure 4D and Figure 4EAs shown, the positive projection of the second initialization signal line Vinit2 on the substrate SUB is located between the positive projection of the first initialization signal line Vinit1 on the substrate SUB and the positive projection of the third initialization signal line Vinit3 on the substrate SUB, and the positive projection of the first reset control signal line Reset_P(n) on the substrate SUB is located on the side of the positive projection of the second initialization signal line Vinit2 on the substrate SUB away from the positive projection of the first initialization signal line Vinit1 on the substrate SUB.

[0157] As Figure 4A , Figure 4F , Figure 4G and Figure 4H shown, the positive projection of the first transfer portion 10 on the substrate SUB also overlaps with the positive projection of the second initialization signal line Vinit2 on the substrate SUB, and the positive projection of the first transfer portion 10 on the substrate SUB does not overlap with the positive projection of the first initialization signal line Vinit1 on the substrate SUB.

[0158] Similarly, the embodiment of the present disclosure can also move the film layer where the third initialization signal line Vinit3 is located and set the specific position of the third initialization signal line Vinit3 in this film layer, so as to ensure that the positive projection of the light emission control signal line EM on the substrate SUB and the positive projection of the third initialization signal line Vinit3 on the substrate SUB do not overlap, and at the same time, it can also ensure that the positive projection of the first transfer portion 10 on the substrate SUB and the positive projection of the first initialization signal line Vinit1 on the substrate SUB do not overlap.

[0159] As Figure 4A , Figure 4F and Figure 4G shown, the first source-drain metal layer SD1 includes a third transfer portion 30, and any one of the positive projection of the second initialization signal line Vinit2 on the substrate SUB and the positive projection of the second pole of the second reset transistor on the substrate SUB overlaps with the positive projection of the third transfer portion 30 on the substrate SUB. The third transfer portion 30 is electrically connected to the second initialization signal line Vinit2 and is electrically connected to the second pole of the second reset transistor through a via. The positive projection of the third transfer portion 30 on the substrate SUB does not overlap with the positive projection of the first reset control signal line Reset_P(n) on the substrate SUB.

[0160] As Figure 4F and Figure 4G shown, the first source-drain metal layer SD1 further includes at least one first connection portion 1. Combining Figure 4A shown, it can be seen that the first connection portion 1 is electrically connected to the second auxiliary signal line Vinit2' and the third transfer portion 30 respectively.

[0161] For example, in Figure 4AIn the display substrate shown, a plurality of pixel circuits are arranged in a plurality of columns, and each column of pixel circuits includes a plurality of pixel circuits arranged along the second direction. Among them, an auxiliary signal line can be set for every two columns of pixel circuits, and the auxiliary signal line can be a first auxiliary signal line Vinit1', a first auxiliary signal line Vinit2', and a first auxiliary signal line Vinit3'. Generally, in order to ensure the uniformity of signal transmission, the first auxiliary signal line Vinit1', the first auxiliary signal line Vinit2', and the first auxiliary signal line Vinit3' are alternately arranged in sequence. Therefore, it can be understood that when the auxiliary signal line closest to the third adapter 30 is the second auxiliary signal line Vinit2', the third adapter 30 is electrically connected to the second auxiliary signal line Vinit2' through the first connecting portion 1. When the auxiliary signal line closest to the third adapter 30 is the first auxiliary signal line Vinit1' or the third auxiliary signal line Vinit3', the third adapter 30 is electrically insulated from the first auxiliary signal line Vinit1' or the third auxiliary signal line Vinit3'.

[0162] In the disclosed embodiment, the third adapter 30 is electrically connected to the second signal line Vinit2' through the first connecting portion 1. Since the third adapter 30 is electrically connected to the second initialization signal line Vinit2, the second auxiliary signal line Vinit2' is electrically connected to the second initialization signal line Vinit2. In the disclosed embodiment, the second auxiliary signal line Vinit2' is electrically connected to the second initialization signal line Vinit2, and the second initialization signal can be transmitted to the second initialization signal line Vinit2 through the second auxiliary signal line Vinit2', and transmitted to the pixel circuit through the second initialization signal line Vinit2. Obviously, the second initialization signal line Vinit2 extending in the first direction and the second auxiliary signal line Vinit2' extending in the second direction make the line for transmitting the second initialization signal form a "grid" shape, which can ensure the uniformity of the second initialization signal in the entire display area, and then ensure the uniformity of the luminous effect of the entire display substrate. And this design is conducive to reducing the pixel size, which is convenient for meeting high PPI requirements.

[0163] like Figure 4A and Figure 4G As shown, the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB and the orthographic projection of the third auxiliary signal line Vinit3' on the substrate SUB have a first overlapping area, and the first overlapping area is located at Figure 4GWithin the wireframe b, the third auxiliary signal line Vinit3' is electrically connected to the third initialization signal line Vinit3 through a via, and the orthographic projection of the via on the substrate SUB is located within the first overlapping region. For example, the third auxiliary signal line Vinit3' is electrically connected to the third initialization signal line Vinit3 through a via penetrating the interlayer dielectric layer ILD, and the first overlapping region overlaps with the orthographic projection of the first reset control signal line Reset_P(n) on the substrate SUB.

[0164] Optionally, in the embodiments of the present disclosure, the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB overlaps with the orthographic projection of the first reset control signal line Reset_P(n) on the substrate SUB.

[0165] Since the position of the third initialization signal line Vinit3 has changed, therefore, in the embodiments of the present disclosure, the electrical connection position between the third initialization signal line Vinit3 and the third auxiliary signal line Vinit3' Figure 2A has changed compared to the electrical connection position between the third initialization signal line Vinit3 and the third auxiliary signal line Vinit3' in the illustrated embodiments.

[0166] As Figure 3A and Figure 3B shown, or as Figure 4A and Figure 4B shown, multiple pixel circuits include multiple rows of pixel circuit rows, the pixel circuit rows include multiple pixel circuit groups arranged in a first direction, the pixel circuit groups include two pixel circuits arranged in the first direction, and the first poles of two first reset transistors in the same pixel circuit group are connected to form a third integrated structure.

[0167] The first source-drain metal layer SD1 further includes a fourth transfer portion 40, and the fourth transfer portion 40 is electrically connected to the first initialization signal line Vinit1 and the third integrated structure through vias respectively. For example, the fourth transfer portion 40 is electrically connected to the first initialization signal line Vinit1 through a via penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, and the second gate insulating layer GI2, and the fourth transfer portion 40 is electrically connected to the integrated structure through a via penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0168] In the embodiments of the present disclosure, the first poles of two first reset transistors in the same pixel circuit group are connected into an integral structure, and the fourth transfer portion 40 is respectively electrically connected to the first initialization signal line Vinit1 and the integral structure through vias, which can reduce the planar space occupied by the fourth transfer portion 40, avoid overlapping with other signals such as the first initialization signal and the second reset control signal, and improve the layout flexibility of other signals. It can be understood that on the basis of solving the foregoing technical problems, the present disclosure reduces the pixel size by connecting the two first reset transistors in the same pixel circuit group into an integral structure, designing the fourth transfer portion 40, and the "grid" design of the auxiliary signal line and the initialization signal line, so as to meet the requirements of high PPI.

[0169] As Figure 3A and Figure 3B shown, or as Figure 4A and Figure 4B shown, the shape of the positive projection of the third integral structure on the substrate SUB is an asymmetric figure.

[0170] Obviously, in the embodiments of the present disclosure, the first reset transistor is an asymmetric design, and the integral structure formed by connecting the two first reset transistors in the same pixel circuit group is also an asymmetric design. Based on this design, the embodiments of the present disclosure can ensure that the first initialization signal is connected to each pixel circuit when the pixel space is insufficient.

[0171] As Figure 3A and Figure 3F , Figure 3G shown, or as Figure 4A and Figure 4B shown, the first source-drain metal layer SD1 further includes at least one second connection portion 2, and the second connection portion 2 is respectively electrically connected to the first auxiliary signal line Vinit1' and the fourth transfer portion 40.

[0172] For example, in the display substrate shown in Figure 3A , when the auxiliary signal line closest to the fourth transfer portion 40 is the first auxiliary signal line Vinit2', the fourth transfer portion 40 is electrically connected to the first auxiliary signal line Vinit2' through the second connection portion 2. When the auxiliary signal line closest to the fourth transfer portion 40 is the second auxiliary signal line Vinit1' or the third auxiliary signal line Vinit3', the fourth transfer portion 40 is electrically insulated from the second auxiliary signal line Vinit2' or the third auxiliary signal line Vinit3'.

[0173] In the disclosed embodiment, the fourth adapter 40 is electrically connected to the first auxiliary line through the second connection part 2. Since the fourth adapter 40 is electrically connected to the first initialization signal line Vinit1, the first auxiliary signal line Vinit1' is electrically connected to the first initialization signal line Vinit1. In the disclosed embodiment, the first auxiliary signal line Vinit1' and the first initialization signal line Vinit1 are electrically connected, and the first initialization signal can be transmitted to the first initialization signal line Vinit1 through the first auxiliary signal line Vinit1', and transmitted to the pixel circuit through the first initialization signal line Vinit1. Obviously, the first initialization signal line Vinit1 extending in the first direction and the first auxiliary signal line Vinit1' extending in the second direction make the line transmitting the first initialization signal form a "grid" shape, which can ensure the uniformity of the first initialization signal in the entire display area, and then ensure the uniformity of the luminous effect of the entire display substrate. And this design is conducive to reducing the pixel size, which is convenient for meeting high PPI requirements.

[0174] From the above, we can see that compared with Figure 3A The display substrate shown, Figure 4A The display substrate shown in FIG. 1 no longer needs to set a redundant transfer portion in the first source-drain metal layer SD1 or other layers. Therefore, the display substrate shown in FIG. Figure 4A The design shown can effectively improve the light transmittance of the display substrate.

[0175] like Figure 3A , Figure 3D and Figure 3E As shown, or as Figure 4A , Figure 4D and Figure 4E As shown, the positive projection of the first electrode of the third reset transistor on the substrate SUB is located on the side of the positive projection of the first initialization signal Vinit1 on the substrate SUB away from the light-emitting control signal line, and the positive projection of the third initialization signal line Vinit3 on the substrate SUB is located on the side of the positive projection of the first initialization signal Vinit1 on the substrate SUB away from the light-emitting control signal line.

[0176] Obviously, in the embodiment of the present disclosure, the orthographic projection of the first electrode of the third reset transistor on the substrate SUB and the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB are located on the same side of the orthographic projection of the first initialization signal Vinit1 on the substrate SUB along the second direction. Therefore, when realizing the electrical connection between the first electrode of the third reset transistor and the third initialization signal line Vinit3, the first adapter 10 no longer needs to cross the first initialization signal line Vinit1, that is, the orthographic projection of the first adapter 10 on the substrate SUB does not overlap with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB, thereby avoiding the problem of burning caused by a large voltage difference between the first initialization signal Vinit1 and the third initialization signal Vinit3.

[0177] In addition, if Figure 3A , Figure 3E and Figure 3G As shown, or as Figure 4A , Figure 4E and Figure 4G As shown, the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB overlaps with the first auxiliary signal line Vinit1' on the substrate SUB, and the first auxiliary signal line Vinit1' is electrically connected to the first initialization signal line Vinit1 through a via, for example, the first auxiliary signal line Vinit1' is electrically connected to the first auxiliary signal line Vinit1' through a via penetrating the interlayer dielectric layer ILD. Similarly, the first initialization signal line Vinit1 extending in the first direction and the first auxiliary signal line Vinit1' extending in the second direction make the line transmitting the first initialization signal form a "grid" shape, which can ensure the uniformity of the first initialization signal in the entire display area, and then ensure the uniformity of the luminous effect of the entire display substrate. And this design is conducive to reducing the pixel size, which is convenient for meeting high PPI requirements.

[0178] It is understandable that compared to Figure 2A The display substrate shown, Figure 3A and Figure 4A In the display substrate shown in FIG. 1 , the position of the first initialization signal line Vinit1 is not changed. Figure 2A , Figure 3A and Figure 4A In the display substrate shown, the specific positions where the first auxiliary signal line Vinit1 ′ is electrically connected to the first initialization signal line Vinit1 may be the same.

[0179] like Figure 3A and Figure 3H As shown, and Figure 4A and Figure 4HAny two of the third initialization signal line Vinit3, the second initialization signal line Vinit2, and the first initialization signal line Vinit1 shown do not overlap in the orthographic projection on the substrate SUB. Therefore, the embodiments of the present disclosure can avoid the problem of poor display caused by the overlap of each initialization signal during the driving process.

[0180] The present disclosure also provides a display panel, including a display substrate as in any embodiment of the present disclosure.

[0181] In summary, the display substrate, the display panel, and the display device of the present disclosure can implement a pixel circuit structure design with a new type of initialization signal line (the first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3) routing on the premise of high PPI and small pixel size, which not only improves the product yield but also meets the strong market and customer demands for low-power and high-PPI panels.

[0182] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A display substrate, characterized in that: include: substrate; A plurality of pixel circuit rows extending along a first direction, a plurality of pixel circuit rows arranged along a second direction, the second direction intersecting the first direction, the pixel circuit rows comprising a plurality of pixel circuit groups arranged along the first direction, the pixel circuit group comprising two pixel circuits arranged along the first direction, the pixel circuit comprising: a driving transistor, a first light emission control transistor, a first reset transistor and a third reset transistor, the gate of the first light emission control transistor being connected to a light emission control signal line, the first electrode of the first light emission control transistor being connected to a first voltage signal line; the gate of the third reset transistor being connected to a second reset control signal line, the first electrode of the third reset transistor being connected to a third initialization signal line, the second electrode of the third reset transistor being electrically connected to the first electrode of the driving transistor and the second electrode of the first light emission control transistor, the gate of the first reset transistor being connected to the first reset control signal line, the first electrodes of two first reset transistors in the same pixel circuit group being connected to form an integral structure, the integral structure being connected to a first initialization signal line, the second electrode of the first reset transistor being connected to the second electrode of the driving transistor; Among them, the second reset control signal line and the light-emitting control signal line both extend along the first direction and are arranged in the same layer, the first auxiliary signal line extends along the second direction and is arranged in a different layer from the first initialization signal line, the first initialization signal line is electrically connected to the first auxiliary signal line, the third initialization signal line is located on a side of the layer where the second reset control signal line is located away from the substrate, and extends along the first direction, and the orthographic projection of the third initialization signal line on the substrate does not overlap with the orthographic projection of the light-emitting control signal line on the substrate.

2. The display substrate according to claim 1, characterized in that: The pixel circuit further includes: a second reset transistor, a gate of the second reset transistor is connected to a second reset control signal line, a first electrode of the second reset transistor is connected to the second reset control signal line, a second electrode of the second reset transistor is connected to the light emitting device, and the first initialization signal line and the second initialization signal line both extend along the first direction; At least two of the first initialization signal line, the second initialization signal line and the third initialization signal line are located in different layers.

3. The display substrate according to claim 2, characterized in that: The orthographic projection of the first electrode of the third reset transistor on the substrate is located on a side of the orthographic projection of the first initialization signal line on the substrate away from the light-emitting control signal line, and the orthographic projection of the third initialization signal line on the substrate is located on a side of the orthographic projection of the third initialization signal line on the substrate away from the light-emitting control signal line.

4. The display substrate according to claim 2, characterized in that: At least one of the third initialization signal line and the second initialization signal line is located in a different layer from the first initialization signal line, and an orthographic projection of at least one of the third initialization signal line and the second initialization signal line on the substrate does not overlap with an orthographic projection of the first initialization signal line on the substrate; And / or, an orthographic projection of the first reset control signal line on the substrate has no overlap with an orthographic projection of the second initialization signal line on the substrate.

5. The display substrate according to claim 2, characterized in that: The light emitting control signal line, the first reset control signal line and the second reset control signal line are located in the first gate metal layer; The third initialization signal line is located in the second gate metal layer; The first initialization signal line and the second initialization signal line are located in the third gate metal layer; The first gate metal layer, the second gate metal layer and the third gate metal layer are sequentially arranged in a direction away from the substrate.

6. The display substrate according to claim 5, characterized in that: The orthographic projection of the third initialization signal line on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the second initialization signal line on the substrate; The display substrate also includes a first source-drain metal layer located on a side of the third gate metal layer away from the substrate, the first source-drain metal layer includes a first transfer portion, an orthographic projection of the first transfer portion on the substrate overlaps with an orthographic projection of any one of the third initialization signal line and the first electrode of the third reset transistor on the substrate, and the first transfer portion is electrically connected to the third initialization signal line and the first electrode of the third reset transistor through vias, respectively, and an orthographic projection of the first transfer portion on the substrate is located between an orthographic projection of the first initialization signal line on the substrate and an orthographic projection of the second initialization signal line on the substrate, and has no overlap with an orthographic projection of the first initialization signal line on the substrate.

7. The display substrate according to claim 5, characterized in that: The display substrate further comprises a first source-drain metal layer located on a side of the third gate metal layer away from the substrate, wherein the first source-drain metal layer comprises at least one third auxiliary signal line extending along the second direction and at least one second transfer portion; Any one of the orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the third auxiliary signal line on the substrate overlaps with the orthographic projection of the second transfer portion on the substrate, and the second transfer portion is electrically connected to the third auxiliary signal line and is electrically connected to the third initialization signal line through a via hole; Furthermore, the orthographic projection of the second adapter on the substrate does not overlap with the orthographic projection of the first initialization signal line on the substrate, and / or the orthographic projection of the second adapter on the substrate does not overlap with the orthographic projection of the second initialization signal line on the substrate.

8. The display substrate according to claim 7, characterized in that: The first source-drain metal layer further includes at least one first auxiliary signal line extending along the second direction and at least one second auxiliary signal line extending along the second direction; The first source-drain metal layer further includes: at least one first redundant adapter, wherein an orthographic projection of the first redundant adapter on the substrate overlaps with an orthographic projection of the third initialization signal line on the substrate, and a direction from the first redundant adapter to the first auxiliary signal line is the same as a direction from the second adapter to the third auxiliary signal line, the first redundant adapter is electrically insulated from the first auxiliary signal line, and the first redundant adapter is electrically connected to the third initialization signal line through a via; And / or, at least one second redundant adapter, the orthographic projection of the second redundant adapter on the substrate overlaps with the orthographic projection of the third initialization signal line on the substrate, and the direction from the second redundant adapter to the second auxiliary signal line is the same as the direction from the second adapter to the third auxiliary signal line, the second redundant adapter is electrically insulated from the second auxiliary signal line, and the second redundant adapter is electrically connected to the third initialization signal line through a via.

9. The display substrate according to claim 8, characterized in that: The distance between the edge of the second transition portion away from the third auxiliary signal line and the third auxiliary signal line is a first distance; The first source-drain metal layer includes at least one first redundant transition portion and at least one second redundant transition portion; The distance between the edge of the first redundant transition portion away from the first auxiliary signal line and the first auxiliary signal line is a second distance; The distance between the edge of the second redundant transition portion away from the second auxiliary signal line and the second auxiliary signal line is a third distance; A ratio of any one of the second distance and the third distance to the first distance is 0.5 to 1.

5.

10. The display substrate according to claim 5, characterized in that: The positive projection of the second electrode of the second reset transistor on the substrate is located on a side of the positive projection of the third initialization signal line on the substrate away from the first initialization signal line; The display substrate also includes a first source-drain metal layer located on a side of the third gate metal layer away from the substrate, the first source-drain metal layer includes a third adapter, any one of the orthographic projection of the second electrode of the second reset transistor on the substrate and the orthographic projection of the second reset control signal line on the substrate overlaps with the orthographic projection of the third adapter on the substrate, the third adapter is electrically connected to the second electrode of the second reset transistor and the second reset control signal line through vias, respectively, and the orthographic projection of the third adapter on the substrate also overlaps with the orthographic projection of the third reset control signal line on the substrate.

11. The display substrate according to claim 4, characterized in that: The light emitting control signal line, the first reset control signal line and the second reset control signal line are located in the first gate metal layer; The second initialization signal line is located in the second gate metal layer; The first initialization signal line and the third initialization signal line are located in the third gate metal layer; The first gate metal layer, the second gate metal layer and the third gate metal layer are sequentially arranged in a direction away from the substrate.

12. The display substrate according to claim 11, characterized in that: The orthographic projection of the second initialization signal line on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the third initialization signal line on the substrate, and the orthographic projection of the first reset control signal line on the substrate is located on a side of the orthographic projection of the second initialization signal line on the substrate away from the orthographic projection of the first initialization signal line on the substrate.

13. The display substrate according to claim 12, characterized in that: The display substrate also includes a first source-drain metal layer located on a side of the third gate metal layer away from the substrate, the first source-drain metal layer includes a first transfer portion, any one of the orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the first electrode of the third reset transistor on the substrate overlaps with the orthographic projection of the first transfer portion on the substrate, and the first transfer portion is electrically connected to the third initialization signal line and the first electrode of the third reset transistor through vias, respectively, the orthographic projection of the first transfer portion on the substrate also overlaps with the orthographic projection of the second initialization signal line on the substrate, and the orthographic projection of the first transfer portion on the substrate does not overlap with the orthographic projection of the first initialization signal line on the substrate.

14. The display substrate according to claim 12, characterized in that: The display substrate also includes a first source-drain metal layer located on a side of the third gate metal layer away from the substrate, the first source-drain metal layer includes a third adapter, any one of an orthographic projection of the second initialization signal line on the substrate and an orthographic projection of the second electrode of the second reset transistor on the substrate overlaps with the orthographic projection of the third adapter on the substrate, the third adapter is electrically connected to the second initialization signal line and the second electrode of the second reset transistor through vias, respectively, and the orthographic projection of the third adapter on the substrate does not overlap with the orthographic projection of the first reset control signal line on the substrate.

15. The display substrate according to claim 14, characterized in that: The first source-drain metal layer further includes at least one second auxiliary signal line extending along the second direction and at least one first connecting portion, and the first connecting portion is electrically connected to the second auxiliary signal line and the third transfer portion respectively.

16. The display substrate according to claim 13, characterized in that: The display substrate further comprises a first source-drain metal layer located on a side of the third gate metal layer away from the substrate, wherein the first source-drain metal layer comprises at least one third auxiliary signal line extending along the second direction; The orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the third auxiliary signal line on the substrate have a first overlapping area, the third auxiliary signal line is electrically connected to the third initialization signal line through a via, the orthographic projection of the via on the substrate is within the range of the orthographic projection of the first overlapping area on the substrate, and the first overlapping area overlaps with the orthographic projection of the first reset control signal line on the substrate.

17. The display substrate according to any one of claims 2 to 16, characterized in that: The first electrode of the first reset transistor is located in a first semiconductor layer, and the first semiconductor layer is located between the first gate metal layer and the substrate; The display substrate further includes a first source-drain metal layer located on a side of the third gate metal layer away from the substrate. The first source-drain metal layer further includes a fourth transfer portion electrically connected to the first initialization signal line and the integrated structure through vias.

18. The display substrate according to claim 17, characterized in that: The shape of the orthographic projection of the integrated structure on the substrate is an asymmetric shape.

19. The display substrate according to claim 17, characterized in that: The first auxiliary signal line is located in a first source-drain metal layer, and the first source-drain metal layer further includes at least one second connection portion, and the second connection portion is electrically connected to the first auxiliary signal line and the fourth transfer portion respectively.

20. A display panel, characterized in that: The invention comprises the display substrate as claimed in any one of claims 1 to 19.

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