Display panel and display device

Abstract

The invention provides a display panel and a display device, and the display panel enables the overlapping area of one clock signal line and all corresponding through holes in one repeating unit to be equal to the overlapping area of the other clock signal line and all corresponding through holes in one repeating unit in any two clock signal lines. The overlapping area of any clock signal line and the through holes in one repeating unit is equal to the product of the width of the clock signal line, the width of the through holes and the number of the through holes in one row in one repeating unit, so that when the positions of the through holes deviate, the overlapping area of any clock signal line and the through holes is kept unchanged; and the overlapping areas of the clock signal lines and the through holes are equal, so that the parasitic capacitances of the clock signal lines are similar and even equal, thereby avoiding different signal delays of adjacent clock signal lines, avoiding signal delay changes caused by impedance changes of the clock signal lines, and enabling the display panel to display normally.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used due to advantages such as self-luminescence, wide color gamut, low power consumption, and flexible display capabilities. OLED display devices adopt GOA (Gate Driver On Array) technology to reduce the bezel. To release moisture in the organic layer in the GOA region and reduce the impact of moisture on the electrical performance of devices in the GOA region, existing OLED display devices perform a grooving design on the large metal above the organic layer. Specifically, existing OLED display devices groove the metal of the anode layer on the clock signal lines, with one groove located on the first and second clock lines, and the other groove located on the third and fourth clock lines, such that the areas of the grooves on each clock line are equal. However, during the actual manufacturing process, due to the problem of mask alignment offset during the grooving of the anode layer, the grooves are offset relative to the clock lines, resulting in different overlapping areas between different clock lines and the grooves, causing changes in the parasitic capacitance between different clock lines and the metal of the anode layer, leading to changes in the total impedance of the clock lines, affecting their signal delay, and the change trends between adjacent clock lines are opposite, increasing the signal delay difference between different clock lines and affecting signal output.

[0003] Therefore, existing OLED display devices have the technical problem that the grooves on the clock lines are offset, resulting in excessive changes in the parasitic capacitance of the clock lines and affecting display. Summary of the Invention

[0004] Embodiments of this application provide a display panel and a display device to improve the technical problem that existing OLED display devices have grooves on the clock lines offset, resulting in excessive changes in the parasitic capacitance of the clock lines and affecting display.

[0005] Embodiments of this application provide a display panel. The display panel includes a display area and a driving circuit area provided on at least one side of the display area. The display panel includes:

[0006] Multiple clock signal lines, provided in the driving circuit area, and the multiple clock signal lines extend along a first direction;

[0007] A low-potential signal line, provided in the driving circuit area, and the positive projections of the multiple clock signal lines on the low-potential signal line are located within the low-potential signal line;

[0008] Among them, a plurality of through holes are formed in the low-potential signal line, and the through holes are arranged in an array to form a plurality of repeating units. In each repeating unit, the number of through holes in each column is the same. Among any two clock signal lines, the overlapping area between one clock signal line and all the corresponding through holes in one repeating unit is equal to the overlapping area between the other clock signal line and all the corresponding through holes in one repeating unit. Moreover, the overlapping area between any one clock signal line and the corresponding through holes in one repeating unit is equal to the product of the width of the clock signal line in the second direction, the length of the through hole in the first direction, and the number of through holes in one column of the repeating unit; the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

[0009] In some embodiments, each column of the through holes is arranged along the first direction, and there is a spacing between adjacent rows of the through holes in the first direction.

[0010] In some embodiments, the number of columns of the through holes is equal to the number of clock signal lines. Each column of the through holes is arranged in one-to-one correspondence with each clock signal line. The through holes are symmetrically arranged about the center line of the clock signal line. Moreover, the spacing between the end of the through holes corresponding to one clock signal line and the other clock signal line is greater than or equal to the maximum offset of the through holes, and the width by which the through holes exceed the width of the clock signal line is greater than or equal to the maximum offset of the through holes.

[0011] In some embodiments, the width of the through holes is equal to the sum of the width of the clock signal line and the spacing between adjacent clock signal lines.

[0012] In some embodiments, the spacing between adjacent clock signal lines is greater than the sum of half of the maximum offset of the through holes and the width of the part by which the through holes exceed the clock signal line.

[0013] In some embodiments, each column of the through holes is arranged in one-to-one correspondence with each clock signal line. In the repeating unit, the minimum spacing between the two ends of the through holes and the corresponding clock signal line is not equal. Among any two clock signal lines, the minimum spacing between one end of each through hole and the corresponding clock signal line is equal, and the minimum spacing between the other end of each through hole and the corresponding clock signal line is equal.

[0014] In some embodiments, each column of the through holes is arranged in one-to-one correspondence with each clock signal line. One end of the through holes corresponding to one clock signal line is aligned with one end of the clock signal line, and the other end of the through holes is aligned with one end of the other clock signal line.

[0015] In some embodiments, the minimum distance between the left end of the through hole and the corresponding clock signal line is greater than the minimum distance between the right end of the through hole and the corresponding clock signal line; or the minimum distance between the left end of the through hole and the corresponding clock signal line is less than the minimum distance between the right end of the through hole and the corresponding clock signal line.

[0016] In some embodiments, the through hole includes a first through hole corresponding to two adjacent clock signal lines and a second through hole corresponding to one clock signal line. Along a first direction, in two adjacent columns of through holes, one end of a column of through holes close to the other column of through holes and one end of the other column of through holes are on the same straight line.

[0017] In some embodiments, the first through hole is symmetrically arranged with respect to the center line of the portion of the low-potential signal line located between two adjacent clock signal lines, and the width of the portion of the second through hole extending beyond the clock signal line is greater than the maximum offset of the through hole.

[0018] In some embodiments, one end of the through hole corresponding to one clock signal line and one end of the through hole corresponding to another clock signal line are respectively located on the center lines of the two clock signal lines.

[0019] In some embodiments, among the first through hole and the second through hole corresponding to the same clock signal line, the overlapping area between one second through hole and the corresponding clock signal line is less than the overlapping area between one first through hole and the corresponding clock signal line, the overlapping area between the other second through hole and the corresponding clock signal line is greater than the overlapping area between the other first through hole and the corresponding clock signal line, and the overlapping areas between any first through hole and the two adjacent clock signal lines corresponding thereto are not equal.

[0020] In some embodiments, the display panel includes two sets of first scan driving units arranged symmetrically, each set of first scan driving units includes four clock signal lines, the through hole includes two columns of second through holes and three columns of first through holes, and the three columns of first through holes are located between the two columns of second through holes.

[0021] Meanwhile, an embodiment of the present application provides a display device, which includes the display panel as described in any one of the above embodiments.

[0022] Beneficial effects: The present application provides a display panel and a display device. The display panel includes a display area and a driving circuit area provided on at least one side of the display area. The display panel includes a plurality of clock signal lines and low-potential signal lines. The clock signal lines are provided in the driving circuit area and extend along a first direction. The low-potential signal lines are provided in the driving circuit area, and the orthographic projections of the plurality of clock signal lines on the low-potential signal lines are located within the low-potential signal lines. Among them, a plurality of through holes are formed in the low-potential signal lines, and the through holes are arranged in an array to form a plurality of repeating units. In each repeating unit, the number of through holes in each column is the same. Among any two clock signal lines, the overlapping area between one clock signal line and all the corresponding through holes in a repeating unit is equal to the overlapping area between the other clock signal line and all the corresponding through holes in a repeating unit, and the overlapping area between any clock signal line and the corresponding through holes in a repeating unit is equal to the product of the width of the clock signal line in the second direction, the length of the through hole in the first direction, and the number of through holes in one column of a repeating unit. The included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By making the overlapping area between one clock signal line and all the corresponding through holes in a repeating unit equal to the overlapping area between the other clock signal line and all the corresponding through holes in a repeating unit among any two clock signal lines, and the overlapping area between any clock signal line and the corresponding through holes in a repeating unit equal to the product of the width of the clock signal line, the width of the through hole, and the number of through holes in one column of a repeating unit, when the position of the through hole is offset, the overlapping area between any clock signal line and the through hole remains unchanged, and the overlapping areas of each clock signal line and the through hole are equal, so that the parasitic capacitances of each clock signal line are similar or even equal, thereby avoiding different signal delays of adjacent clock signal lines, and avoiding signal delay changes caused by impedance changes of the clock signal lines, enabling the display panel to display normally. Description of the Drawings

[0023] The following will, by describing the specific embodiments of the present application in detail with reference to the drawings, make the technical solutions and other beneficial effects of the present application obvious.

[0024] Figure 1 It is a schematic diagram when the grooves of the clock line and the low-potential power supply signal line in the existing display device do not shift.

[0025] Figure 2 It is Figure 1 a schematic diagram when the grooves of the clock line and the low-potential power supply signal line in

[0026] Figure 3 It is Figure 1 a bar chart of the offset amount of the grooves of the clock line and the low-potential power supply signal line in

[0027] Figure 4The first schematic diagram of the display panel provided by the embodiment of the present application.

[0028] Figure 5 The second schematic diagram of the display panel provided by the embodiment of the present application.

[0029] Figure 6 The third schematic diagram of the display panel provided by the embodiment of the present application.

[0030] Figure 7 The fourth schematic diagram of the display panel provided by the embodiment of the present application.

[0031] Figure 8 The first schematic diagram when the through holes of the clock signal line and the low-potential signal line provided by the embodiment of the present application do not shift.

[0032] Figure 9 For Figure 8 The schematic diagram when the positions of the through holes in the clock signal line and the low-potential signal line in shift.

[0033] Figure 10 For Figure 8 The bar chart of the offset amount of the through holes in the clock signal line and the low-potential signal line in and the change amount of the parasitic capacitance of the clock signal line.

[0034] Figure 11 The second schematic diagram when the through holes of the clock signal line and the low-potential signal line provided by the embodiment of the present application do not shift.

[0035] Figure 12 For Figure 11 The schematic diagram when the positions of the through holes in the clock signal line and the low-potential signal line provided by shift.

[0036] Figure 13 For Figure 11 The bar chart of the offset amount of the through holes in the clock signal line and the low-potential signal line provided by and the change amount of the parasitic capacitance of the clock signal line. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0038] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0039] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected" and "coupled" shall be construed broadly. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection, an electrical connection or a connection capable of mutual communication; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0040] In the present application, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely means that the horizontal height of the first feature is lower than that of the second feature.

[0041] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0042] As Figure 1 shown, Figure 1 in (a) is a stacked diagram of a low-potential power supply signal line and a clock line, Figure 1 in (b) is Figure 1 a decomposition diagram of the low-potential power supply signal line in (a) of Figure 1 in (c) is Figure 1 a decomposition diagram of the clock line in (a) of Figure 1 As can be seen from Figure 1 shown, in order to release the water vapor in the organic layer in the gate driving circuit region, the existing OLED display device will groove the low-potential power supply signal line 12 of the anode layer in the corresponding region of the clock line. Specifically, as

[0043] As Figure 2 shown, Figure 2 in (a) is a schematic diagram of an OLED display device when the groove is offset 3 microns to the left, Figure 2 in (b) is a schematic diagram of an OLED display device when the groove is offset 2 microns to the left, Figure 2 in (c) is a schematic diagram of an OLED display device when the groove is offset 1 micron to the left, Figure 2 in (d) is a schematic diagram of an OLED display device when the groove is offset 1 micron to the right, Figure 2 in (e) is a schematic diagram of an OLED display device when the groove is offset 2 microns to the right, Figure 2 in (f) is a schematic diagram of an OLED display device when the groove is offset 3 microns to the right. As can be seen from Figure 2 it, when the groove is offset, the overlapping area between two adjacent clock lines and the groove changes, and the overlapping areas between two adjacent clock lines and the groove are different, so that the parasitic capacitance between the clock line and the low-potential power supply signal line changes.

[0044] As Figure 3 shown, Figure 3 in (a), -3 on the abscissa indicates that the grooving is offset 3 microns to the left, and 3 indicates that the grooving is offset 3 microns to the right. Similarly, other values and Figure 3 the values in (b) can be referred to the above description. Figure 3 In (a), it is the change amount of the parasitic capacitance between each clock line and the low - potential power signal line at different offsets. Figure 3 In (a), the abscissa represents the offset amount of the grooving of the clock line and the low - potential power signal line, and the ordinate represents the change amount of the parasitic capacitance of the clock line and the low - potential power signal line compared with when there is no offset in the grooving of the clock line and the low - potential power signal line. Figure 3 In the bar chart, it is the change amount of the parasitic capacitance of different clock lines and the low - potential power signal line. CK1 - ANO represents the change amount of the parasitic capacitance of the first clock line and the low - potential power signal line, CK2 - ANO represents the change amount of the parasitic capacitance of the second clock line and the low - potential power signal line, CK3 - ANO represents the change amount of the parasitic capacitance of the third clock line and the low - potential power signal line, and CK4 - ANO represents the change amount of the parasitic capacitance of the fourth clock line and the low - potential power signal line. Figure 3 In (b), it is the change amount of the parasitic capacitance between each clock line and all signal lines at different offsets. Figure 3 In (b), the abscissa represents the offset amount of the grooving of the clock line and the low - potential power signal line, and the ordinate represents the change amount of the parasitic capacitance of the clock line and all signal lines compared with when there is no offset in the grooving of the clock line and the low - potential power signal line. Figure 3 In the bar chart, it is the change amount of the parasitic capacitance of different clock lines and all signal lines. CK1 - Total represents the change amount of the parasitic capacitance of the first clock line and all signal lines, CK2 - Total represents the change amount of the parasitic capacitance of the second clock line and all signal lines, CK3 - Total represents the change amount of the parasitic capacitance of the third clock line and all signal lines, and CK4 - Total represents the change amount of the parasitic capacitance of the fourth clock line and all signal lines.

[0045] From Figure 2 and Figure 3As can be seen, compared with the case where the grooving of the clock line and the low-potential power supply signal line does not shift, when the low-potential power supply signal line is misaligned with the mask plate, resulting in the grooving of the low-potential power supply signal line shifting relative to the clock line, the parasitic capacitance between each clock line and the low-potential power supply signal line changes, and the change trends of the parasitic capacitance between adjacent clock lines and the low-potential power supply signal line are opposite. For example, the change trends of the parasitic capacitance between the first clock line 111 and the second clock line 112 and the low-potential power supply signal line 12 are opposite, resulting in an increase in the signal delay difference between different clock lines. It can be understood that, due to the change in the parasitic capacitance between the clock line and the low-potential power supply signal line, the electrical signal output by the clock line does not match the preset electrical signal, and the signal delay difference between different clock lines increases, resulting in different turn-on times or turn-on voltages of different transistors, affecting the display effect. Therefore, there is a technical problem in the existing OLED display device that the grooving on the clock line shifts, resulting in too large a change in the parasitic capacitance of the clock line and affecting the display.

[0046] In an embodiment of the present application, in view of the above technical problems, a display panel and a display device are provided to improve the above technical problems.

[0047] Figure 4 It is the first schematic diagram of the display panel provided by the embodiment of the present application. Figure 5 It is the second schematic diagram of the display panel provided by the embodiment of the present application. Figure 6 It is the third schematic diagram of the display panel provided by the embodiment of the present application. Figure 7 It is the fourth schematic diagram of the display panel provided by the embodiment of the present application. Figure 8 It is the first schematic diagram when the through holes of the clock signal line and the low-potential signal line provided by the embodiment of the present application do not shift. Figure 9 is Figure 8 a schematic diagram when the positions of the through holes in the clock signal line and the low-potential signal line in Figure 10 is Figure 8 a bar chart of the offset amount of the through holes in the clock signal line and the low-potential signal line in Figure 11 It is the second schematic diagram when the through holes of the clock signal line and the low-potential signal line provided by the embodiment of the present application do not shift. Figure 12 is Figure 11 a schematic diagram when the positions of the through holes in the clock signal line and the low-potential signal line provided by Figure 13 is Figure 11 a bar chart of the offset amount of the through holes in the clock signal line and the low-potential signal line provided by

[0048] As Figures 4 to 13As shown in the figure, an embodiment of the present application provides a display panel 2, which includes a display area 21 and a driving circuit area 221 disposed on at least one side of the display area 21. The display panel 2 includes:

[0049] A plurality of clock signal lines 41 are disposed in the driving circuit area 221, and the plurality of clock signal lines 41 extend along the first direction X;

[0050] A low-potential signal line 42 is disposed in the driving circuit area 221, and the positive projections of the plurality of clock signal lines 41 on the low-potential signal line 42 are located within the low-potential signal line 42;

[0051] Wherein, a plurality of through holes 421 are formed on the low-potential signal line 42, and the through holes 421 are arranged in an array to form a plurality of repeating units 40. Within the repeating unit 40, the number of through holes 421 in each column is the same (for example Figure 8 in each repeating unit 40, the number of through holes in each column is 1). Among any two clock signal lines 41, the overlapping area between one clock signal line 41 and all the corresponding through holes 421 in a repeating unit 40 is equal to the overlapping area between the other clock signal line 41 and all the corresponding through holes 421 in a repeating unit 40 (for example, in Figure 8 the overlapping area between the first clock signal line 311 and all the corresponding through holes 421 in a repeating unit 40 is L4*L1*1, and the overlapping area between the second clock signal line 312 and all the corresponding through holes 421 in a repeating unit 40 is L4*L1*1, and the two are equal), and the overlapping area between any clock signal line 41 and the corresponding through holes 421 in a repeating unit 40 is equal to the product of the width L1 of the clock signal line 41 in the second direction Y, the length L4 of the through hole 421 in the first direction X, and the number of through holes 421 in one column of a repeating unit 40 (for example, in Figure 8 the overlapping area between the first clock signal line 311 and all the corresponding through holes 421 in a repeating unit 40 is L4*L1*1); the included angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0052] An embodiment of the present application provides a display panel. By making the overlapping area between one clock signal line and all corresponding vias in a repeating unit equal to the overlapping area between another clock signal line and all corresponding vias in the repeating unit among any two clock signal lines, and making the overlapping area between any clock signal line and the vias in a repeating unit equal to the product of the width of the clock signal line, the width of the via, and the number of vias in one column of the repeating unit, when the position of the via is offset, the overlapping area between any clock signal line and the via remains unchanged, and the overlapping areas between each clock signal line and the vias are equal, making the parasitic capacitances of each clock signal line similar or even equal, thereby avoiding different signal delays between adjacent clock signal lines and avoiding signal delay changes caused by impedance changes of the clock signal lines, enabling the display panel to display normally.

[0053] Specifically, in the drawings of the present application, the number of vias in each column of the repeating unit 40 is 1, but the embodiments of the present application are not limited thereto. For example, the number of vias in each column of the repeating unit 40 is 2.

[0054] Specifically, as Figure 4 shown, the display panel 2 includes a display area 21 and a non-display area 22. The non-display area 22 includes a driving circuit area 221 and a bonding area 222. A gate driving circuit is provided in the driving circuit area 221. As Figure 5 shown, the gate driving circuit includes a first scanning driving unit 31, a second scanning driving unit 32, a third scanning driving unit 34, and a signal control unit 33. The first scanning driving unit 31 and the signal control unit 33 can be provided in the driving circuit area 221 on both sides of the display area 21. The first scanning driving unit 31 includes a clock signal line 41.

[0055] Specifically, the low-potential signal line 42 refers to the low-potential power signal line connected to the light-emitting device of the display panel. After being connected to the common electrode of the display panel, the low-potential signal line 42 will be transferred through the pixel electrode layer 521 and then connected to the signal line of the second source-drain layer 517 for signal input (other parts of the low-potential signal line 42 are not shown in the figure). Therefore, in Figure 7 , a part of the pixel electrode layer 521 is the low-potential signal line 42, and the low-potential signal line 42 does not contact the pixel electrodes in the pixel electrode layer 521.

[0056] Specifically, as Figure 5 , Figure 8 shown, multiple clock signal lines 41 include a first clock signal line 311, a second clock signal line 312, a third clock signal line 313, and a fourth clock signal line 314. The widths of each clock signal line 41 are equal, and the spacing between adjacent clock signal lines 41 is equal.

[0057] Specifically, as Figure 7As shown, the clock signal line 41 will adopt the parallel routing of the second source-drain layer 517 and the third source-drain layer 519.

[0058] In some embodiments, as Figure 8 shown, each column of the vias 421 is arranged along the first direction X, and there is a pitch between adjacent two rows of the vias 421 in the first direction X. By making adjacent two columns of vias alternate up and down in the setting direction of the clock signal line, the distribution of the vias on each clock signal line is relatively uniform, and the moisture in each area can be released, improving the performance of the display panel.

[0059] Specifically, Figure 8 (a) in is the first stacked diagram of the clock signal line 41 and the low-potential signal line 42, Figure 8 (b) in is Figure 8 the exploded view of the low-potential signal line 42 in (a) in, Figure 8 (c) in is Figure 8 the exploded view of the clock signal line 41 in (a) in.

[0060] Specifically, it can be understood that Figure 8 and Figure 9 each of the attached drawings in can be the design in different display panels during the actual manufacturing process.

[0061] Specifically, it can be seen that in adjacent two columns of vias, in the setting direction of the clock signal line, one column of vias is translated downward relative to the other column of vias, so that the distribution of the vias on each clock signal line is relatively uniform, and the moisture in each area is released, avoiding the change of the performance of the thin-film transistor caused by the invasion of moisture. However, the embodiments of the present application are not limited thereto, and adjacent two columns of vias can be in contact in the setting direction of the clock signal line.

[0062] In some embodiments, the left end of the leftmost via extends beyond the leftmost clock signal line, and the right end of the rightmost via extends beyond the rightmost clock signal line, and half of the width of the part where the via extends beyond the clock signal line is greater than the maximum offset of the via. By making the via overlap with each clock signal line and half of the width of the part where the via extends beyond the clock signal line is greater than the maximum offset of the via, when the position of the via is offset, the overlapping area between the via and any clock signal line is equal, so that the difference in the parasitic capacitance between each clock signal line and the low-potential signal line changes less, and the change differences in the parasitic capacitance between adjacent clock signal lines and the low-potential signal line are similar or even the same, thus avoiding the display defect caused by the excessive change of the parasitic capacitance between the clock signal line and the low-potential signal line, and avoiding the excessive difference in the parasitic capacitance between different clock signal lines and the low-potential signal line, further avoiding the display defect.

[0063] Specifically, as Figure 8 shown, the left end of the through hole 421 located at the leftmost side extends beyond the leftmost clock signal line ( Figure 8 the first clock signal line 311 in Figure 8 ), and the right end of the through hole 421 located at the rightmost side extends beyond the rightmost clock signal line ( Figure 8 the second clock signal line 314 in

[0064] ), and half of the width of the part where the through hole 421 extends beyond the clock signal line 41 is greater than the maximum offset of the through hole 421, so that

[0065] taking the through hole 421 as an example, half of the width of the part where the through hole 421 extends beyond the clock signal line 41 is (L3 - L1) / 2, making this value greater than the maximum offset of the through hole, then the overlapping area of the through hole with any clock signal line can be made equal.

[0066] In some embodiments, as Figure 8 shown, the number of columns of the through holes 421 is equal to the number of the clock signal lines 41, each column of the through holes 421 is arranged in one-to-one correspondence with each clock signal line 41, the through holes 421 are symmetrically arranged about the center line of the clock signal line 41, and the distance between the end of the through hole 421 corresponding to a clock signal line 41 close to another clock signal line 41 is greater than or equal to the maximum offset of the through hole 421, and the width of the part where any side of the through hole 421 extends beyond the clock signal line 41 (for example, ( Figure 8 (L3 - L1) / 2 in

[0067] Specifically, when designing the relative positions of the vias and the clock signal lines, the vias can be in an unshifted state or, in an actual product, the vias are symmetric about the center line of the clock signal lines. Thus, during the actual manufacturing process, even if the vias are shifted relative to the clock signal lines, since the width of the portion of either side of the via that extends beyond the clock signal line is greater than or equal to the maximum shift amount of the via, and the distance between the end of the via close to another clock signal line and the other clock signal line is greater than or equal to the maximum shift amount of the via, the overlapping area between the clock signal line and the corresponding via does not change. As a result, the change in the parasitic capacitance between the clock signal line and the low-power signal line can be made small or even unchanged, the change in the impedance of the clock signal line can be made small or even unchanged, and the difference in the impedance change between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0068] Specifically, as Figure 8 shown, the number of columns of the vias 421 is 4, and the number of clock signal lines 41 is 4, and the two are equal, such that each column of vias 421 is arranged in one-to-one correspondence with each clock signal line 41, and the vias 421 are symmetrically arranged about the center line of the clock signal line 41, such that the widths of the two portions of the via 421 that extend beyond the clock signal line 41 are equal, and the distance between the vias 421 corresponding to each clock signal line 41 and another clock signal line 41 is greater than or equal to the maximum shift amount of the via 421. For example, the distance between the vias 421 corresponding to the first clock signal line 311 and the second clock signal line 312 is greater than the maximum shift amount of the via 421, which can prevent the vias corresponding to the first clock signal line from shifting to the second clock signal line. Thus, the overlapping area between each clock signal line and the vias can be kept unchanged, and the width of the portion of either side of the via that extends beyond the clock signal line 41 is greater than or equal to the maximum shift amount of the via 421. For example, Figure 8 the width of the right side of the via in

[0069] Specifically, by setting each column of vias in one-to-one correspondence with the clock signal lines, and when the vias are in the non-offset state, the vias are axially symmetrically arranged with respect to the clock signal lines, and the distance between the end of the vias corresponding to one clock signal line close to the other clock signal line and the other clock signal line is greater than or equal to the maximum offset of the vias, and the width by which the vias exceed the clock signal lines is greater than the maximum offset of the vias, so that when the vias are offset, the vias will not be offset onto another clock signal line, and the overlapping area between a single via and the corresponding clock signal line remains the product of the length of the via and the width of the clock signal line, so that the overlapping area between the vias and the clock signal lines does not change, making the change in the parasitic capacitance between the clock signal lines and the low-power signal lines smaller or even unchanged, the impedance change of the clock signal lines smaller or even unchanged, and the impedance change differences between any two clock signal lines smaller or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0070] Specifically, the above embodiment is described by taking the axial symmetry of the vias with respect to the center line of the clock signal lines as an example, but the embodiments of the present application are not limited thereto. For example, when the vias are in the non-offset state, that is, in the theoretical design or the actual product, the vias may not be axially symmetrically arranged with respect to the center line of the clock signal lines, but the distances between both ends of the vias and other clock signal lines are greater than or equal to the maximum offset of the vias, and the width of the part where the vias exceed the corresponding clock signal lines is greater than or equal to the maximum offset of the vias, so that the vias will not be offset onto another clock signal line, and the overlapping area between the vias and the corresponding clock signal lines does not change.

[0071] For example, the leftmost via is not symmetric with respect to the center line of the first clock signal line 311, but the width of the part where either side of the leftmost via exceeds the first clock signal line 311 is greater than or equal to the maximum offset of the vias, and the distances between both sides of the via and other clock signal lines are greater than or equal to the maximum offset of the vias. For example, the width of the part where the left side of the via exceeds the first clock signal line 311 is 4, and the width of the part where the right side of the via exceeds the first clock signal line 311 is 3, but both are greater than the maximum offset of the vias, then the overlapping area between the first clock signal line and the via can be made equal to the overlapping area between other clock signal lines and the via.

[0072] In some embodiments, such as Figure 8As shown, the width L3 of the through hole 421 is equal to the sum of the width L1 of the clock signal line 41 and the spacing L2 between adjacent clock signal lines 41. By making the width of the through hole equal to the sum of the width of the clock signal line and the spacing between adjacent clock signal lines, and the through hole is symmetrically arranged with respect to the clock signal line, the width of the through hole exceeding the clock signal line is greater than or equal to the maximum offset of the through hole, then the two parts of the through hole exceeding the clock signal line are symmetric with respect to the clock signal line, and in adjacent two columns of through holes, the right end of one column of through holes is aligned with the left end of the other column of through holes, so that when the through hole is offset, whether it is offset to the left or to the right, the overlapping area between the clock signal line and the through hole does not change, and the overlapping areas between each clock signal line and the through hole are close or even equal, so that the impedance change of each clock signal line is small or even does not change, and the impedance change difference between any two clock signal lines is small or even equal, avoiding display defects caused by the impedance difference between different clock signal lines.

[0073] Specifically, taking the width of the clock signal line as 8 microns and the spacing between adjacent clock signal lines as 6 microns as an example, the width of the through hole is 14 microns and the length is 14 microns. Then the width of the part of the through hole exceeding the clock signal line on one side is 3 microns. Taking the maximum offset of the through hole as 3 microns as an example, no matter whether the through hole is offset to the left or to the right, the overlapping area between a single through hole and the clock signal line remains 14 microns * 8 microns, and the overlapping areas between each clock signal line and the through hole are the same. Therefore, the impedance change differences between each clock signal line are small (the reason for the change may be that the fine change of the electrical properties of each signal line caused by the offset of the through hole position causes the impedance change of the clock signal line) or even do not change, avoiding display defects caused by the impedance change of the clock signal line, and the impedance change differences between any two clock signal lines are small or even equal, avoiding display defects caused by the impedance difference between different clock signal lines.

[0074] In some embodiments, as Figure 8 shown, the spacing L2 between adjacent clock signal lines 41 is greater than the sum of the maximum offset of the through hole 421 and half of the width of the part of the through hole exceeding the clock signal line 41. By making the spacing between adjacent clock signal lines greater than the sum of the maximum offset of the through hole and half of the width of the part of the through hole exceeding the clock signal line, in the actual manufacturing process, even if the through hole is offset, the through hole will not be offset to the adjacent clock signal line, and the width of the through hole exceeding the clock signal line is greater than or equal to the maximum offset of the through hole, so that the overlapping area between the clock signal line and the through hole does not change, and the overlapping areas between each clock signal line and the through hole are close or even equal, so that the impedance change of each clock signal line is small or even does not change, and the impedance change difference between any two clock signal lines is small or even equal, avoiding display defects caused by the impedance difference between different clock signal lines.

[0075] Specifically, taking the distance between adjacent clock signal lines as 8 microns, the maximum offset of the via as 3 microns, and the width of the part of the via exceeding the clock signal line as 8 microns as an example, the distance between adjacent clock signal lines is greater than the sum of half of the maximum offset of the via and the width of the part of the via exceeding the clock signal line. When the via is offset, the via will not be offset to other clock signal lines, and the overlapping area between the via and the clock signal line remains unchanged.

[0076] Specifically, the above embodiment is described by taking the case where the via is symmetrically arranged about the center line of the clock signal line as an example, but the embodiments of the present application are not limited thereto. For example, when the via is in an un-offset state, the width of the part of any side of the via exceeding the clock signal line is greater than or equal to the maximum offset of the via, and the distance between adjacent clock signal lines is greater than or equal to the sum of the maximum offset of the via and the maximum width of the part of the via exceeding the clock signal line. For example, the widths of the two parts of the via exceeding the clock signal line are not equal. The width of one part of the via exceeding the clock signal line is 4 microns, and the width of the other part of the via exceeding the clock signal line is 3 microns. Then the maximum width of the part of the via exceeding the clock signal line is 4 microns. At the same time, the distance between adjacent clock signal lines is greater than or equal to the sum of the maximum offset of the via and the maximum width of the part of the via exceeding the clock signal line. For example, the distance between adjacent clock signal lines is 8 microns, and the maximum offset of the via is 3 microns, so that when the via is offset, it will not be offset to other clock signal lines, and the overlapping area between each clock signal line and the via will not change.

[0077] In some embodiments, as Figure 9 shown, each column of the vias 421 is arranged in one-to-one correspondence with each clock signal line 41. In the repeating unit 40, the minimum distances between the two ends of the via 421 and the corresponding clock signal line 41 are not equal, and among any two clock signal lines 41, the minimum distance between one end of each via 421 and the corresponding clock signal line 41 is equal, and the minimum distance between the other end of each via 421 and the corresponding clock signal line 41 is equal.

[0078] Specifically, during the actual manufacturing process, due to process offsets, the positions of the vias may shift relative to the theoretically designed positions. At this time, the minimum distances between the two ends of the vias and the corresponding clock signal lines are not equal. However, within any two clock signal lines, the minimum distance between one end of each via and the corresponding clock signal line is equal, and the minimum distance between the other end of each via and the corresponding clock signal line is equal. This makes the relative offset amounts of each via and the clock signal line the same, and the overlapping areas between each via and the corresponding clock signal line remain unchanged and are equal. As a result, the change in parasitic capacitance between the clock signal line and the low-power signal line can be relatively small or even unchanged, the impedance change of the clock signal line is relatively small or even unchanged, and the impedance change differences between any two clock signal lines are relatively small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0079] Specifically, the minimum distances between the two ends of the via 421 and the corresponding clock signal line 41 mean that the via has left and right ends. The distance L6 between the left end of the via and the left end of the corresponding clock signal line is the minimum distance between the left end of the via and the corresponding clock signal line, and the distance L7 between the right end of the via and the right end of the corresponding clock signal line is the minimum distance between the right end of the via and the corresponding clock signal line. Then, the distance between the left end of the via and the left end of the corresponding clock signal line and the distance between the right end of the via and the right end of the corresponding clock signal line are the minimum distances between the two ends of the via and the corresponding clock signal line.

[0080] Specifically, as Figure 9 shown, it can be seen that the distance L6 between the left end of the via and the left end of the corresponding clock signal line and the distance L7 between the right end of the via and the right end of the corresponding clock signal line are not equal. However, within any two clock signal lines 41, for example, in the first clock signal line 311 and the second clock signal line 312, the distance between the left end of the via 421 corresponding to the first clock signal line 311 and the left end of the first clock signal line 311 is equal to the distance between the left end of the via 421 corresponding to the second clock signal line 312 and the left end of the second clock signal line 312, and the distance between the right end of the via 421 corresponding to the first clock signal line 311 and the right end of the first clock signal line 311 is equal to the distance between the right end of the via 421 corresponding to the second clock signal line 312 and the right end of the second clock signal line 312. This makes the offset amounts of the vias corresponding to each clock signal line and the clock signal line equal, and the overlapping areas between each via and the corresponding clock signal line remain unchanged.

[0081] In some embodiments, as Figure 9 shown in (a) and Figure 9As shown in (f) therein, each of the through holes 421 is provided corresponding to each clock signal line 41 one by one. One end of the through hole 421 corresponding to one clock signal line 41 is aligned with one end of the clock signal line 41, and the other end of the through hole 421 is aligned with one end of the other clock signal line 41. By aligning one end of a through hole with one end of another clock signal line, it is avoided that the through hole shifts onto another clock signal line, so that the overlapping area of each clock signal line and the through hole remains unchanged, making the impedance change of each clock signal line smaller or even unchanged, and the impedance change difference between any two clock signal lines is smaller or even equal, thus avoiding display defects caused by impedance differences between different clock signal lines.

[0082] In some embodiments, as Figure 9 shown, when the through hole 421 is in an offset state, one end of the through hole 421 corresponding to one clock signal line 41 is aligned with one end of the other clock signal line 41. By aligning one end of a through hole with one end of another clock signal line when the through hole is in an offset state, it is avoided that the through hole shifts onto another clock signal line, so that the overlapping area of each clock signal line and the through hole remains unchanged, making the impedance change of each clock signal line smaller or even unchanged, and the impedance change difference between any two clock signal lines is smaller or even equal, thus avoiding display defects caused by impedance differences between different clock signal lines.

[0083] Specifically, taking the maximum offset of the through hole as 3 microns as an example, Figure 9 (a) in Figure 8 is a stacked diagram of the clock signal line and the low - potential signal line when the through hole in Figure 9 shifts 3 microns to the left relative to the clock signal line, Figure 8 (b) in Figure 9 is a stacked diagram of the clock signal line and the low - potential signal line when the through hole in Figure 8 shifts 2 microns to the left relative to the clock signal line, Figure 9 (c) in Figure 8 is a stacked diagram of the clock signal line and the low - potential signal line when the through hole in Figure 9 shifts 1 micron to the left relative to the clock signal line, Figure 8 (d) in Figure 9 is a stacked diagram of the clock signal line and the low - potential signal line when the through hole in Figure 8 shifts 1 micron to the right relative to the clock signal line,

[0084] As Figure 9As shown in (a) thereof, when the through hole 421 is in an offset state, the left end of the through hole 421 corresponding to the second clock signal line 312 is aligned with the right end of the first clock signal line 311, the left end of the through hole 421 corresponding to the third clock signal line 313 is aligned with the right end of the second clock signal line 312, and the left end of the through hole 421 corresponding to the fourth clock signal line 314 is aligned with the right end of the third clock signal line 313. As Figure 9 shown in (f) thereof, the right end of the through hole 421 corresponding to the first clock signal line 311 is aligned with the left end of the second clock signal line 312, the right end of the through hole 421 corresponding to the second clock signal line 312 is aligned with the left end of the third clock signal line 313, and the right end of the through hole 421 corresponding to the third clock signal line 313 is aligned with the left end of the fourth clock signal line 314.

[0085] Specifically, when the through hole is at the maximum offset degree, one end of the through hole is aligned with one end of another clock signal line, so that the through hole will not be offset to other clock signal lines, avoiding the change of the impedance of the clock signal line caused by the change of the overlapping area between the clock signal line and the through hole, and improving the display effect of the display panel.

[0086] In some embodiments, as Figure 9 shown in (a) to Figure 9 shown in (c) thereof, the minimum distance L6 between the left end of the through hole 421 and the corresponding clock signal line 41 is greater than the minimum distance L7 between the right end of the through hole 421 and the corresponding clock signal line 41; or as Figure 9 shown in (d) to Figure 9 shown in (f) thereof, the minimum distance L6 between the left end of the through hole 421 and the corresponding clock signal line 41 is less than the minimum distance L7 between the right end of the through hole 421 and the corresponding clock signal line 41 ( Figure 9 L7 is 0 in (a) thereof, Figure 9 L6 is 0 in (f) thereof).

[0087] In some embodiments, as Figure 9As shown, when the through-hole 421 is in an offset state, there are distances between both ends of the through-hole 421 corresponding to one of the clock signal lines 41 and the two clock signal lines 41 on both sides of the clock signal line 41, and the distances between both ends of the through-hole 421 and the two clock signal lines 41 on both sides of the clock signal line 41 are not equal. By making there be distances between both ends of the through-hole and the two clock signal lines on both sides, and the distances between both ends of the through-hole and the two clock signal lines on both sides of the clock signal line are not equal, when the through-hole is offset, the through-hole will not offset to other clock signal lines, and the overlapping area between the through-hole and the corresponding clock signal line remains unchanged, so that the impedance change of each clock signal line is small or even does not change, and the impedance change difference between any two clock signal lines is small or even equal, avoiding display defects caused by the impedance difference between different clock signal lines.

[0088] Specifically, as Figure 9 shown in (b) of Figure 9 shown in (c) of Figure 9 shown in (d) of Figure 9 and shown in (e) of

[0089] Specifically, for the through-hole with clock signal lines on both sides, there can be distances between it and the clock signal lines on both sides. For the through-hole with a clock signal line on only one side, there can be a distance between the through-hole and the clock signal line on one side, and the widths of the two parts where the through-hole extends beyond the corresponding clock signal line are not equal.

[0090] Specifically, the lengths of the through-holes corresponding to each clock signal line are the same, and the widths of the through-holes are the same.

[0091] Specifically, as Figure 10 shown Figure 10 in (a), -3 on the abscissa indicates that the through-hole is offset 3 microns to the left, and 3 indicates that the through-hole is offset 3 microns to the right. Similarly, other values and Figure 10 the values in (b) of Figure 10 can refer to the above description. Figure 8 In (a) of Figure 10 is the change amount of the parasitic capacitance between each clock signal line and the low-potential signal line at different offset amounts. In (a) of Figure 10The bar chart in [Figure] shows the change in the parasitic capacitance between different clock signal lines and the low-potential signal line. CK1-ANO represents the change in the parasitic capacitance between the first clock signal line 311 and the low-potential signal line, CK2-ANO represents the change in the parasitic capacitance between the second clock signal line 312 and the low-potential signal line, CK3-ANO represents the change in the parasitic capacitance between the third clock signal line 313 and the low-potential signal line, and CK4-ANO represents the change in the parasitic capacitance between the fourth clock signal line 314 and the low-potential signal line. Figure 10 In [Figure] (b), it is Figure 8 the change in the parasitic capacitance between each clock signal line and all signal lines in [Figure] at different offsets. Figure 10 In [Figure] (b), the abscissa represents the offset of the via hole between the clock signal line and the low-potential signal line, and the ordinate represents the change in the parasitic capacitance between the clock signal line and all signal lines compared with when there is no offset of the via hole between the clock signal line and the low-potential signal line. Figure 10 The bar chart in [Figure] shows the change in the parasitic capacitance between different clock signal lines and all signal lines. CK1-Total represents the change in the parasitic capacitance between the first clock signal line and all signal lines, CK2-Total represents the change in the parasitic capacitance between the second clock signal line and all signal lines, CK3-Total represents the change in the parasitic capacitance between the third clock signal line and all signal lines, and CK4-Total represents the change in the parasitic capacitance between the fourth clock signal line and all signal lines.

[0092] From Figure 3 and Figure 10 the comparison in [Figure] and [Figure], it can be seen that compared with the display device in the prior art, in the display panel provided in the present application, with the change in the offset of the via hole, the change in the parasitic capacitance between each clock signal line and the low-potential signal line, and the change in the parasitic capacitance between each clock signal line and all signal lines are significantly reduced. For example, Figure 3 in [Figure], the change in the parasitic capacitance between each clock line and the low-potential power signal line reaches 3.3%, and the change in the parasitic capacitance between each clock line and all signal lines reaches 2.7%. While in Figure 10 [Figure], the change in the parasitic capacitance between each clock signal line and the low-potential signal line is less than 0.9%, and the change in the parasitic capacitance between each clock signal line and all signal lines is less than 0.3%. That is, in the present application, the change in the parasitic capacitance on each clock signal line becomes smaller, the parasitic capacitance on the clock signal line is relatively stable, and the change trends of some clock signal lines are the same, making the parasitic capacitances of each clock signal line similar or even equal, thereby avoiding different signal delays between adjacent clock signal lines and avoiding signal delay changes caused by impedance changes in the clock signal lines, enabling the display panel to display normally.

[0093] In some embodiments, such as Figure 11As shown, the through hole 421 includes a first through hole 421a corresponding to two adjacent clock signal lines 41 and a second through hole 421b corresponding to one clock signal line 41. In the first direction X, in two adjacent columns of through holes 421, one end of one column of through holes 421 close to the other column of through holes 421 and one end of the other column of through holes 421 are on the same straight line. By aligning one end of the second through hole with one end of the first through hole and making the width of the part of the second through hole exceeding the clock signal line greater than the maximum offset of the through hole, the overlapping area between the clock signal line and the through hole does not change, so that the impedance change of each clock signal line is small or even unchanged, and the impedance change difference between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0094] In some embodiments, as Figure 11 shown, the first through hole 421a is symmetrically arranged about the center line of the part of the low-potential signal line 42 located between two adjacent clock signal lines 41, and the width of the part of the second through hole 421b exceeding the clock signal line 41 (for example, L5 in Figure 11 ) is greater than the maximum offset of the through hole 421. By symmetrically arranging the first through hole about the center line of the part of the low-potential signal line located between two adjacent clock signal lines, aligning one end of the second through hole with one end of the first through hole, and making the width of the part of the second through hole exceeding the clock signal line greater than the maximum offset of the through hole, the overlapping area between the clock signal line and the through hole does not change, so that the impedance change of each clock signal line is small or even unchanged, and the impedance change difference between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0095] Specifically, taking Figure 11 the relative position between the through hole and the clock signal line in the shown display panel as the through hole being in the non-offset state or in the theoretically designed position, it is the relative position between the through hole and the clock signal line. As can be seen from Figure 11 , even during the actual manufacturing process, when the position of the through hole is offset, the overlapping area between the through hole and the clock signal line does not change, and the overlapping area between each clock signal line and the through hole remains unchanged, so that the impedance change of each clock signal line is small or even unchanged, and the impedance change difference between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0096] Specifically, Figure 11 (a) in is the second stack-up diagram of the clock signal line 41 and the low-potential signal line 42, Figure 11 (b) in is Figure 11 the exploded view of the low-potential signal line 42 in (a) inFigure 11 In (c) of Figure 11 is the exploded view of the clock signal line 41 in (a) of

[0097] Specifically, it can be understood that Figure 11 and Figure 12 each of the attached drawings in

[0098] Specifically, such as Figure 11 as shown, it can be seen that some of the vias 421 are located on two clock signal lines 41, and some of the vias 421 are located on one clock signal line 41.

[0099] In some embodiments, such as Figure 11 as shown, one end of the via 421 corresponding to one clock signal line 41 and one end of the via 421 corresponding to the other clock signal line 41 are respectively located on the center lines of the two clock signal lines 41. When adjacent two columns of vias are offset, the increased overlapping area between one column of vias and the clock signal line is equal to the decreased overlapping area between the other column of vias and the clock signal line, so that the overlapping area between the clock signal line and the vias does not change, the impedance change of each clock signal line is small or even does not change, and the impedance change difference between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences of different clock signal lines.

[0100] Specifically, when the via 421 is in an un-offset state, when adjacent two columns of vias are offset, the increased overlapping area between one column of vias and the clock signal line is equal to the decreased overlapping area between the other column of vias and the clock signal line, so that the overlapping area between the clock signal line and the vias does not change, the impedance change of each clock signal line is small or even does not change, and the impedance change difference between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences of different clock signal lines.

[0101] Specifically, both ends of the first via are respectively located on the center lines of two clock signal lines, and one end of the second via is located on the center line of one clock signal line.

[0102] Specifically, such as Figure 11 as shown, the left end of the first via 421a located on the first clock signal line 311 is located on the center line of the first clock signal line 311, and the right end of the first via 421a is located on the center line of the second clock signal line 312.

[0103] In some embodiments, such as Figure 12As shown, among the first through-hole 421a and the second through-hole 421b corresponding to the same clock signal line 41, the overlapping area of one of the second through-holes 421b and the corresponding clock signal line 41 is smaller than the overlapping area of one of the first through-holes 421a and the corresponding clock signal line 41, and the overlapping area of the other second through-hole 421b and the corresponding clock signal line 41 is larger than the overlapping area of the other first through-hole 421a and the corresponding clock signal line 41, and the overlapping areas of any one of the first through-holes 421a and the corresponding adjacent two clock signal lines 41 are not equal. When the through-hole is offset, the overlapping area of one second through-hole and the clock signal line decreases, and the overlapping area of the corresponding first through-hole and the clock signal line increases. The overlapping area of one second through-hole and the clock signal line increases, and the overlapping area of the corresponding first through-hole and the clock signal line decreases, so that when the through-hole is offset, the overlapping areas of each clock signal line and the through-hole do not change, so that the impedance change of each clock signal line is small or even does not change, and the impedance change differences of any two clock signal lines are small or even equal, avoiding display defects caused by impedance differences of different clock signal lines.

[0104] Specifically, when the through-hole 421 is in an offset state, the offset amounts of the through-holes corresponding to any two clock signal lines are equal, so that the overlapping area of each clock signal line and the corresponding through-hole remains unchanged.

[0105] Specifically, as Figure 11 shown, the display panel further includes a low-voltage signal line 44 and a start signal line 43. Since a DC signal is transmitted on the low-voltage signal line 44, therefore, the overlapping of the low-voltage signal line 44 and the through-hole does not affect the signal on the low-voltage signal line 44. For the start signal line 43, the overlapping of the through-hole and the start signal line 43 will reduce the impedance of the start signal line and reduce signal loss.

[0106] Specifically, taking the maximum offset amount of the through-hole as 3 microns as an example, Figure 12 in (a) of Figure 11 is the stacked diagram of the clock signal line and the low-potential signal line when the through-hole in Figure 12 is offset 3 microns to the left relative to the clock signal line, Figure 11 in (b) of Figure 12 is the stacked diagram of the clock signal line and the low-potential signal line when the through-hole in Figure 11 is offset 2 microns to the left relative to the clock signal line, Figure 12 in (c) of Figure 11 is the stacked diagram of the clock signal line and the low-potential signal line when the through-hole in Figure 12 is offset 1 micron to the left relative to the clock signal line,Figure 11 The stacked diagram of the clock signal line and the low-potential signal line when the through-hole in [[ ]] is offset 2 microns to the right relative to the clock signal line, Figure 12 (f) in [[ ]] is Figure 11 The stacked diagram of the clock signal line and the low-potential signal line when the through-hole in [[ ]] is offset 3 microns to the right relative to the clock signal line.

[0107] As Figure 11 、 Figure 12 (a) in [[ ]], Figure 12 (b) in [[ ]] and Figure 12 (c) in [[ ]] show that when the through-hole 421 is in the left-offset state, the overlapping area between the first clock signal line 311 and the corresponding second through-hole 421b is smaller than the overlapping area between the first clock signal line 311 and the corresponding first through-hole 421a, and the overlapping area between the fourth clock signal line 314 and the corresponding second through-hole 421b is larger than the overlapping area between the fourth clock signal line 314 and the corresponding first through-hole 421a; as Figure 11 、 Figure 12 (d) in [[ ]], Figure 12 (e) in [[ ]] and Figure 12 (f) in [[ ]] show that when the through-hole 421 is in the right-offset state, the overlapping area between the first clock signal line and the corresponding second through-hole 421b is larger than the overlapping area between the first clock signal line 311 and the corresponding first through-hole 421a, and the overlapping area between the fourth clock signal line 314 and the corresponding second through-hole 421b is smaller than the overlapping area between the fourth clock signal line 314 and the corresponding first through-hole 421a. And in Figure 12 (a) to Figure 12 (f) in [[ ]], the overlapping areas of any clock signal line 41 with the corresponding two first through-holes are different.

[0108] Specifically, when the through-hole is offset, the offset directions of the first through-hole and the second through-hole are the same. The increased overlapping area between a second through-hole and the clock signal line is equal to the decreased overlapping area between the corresponding first through-hole and the clock signal line, the decreased overlapping area between a second through-hole and the clock signal line is equal to the increased overlapping area between the corresponding first through-hole and the clock signal line, and the increased overlapping area between a first through-hole and the clock signal line is equal to the decreased overlapping area between the other first through-hole and the clock signal line, so that the overlapping areas of each clock signal line and the through-hole do not change.

[0109] Specifically, as Figure 13 shown, Figure 13 -3 on the abscissa of (a) in [[ ]] indicates that the through-hole is offset 3 microns to the left, and 3 indicates that the through-hole is offset 3 microns to the right. Similarly, the other values and Figure 13 the values in (b) in [[ ]] can be referred to the above description. Figure 13 (a) in [[ ]] is Figure 11The variation of the parasitic capacitance between each clock signal line and the low-potential signal line at different offsets Figure 13 In (a) of, the abscissa represents the offset of the vias between the clock signal line and the low-potential signal line, and the ordinate represents the variation of the parasitic capacitance between the clock signal line and the low-potential signal line compared with when there is no offset of the vias between the clock signal line and the low-potential signal line Figure 13 The bar graph in shows the variations of the parasitic capacitances between different clock signal lines and the low-potential signal line. CK1-ANO represents the variation of the parasitic capacitance between the first clock signal line 311 and the low-potential signal line, CK2-ANO represents the variation of the parasitic capacitance between the second clock signal line 312 and the low-potential signal line, CK3-ANO represents the variation of the parasitic capacitance between the third clock signal line 313 and the low-potential signal line, and CK4-ANO represents the variation of the parasitic capacitance between the fourth clock signal line 314 and the low-potential signal line Figure 13 In (b) of is Figure 11 The variation of the parasitic capacitance between each clock signal line and all signal lines at different offsets in Figure 13 In (b) of, the abscissa represents the offset of the vias between the clock signal line and the low-potential signal line, and the ordinate represents the variation of the parasitic capacitance between the clock signal line and all signal lines compared with when there is no offset of the vias between the clock signal line and the low-potential signal line Figure 13 The bar graph in shows the variations of the parasitic capacitances between different clock signal lines and all signal lines. CK1-Total represents the variation of the parasitic capacitance between the first clock signal line and all signal lines, CK2-Total represents the variation of the parasitic capacitance between the second clock signal line and all signal lines, CK3-Total represents the variation of the parasitic capacitance between the third clock signal line and all signal lines, and CK4-Total represents the variation of the parasitic capacitance between the fourth clock signal line and all signal lines

[0110] From Figure 3 and Figure 13 In the comparison in and, it can be seen that compared with the display device in the prior art, in the display panel provided in the present application, with the change of the offset of the vias, the variation of the parasitic capacitance between each clock signal line and the low-potential signal line, and the variation of the parasitic capacitance between each clock signal line and all signal lines are greatly reduced. For example Figure 3 in, the variation of the parasitic capacitance between each clock line and the low-potential power signal line reaches 3.3%, and the variation of the parasitic capacitance between each clock line and all signal lines reaches 2.7%, while in Figure 13Among them, the change amount of the parasitic capacitance between each clock signal line and the low-potential signal line is less than 0.3%, and the change amount of the parasitic capacitance between each clock signal line and all signal lines is less than 0.1%. That is, in this application, the change amount of the parasitic capacitance on each clock signal line becomes smaller, the parasitic capacitance on the clock signal line is relatively stable, and the change trends of some clock signal lines are the same, making the parasitic capacitances of each clock signal line similar or even equal, thereby avoiding different signal delays of adjacent clock signal lines and avoiding signal delay changes caused by impedance changes of the clock signal lines, enabling the display panel to display normally.

[0111] In some embodiments, such as Figures 5 to 11 shown, the display panel 2 includes two sets of first scan driving units 31 arranged symmetrically, and each set of first scan driving units 31 includes four of the clock signal lines 41.

[0112] In some embodiments, the through hole 421 includes two columns of second through holes 421b and three columns of first through holes 421a, and the three columns of the first through holes 421a are located between the two columns of the second through holes 421b.

[0113] Specifically, the width of the first through hole and the width of the second through hole may not be equal, and the lengths of the first through hole and the second through hole are equal.

[0114] Specifically, when the through hole is in an unshifted state, the second through hole 421b may not overlap with the low-voltage signal line 44, and / or the second through hole 421b may not overlap with the start signal line 43. It is also possible to make the second through hole 421b not overlap with the low-voltage signal line, the second through hole 421b overlap with the start signal line 43, or to make the second through hole 421b overlap with the low-voltage signal line and the second through hole 421b not overlap with the start signal line 43.

[0115] Specifically, in the above embodiments, the areas, lengths, and widths of each through hole are taken as equal for illustration, but the embodiments of this application are not limited thereto. It is only necessary to make the overlapping area between any clock signal line and the corresponding through hole unchanged in any state, and the overlapping areas between any two clock signal lines and the through hole are equal.

[0116] In some embodiments, such as Figure 6As shown, the display panel 2 includes: a substrate 501, a light-shielding layer 502, a buffer layer 503, a barrier layer 504, a first active layer 505, a first gate insulating layer 506, a first metal layer 507, a second gate insulating layer 508, a second metal layer 509, a first interlayer insulating layer 510, a second active layer 511, a third gate insulating layer 512, a third metal layer 513, a second interlayer insulating layer 514, a first source-drain layer 515, a first planarization layer 516, a second source-drain layer 517, a second planarization layer 518, a third source-drain layer 519, a third planarization layer 520, a pixel electrode layer 521, and a pixel definition layer 522. The first active layer 505 is disposed on one side of the substrate 501, the first gate insulating layer 506 is disposed on one side of the first active layer 505, the first metal layer 507 is disposed on the side of the first gate insulating layer 506 away from the first active layer 505, the second gate insulating layer 508 is disposed on the side of the first metal layer 507 away from the first gate insulating layer 506, the second metal layer 509 is disposed on the side of the second gate insulating layer 508 away from the first metal layer 507, the first interlayer insulating layer 510 is disposed on the side of the second metal layer 509 away from the second gate insulating layer 508, the second active layer 511 is disposed on the side of the first interlayer insulating layer 510 away from the second metal layer 509, the third gate insulating layer 512 is disposed on the side of the second active layer 511 away from the first interlayer insulating layer 510, the third metal layer 513 is disposed on the side of the third gate insulating layer 512 away from the second active layer 511, the second interlayer insulating layer 514 is disposed on the side of the third metal layer 513 away from the third gate insulating layer 512, the first source-drain layer 515 is disposed on the side of the second interlayer insulating layer 514 away from the third metal layer 513, the first planarization layer 516 is disposed on the side of the first source-drain layer 515 away from the second interlayer insulating layer 514, the second source-drain layer 517 is disposed on the side of the first planarization layer 516 away from the first source-drain layer 515, the second planarization layer 518 is disposed on the side of the second source-drain layer 517 away from the first planarization layer 516, the third source-drain layer 519 is disposed on the side of the second planarization layer 518 away from the second source-drain layer 517, the third planarization layer 520 is disposed on the side of the third source-drain layer 519 away from the second planarization layer 518, the pixel electrode layer 521 is disposed on the side of the third planarization layer 520 away from the third source-drain layer 519, and the pixel definition layer 522 is disposed on the side of the pixel electrode layer 521 away from the third planarization layer 520.

[0117] Specifically, the substrate 501 supports each layer disposed on the substrate 501. When the display panel 2 is a bottom-emission light-emitting display device or a double-sided emission light-emitting display device, a transparent substrate is used. When the display panel 2 is a top-emission light-emitting display device, a semi-transparent or opaque substrate as well as a transparent substrate can be used.

[0118] Specifically, the substrate 501 is used to support each film layer disposed on the substrate 501, and the substrate 501 can be made of an insulating material such as glass, quartz or polymer resin. The substrate 501 can be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0119] Specifically, the substrate 501 can include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer that are stacked. The first flexible substrate and the second flexible substrate can be formed of the same material such as polyimide, and the first barrier layer and the second barrier layer can be formed of an inorganic material including at least one of SiOx and SiNx, for example.

[0120] Specifically, the thin-film transistors in the display panel can be of an etch-stop type, a back-channel etch type, or can be divided into structures such as bottom-gate thin-film transistors and top-gate thin-film transistors according to the positions of the gate and the active layer, or can be divided into N-type thin-film transistors and P-type thin-film transistors according to the performance of the thin-film transistors.

[0121] Specifically, the above embodiments illustrate the display panel in the embodiments of the present application from different perspectives. When there is no conflict among the embodiments, the embodiments can be combined to achieve better technical effects.

[0122] Meanwhile, the embodiments of the present application provide a display device, and the display device includes the display panel as described in any one of the above embodiments. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function.

[0123] It can be seen from the above embodiments that:

[0124] Embodiments of the present application provide a display panel and a display device. The display panel includes a display area and a driving circuit area provided on at least one side of the display area. The display panel includes a plurality of clock signal lines and low-potential signal lines. The clock signal lines are provided in the driving circuit area and extend along a first direction. The low-potential signal lines are provided in the driving circuit area, and the orthographic projections of the plurality of clock signal lines on the low-potential signal lines are located within the low-potential signal lines. Wherein, a plurality of through holes are formed in the low-potential signal lines, and the through holes are arranged in an array to form a plurality of repeating units. In each repeating unit, the number of through holes in each column is the same. Among any two clock signal lines, the overlapping area between one clock signal line and all the corresponding through holes in a repeating unit is equal to the overlapping area between the other clock signal line and all the corresponding through holes in a repeating unit, and the overlapping area between any clock signal line and the corresponding through holes in a repeating unit is equal to the product of the width of the clock signal line in the second direction, the length of the through hole in the first direction, and the number of through holes in a column in a repeating unit. The included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. In the present application, by making the overlapping area between one clock signal line and all the corresponding through holes in a repeating unit equal to the overlapping area between the other clock signal line and all the corresponding through holes in a repeating unit among any two clock signal lines, and the overlapping area between any clock signal line and the through holes in a repeating unit equal to the product of the width of the clock signal line, the width of the through hole, and the number of through holes in a column in a repeating unit, when the position of the through hole is shifted, the overlapping area between any clock signal line and the through hole remains unchanged, and the overlapping areas between each clock signal line and the through hole are equal, so that the parasitic capacitances of each clock signal line are similar or even equal, thereby avoiding different signal delays between adjacent clock signal lines, and avoiding signal delay changes caused by impedance changes of the clock signal lines, so that the display panel can display normally.

[0125] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0126] The above has introduced in detail a display panel and a display device provided by embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, It includes a display area and a driving circuit area disposed on at least one side of the display area. The display panel includes: Multiple clock signal lines are disposed in the driving circuit area, and the multiple clock signal lines extend along a first direction; A low-potential signal line is disposed in the driving circuit area, and the positive projections of the multiple clock signal lines on the low-potential signal line are located within the low-potential signal line; Wherein, a plurality of through holes are formed in the low-potential signal line, and the through holes are arranged in an array to form a plurality of repeating units. In the repeating unit, the number of through holes in each column is the same. Among any two clock signal lines, the overlapping area between one clock signal line and all the corresponding through holes in one repeating unit is equal to the overlapping area between the other clock signal line and all the corresponding through holes in one repeating unit, and the overlapping area between any one clock signal line and the corresponding through holes in one repeating unit is equal to the product of the width of the clock signal line in the second direction, the length of the through hole in the first direction, and the number of through holes in one column of the repeating unit; the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

2. The display panel according to claim 1, characterized in that, Each column of the through holes is arranged along the first direction, and there is a spacing between adjacent two rows of the through holes in the first direction.

3. The display panel according to claim 1, characterized in that, The number of columns of the through holes is equal to the number of clock signal lines. Each column of the through holes is arranged in one-to-one correspondence with each clock signal line. The through holes are symmetrically arranged about the center line of the clock signal line, and the spacing between the end of the through hole corresponding to one clock signal line close to the other clock signal line and the other clock signal line is greater than or equal to the maximum offset of the through hole, and the width by which the through hole exceeds the clock signal line is greater than or equal to the maximum offset of the through hole.

4. The display panel according to claim 3, characterized in that, The width of the through hole is equal to the sum of the width of the clock signal line and the spacing between adjacent clock signal lines.

5. The display panel according to claim 3, characterized in that, The spacing between adjacent clock signal lines is greater than the sum of half of the maximum offset of the through hole and the width of the part by which the through hole exceeds the clock signal line.

6. The display panel according to claim 1, characterized in that, Each column of the through holes is arranged in one-to-one correspondence with each clock signal line. In the repeating unit, the minimum spacing between the two ends of the through hole and the corresponding clock signal line is not equal, and among any two clock signal lines, the minimum spacing between one end of each through hole and the corresponding clock signal line is equal, and the minimum spacing between the other end of each through hole and the corresponding clock signal line is equal.

7. The display panel according to claim 6, characterized in that, Each column of the through holes is arranged in one-to-one correspondence with each clock signal line. One end of the through hole corresponding to one clock signal line is aligned with one end of the clock signal line, and the other end of the through hole is aligned with one end of the other clock signal line.

8. The display panel according to claim 6, characterized in that, The minimum spacing between the left end of the through hole and the corresponding clock signal line is greater than the minimum spacing between the right end of the through hole and the corresponding clock signal line; or the minimum spacing between the left end of the through hole and the corresponding clock signal line is less than the minimum spacing between the right end of the through hole and the corresponding clock signal line.

9. The display panel according to claim 1, characterized in that, The through holes include first through holes corresponding to two adjacent clock signal lines and second through holes corresponding to one clock signal line. Along a first direction, in two adjacent columns of the through holes, one end of a column of through holes close to the other column of through holes and one end of the other column of through holes are located on the same straight line.

10. The display panel according to claim 9, characterized in that, The first through holes are symmetrically arranged with respect to the center line of the portion of the low-potential signal line located between two adjacent clock signal lines, and the width of the portion of the second through holes extending beyond the clock signal lines is greater than the maximum offset of the through holes.

11. The display panel according to claim 10, characterized in that, One end of the through hole corresponding to one clock signal line and one end of the through hole corresponding to the other clock signal line are respectively located on the center lines of the two clock signal lines.

12. The display panel according to claim 9, characterized in that, Among the first through holes and the second through holes corresponding to the same clock signal line, the overlapping area of one second through hole and the corresponding clock signal line is smaller than the overlapping area of one first through hole and the corresponding clock signal line, and the overlapping area of the other second through hole and the corresponding clock signal line is greater than the overlapping area of the other first through hole and the corresponding clock signal line. Moreover, the overlapping areas of any first through hole and the two adjacent corresponding clock signal lines are not equal.

13. The display panel according to claim 9, characterized in that, The display panel includes two sets of first scanning driving units arranged symmetrically. Each set of first scanning driving units includes four clock signal lines. The through holes include two columns of second through holes and three columns of first through holes, and the three columns of first through holes are located between the two columns of second through holes.

14. A display device, characterized in that, It includes the display panel according to any one of claims 1 to 13.

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