Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel includes: an array substrate; the opposite substrate is arranged opposite to the array substrate; the liquid crystal layer is located between the array substrate and the opposite substrate; the plurality of spacers are arranged in the liquid crystal layer, each spacer comprises a first sub spacer and a second sub spacer, the first sub spacer is arranged on the array substrate, the second sub spacer is arranged on the opposite substrate, and the first sub spacer and the second sub spacer of each spacer are oppositely arranged; the plurality of first shading patterns are arranged on the opposite substrate, and the first shading patterns are in one-to-one correspondence with the spacers; wherein the orthographic projection of the second sub-spacer on the array substrate covers the orthographic projection of the first sub-spacer on the array substrate, and the orthographic projection of the first shading pattern on the array substrate covers the orthographic projection of the second sub-spacer on the array substrate.

Description

Display panel and display device

[0001] This disclosure claims priority to the PCT patent application filed with the Patent Office of China on October 17, 2023, with application number PCT / CN2023 / 124967 and invention name “Array substrate and preparation method thereof, display panel, and display device”, the entire contents of which are incorporated by reference in this disclosure. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Liquid Crystal Display (LCD) is a display technology that uses liquid crystals as a key component. Liquid crystals have the ability to change their optical properties under the influence of an electric field, enabling the display of images. LCD technology is widely used in various electronic devices, such as computer monitors, televisions, mobile phones, and tablets.

[0004] LCD products usually include an array substrate, a color filter substrate, and a liquid crystal layer arranged between the two. At the same time, PS (Post Spacer, columnar spacer) is often used as a supporting structure in the liquid crystal layer. However, under the influence of external forces, PS often scratches the orientation layer, causing the liquid crystal near the PS to lose its anchoring force and become abnormally oriented, which in turn causes L0 grayscale light leakage near the PS position. Therefore, in the related art, PS is formed on the array substrate and the color filter substrate respectively in the product (the PS on the array substrate side is named XPS). At the same time, in the related art, the sub-pixels of the liquid crystal display device include a thin film transistor and a pixel electrode. A planarization layer is provided between the thin film transistor and the pixel electrode, and the pixel electrode is electrically connected to the thin film transistor through a via hole penetrating the planarization layer.

[0005] In order to avoid the L0 grayscale light leakage problem caused by abnormal orientation of liquid crystal near the flat layer via position, the existing design uses XPS on the array substrate side to fill the flat layer via. This design requires filling the flat layer via first and then forming the XPS boss. In order to better fill the flat layer via, a larger XPS boss is often required. The existing design sets the PS light leakage compensation block on the side of the color filter substrate. Considering the assembly alignment fluctuation between the color filter substrate and the array substrate (1μm-3μm), it is often necessary to design a larger BM package size, further sacrificing the RGB aperture ratio that is already not large enough.

[0006] Summary of the Invention

[0007] A first aspect of an embodiment of the present disclosure provides a display panel, the display panel comprising:

[0008] array substrate;

[0009] an opposite substrate, arranged opposite to the array substrate;

[0010] a liquid crystal layer, located between the array substrate and the opposite substrate;

[0011] a plurality of spacers disposed in the liquid crystal layer, the spacers including a first sub-spacer and a second sub-spacer, the first sub-spacer being disposed on the array substrate, the second sub-spacer being disposed on the counter substrate, and the first sub-spacer and the second sub-spacer of each spacer being disposed opposite to each other;

[0012] a plurality of first light-shielding patterns, arranged on the opposite substrate, wherein the first light-shielding patterns correspond to the spacers one by one;

[0013] The orthographic projection of the second sub-spacer on the array substrate covers the orthographic projection of the first sub-spacer on the array substrate, and the orthographic projection of the first light-shielding pattern on the array substrate covers the orthographic projection of the second sub-spacer on the array substrate.

[0014] Optionally, the array substrate includes:

[0015] a first substrate;

[0016] A plurality of thin film transistors are located on one side of the first substrate, wherein the thin film transistors include a gate, a source, and a drain;

[0017] a planarization layer located on a side of the drain electrode facing away from the first substrate, the planarization layer comprising first via holes corresponding one to one with the thin film transistors, the first via holes exposing at least a portion of a surface of the drain electrode facing away from the first substrate;

[0018] a plurality of first electrodes, located on a side of the planarization layer facing away from the first substrate, the first electrodes being connected to the drain electrode through the first via holes;

[0019] a plurality of first filling portions, located at least in the first via hole and on a side of the first electrode facing away from the first substrate;

[0020] a plurality of second electrodes, located on a side of the first electrode and the first filling portion facing away from the first substrate, the second electrodes being in contact with the first electrode outside the first via hole;

[0021] The orthographic projection of the first sub-spacer on the first base substrate is located within the orthographic projection range of the first filling portion on the first base substrate.

[0022] Optionally, the first sub-spacer and the second sub-spacer are truncated cone-shaped, and the end of the truncated cone-shaped first sub-spacer with a smaller diameter is connected to the end of the truncated cone-shaped second sub-spacer with a smaller diameter.

[0023] Optionally, the diameter of the smaller end of the first sub-spacer is greater than 4 μm.

[0024] Optionally, a diameter of the smaller end of the first sub-spacer is less than or equal to 4 μm.

[0025] Optionally, strip units are provided on both sides of the first sub-spacer, the strip units extend along the first direction, the strip units on both sides are symmetrically distributed about the first sub-spacer, and the strip units of multiple first sub-spacers are independent of each other.

[0026] Optionally, the first substrate includes a display area and a peripheral area surrounding the display area, and the display area includes a plurality of sub-pixel areas arranged in an array along the first direction and the second direction;

[0027] The size of the stripe unit in the first direction is at least the sum of the sizes of the three sub-pixel areas in the first direction;

[0028] The second direction is perpendicular to the first direction.

[0029] Optionally, the cross-sectional shape of the strip-shaped unit in the second direction is trapezoidal.

[0030] Optionally, the array substrate includes a first base substrate and a second light-shielding pattern provided on the first base substrate, and the difference between the maximum dimension of the strip unit in the second direction and the minimum dimension of the strip unit in the second direction is the wrapping size;

[0031] The maximum size of the strip unit in the second direction is the difference between the size of the second light-shielding pattern in the second direction and the package size.

[0032] Optionally, the size of the first sub-spacer in the second direction is larger than the size of the first sub-spacer in the first direction;

[0033] The first direction is perpendicular to the second direction.

[0034] Optionally, the first sub-spacer has an elliptical planar shape.

[0035] Optionally, the first sub-spacer has a rectangular planar shape.

[0036] A second aspect of an embodiment of the present disclosure provides a display panel, the display panel comprising:

[0037] array substrate;

[0038] an opposite substrate, arranged opposite to the array substrate;

[0039] a liquid crystal layer, located between the array substrate and the opposite substrate;

[0040] a plurality of spacers disposed in the liquid crystal layer, the spacers including a first sub-spacer and a second sub-spacer, the first sub-spacer being disposed on the array substrate, the second sub-spacer being disposed on the counter substrate, and the first sub-spacer and the second sub-spacer of each spacer being disposed opposite to each other;

[0041] a plurality of third light-shielding patterns, arranged on the array substrate, wherein the third light-shielding patterns correspond to the spacers one by one;

[0042] The orthographic projection of the first sub-spacer on the array substrate covers the orthographic projection of the second sub-spacer on the array substrate, and the orthographic projection of the third light-shielding pattern on the array substrate covers the orthographic projection of the first sub-spacer on the array substrate.

[0043] Optionally, the array substrate includes:

[0044] a first substrate;

[0045] A plurality of thin film transistors are located on one side of the first substrate, wherein the thin film transistors include a gate, a source, and a drain;

[0046] a planarization layer located on a side of the drain electrode facing away from the first substrate, the planarization layer comprising first via holes corresponding one to one with the thin film transistors, the first via holes exposing at least a portion of a surface of the drain electrode facing away from the first substrate;

[0047] a plurality of first electrodes, located on a side of the planarization layer facing away from the first substrate, the first electrodes being connected to the drain electrode through the first via holes;

[0048] a plurality of first filling portions, located at least in the first via hole and on a side of the first electrode facing away from the first substrate;

[0049] a plurality of second electrodes, located on a side of the first electrode and the first filling portion facing away from the first substrate, the second electrodes being in contact with the first electrode outside the first via hole;

[0050] The orthographic projection of the first sub-spacer on the first base substrate is located within the orthographic projection range of the first filling portion on the first base substrate.

[0051] Optionally, the array substrate further includes:

[0052] a buffer layer, disposed between the first substrate and the thin film transistor;

[0053] The third light-shielding pattern is located between the first base substrate and the buffer layer.

[0054] Optionally, the diameter of the smaller end of the second sub-spacer is greater than 4 μm.

[0055] Optionally, a diameter of the smaller end of the second sub-spacer is less than or equal to 4 μm.

[0056] Optionally, strip units are provided on both sides of the second sub-spacer, the strip units extend along the first direction, the strip units on both sides are symmetrically distributed about the second sub-spacer, and the strip units of multiple second sub-spacers are independent of each other.

[0057] Optionally, the size of the second sub-spacer in the second direction is greater than the size of the second sub-spacer in the first direction;

[0058] The first direction is perpendicular to the second direction.

[0059] Optionally, the second sub-spacer has an elliptical planar shape.

[0060] Optionally, the second sub-spacer has a rectangular planar shape.

[0061] A third aspect of an embodiment of the present disclosure provides a display device, which includes the display panel provided in the first aspect of the embodiment of the present disclosure, or includes the display panel provided in the second aspect of the embodiment of the present disclosure.

[0062] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0064] FIG1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure (only the array substrate is shown);

[0065] FIG2 is a schematic diagram of the structure of a single sub-pixel in a display panel provided by an embodiment of the present disclosure;

[0066] FIG3 is a schematic structural diagram of the BB' section in FIG2;

[0067] FIG4 is a schematic diagram showing the distribution of spacers in a display panel provided by an embodiment of the present disclosure;

[0068] 5 is a schematic diagram of projections of a first sub-spacer, a second sub-spacer, and a first light-shielding pattern on an array substrate in a display panel provided by an embodiment of the present disclosure;

[0069] FIG6 is a schematic structural diagram of the CC' section (left) and the DD' section (right) in FIG5;

[0070] FIG7 is a schematic structural diagram of a first sub-spacer having strip-shaped units provided by an embodiment of the present disclosure;

[0071] 8 is a schematic diagram of projections of a first sub-spacer, a second sub-spacer, and a first light-shielding pattern having strip-shaped units on an array substrate in a display panel provided by an embodiment of the present disclosure;

[0072] FIG9 is a schematic structural diagram of the FF' section (left) and the EE' section (right) in FIG8 ;

[0073] FIG10 is a schematic diagram of the distribution of a first sub-spacer having strip-shaped units provided by an embodiment of the present disclosure;

[0074] FIG11 is a schematic structural diagram of a first sub-spacer having strip-shaped units and a rectangular planar shape provided by an embodiment of the present disclosure;

[0075] 12 is a schematic diagram of projections of a first sub-spacer, a second sub-spacer, and a first light-shielding pattern having strip-shaped units and a rectangular planar shape on an array substrate in a display panel provided by an embodiment of the present disclosure;

[0076] FIG13 is a schematic structural diagram of the H-H' section (left) and the G-G' section (right) in FIG12;

[0077] FIG14 is a schematic structural diagram of a first sub-spacer having strip-shaped units and an elliptical planar shape provided by an embodiment of the present disclosure;

[0078] FIG15 is a schematic diagram of projections of a first sub-spacer, a second sub-spacer, and a first light-shielding pattern having strip-shaped units and an elliptical planar shape on an array substrate in a display panel provided by an embodiment of the present disclosure;

[0079] FIG16 is a schematic structural diagram of the JJ' section (left) and the II' section (right) in FIG15;

[0080] FIG17 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0081] FIG18 is a schematic diagram of projections of a first sub-spacer, a second sub-spacer, and a third light-shielding pattern on an array substrate in another display panel provided by an embodiment of the present disclosure;

[0082] FIG19 is a schematic structural diagram of the L-L' section (left) and the K-K' section (right) in FIG18;

[0083] FIG20 is a schematic structural diagram of a second sub-spacer having a strip-shaped unit and a rectangular planar shape in a display panel provided by an embodiment of the present disclosure;

[0084] FIG21 is a schematic diagram of projections of a second sub-spacer, a first sub-spacer, and a first light-shielding pattern having strip-shaped units on an array substrate in a display panel provided by an embodiment of the present disclosure;

[0085] FIG22 is a schematic structural diagram of the M-M' section (left) and the N-N' section (right) in FIG21;

[0086] FIG23 is a schematic diagram of projections of a second sub-spacer, a first sub-spacer, and a first light-shielding pattern having strip-shaped units and a rectangular planar shape on an array substrate in a display panel provided by an embodiment of the present disclosure;

[0087] FIG24 is a schematic structural diagram of the R-R' section (left) and the Q-Q' section (right) in FIG23;

[0088] FIG25 is a schematic diagram showing projections of a second sub-spacer having a strip-shaped unit and an elliptical planar shape, a first sub-spacer, and a first light-shielding pattern on an array substrate in a display panel provided by an embodiment of the present disclosure;

[0089] FIG26 is a schematic structural diagram of the PP' section (left) and the O-O' section (right) in FIG25;

[0090] FIG27 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. Specific embodiments

[0091] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0092] 3 , an embodiment of the present disclosure provides a display panel including an array substrate 1 , an opposite substrate 2 disposed opposite to the array substrate 1 , and a liquid crystal layer 3 disposed between the array substrate 1 and the opposite substrate 2 .

[0093] 3 , the array substrate 1 includes a first base substrate 10 , a plurality of thin film transistors 15 , a planarization layer 16 , a plurality of first electrodes 171 , a plurality of first filling portions 162 , and a plurality of second electrodes 172 .

[0094] Specifically, the material of the first base substrate 10 may include glass, and before forming the plurality of thin film transistors 15, a buffer layer 12, a first insulating layer 13, and a light shielding layer 14 may be sequentially formed on the first base substrate 10, wherein the light shielding layer 14 includes a plurality of second light shielding patterns 141. The materials of the buffer layer 12 and the first insulating layer 13 may include silicon nitride or silicon oxide, and the material of the light shielding layer 14 may include a metal material or an alloy material.

[0095] 3 , a plurality of thin film transistors 15 are disposed on one side of the first base substrate 10 . The thin film transistors 15 may include a gate 151 , a source 152 , a drain 153 and an active layer 154 . A first dielectric layer 155 is formed on the side of the light-shielding layer 14 facing away from the first base substrate 10, and an active layer 154 is arranged on the side of the first dielectric layer 155 facing away from the first base substrate 10; a second insulating layer 156 is formed on the side of the active layer 154 facing away from the first base substrate 10, and a gate 151 is formed on the side of the second insulating layer 156 facing away from the first base substrate 10; a second dielectric layer 157 is formed on the side of the gate 151 facing away from the first base substrate 10, and a source electrode 152 is formed on the side of the second dielectric layer 157 facing away from the substrate; a third dielectric layer 158 is formed on the side of the source electrode 152 facing away from the first base substrate 10, and a drain electrode 153 is formed on the side of the third dielectric layer 158 facing away from the substrate; and the source electrode 152 and the drain electrode 153 are respectively electrically connected to the active layer 154 through vias penetrating each film layer.

[0096] 3 , the planarization layer 16 is disposed on the side of the drain electrode 153 away from the first substrate 10 . The planarization layer 16 includes first via holes 161 corresponding to the thin film transistors 15 . The first via holes 161 expose at least a portion of the surface of the drain electrode 153 away from the first substrate 10 .

[0097] 3 , a plurality of first electrodes 171 are located on a side of the planarization layer 16 away from the first base substrate 10 , and the first electrodes 171 are connected to the drain electrode 153 through the first via hole 161 .

[0098] 3 , a plurality of first filling portions 162 are located at least within the first via hole 161 and on the side of the first electrode 171 facing away from the first base substrate 10 . The first filling portions 162 fill the first via hole 161 to form a flat portion in the first via hole 161 region of the planarization layer 16 .

[0099] 3 , the plurality of second electrodes 172 are located on a side of the first electrode 171 and the first filling portion 162 away from the first base substrate 10 , and the second electrodes 172 and the first electrodes 171 are in contact with each other outside the first via hole 161 .

[0100] 3 , a passivation layer 18 is formed on a side of the second electrode 172 away from the first substrate 10 , and a plurality of third electrodes 173 are further formed on a side of the passivation layer 18 away from the first substrate 10 .

[0101] As shown in Figures 1 and 2, in the embodiment of the present disclosure, a first base substrate 10 includes a display area AA and a peripheral area NA surrounding the display area AA. The display area AA includes a plurality of sub-pixel areas 101 arranged in an array along a first direction XX and a second direction YY, and a first signal line 102 located in the peripheral area NA. The sub-pixel area 101 may include a first light-transmitting area 1011, a first light-shielding area 1012, and a second light-shielding area 1013. The first light-shielding area 1012 is located to one side of the first light-transmitting area 1011 in the second direction Y, and the second light-shielding area 1013 is located to one side of the first light-transmitting area 1011 in the first direction X.

[0102] In a specific implementation, the first signal line 102 is electrically connected to the third electrode 173 .

[0103] In a specific implementation, the second electrode 172 serves as a pixel electrode, the first electrode 171 can be considered a connecting electrode between the second electrode 172 and the drain electrode 153, and the third electrode 173 serves as a common electrode. The first signal line 102 provides a common voltage signal to the third electrode 173. The first electrode 171, the second electrode 172, and the third electrode 173 all include a transparent material. The transparent material is, for example, indium tin oxide (ITO).

[0104] As shown in Figure 1, in the embodiment of the present disclosure, the array substrate 1 further includes: a plurality of second signal lines 103 and a plurality of scan lines 104 that cross each other horizontally and vertically; the second signal lines 103 extend from the display area AA to the peripheral area NA along the first direction X, and the scan lines 104 extend from the display area to the peripheral area along the second direction Y; the scan lines 104 are electrically connected to the gate 151 of the thin film transistor 15.

[0105] In a specific implementation, the second signal lines 103 and the scan lines 104 are usually made of metal. The second signal lines 103 and the scan lines 104 in the display area are both located in the first light shielding area 1012, that is, the second signal lines 103 and the scan lines 104 are shielded by the light shielding pattern.

[0106] In a specific implementation, in FIG1 , each scan line 104 corresponds to a row of sub-pixel areas 101 arranged along the first direction XX, and only one scan line 104 is included between two adjacent sub-pixel areas 101 in the second direction YY; the plurality of second signal lines 103 are all data lines, and the second signal lines 103 are electrically connected to the source 152 of the thin film transistor 15 .

[0107] Alternatively, in a specific implementation, a row of sub-pixel areas 101 arranged along the first direction XX may correspond to two scan lines 104, and two scan lines 104 may be included between two adjacent sub-pixel areas 101 in the second direction YY; the plurality of second signal lines 103 may include a plurality of data lines and a plurality of common voltage lines; the data lines and the common voltage lines may be alternately arranged in the first direction X; and the common voltage lines may also be electrically connected to the third electrode 173.

[0108] As shown in Figure 3, in the embodiment of the present disclosure, the array substrate 1 also includes: a plurality of color resists 19 corresponding one-to-one to the sub-pixel areas 101, and the plurality of color resists 19 are located on the side of the planarization layer 16 close to the first base substrate 10; the orthographic projection of the color resist 19 on the first base substrate 10 at least covers the first light-transmitting area 1011.

[0109] The array substrate 1 provided in the embodiment of the present disclosure has a color resist 19 provided on the array substrate 1. When the array substrate 1 is applied to a liquid crystal display panel with a high pixel density, the opposite substrate 2 of the liquid crystal display panel does not need to be provided with the color resist 19, thereby avoiding the problem of color mixing and cross-coloring that is easily caused by providing the color resist 19 on the opposite substrate 2, thereby improving the display effect.

[0110] In some embodiments, the multiple sub-pixel areas 101 include multiple red sub-pixel areas 101, multiple blue sub-pixel areas 101, and multiple green sub-pixel areas 101; accordingly, the multiple color resists 19 include: red color resists 19 corresponding to the red sub-pixel areas 101, blue color resists 19 corresponding to the blue sub-pixel areas 101, and green color resists 19 corresponding to the green sub-pixel areas 101.

[0111] As shown in FIG3 , in the embodiment of the present disclosure, the counter substrate 2 includes a second base substrate 20 and a plurality of first light-shielding patterns 21 disposed on the second base substrate 20. The first light-shielding patterns 21 correspond one-to-one to the thin-film transistors 15. Furthermore, in the display area, the orthographic projections of the first light-shielding patterns 21 on the first base substrate 10 overlap with the first light-shielding regions 1012 and second light-shielding regions 1013 of the sub-pixel region 101. The orthographic projections of the first light-shielding patterns 21 on the first base substrate 10 cover the orthographic projections of the second light-shielding patterns 141 on the first base substrate 10.

[0112] 3 , in the embodiment of the present disclosure, an interlayer dielectric layer 23 is further provided on a side of the first light-shielding pattern 21 away from the second base substrate 20 .

[0113] As shown in Figure 3, in the embodiment of the present disclosure, the display panel further includes a plurality of spacers 4 disposed in the liquid crystal layer 3. The spacers 4 include a first sub-spacer 41 and a second sub-spacer 42. The first sub-spacer 41 is disposed on the array substrate 1, that is, on the side of the passivation layer 18 facing away from the first base substrate 10; the second sub-spacer 42 is disposed on the counter substrate 2, that is, on the second base substrate 20. Furthermore, the first sub-spacer 41 and the second sub-spacer 42 of each spacer 4 are disposed opposite each other.

[0114] 4 , the first sub-spacer 41 and the second sub-spacer 42 both adopt a single independent island structure design.

[0115] 3 and 5 , in the embodiment of the present disclosure, the orthographic projection of the second sub-spacer 42 on the array substrate 1 covers the orthographic projection of the first sub-spacer 41 on the array substrate 1, and the orthographic projection of the first light-shielding pattern 21 on the array substrate 1 covers the orthographic projection of the second sub-spacer 42 on the array substrate 1. Furthermore, the orthographic projection of the first sub-spacer 41 on the first base substrate 10 is within the orthographic projection range of the first filling portion 162 on the first base substrate 10.

[0116] That is to say, in the embodiment of the present disclosure, the second sub-spacer 42 completely blocks the first sub-spacer 41, and at the same time, the first shading pattern 21 completely blocks the second sub-spacer 42. In this way, the embodiment of the present disclosure adopts a spacer structure that is larger at the top and smaller at the bottom, and then adopts the first shading pattern 21 to block light leakage at the spacer position, so that the light leakage wrapping distance of the first shading pattern 21 to the first sub-spacer 41 is larger, thereby minimizing the compensation size of the first shading pattern 21, and further ensuring that the first shading pattern 21 has the least effect on the aperture ratio of the sub-pixel. Therefore, the display panel provided by the embodiment of the present disclosure can be applied to high-pixel-density display products, such as high-pixel-density VR (Virtual Reality) / AR (Augmented Reality) / MR (Mixed Reality) display products.

[0117] In addition, in related technologies, a horizontal strip structure design is also used to prevent spacers from falling and reduce fluctuations in PS supporting force. However, relevant experiments have shown that this entire strip structure setting hinders the fluidity of the orientation layer and liquid crystal, resulting in various display moiré problems in display products.

[0118] In the disclosed embodiment, by setting the first sub-spacer 41 on the first filling portion 162, the spacer can be provided with support stability. Therefore, the strip structure design is eliminated in the disclosed embodiment, thereby avoiding the display moiré problem caused by uneven flow of the orientation layer and liquid crystal.

[0119] As shown in Figures 5 and 6, in one embodiment, the first sub-spacer 41 and the second sub-spacer 42 are both truncated cone-shaped. That is, from a top-down perspective, the first sub-spacer 41 and the second sub-spacer 42 are circular in shape, and the cross-sections of the first sub-spacer 41 and the second sub-spacer 42 are both trapezoidal. Furthermore, the smaller diameter end of the truncated cone-shaped first sub-spacer 41 is connected to the smaller diameter end of the truncated cone-shaped second sub-spacer 42.

[0120] It should be noted that, considering the fluctuations in film alignment and size, the relative displacement of the contact portion between the first sub-spacer 41 and the second sub-spacer 42 is 2μm-3μm (related to the equipment process capabilities). Therefore, if the diameter of the smaller end of the first sub-spacer 41 (i.e., the end in contact with the second sub-spacer 42) is greater than 4μm, the strip structure can be omitted. However, if the diameter of the smaller end of the first sub-spacer 41 is less than or equal to 4μm, process fluctuations may cause relative displacement between the first sub-spacer 41 and the second sub-spacer 42, which may result in only half of the first sub-spacer 41 providing support, resulting in significant fluctuations in the spacer support force.

[0121] To this end, referring to FIG. 7 , in an optional implementation, the present disclosure further provides a display panel, in which strip-shaped units 43 are provided on both sides of the first sub-spacer 41 .

[0122] Specifically, as shown in Figures 7, 8, and 9, the strip units 43 extend along the first direction X, and the strip units 43 on both sides are symmetrically distributed about the first sub-spacer 41. In the embodiment of the present disclosure, the strip units 43 and the first sub-spacer 41 can be integrally formed, so the thickness of the strip units 43 is the same as the thickness of the first sub-spacer 41. That is, in this embodiment, the first sub-spacer 41 includes a central circular portion and strip portions on both sides of the circular portion, wherein the circular portion is in contact with the second sub-spacer 42.

[0123] Such a design allows the first sub-spacer 41 and the second sub-spacer 42 to have more relative displacement space in the first direction X, that is, when the second sub-spacer 42 is displaced relative to the first sub-spacer 41 by more than half the size of the first sub-spacer 41, the strip portion can still provide a certain supporting force, thereby reducing the fluctuation of the supporting force of the entire spacer.

[0124] Meanwhile, as shown in Figure 10 , in the disclosed embodiment, the strip-shaped units 43 of the plurality of first sub-spacers 41 are independent of one another, that is, the strip-shaped units 43 are not connected to one another but are isolated from one another. Such discontinuous strip-shaped units 43 provide space for the alignment layer and the flow of liquid crystals, thereby reducing the problem of display moiré.

[0125] In the embodiment of the present disclosure, the total size of the first sub-spacer 41 and the strip-shaped units 43 on both sides in the first direction X is at least the sum of the sizes of the three sub-pixel areas 101 in the first direction X.

[0126] In the disclosed embodiment, the cross-sectional shape of the strip unit 43 in the second direction Y is a trapezoid, with the wider side of the trapezoidal strip unit 43 closer to the first base substrate 10, and the smaller side of the trapezoidal strip unit 43 closer to the second base substrate 20. Furthermore, the difference between the maximum dimension of the strip unit 43 in the second direction Y and the minimum dimension of the strip unit 43 in the second direction Y is the package size. The maximum dimension of the strip unit 43 in the second direction Y is the difference between the dimension of the second light-shielding pattern 141 in the second direction Y and the package size. This allows the strip unit 43 to fall within the second light-shielding pattern 141 in the second direction Y, thereby reducing light leakage.

[0127] The display panel provided by this embodiment can ensure that the first shading pattern 21 has minimal impact on the aperture ratio of the sub-pixel while allowing the first sub-spacer 41 and the second sub-spacer 42 to have more relative displacement space in the first direction X, thereby reducing the fluctuation of the supporting force of the entire spacer.

[0128] 11 and 14 , in an optional implementation, the present disclosure further provides a display panel, in which the dimension of the first sub-spacer 41 in the second direction Y is greater than the dimension of the first sub-spacer 41 in the first direction X.

[0129] Specifically, this embodiment further optimizes the shape of the first sub-spacer 41 by adding the strip-shaped units 43. Specifically, the first sub-spacer 41 is designed as a long strip, shorter in the horizontal direction and longer in the vertical direction. The horizontal direction is the first direction X, and the vertical direction is the second direction Y. However, in practical applications, the extension direction of the first sub-spacer 41 can be perpendicular to the extension direction of the strip-shaped units 43.

[0130] Such a design allows the first sub-spacer 41 and the second sub-spacer 42 to have more relative sliding space in the second direction Y, thereby better reducing the fluctuation of the supporting force and improving the supporting effect of the spacers.

[0131] 11 , 12 and 13 , in one embodiment, viewed from above, the planar shape of the first sub-spacer 41 can be set to a rectangle, and the dimension of the rectangular first sub-spacer 41 in the second direction Y is larger than the dimension of the rectangular first sub-spacer 41 in the first direction X, so that the first sub-spacer 41 and the second sub-spacer 42 have more relative sliding space in a direction perpendicular to the strip unit 43.

[0132] As shown in Figures 14, 15, and 16, in one embodiment, the planar shape of the first sub-spacer 41 can be set to be elliptical when viewed from above, and the dimension of the elliptical first sub-spacer 41 in the second direction Y is larger than the dimension of the elliptical first sub-spacer 41 in the first direction X. Compared with the rectangular first sub-spacer 41, the elliptical first sub-spacer 41 can further reduce the contact area between the first sub-spacer 41 and the second sub-spacer 42. Therefore, by increasing the density of the spacers, the support force of the first sub-spacer 41 and the second sub-spacer 42 in a single spacer is reduced. This design can further reduce the impact of process fluctuations on the spacer support force.

[0133] In addition, in related experiments, the inventors of the present disclosure also found that the light leakage blocking block (i.e., the first light blocking pattern 21) of the spacer under a large viewing angle will produce a viewing angle displacement, causing the opening ratio of the sub-pixel to change, resulting in the problem of color point offset of the L255 picture.

[0134] To solve this problem, based on the same inventive concept, as shown in Figure 17, an embodiment of the present disclosure also provides a display panel, which includes an array substrate 1, an opposing substrate 2 arranged opposite to the array substrate 1, and a liquid crystal layer 3 arranged between the array substrate 1 and the opposing substrate 2.

[0135] 17 , the array substrate 1 includes a first base substrate 10 , a plurality of thin film transistors 15 , a planarization layer 16 , a plurality of first electrodes 171 , a plurality of first filling portions 162 , and a plurality of second electrodes 172 .

[0136] Specifically, the material of the first base substrate 10 may include glass, and before forming the plurality of thin film transistors 15, a buffer layer 12, a first insulating layer 13, and a light shielding layer 14 may be sequentially formed on the first base substrate 10, wherein the light shielding layer 14 includes a plurality of second light shielding patterns 141. The materials of the buffer layer 12 and the first insulating layer 13 may include silicon nitride or silicon oxide, and the material of the light shielding layer 14 may include a metal material or an alloy material.

[0137] 17 , a plurality of thin film transistors 15 are disposed on one side of the first base substrate 10 . The thin film transistors 15 may include a gate 151 , a source 152 , a drain 153 and an active layer 154 . A first dielectric layer 155 is formed on the side of the light-shielding layer 14 facing away from the first base substrate 10, and an active layer 154 is arranged on the side of the first dielectric layer 155 facing away from the first base substrate 10; a second insulating layer 156 is formed on the side of the active layer 154 facing away from the first base substrate 10, and a gate 151 is formed on the side of the second insulating layer 156 facing away from the first base substrate 10; a second dielectric layer 157 is formed on the side of the gate 151 facing away from the first base substrate 10, and a source electrode 152 is formed on the side of the second dielectric layer 157 facing away from the substrate; a third dielectric layer 158 is formed on the side of the source electrode 152 facing away from the first base substrate 10, and a drain electrode 153 is formed on the side of the third dielectric layer 158 facing away from the substrate; and the source electrode 152 and the drain electrode 153 are respectively electrically connected to the active layer 154 through vias penetrating each film layer.

[0138] 17 , the planarization layer 16 is disposed on the side of the drain electrode 153 away from the first substrate 10 . The planarization layer 16 includes first via holes 161 corresponding to the thin film transistors 15 . The first via holes 161 expose at least a portion of the surface of the drain electrode 153 away from the first substrate 10 .

[0139] 17 , a plurality of first electrodes 171 are located on a side of the planarization layer 16 away from the first base substrate 10 . The first electrodes 171 are connected to the drain electrode 153 through the first via holes 161 .

[0140] 17 , a plurality of first filling portions 162 are located at least within the first via hole 161 and on the side of the first electrode 171 facing away from the first base substrate 10 . The first filling portions 162 fill the first via hole 161 to form a flat portion in the first via hole 161 region of the planarization layer 16 .

[0141] 17 , the plurality of second electrodes 172 are located on a side of the first electrode 171 and the first filling portion 162 away from the first base substrate 10 , and the second electrodes 172 and the first electrodes 171 are in contact with each other outside the first via hole 161 .

[0142] 17 , at the same time, a passivation layer 18 is formed on the side of the second electrode 172 away from the first base substrate 10 , and a plurality of third electrodes 173 are further formed on the side of the passivation layer 18 away from the first base substrate 10 .

[0143] 17 , in this embodiment, the array substrate 1 further includes a plurality of third light-shielding patterns 105 . The third light-shielding patterns 105 are disposed between the first base substrate 10 and the buffer layer 12 .

[0144] 17 , in the embodiment of the present disclosure, the counter substrate 2 includes a second base substrate 20 and an interlayer dielectric layer 23 disposed on one side of the second base substrate 20 .

[0145] As shown in FIG17 , in the embodiment of the present disclosure, the display panel further includes a plurality of spacers 4 disposed in the liquid crystal layer 3. The spacers 4 include a first sub-spacer 41 and a second sub-spacer 42. The first sub-spacer 41 is disposed on the array substrate 1, that is, on the side of the passivation layer 18 facing away from the first base substrate 10; the second sub-spacer 42 is disposed on the counter substrate 2, that is, on the second base substrate 20. Furthermore, the first sub-spacer 41 and the second sub-spacer 42 of each spacer 4 are disposed opposite each other.

[0146] 19 and 20 , in the disclosed embodiment, the orthographic projection of the first sub-spacer 41 on the array substrate 1 covers the orthographic projection of the second sub-spacer 42 on the array substrate 1, and the orthographic projection of the third light-shielding pattern 105 on the array substrate 1 covers the orthographic projection of the first sub-spacer 41 on the array substrate 1. Furthermore, the orthographic projection of the first sub-spacer 41 on the first base substrate 10 is within the orthographic projection range of the first filling portion 162 on the first base substrate 10.

[0147] That is, in the disclosed embodiment, the first sub-spacer 41 completely blocks the second sub-spacer 42, while the third light-shielding pattern 105 completely blocks the first sub-spacer 41. Thus, the disclosed embodiment employs a spacer structure that is smaller at the top and larger at the bottom, and employs the third light-shielding pattern 105 to block light leakage from the spacer position. This allows the first light-shielding pattern 21 to provide a greater distance for light leakage from the first sub-spacer 41, thereby minimizing the compensation size of the third light-shielding pattern 105 and ensuring that the third light-shielding pattern 105 has the least impact on the sub-pixel aperture ratio. This also avoids the problem of viewing angle displacement caused by the light-shielding pattern at a wide viewing angle, thereby avoiding the problem of L255 image color point shift caused by changes in the sub-pixel aperture ratio.

[0148] 19 and 20 , similarly, in this embodiment, the first sub-spacer 41 and the second sub-spacer 42 are both truncated cone-shaped, with the smaller end of the truncated cone-shaped first sub-spacer 41 connected to the smaller end of the truncated cone-shaped second sub-spacer 42. Therefore, when the smaller end of the second sub-spacer 42 has a diameter greater than 4 μm, the first sub-spacer 41 and the second sub-spacer 42 can be designed as a single, independent island structure.

[0149] When the diameter of the smaller end of the second sub-spacer 42 is less than or equal to 4 μm, strip-shaped units 43 are provided on both sides of the second sub-spacer 42. The strip-shaped units 43 extend along the first direction X, and the strip-shaped units 43 on both sides are symmetrically distributed with respect to the second sub-spacer 42. In the disclosed embodiment, the strip-shaped units 43 and the second sub-spacer 42 can be integrally formed, and thus the thickness of the strip-shaped units 43 is the same as that of the second sub-spacer 42. That is, in this embodiment, the second sub-spacer 42 includes a central circular portion and strip-shaped portions on both sides of the circular portion, wherein the circular portion contacts the first sub-spacer 41.

[0150] 23 and 25 , in an optional implementation, the present disclosure further provides a display panel, in which the size of the second sub-spacer 42 in the second direction Y is greater than the size of the second sub-spacer 42 in the first direction X.

[0151] Specifically, this embodiment further optimizes the shape of the second sub-spacer 42 by adding the strip-shaped units 43. Specifically, the second sub-spacer 42 is designed as a long strip, shorter in the horizontal direction and longer in the vertical direction. The horizontal direction is the first direction X, and the vertical direction is the second direction Y. However, in practical applications, the second sub-spacer 42 can be extended perpendicularly to the direction of extension of the strip-shaped units 43.

[0152] Such a design allows the first sub-spacer 41 and the second sub-spacer 42 to have more relative sliding space in the second direction Y, thereby better reducing the fluctuation of the supporting force and improving the supporting effect of the spacers.

[0153] In one embodiment, as shown in Figures 23 and 24, from a top view, the planar shape of the second sub-spacer 42 can be set to a rectangle, and the size of the rectangular second sub-spacer 42 in the second direction Y is larger than the size of the rectangular second sub-spacer 42 in the first direction X, so that the first sub-spacer 41 and the second sub-spacer 42 can have more relative sliding space in the direction perpendicular to the strip unit 43.

[0154] In one embodiment, as shown in Figures 25 and 26 , the planar shape of the second sub-spacer 42 can be set to be elliptical when viewed from above, and the dimension of the elliptical second sub-spacer 42 in the second direction Y is larger than the dimension of the elliptical second sub-spacer 42 in the first direction X. Compared with the rectangular second sub-spacer 42, the elliptical first sub-spacer 41 can further reduce the contact area between the first sub-spacer 41 and the second sub-spacer 42. Therefore, by increasing the density of the spacers, the support force of the first sub-spacer 41 and the second sub-spacer 42 in a single spacer is reduced. This design can further reduce the impact of process fluctuations on the spacer support force.

[0155] An embodiment of the present disclosure provides a display device, as shown in FIG27 , which includes a display panel provided by an embodiment of the present disclosure.

[0156] [Corrected 11.09.2024 according to Rule 91] In some embodiments, the display device provided in the embodiments of the present disclosure may further include a backlight module 5 located on the light incident side of the array substrate 1, as shown in FIG27 . The backlight module 5 may be a direct-lit backlight module or an edge-lit backlight module.

[0157] In a specific implementation, the side-entry backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet stacked on the light-emitting side of the matrix light source, a diffuser, and a brightening film, etc. The reflective sheet includes an opening arranged directly opposite the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.). Submillimeter or even micron-scale micro light-emitting diodes are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, it has a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. Moreover, when micro-light-emitting diodes are used as backlight sources, more sophisticated dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0158] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the above-described display panel embodiments, and any repetitive details will not be repeated.

[0159] To sum up, the display panel and display device provided by the embodiments of the present disclosure adopt a spacer structure that is larger at the top and smaller at the bottom, and then adopt a first light-shielding pattern 21 to block light leakage at the spacer position, so that the light leakage wrapping distance of the first light-shielding pattern 21 to the first sub-spacer 41 is larger; or, adopt a spacer structure that is smaller at the top and larger at the bottom, and then adopt a third light-shielding pattern 105 to block light leakage at the spacer position, so that the light leakage wrapping distance of the third light-shielding pattern 105 to the first sub-spacer 41 is larger; thereby, the compensation size of the first light-shielding pattern 21 or the third light-shielding pattern 105 can be minimized, thereby ensuring that the first light-shielding pattern 21 or the third light-shielding pattern 105 has the least effect on the aperture ratio of the sub-pixel.

[0160] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0161] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0162] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0163] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display panel, wherein: The display panel comprises: An array substrate; an opposite substrate, arranged opposite to the array substrate; A liquid crystal layer, located between the array substrate and the opposite substrate; A plurality of spacers are arranged in the liquid crystal layer, the spacers include a first sub-spacer and a second sub-spacer, the first sub-spacer is arranged on the array substrate, the second sub-spacer is arranged on the opposite substrate, and the first sub-spacer and the second sub-spacer of each spacer are arranged opposite to each other; A plurality of first light shielding patterns are arranged on the opposite substrate, wherein the first light shielding patterns correspond to the spacers one by one; The orthographic projection of the second sub-spacer on the array substrate covers the orthographic projection of the first sub-spacer on the array substrate, and the orthographic projection of the first shading pattern on the array substrate covers the orthographic projection of the second sub-spacer on the array substrate.

2. The display panel according to claim 1, wherein: The array substrate comprises: a first substrate base plate; A plurality of thin film transistors are located on one side of the first substrate, and the thin film transistors include a gate, a source and a drain; a planarization layer, located on a side of the drain electrode away from the first substrate, the planarization layer comprising first via holes corresponding to the thin film transistors one by one, the first via holes exposing at least a portion of a surface of the drain electrode away from the first substrate; A plurality of first electrodes are located on a side of the planarization layer away from the first substrate, and the first electrodes are connected to the drain electrode through the first via holes; a plurality of first filling portions, at least located in the first via hole and located on a side of the first electrode away from the first substrate; A plurality of second electrodes are located on a side of the first electrode and the first filling portion away from the first substrate, and the second electrodes are in contact with the first electrode outside the first via hole; The orthographic projection of the first sub-spacer on the first base substrate is located within the orthographic projection range of the first filling portion on the first base substrate.

3. The display panel according to claim 1, wherein: The first sub-spacer and the second sub-spacer are truncated cone-shaped, and an end of the truncated cone-shaped first sub-spacer with a smaller diameter is connected to an end of the truncated cone-shaped second sub-spacer with a smaller diameter.

4. The display panel according to claim 3, wherein: The diameter of the smaller end of the first sub-spacer is greater than 4 μm.

5. The display panel according to claim 3, wherein: The diameter of the end of the first sub-spacer with a smaller diameter is less than or equal to 4 μm.

6. The display panel according to claim 5, wherein: Strip units are arranged on both sides of the first sub-spacer, and the strip units extend along a first direction. The strip units on both sides are symmetrically distributed about the first sub-spacer, and the strip units of a plurality of the first sub-spacers are independent of each other.

7. The display panel according to claim 6, wherein: The first substrate includes a display area and a peripheral area surrounding the display area, and the display area includes a plurality of sub-pixel areas arranged in an array along the first direction and the second direction; The total size of the first sub-spacer and the strip-shaped unit in the first direction is at least the sum of the sizes of the three sub-pixel areas in the first direction; The second direction is perpendicular to the first direction.

8. The display panel according to claim 7, wherein: The cross-sectional shape of the strip-shaped unit in the second direction is a trapezoid.

9. The display panel according to claim 8, wherein: The array substrate comprises a first base substrate and a second light shielding pattern arranged on the first base substrate, and the difference between the maximum size of the strip unit in the second direction and the minimum size of the strip unit in the second direction is the package size; The maximum size of the strip unit in the second direction is the difference between the size of the second shading pattern in the second direction and the package size.

10. The display panel according to claim 6, wherein: The size of the first sub-spacer in the second direction is greater than the size of the first sub-spacer in the first direction; The first direction is perpendicular to the second direction.

11. The display panel according to claim 10, wherein: The plane shape of the first sub-spacer is an ellipse.

12. The display panel according to claim 1, wherein: The first sub-spacer has a rectangular planar shape.

13. A display panel, wherein: The display panel comprises: An array substrate; an opposite substrate, arranged opposite to the array substrate; A liquid crystal layer, located between the array substrate and the opposite substrate; A plurality of spacers are arranged in the liquid crystal layer, the spacers include a first sub-spacer and a second sub-spacer, the first sub-spacer is arranged on the array substrate, the second sub-spacer is arranged on the opposite substrate, and the first sub-spacer and the second sub-spacer of each spacer are arranged opposite to each other; A plurality of third light shielding patterns are arranged on the array substrate, and the third light shielding patterns correspond to the spacers one by one; The orthographic projection of the first sub-spacer on the array substrate covers the orthographic projection of the second sub-spacer on the array substrate, and the orthographic projection of the third shading pattern on the array substrate covers the orthographic projection of the first sub-spacer on the array substrate.

14. The display panel according to claim 13, wherein: The array substrate comprises: a first substrate base plate; A plurality of thin film transistors are located on one side of the first substrate, and the thin film transistors include a gate, a source and a drain; a planarization layer, located on a side of the drain electrode away from the first substrate, the planarization layer comprising first via holes corresponding to the thin film transistors one by one, the first via holes exposing at least a portion of a surface of the drain electrode away from the first substrate; A plurality of first electrodes are located on a side of the planarization layer away from the first substrate, and the first electrodes are connected to the drain electrode through the first via holes; a plurality of first filling portions, at least located in the first via hole and located on a side of the first electrode away from the first substrate; A plurality of second electrodes are located on a side of the first electrode and the first filling portion away from the first substrate, and the second electrodes are in contact with the first electrode outside the first via hole; The orthographic projection of the first sub-spacer on the first base substrate is located within the orthographic projection range of the first filling portion on the first base substrate.

15. The display panel according to claim 14, wherein: The array substrate further includes: A buffer layer, disposed between the first substrate and the thin film transistor; The third light shielding pattern is located between the first base substrate and the buffer layer.

16. The display panel according to claim 13, wherein: The diameter of the end with the smaller diameter of the second sub-spacer is greater than 4 μm.

17. The display panel according to claim 13, wherein: The diameter of the end of the second sub-spacer with a smaller diameter is less than or equal to 4 μm.

18. The display panel according to claim 17, wherein: Strip units are arranged on both sides of the second sub-spacer, and the strip units extend along the first direction. The strip units on both sides are symmetrically distributed about the second sub-spacer, and the strip units of the plurality of second sub-spacers are independent of each other.

19. The display panel according to claim 18, wherein: The size of the second sub-spacer in the second direction is greater than the size of the second sub-spacer in the first direction; The first direction is perpendicular to the second direction.

20. The display panel according to claim 19, wherein: The plane shape of the second sub-spacer is an ellipse.

21. The display panel according to claim 19, wherein: The second sub-spacer has a rectangular planar shape.

22. A display device, wherein: Includes the display panel as described in any one of claims 1-12, or includes the display panel as described in any one of claims 13-21.

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