Array substrate and preparation method thereof, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a preparation method of the array substrate, a display panel and a display device. The array substrate comprises: a first substrate; the plurality of thin film transistors are positioned on one side of the first substrate; the thin film transistor comprises a grid electrode, a source electrode and a drain electrode; the planarization layer is located on the side, away from the first substrate, of the drain electrode and comprises first via holes in one-to-one correspondence with the thin film transistors; the first via hole exposes at least partial area of the surface of one side, far away from the first substrate, of the drain electrode; the multiple first electrodes are located on the side, away from the first substrate, of the planarization layer; the first electrode is connected with the drain electrode through the first via hole; the multiple first filling parts are at least located in the first via holes and located on the sides, away from the first substrate, of the first electrodes; the plurality of second electrodes are positioned on one side, deviating from the first substrate, of the first electrode and the first filling part; the second electrode and the first electrode are in contact with each other outside the first via hole.

Description

Array substrate and manufacturing method thereof, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel, and a display device. Background Art

[0002] Liquid crystal display devices have the advantages of light weight and low power consumption and are therefore widely used in modern information equipment.

[0003] A subpixel in a liquid crystal display device includes a thin-film transistor (TFT) and a pixel electrode. A planarization layer is interposed between the TFT and the pixel electrode, and the pixel electrode is electrically connected to the TFT via a via that penetrates the planarization layer. However, the presence of the via in the planarization layer can cause turbulence in the liquid crystal within the via and its surrounding area, leading to light leakage. Therefore, a light-shielding pattern needs to shield the via and the surrounding area from turbulent liquid crystals. This large size of the light-shielding pattern affects the aperture ratio of the subpixel.

[0004] Summary of the Invention

[0005] An embodiment of the present disclosure provides an array substrate, the array substrate comprising:

[0006] a first substrate;

[0007] A plurality of thin film transistors are located on one side of the first substrate; the thin film transistors include: a gate, a source and a drain;

[0008] a planarization layer located on a side of the drain electrode facing away from the first substrate, and comprising first via holes corresponding one to one with the thin film transistors; the first via holes exposing at least a portion of the surface of the drain electrode facing away from the first substrate;

[0009] A plurality of first electrodes are located on a side of the planarization layer away from the first substrate; the first electrodes are connected to the drain electrode through a first via hole;

[0010] a plurality of first filling portions, at least located in the first via hole and located on a side of the first electrode facing away from the first base substrate;

[0011] A plurality of second electrodes are located on a side of the first electrode and the first filling portion away from the first base substrate; the second electrodes are in contact with the first electrodes outside the first via hole.

[0012] In some embodiments, the first substrate includes a display area and a peripheral area surrounding the display area; the display area includes a plurality of sub-pixel areas arranged in an array along a first direction and a second direction; the sub-pixel area includes a first light-transmitting area and a first light-shielding area, and the first light-shielding area is located on one side of the first light-transmitting area in the second direction;

[0013] The orthographic projection of the second electrode on the first base substrate overlaps with the first light-transmitting area;

[0014] The orthographic projection of the first via hole on the first substrate falls into the first light-shielding area;

[0015] The orthographic projection of the first filling portion on the first base substrate at least includes a portion falling into the first light-shielding area.

[0016] In some embodiments, the orthographic projection of the first electrode on the first substrate overlaps with the first light-transmitting area;

[0017] In the first light-transmitting area and in the second direction, the width of the second electrode is greater than the width of the first electrode.

[0018] In some embodiments, an orthographic projection of the second electrode on the first base substrate overlaps with the first light-shielding region.

[0019] In some embodiments, in the second direction, the first electrode and the second electrode that are in contact with each other are arranged in a staggered manner.

[0020] In some embodiments, the first electrode includes: a first portion located outside the first via hole and a second portion located on one side of the first portion in the second direction and at least a portion of the second portion located within the first via hole;

[0021] The second electrode includes: a third portion located outside the first via hole and a fourth portion located on one side of the third portion in the second direction and at least a portion of which is located within the first via hole;

[0022] In the second direction, the width of the first portion is smaller than the width of the third portion, and the width of the second portion is larger than the width of the fourth portion.

[0023] In some embodiments, the second portion completely covers the surface of the drain electrode exposed by the first via hole.

[0024] In some embodiments, in the second direction, the orthographic projection of the region between two adjacent second electrodes on the first base substrate overlaps with both the first light-transmitting region and the first light-shielding region.

[0025] In some embodiments, the second electrode further includes: a fifth portion located on a side of the third portion away from the fourth portion in the second direction;

[0026] The orthographic projection of the fifth portion on the first substrate falls into the first light-shielding area;

[0027] In the second direction, the orthographic projection of the gap between two adjacent second electrodes on the first base substrate falls within the orthographic projection of the first filling portion on the first base substrate.

[0028] In some embodiments, a surface of the first filling portion facing away from the first base substrate and a surface of the first portion facing away from the first base substrate are substantially located in the same plane.

[0029] In some embodiments, in the first direction, the width of the first electrode is substantially equal to the width of the second electrode;

[0030] The first electrode and the second electrode are located on the same side and their edges extending along the second direction substantially overlap.

[0031] In some embodiments, the array substrate further includes:

[0032] A plurality of color resists correspond to the sub-pixel areas one by one and are located on a side of the planarization layer close to the first base substrate; the orthographic projection of the color resists on the first base substrate at least covers the first light-transmitting area.

[0033] In some embodiments, the color resist and the drain electrode are located in the same layer;

[0034] The orthographic projection of the color resist on the first base substrate does not overlap with the orthographic projection of the drain on the first base substrate, and the orthographic projection of the color resist on the first base substrate does not overlap with the orthographic projection of the first via hole on the first base substrate.

[0035] In some embodiments, the source is located on the side of the drain facing the first base substrate; the array substrate further includes a first interlayer insulating layer between the source and the drain; the color resist and the drain are located between the first interlayer insulating layer and the planarization layer.

[0036] In some embodiments, the array substrate further includes: a first signal line located in the peripheral area, and a plurality of second filling portions; the first signal line is electrically connected to the third electrode;

[0037] The first signal line includes: a first sub-signal line, a second sub-signal line and a third sub-signal line arranged in a stacked manner;

[0038] The first sub-signal line is located on a side of the planarization layer facing the first base substrate;

[0039] The second sub-signal line is disposed in the same layer as the first electrode; the planarization layer further includes a plurality of second via holes extending through the thickness thereof, the second sub-signal line being electrically connected to the first sub-signal line through the second via holes, the second sub-signal line having a first groove at the second via holes; the second filling portion being located within the first groove;

[0040] The third sub-signal line is provided in the same layer as the second electrode, and the third sub-signal line contacts the second sub-signal line at a side of the second sub-signal line and the second filling portion facing away from the first base substrate.

[0041] In some embodiments, an orthographic projection of the second filling portion on the first base substrate falls within an orthographic projection of the second sub-signal line and the third sub-signal line on the first base substrate.

[0042] In some embodiments, the first sub-signal line is disposed in the same layer as the source.

[0043] In some embodiments, in the display area, the array substrate further includes: a third electrode located on a side of the second electrode facing away from the first base substrate;

[0044] The first signal line further includes: a fourth sub-signal line provided in the same layer as the third electrode;

[0045] The array substrate further includes: a first protection layer located between the third sub-signal line and the fourth sub-signal line; and the fourth sub-signal line is electrically connected to the third sub-signal line through a via hole penetrating the first protection layer.

[0046] In some embodiments, the peripheral area includes: a first binding area located on one side of the display area in the second direction;

[0047] The array substrate further includes: a plurality of binding electrodes located in the first binding area;

[0048] The planarization layer further includes a third via hole, and the orthographic projection of the binding electrode on the first base substrate falls within the orthographic projection of the third via hole on the first base substrate.

[0049] In some embodiments, the binding electrode includes: a first sub-electrode, a second sub-electrode, a third sub-electrode, and a fourth sub-electrode;

[0050] The first sub-electrode is located on a side of the planarization layer facing the first substrate;

[0051] The second sub-electrode is provided in the same layer as the first electrode and is electrically connected to the first sub-electrode;

[0052] The third sub-electrode is provided in the same layer as the second electrode and is electrically connected to the second sub-electrode;

[0053] The array substrate further includes: a third filling portion located in the third via hole and between the second sub-electrode and the third sub-electrode;

[0054] The fourth sub-electrode contacts the third sub-electrode at a side of the third sub-electrode facing away from the first substrate.

[0055] In some embodiments, the array substrate includes a third electrode; and the fourth sub-electrode is disposed in the same layer as the third electrode.

[0056] In some embodiments, the distance from the surface of the binding electrode facing away from the first substrate to the first substrate is smaller than the distance from the surface of the planarization layer facing away from the first substrate to the first substrate, and the surface of the binding electrode facing away from the first substrate is not covered.

[0057] In some embodiments, the array substrate further includes: a third filling portion located in a partial area within the third via hole; the orthographic projection of the third filling portion on the first base substrate and the orthographic projection of the surface of the third via hole that exposes the binding electrode away from the first base substrate on the first base substrate do not overlap.

[0058] In some embodiments, the orthographic projections of the plurality of binding electrodes on the first base substrate all fall within the orthographic projection of the same third via hole on the first base substrate.

[0059] An embodiment of the present disclosure provides a method for preparing an array substrate, comprising:

[0060] providing a first substrate;

[0061] A plurality of thin film transistors are formed on one side of the first substrate; the thin film transistors include: a gate, a source and a drain;

[0062] A planarization layer is formed on a side of the plurality of thin film transistors facing away from the first substrate, and a plurality of first via holes are formed in the planarization layer; the first via holes correspond one to one with the thin film transistors, and the first via holes expose at least a portion of the surface of the drain electrode facing away from the first substrate;

[0063] A pattern of a plurality of first electrodes is formed on a side of the planarization layer away from the first base substrate; the first electrodes are connected to the drain electrode through a first via hole;

[0064] forming a pattern of a first filling portion on a side of the first electrode facing away from the first base substrate and in an area of ​​the first via hole;

[0065] A plurality of second electrode patterns are formed on the first electrode and the first filling portion on a side away from the first base substrate; the second electrodes are in one-to-one contact with the first electrodes located outside the first via holes.

[0066] In some embodiments, forming a pattern of a first filling portion in a region of the first via hole on a side of the first electrode facing away from the first substrate specifically includes:

[0067] forming a filling layer;

[0068] The filling layer is patterned to form a pattern of a first filling portion in the region of the first via hole.

[0069] In some embodiments, the first base substrate includes a display area and a peripheral area surrounding the display area;

[0070] Before forming the planarization layer, it also includes:

[0071] forming a first sub-signal line of the first signal line;

[0072] While forming a plurality of first via holes, the method further includes:

[0073] forming a plurality of second via holes in the planarization layer that penetrate the thickness of the planarization layer;

[0074] While forming the patterns of the plurality of first electrodes, the method further comprises:

[0075] forming a pattern of a second sub-signal line of the first signal line; the second sub-signal line is electrically connected to the first sub-signal line through a second via hole;

[0076] The filling layer is patterned to form a pattern of a first filling portion in the region of the first via hole, and further includes:

[0077] forming a pattern of a second filling portion in a region of the second via hole;

[0078] While forming the patterns of the plurality of second electrodes, the method further comprises:

[0079] A pattern of a third sub-signal line of the first signal line is formed on a side of the second filling portion away from the first base substrate.

[0080] In some embodiments, the first base substrate includes a display area and a peripheral area surrounding the display area; the peripheral area includes: a first binding area located on one side of the display area in the second direction;

[0081] Before forming the planarization layer, it also includes:

[0082] forming a first sub-electrode of the binding electrode;

[0083] While forming a plurality of first via holes, the method further includes:

[0084] forming a third via hole in the planarization layer; and causing the orthographic projection of the binding electrode on the first base substrate to fall within the orthographic projection of the third via hole on the first base substrate;

[0085] While forming the patterns of the plurality of first electrodes, the method further comprises:

[0086] forming a pattern of a second sub-electrode of the binding electrode; the second sub-electrode is electrically connected to the first sub-electrode through a third via hole;

[0087] The filling layer is patterned to form a pattern of a first filling portion in the region of the first via hole, and further includes:

[0088] forming a pattern of a third filling portion in the region of the third via hole;

[0089] While forming the patterns of the plurality of second electrodes, the method further comprises:

[0090] A pattern of a third sub-electrode of the binding electrode is formed on a side of the third filling portion facing away from the first base substrate.

[0091] In some embodiments, the first base substrate includes a display area and a peripheral area surrounding the display area; the peripheral area includes: a first binding area located on one side of the display area in the second direction;

[0092] While forming a plurality of first via holes, the method further includes:

[0093] forming a third via hole in the planarization layer; and causing the orthographic projection of the binding electrode on the first base substrate to fall within the orthographic projection of the third via hole on the first base substrate;

[0094] The filling layer is patterned to form a pattern of a first filling portion in the region of the first via hole, and further includes:

[0095] The filling layer at the third via hole is removed.

[0096] In some embodiments, after removing the filling layer at the third via hole, the method further includes:

[0097] Detect whether a filling layer remains at the third via hole, and if so, perform exposure and development processes on all the filling layers at the third via hole again to remove the filling layer.

[0098] In some embodiments, the first substrate includes a display area and a peripheral area surrounding the display area; the peripheral area includes: a first binding area located on one side of the display area in the second direction;

[0099] While forming a plurality of first via holes, the method further includes:

[0100] forming a third via hole in the planarization layer; and causing the orthographic projection of the binding electrode on the first base substrate to fall within the orthographic projection of the third via hole on the first base substrate;

[0101] The filling layer is patterned to form a pattern of a first filling portion in the region of the first via hole, and further includes:

[0102] Part of the filling layer at the third via is removed to form a third filling portion and multiple first removal areas; the orthographic projection of the third filling portion on the first base substrate and the orthographic projection of the surface of the binding electrode on the side facing away from the first base substrate on the first base substrate do not overlap with each other, and the orthographic projection of the surface of the binding electrode on the side facing away from the first base substrate on the first base substrate falls within the orthographic projection of the first removal area on the first base substrate.

[0103] An embodiment of the present disclosure provides a display panel, the display panel comprising:

[0104] The array substrate provided by the embodiment of the present disclosure;

[0105] an opposite substrate, arranged opposite to the array substrate;

[0106] The liquid crystal layer is located between the array substrate and the opposite substrate.

[0107] In some embodiments, the array substrate includes a first light-transmitting area; and the opposite substrate includes:

[0108] a second substrate;

[0109] The first light-shielding pattern is located on a side of the second base substrate facing the liquid crystal layer and includes a plurality of first openings. The orthographic projection of the first light-shielding pattern on the first base substrate covers the first light-shielding area.

[0110] An embodiment of the present disclosure provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0111] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0112] FIG1 is a schematic structural diagram of a display panel provided by the related art;

[0113] FIG2 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

[0114] FIG3 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0115] FIG4 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0116] FIG5 is a cross-sectional view along line BB′ in FIG3 provided by an embodiment of the present disclosure;

[0117] FIG6 is another cross-sectional view along line BB′ in FIG3 provided by an embodiment of the present disclosure;

[0118] FIG7 is a cross-sectional view along CC' in FIG4 provided by an embodiment of the present disclosure;

[0119] FIG8 is another cross-sectional view along CC in FIG4 provided by an embodiment of the present disclosure;

[0120] FIG9 is a schematic structural diagram of another display panel provided by the related art;

[0121] FIG10 is a schematic structural diagram of another display panel provided by the related art;

[0122] FIG11 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0123] FIG12 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0124] FIG13 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0125] FIG14 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0126] FIG15 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0127] FIG16 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0128] FIG17 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0129] FIG18 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0130] FIG19 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0131] FIG20 is a cross-sectional view along line KK' in FIG19 provided by an embodiment of the present disclosure;

[0132] FIG21 is another cross-sectional view along line KK' in FIG19 provided by an embodiment of the present disclosure;

[0133] FIG22 is another cross-sectional view along line KK' in FIG19 provided by an embodiment of the present disclosure;

[0134] FIG23 is another cross-sectional view along line KK' in FIG19 provided by an embodiment of the present disclosure;

[0135] FIG24 is a schematic diagram of a process for preparing an array substrate according to an embodiment of the present disclosure;

[0136] FIG25 is a schematic flow chart of another method for preparing an array substrate provided in an embodiment of the present disclosure;

[0137] FIG26 is a schematic diagram of a process of another method for preparing an array substrate provided in an embodiment of the present disclosure;

[0138] FIG27 is a schematic diagram of a process of another method for preparing an array substrate provided in an embodiment of the present disclosure;

[0139] FIG28 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0140] FIG29 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0141] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0142] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0143] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0144] In the related art, the structure of a display panel is shown in FIG1 . The pixel electrode P1 in the array substrate is connected to the drain electrode D of the thin-film transistor 2 via a first via 301 extending through the planarization layer 3. The pixel electrode P1 is very thin, much thinner than the thickness of the planarization layer 3. The first protective layer 24 covering the pixel electrode P1 is also relatively thin. The area around the first via 301 is not filled, and after the first protective layer 24 is formed, a recessed area still exists at the location of the first via 301. The spacer 16 positioned in the recessed area has poor flatness beneath it, affecting the stability of the spacer 16. If process fluctuations in the spacer 16 cause deviations in its placement, or if the spacer 16 positioned at the first via 301 is squeezed, a recessed area may form at the edge of the spacer 16. The liquid crystal 27 in this area may deflect abnormally under the electric field, posing a risk of light leakage. Therefore, the light-shielding pattern 17 on the opposing substrate needs to shield this light-leakage risk area A1, which increases the size of the light-shielding pattern 17 and affects the aperture ratio of the sub-pixel. Especially for display products with high pixel density, the size of the sub-pixel is very small. If the light-shielding pattern is used to block the light leakage risk area caused by the planarization layer via, the aperture ratio of the sub-pixel will be seriously lost, affecting the display effect.

[0145] The present disclosure provides an array substrate, as shown in FIG5 to FIG8 , which includes:

[0146] A first substrate 1;

[0147] A plurality of thin film transistors 2 are located on one side of the first substrate 1; the thin film transistors 2 include: a gate G, a source S and a drain D;

[0148] The planarization layer 3 is located on the side of the drain electrode D away from the first substrate 1 and includes first via holes 301 corresponding to the thin film transistors 2 one by one; the first via holes 301 expose at least a portion of the surface of the drain electrode D away from the first substrate 1;

[0149] A plurality of first electrodes 4 are located on a side of the planarization layer 3 facing away from the first base substrate 1 ; the first electrodes 4 are connected to the drain electrode D through a first via hole 301 ;

[0150] a plurality of first filling portions 5 located at least in the first via hole 301 and on a side of the first electrode 4 facing away from the first base substrate 1; a plurality of second electrodes 6 located on a side of the first electrode 4 and the first filling portion 5 facing away from the first base substrate 1;

[0151] The second electrode 6 and the first electrode 4 are in contact with each other outside the first via hole 301 .

[0152] In an array substrate provided by an embodiment of the present disclosure, a first filling portion is used to fill a first via hole on the side of the first electrode facing away from the drain electrode, thereby improving the flatness of the array substrate in the area of ​​the first via hole and thereby improving the thickness uniformity of the array substrate. When the array substrate is used in a liquid crystal display panel, this avoids the presence of a recessed area at the edge of the spacer at the first via hole, which could cause liquid crystal disorder and a light leakage risk area. As a result, the light-shielding pattern does not need to block the light leakage risk area, allowing the size of the light-shielding pattern to be reduced, thereby increasing the sub-pixel aperture ratio. Especially for high-pixel density display products, even if the sub-pixel size is small, the sub-pixel aperture ratio is not compromised because the light leakage risk area does not need to be blocked. In other words, the array substrate provided by an embodiment of the present disclosure can be used in high-pixel density display products. Furthermore, in an array substrate provided by an embodiment of the present disclosure, a second electrode is provided on the side of the first electrode facing away from the first base substrate, outside the first via hole and in contact therewith. In other words, the second electrode is electrically connected to the drain electrode via the first electrode. When the array substrate is used in a liquid crystal display panel, the light efficiency of the liquid crystal display panel is determined by the second electrode. The size of the second electrode does not need to avoid the first via hole, which facilitates improving light efficiency by increasing the size of the second electrode.

[0153] In some embodiments, as shown in FIG. 2 , the first base substrate 1 includes a display area AA and a peripheral area NA surrounding the display area AA; the display area AA includes a plurality of sub-pixel areas 101 arrayed along a first direction X and a second direction Y.

[0154] In some embodiments, as shown in FIG. 2 , the array substrate further includes a first signal line 10 located in the peripheral area NA.

[0155] In some embodiments, as shown in FIG5 to FIG8 , the array substrate further includes:

[0156] The third electrode 9 is located on a side of the second electrode 6 facing away from the first substrate 1 .

[0157] In a specific implementation, the first signal line is electrically connected to the third electrode.

[0158] In a specific implementation, the second electrode serves as a pixel electrode, the first electrode can be considered a connecting electrode between the second electrode and the drain electrode, and the third electrode serves as a common electrode. The first signal line provides a common voltage signal to the third electrode. The first, second, and third electrodes all include a transparent material, such as indium tin oxide.

[0159] In some embodiments, as shown in FIG2 , the array substrate further includes: a plurality of second signal lines 30 and a plurality of scan lines 31 that cross each other horizontally and vertically; the second signal lines 30 extend from the display area AA to the peripheral area NA along a first direction X, and the scan lines 31 extend from the display area AA to the peripheral area NA along a second direction Y; the scan lines 31 are electrically connected to the gate of the thin film transistor TFT.

[0160] In a specific implementation, the second signal line and the scan line usually comprise metal materials. The second signal line and the scan line in the display area are both located in the first light shielding area, that is, the second signal line and the scan line are shielded by the light shielding pattern.

[0161] In a specific implementation, in FIG2 , each scan line 31 corresponds to a row of sub-pixel areas 101 arranged along the first direction X, and only one scan line 31 is included between two adjacent sub-pixel areas 101 in the second direction Y; the plurality of second signal lines 30 are all data lines, and the second signal lines 30 are electrically connected to the source electrode of the thin film transistor TFT.

[0162] Alternatively, in a specific implementation, a row of sub-pixel areas arranged along the first direction X may correspond to two scan lines, and two scan lines may be included between two adjacent sub-pixel areas in the second direction Y; the plurality of second signal lines may include a plurality of data lines and a plurality of common voltage lines; the data lines and the common voltage lines may be alternately arranged in the first direction; and the common voltage lines may also be electrically connected to the third electrode.

[0163] In some embodiments, due to the large difference in thickness between the planarization layer and the first electrode, as shown in Figures 5 to 8, the first electrode 4 does not fill the first via 301. After the first electrode 4 overlaps with the drain D, a groove 29 is formed at the first via 301, and the first filling part 5 fills the groove 29.

[0164] In some embodiments, as shown in Figures 5 to 8 , the first via 301 has a trapezoidal shape perpendicular to the cross-section of the first substrate 1, and the cross-sectional area of ​​the first via 301 parallel to the first substrate 1 gradually increases in a direction away from the first substrate 1. That is, the side surface of the planarization layer 3 at the first via 301 is an inclined surface, which facilitates the first electrode 4 extending to the bottom of the first via 301 and overlapping the drain D, thereby avoiding the risk of disconnection at the first via 301.

[0165] In some embodiments, as shown in Figures 5 to 8 , the distance between the surface of the first filling portion 5 facing away from the first substrate 1 and the first substrate 1 is no less than the distance between the surface of the planarization layer 3 facing away from the first substrate 1 and the first substrate 1. That is, the first filling portion and the first electrode located at the first via hole at least fill the first via hole, further improving the flatness of the first via hole region.

[0166] In the array substrate provided by the embodiment of the present disclosure, the first filling portion and the first electrode located at the first via hole at least fill the first via hole. Even after the subsequent film layer is formed, there will be no recessed area in the area corresponding to the first via hole. The entire area corresponding to the first via hole is no longer a risk area for light leakage that causes liquid crystal disorder. The setting of the shading pattern does not need to consider the size of the first via hole, which is beneficial to increasing the sub-pixel aperture ratio.

[0167] In some embodiments, as shown in FIG. 5 to FIG. 8 , the surface of the first filling portion 5 facing away from the first base substrate 1 and the surface of the first electrode 4 outside the first via hole 301 facing away from the first base substrate 1 are substantially in the same plane.

[0168] It should be noted that the surface of the first filling portion facing away from the first base substrate and the surface of the first electrode outside the first via hole facing away from the first base substrate are approximately located in the same plane, which means that the difference between the distance between the surface of the first filling portion facing away from the first base substrate and the first base substrate and the distance between the surface of the first electrode outside the first via hole facing away from the first base substrate and the first base substrate is within a reasonable error range, and it can be considered that the surface of the first filling portion facing away from the first base substrate and the surface of the first electrode outside the first via hole facing away from the first base substrate are located in the same plane.

[0169] In the array substrate provided by the embodiments of the present disclosure, the surface of the first filling portion facing away from the first base substrate and the surface of the first electrode located outside the first via hole facing away from the first base substrate are coplanar, thereby improving the flatness of the film layer. Furthermore, because the second electrode is located on the first electrode and the side of the first filling portion facing away from the first base substrate, the surface of the first filling portion facing away from the first base substrate and the surface of the first electrode located outside the first via hole facing away from the first base substrate are coplanar, further improving the flatness of the second electrode.

[0170] It should be noted that Figures 5 and 7 illustrate the example where the first filling portion 5 does not cover the planarization layer 3 in the area outside the first via 301. The orthographic projection of the first filling portion 5 on the first base substrate 1 coincides with the orthographic projection of the first via 301 on the first base substrate 1. This allows the same mask to be used for the patterning of the first filling portion and the first via during array substrate fabrication, saving costs.

[0171] Alternatively, in some embodiments, as shown in Figures 6 and 8 , the surface of the first filling portion 5 facing away from the first base substrate 1 and the surface of the portion of the first electrode 4 outside the first via 301 facing away from the first base substrate 1 are approximately coplanar. In the area outside the first via 301, the first filling portion 5 covers the planarization layer 3 and contacts the side surface of the first electrode 4 outside the first via 301. Thus, the patterns formed by the orthographic projections of the first filling portion 5 and the first electrode 4 outside the first via 301 on the first base substrate complement each other. In any area, the surface of the film layer below the second electrode is planar, thereby improving the flatness of the surface on which the second electrode is disposed.

[0172] In a specific implementation, the material of the planarization layer is the same as the material of the first filling portion. For example, the material of the planarization layer and the material of the first filling portion include polyimide.

[0173] In some embodiments, as shown in FIG. 5 to FIG. 8 , the array substrate further includes: a first protective layer 24 located on a side of the second electrode 6 facing away from the first base substrate 1 ; specifically, the first protective layer 24 is located between the second electrode 6 and the third electrode 9 .

[0174] In the array substrate provided by the embodiment of the present disclosure, since the first filling portion fills the first via hole with the first electrode at the first via hole, the surface of the first filling portion facing away from the first base substrate and the surface of the first electrode outside the first via hole facing away from the first base substrate are located in the same plane. In the area corresponding to the first via hole, the surface of the first protective layer facing away from the first base substrate is a plane, that is, the first protective layer will not have a recessed area as in the related art at the first via hole. In this way, when the array substrate is applied to a liquid crystal display panel, in the area corresponding to the first via hole, the flatness under the spacer is good, and there is no recessed area at the edge of the spacer, thereby avoiding the presence of a light leakage risk area due to liquid crystal disorder. Therefore, the light-shielding pattern of the liquid crystal display panel does not need to block the light leakage risk area of ​​the related art, and the size of the light-shielding pattern can be reduced, thereby increasing the sub-pixel aperture ratio.

[0175] In some embodiments, as shown in FIG3 , FIG4 , and FIG5 to FIG8 , the sub-pixel region 101 includes: a first light-transmitting region 1011 and a first light-shielding region 1012 ; the first light-shielding region 1012 is located on one side of the first light-transmitting region 1011 in the second direction Y.

[0176] It should be noted that FIG. 5 and FIG. 6 are, for example, cross-sectional views along line BB′ in FIG. 3 , and FIG. 7 and FIG. 8 are, for example, cross-sectional views along line CC′ in FIG. 4 .

[0177] It should be noted that the liquid crystal display panel includes an array substrate and an opposing substrate arranged opposite to the array substrate, the opposing substrate includes a first shading pattern, the first shading pattern has multiple first opening areas; the first opening area has an overlap with the first light-transmitting area on the orthographic projection of the first base substrate.

[0178] In some embodiments, as shown in FIG5 to FIG8 , the array substrate further includes:

[0179] The plurality of second light shielding patterns 25 are located between the first base substrate 1 and the thin film transistor TFT.

[0180] In some embodiments, as shown in Figures 5 to 8 , the first light-shielding region 1012 overlaps with the orthographic projection of the second light-shielding pattern 25 on the first base substrate 1. That is, the first light-shielding region 1012 is the area shielded by the second light-shielding pattern 25. The orthographic projection of the second light-shielding pattern 25 on the first base substrate 1 at least covers the orthographic projection of the thin-film transistor channel on the first base substrate 1. For example, the second light-shielding pattern includes a light-shielding conductive material.

[0181] In some embodiments, as shown in FIG. 3 and FIG. 4 , the sub-pixel region 101 further includes a second light-shielding region 1013 ; the second light-shielding region 1013 is located on one side of the first light-transmitting region 1011 in the first direction X.

[0182] Alternatively, in some embodiments, the orthographic projection of the first opening area on the first substrate overlaps with the first light-transmitting area, and in the display area, the orthographic projection of the first shading pattern on the first substrate overlaps with all first shading areas and all second shading areas of the multiple sub-pixel areas.

[0183] In a specific implementation, for example, the orthographic projection of the first light-shielding pattern on the first substrate covers the orthographic projection of the second light-shielding pattern on the first substrate. In a specific implementation, for example, between adjacent opening areas in the second direction Y, the width of the first light-shielding pattern is greater than or equal to the width of the second light-shielding pattern.

[0184] In some embodiments, as shown in FIG. 3 , FIG. 4 , and FIG. 5 to FIG. 8 , the orthographic projection of the second electrode 6 on the first base substrate 1 overlaps with the first light-transmitting region 1011 .

[0185] In a specific implementation, when the array substrate provided by the embodiment of the present disclosure is applied to a liquid crystal display panel, the orthographic projection of the opening area of ​​the display panel on the first base substrate falls within the orthographic projection of the second electrode on the first base substrate.

[0186] In some embodiments, as shown in FIG. 5 to FIG. 8 , in the area outside the first via hole 301 , no insulating layer is included between the second electrode 6 and the first electrode 4 , that is, the second electrode 6 and the first electrode 4 are directly overlapped in the area outside the first via hole 301 .

[0187] It should be noted that because the second electrode is located on the side of the first electrode facing away from the base substrate, the size of the second electrode is the same as the size of the pixel electrode. Therefore, when the array substrate provided by the embodiments of the present disclosure is applied to a liquid crystal display panel, the size of the area driving liquid crystal deflection is related to the size of the second electrode, and not to the size of the first electrode. A larger area where the orthographic projection of the second electrode on the first base substrate overlaps with the first light-transmitting area is more conducive to increasing the aperture ratio of the display panel, thereby improving the light efficiency of the display panel.

[0188] In some embodiments, as shown in FIG3 , FIG4 , and FIG5 to FIG8 , the orthographic projection of the first via hole 301 on the first base substrate 1 falls into the first light shielding area 1012 ;

[0189] As shown in FIG. 5 to FIG. 8 , the orthographic projection of the first filling portion 5 on the first base substrate 1 at least includes a portion falling into the first light shielding area 1012 .

[0190] In a specific implementation, when the array substrate is applied to a display panel, the first shading area is covered by the second shading pattern, and the area at the first via hole corresponding to the drain of the thin film transistor, that is, the drain is arranged in the first shading area, is covered by the second shading pattern, thereby avoiding light leakage caused by reflection of the drain metal material.

[0191] In some embodiments, as shown in Figures 5 and 7 , the first filling portion 5 is located only in the area corresponding to the first opening 301 and does not cover the planarization layer 3 and the first electrode 4 in the area outside the first via hole 301. The orthographic projection of the first filling portion 5 on the first base substrate 1 falls within the first light-shielding area 1012. Alternatively, as shown in Figures 6 and 8 , the first filling portion 5 covers the planarization layer 3 in the area outside the first via hole 301. The orthographic projection of the first filling portion 5 on the first base substrate 1 overlaps both the first light-shielding area 1012 and the first light-transmitting area 1011.

[0192] In some embodiments, as shown in Figures 3 and 4, the first light-shielding area 1012 is located on one side of the first light-transmitting area 1011 in the second direction Y. Accordingly, the first via 301 is located on one side of the first light-transmitting area 1011 in the second direction Y on the orthographic projection of the first base substrate 1.

[0193] In some embodiments, as shown in Figures 3 and 4, the planarization layer (not shown) has a first opening 3011 and a second opening 3012 at the first via 301. The first opening 3011 is an opening on the surface of the planarization layer close to the first substrate 1, that is, an opening exposing the drain of the thin film transistor (not shown). The area of ​​the first opening 3011 is the area of ​​the drain of the thin film transistor exposed by the first via 301; the second opening 3012 is an opening on the surface of the planarization layer away from the first substrate 1.

[0194] In some embodiments, as shown in Figures 3 and 4, the shapes of the orthographic projections of the first opening 3011 and the second opening 3012 on the first substrate 1 are both circular; the diameter of the first opening 3011 is smaller than the diameter of the second opening 3012, and the orthographic projection of the first opening 3011 on the first substrate 1 falls within the orthographic projection of the second opening 3012 on the first substrate 1.

[0195] In some embodiments, as shown in FIG3 and FIG4 , in the second direction Y, the width of the first light-shielding region 1012 is substantially equal to the diameter of the second opening 3012. That is, if the difference between the width of the first light-shielding region and the diameter of the second opening is within an allowable error range, the width of the first light-shielding region can be considered equal to the diameter of the second opening.

[0196] Because the array substrate provided by the present disclosure includes a first filling portion at the first via hole to improve its flatness, light leakage due to the via hole will not occur even if the area near the edge of the first via hole is no longer within the light-shielding zone. Setting the width of the first light-shielding zone to be equal to the diameter of the second opening can improve the sub-pixel aperture ratio while preventing light reflection from metal materials.

[0197] In some embodiments, as shown in Figures 3, 4, and 5 to 8, since the orthographic projection of the first via hole 301 on the first substrate 1 falls within the first light-shielding area 1012, the orthographic projection of the portion of the first electrode 4 located in the first via hole 301 on the first substrate 1 also falls within the first light-shielding area 1012. Since the width of the first light-shielding area 1012 in the second direction Y is approximately equal to the diameter of the second opening 3012, the orthographic projection of the first electrode 4 located outside the first via hole 301 in the second direction Y on the first substrate 1 is located in the first light-transmitting area 1011. In other words, the orthographic projection of the first electrode 4 on the first substrate 1 overlaps with both the first light-transmitting area 1011 and the first light-shielding area 1012.

[0198] In some embodiments, as shown in FIG3 and FIG4 , in the second direction Y, the orthographic projection of the first electrode 4 on the first base substrate 1 does not overlap with the orthographic projection of the first via hole 301 corresponding to the adjacent sub-pixel region 101 on the first base substrate 1. This prevents the first electrode from falling into the first via hole of the adjacent sub-pixel region, causing the first electrodes of the adjacent sub-pixels to overlap at the first via hole.

[0199] In some embodiments, as shown in FIG. 3 and FIG. 4 , in the second direction Y, a distance h1 between the first electrode 4 and the second opening 3012 corresponding to the adjacent sub-pixel region 101 is greater than or equal to a first preset value.

[0200] It should be noted that the first preset value is a minimum value of the first via hole that prevents the first electrode from falling into an adjacent sub-pixel region in consideration of fluctuations in alignment of the planarization layer, the first electrode, and the size of the first opening.

[0201] In the array substrate provided by the embodiment of the present disclosure, h1 is greater than or equal to a first preset value, thereby preventing the first electrodes of adjacent sub-pixel regions from overlapping at the first via holes due to process errors.

[0202] In specific implementations, when the capabilities of the equipment for preparing the array substrate are different, the first preset value is also different, such as 1 micron, 0.5 micron, etc.

[0203] In some embodiments, as shown in FIG. 3 , FIG. 4 , and FIG. 5 to FIG. 8 , in the first light-transmitting region 1011 and in the second direction Y, the width of the second electrode 6 is greater than the width of the first electrode 4 .

[0204] It should be noted that in the related art, process fluctuations are taken into consideration, such as fluctuations in the alignment of the planarization layer and the first electrode, and fluctuations in the size of the first opening. In order to avoid overlapping of the first electrodes of adjacent sub-pixels at the first via hole, that is, to avoid the first part falling into the first via hole, the size of the first electrode in the first light-transmitting area is relatively small. Therefore, the size of the first electrode limits the aperture ratio of the sub-pixel, thereby affecting the light efficiency of the liquid crystal display panel.

[0205] In the array substrate provided by the embodiments of the present disclosure, since a second electrode is disposed on the side of the first electrode facing away from the first base substrate, the size of the first electrode does not limit the sub-pixel aperture ratio. Furthermore, since the second electrode does not electrically connect to the first electrode at the first via hole in the adjacent sub-pixel region, even if the second electrode extends to the first via hole in the adjacent sub-pixel region, it does not cause conduction between the electrodes of the adjacent sub-pixels. Therefore, the width of the second electrode in the second direction and in the first light-transmitting region is greater than the width of the first electrode. This prevents overlapping of the first electrodes of adjacent sub-pixels at the first via hole, while increasing the size of the second electrode in the first light-transmitting region, thereby increasing the sub-pixel aperture ratio and, consequently, improving light efficiency.

[0206] In a specific implementation, in the second direction Y, when the distance h1 between the first electrode and the second opening corresponding to the adjacent sub-pixel area is equal to the first preset value, it is possible to maximize the contact area between the first electrode and the second electrode while avoiding overlapping of the first electrodes of adjacent sub-pixels at the first via hole, thereby reducing the contact resistance therebetween and improving the conductive effect between the first electrode and the second electrode.

[0207] In some embodiments, as shown in FIG. 3 , FIG. 4 , and FIG. 5 to FIG. 8 , the orthographic projection of the second electrode 6 on the first base substrate 1 overlaps with the first light-shielding area 1012 .

[0208] In the array substrate provided by the embodiments of the present disclosure, the orthographic projection of the second electrode on the first substrate overlaps with both the first light-transmitting area and the first light-shielding area. This allows the second electrode to be larger, which is beneficial for increasing the size of the second electrode, thereby increasing the area of ​​the region where the orthographic projection of the second electrode on the first substrate overlaps with the first light-transmitting area, thereby increasing the aperture ratio of the display panel and improving the light efficiency of the existing display panel. Furthermore, the orthographic projection of the second electrode on the first substrate overlaps with both the first light-transmitting area and the first light-shielding area, thereby preventing the impact of alignment deviations in the array substrate manufacturing process on the area of ​​the region where the orthographic projection of the second electrode on the first substrate overlaps with the first light-transmitting area.

[0209] In some embodiments, as shown in Figures 5 to 8 , the orthographic projection of the second electrode 6 on the first base substrate 1 overlaps the orthographic projection of the first filling portion 5 on the first base substrate 1. That is, in addition to covering the first electrode 4, the second electrode 6 also covers a portion of the first filling portion 5 located in the area of ​​the first via 301. This allows the size of the second electrode to be increased, thereby improving light efficiency.

[0210] In some embodiments, in the second direction Y, in the first light-transmitting area 1011 , a distance h2 between the second electrodes 6 of two adjacent sub-pixel areas is greater than or equal to a second preset value.

[0211] It should be noted that the second preset value refers to the minimum distance between adjacent patterns achievable during the same-layer process during array substrate fabrication. In practice, when h2 is equal to the second preset value, the size of the second electrode can be maximized, which helps increase the area where the orthographic projection of the second electrode on the first base substrate overlaps the first light-transmitting region, thereby improving light efficiency.

[0212] In some embodiments, the second preset value is 1.8 micrometers.

[0213] In some embodiments, as shown in FIG3 , FIG4 , and FIG5 to FIG8 , the first electrode 4 includes: a first portion 401 located outside the first via hole 301 and a second portion 402 located on one side of the first portion 401 in the second direction Y and at least partially located within the first via hole 301 ;

[0214] The second electrode 6 includes a third portion 601 located outside the first via hole 301 and a fourth portion 602 located on one side of the third portion 601 in the second direction Y and at least partially located within the first via hole 301 .

[0215] In some embodiments, as shown in FIG. 3 , FIG. 4 , and FIG. 5 to FIG. 8 , the first portion 401 and the third portion 601 are only located in the first light-transmitting area 1011 , and the second portion 402 and the fourth portion 602 are only located in the first light-shielding area 1012 .

[0216] In some embodiments, as shown in FIG. 3 , FIG. 4 , and FIG. 5 to FIG. 8 , the orthographic projection of the fourth portion 602 on the first base substrate 1 partially overlaps with the orthographic projection of the first filling portion 5 on the first base substrate 1 .

[0217] 5 to 8 , the third portion 601 overlaps the first portion 401 , the second portion 402 is covered by the first filling portion 5 , and the fourth portion 602 contacts the first filling portion 5 on a side of the first filling portion 5 away from the first base substrate 1 .

[0218] In some embodiments, as shown in FIG. 5 to FIG. 8 , the surface of the first filling portion 5 facing away from the first base substrate 1 and the surface of the first portion 401 facing away from the first base substrate 1 are substantially located in the same plane.

[0219] In some embodiments, as shown in FIG. 3 , FIG. 4 , and FIG. 5 to FIG. 8 , in the second direction Y, the width of the first portion 401 is smaller than the width of the third portion 601 .

[0220] In a specific implementation, in the second direction Y, the distance h1 between the first electrode and the second opening corresponding to the adjacent sub-pixel region is equal to the distance between the third portion and the second opening corresponding to the adjacent sub-pixel region. That is, the distance between the third portion and the second opening corresponding to the adjacent sub-pixel region is greater than or equal to the first preset value.

[0221] In some embodiments, as shown in FIG3 and FIG4 , in the second direction Y, a distance h5 between adjacent first electrodes 4 (i.e., a distance between adjacent first portions 401 and second portions 402 located on different first electrodes 4) is greater than or equal to a second predetermined value. That is, the distance h5 between adjacent first electrodes 4 is greater than the minimum distance between adjacent patterns achievable in the same-layer process, thereby preventing conduction between adjacent first electrodes 4.

[0222] It should be noted that in related art, the first electrode serves as the pixel electrode, so both process fluctuations and sub-pixel aperture ratios need to be considered. As shown in Figure 9, h3 is the distance between the orthographic projection of the first electrode 4 on the first substrate 1 and the orthographic projection of the first opening 3011 of the adjacent sub-pixel region 101 on the first substrate 1; h4 is the distance between the orthographic projection of the first opening 3011 on the first substrate 1 and the orthographic projection of the second opening 3012 on the first substrate 1; and h1 is the distance between the orthographic projection of the first electrode 4 on the first substrate 1 and the orthographic projection of the second opening 3012 of the adjacent sub-pixel region 101 on the first substrate 1. Distance h1 is no less than a first preset value. If h3 is less than the minimum distance between adjacent patterns achievable in the same-layer process for array substrate fabrication, then, if h3 remains unchanged, to maintain the sub-pixel aperture ratio and avoid overlapping of the first electrodes 4 of adjacent sub-pixel regions 101 at the first via 301, the first electrodes 4 need to be reduced upward at the boundary of the first via 301 to ensure that distance h5 between adjacent first electrodes 4 is no less than the minimum distance between adjacent patterns achievable in the same-layer process, i.e., the second preset value. Therefore, the first electrode 4 does not completely cover the first opening 3011, that is, the first electrode 4 does not completely cover the drain electrode (not shown) exposed by the first opening 3011, resulting in a reduced contact area between the first electrode 4 and the drain electrode and a high contact resistance. Furthermore, the fact that the first electrode 4 does not completely cover the first opening 3011 also results in insufficient wrapping of the first electrode 4 around the edge of the first via hole 301 in the planarization layer 3. Due to the presence of moisture in the planarization layer, the adhesion between the first electrode and the planarization layer is insufficient, and during the etching process, the etching solution may penetrate and drill upward. As shown in FIG10 , the first electrode 4 is missing from the sidewall of the first via hole 301. For example, the first electrode 4 is missing from area F in FIG10 . As a result, the portion of the first electrode 4 outside the first via hole 301 cannot be electrically connected to the drain electrode, and thus the first electrode 4 cannot be charged, affecting the yield rate of the array substrate. When the array substrate is used in a liquid crystal display panel, dark spots will appear in the area where the first electrode 4 cannot be charged, affecting the display effect. It should be noted that FIG10 is a cross-sectional view along line EE' in FIG9 .

[0223] In some embodiments, as shown in Figures 5 to 8 , the second portion 402 completely covers the surface of the drain electrode D exposed by the first via 301. That is, as shown in Figures 3 and 4 , the orthographic projection of the first opening 3011 on the first base substrate 1 falls within the orthographic projection of the second portion 402 on the first base substrate 1. Accordingly, as shown in Figures 5 to 8 , the second portion 402 covers the side surface of the planarization layer 3 around the bottom of the first via 301. This can improve the covering effect of the second portion 402 on the bottom of the first via 301, increase the contact area between the first electrode 4 and the drain electrode D, and reduce the contact resistance. It can also prevent drilling during the etching process, which could result in the loss of the first electrode 4 and the inability to conduct electricity with the drain electrode D. This improves the yield rate of array substrate production and prevents dark spots when the array substrate is used in a display panel.

[0224] In the array substrate provided by the embodiments of the present disclosure, since a second electrode is disposed on the side of the first electrode facing away from the first base substrate and in contact with the first electrode, the size of the first electrode does not affect the aperture ratio of the sub-pixel. Therefore, while the orthographic projection of the first opening on the first base substrate falls within the orthographic projection of the second portion on the first base substrate, the distance between adjacent first electrodes can be greater than the minimum distance between adjacent patterns achievable using the same-layer process without affecting the aperture ratio.

[0225] In some embodiments, to ensure that the second portion 402 of the first electrode 4 covers the bottom edge of the first via 301, as shown in Figures 3 and 4, the distance h6 between the edge of the orthographic projection of the second portion 402 on the first substrate 1 and the edge of the orthographic projection of the first opening 3011 on the first substrate 1 is greater than or equal to 0. It should be noted that in Figures 3 and 4, the distance between the edge of the orthographic projection of the second portion 402 on the first substrate 1 extending along the second direction Y and the edge of the orthographic projection of the first opening 3011 on the first substrate 1 is 0, and the distance between the edge of the orthographic projection of the second portion 402 on the first substrate 1 extending along the first direction X and away from the first portion 401 and the edge of the orthographic projection of the first opening 3011 on the first substrate 1 is greater than 0 is used as an example for illustration. In a specific implementation, in order to ensure the contact area between the first portion 401 of the first electrode 4 and the third portion 601 of the second electrode 6, h5 can be set equal to the second preset value, and the distance h6 between the edge of the orthographic projection of the second portion 402 on the first base substrate 1 extending along the first direction X and away from the side of the first portion 401 and the edge of the orthographic projection of the first opening 3011 on the first base substrate 1 is equal to 0.

[0226] In some embodiments, as shown in FIG. 3 and FIG. 4 , in the second direction Y, a width h7 of the fourth portion 602 is greater than or equal to a third preset value.

[0227] It should be noted that when the size of the second electrode fluctuates and the alignment fluctuates in the second direction, if h7 is small, in the second direction, if the fourth part is offset upward away from the edge of the third part, the fourth part may be offset to the first light-transmitting area and the edge of the fourth part away from the third part and the edge of the first light-shielding area closest to it may be greater than 0, which may cause the overlapping area between the second electrode and the first light-transmitting area to decrease, affecting the sub-pixel aperture ratio and thus affecting the light efficiency.

[0228] It should be noted that the third preset value is the minimum value that prevents the fourth portion from falling within the first light-shielding area when the second electrode's size and alignment fluctuate. Therefore, h7 being greater than or equal to the third preset value prevents fluctuations in the second electrode's size and alignment in the second direction from affecting the sub-pixel aperture ratio and, consequently, the light efficiency. The third preset value can vary depending on the capabilities of the equipment used to manufacture the array substrate. For example, the third preset value can be 1.5 microns, 0.6 microns, etc.

[0229] 3 and 4 , the first electrodes 4 and the second electrodes 6 that are in contact with each other are staggered in the second direction Y. That is, in the second direction Y, the width of the fourth portion 602 is smaller than the width of the second portion 402 .

[0230] In the array substrate provided by the embodiment of the present disclosure, the width of the fourth part is smaller than the width of the second part and the width of the fourth part is greater than or equal to the third preset value. This can avoid the influence of the second electrode size fluctuation and alignment fluctuation in the second direction on the sub-pixel aperture ratio, and avoid the increase in cost caused by the excessive width of the fourth part.

[0231] In some embodiments, as shown in FIG. 3 , FIG. 5 , and FIG. 6 , in the second direction Y, the orthographic projection of the region between two adjacent second electrodes 6 on the first base substrate 1 overlaps with both the first light-transmitting region 1011 and the first light-shielding region 1012 .

[0232] Alternatively, in some embodiments, as shown in FIG. 4 , FIG. 7 , and FIG. 8 , the second electrode 6 further includes: a fifth portion 603 located on a side of the third portion 601 away from the fourth portion 602 in the second direction Y;

[0233] The orthographic projection of the fifth portion 603 on the first substrate 1 falls into the first light-shielding area 1012 ;

[0234] In the second direction Y, the orthographic projection of the gap between two adjacent second electrodes 6 on the first base substrate 1 falls within the orthographic projection of the first filling portion 5 on the first base substrate 1 .

[0235] 4, 7, and 8, in the second direction Y, the width of the third portion 601 is equal to the width of the first light-transmitting area 1011. This can increase the overlapping area between the third portion 601 and the first light-transmitting area 1011, thereby increasing the sub-pixel aperture ratio and improving light efficiency.

[0236] In some embodiments, as shown in FIG. 4 , in the second direction Y, a width h8 of the fifth portion 603 is greater than or equal to a third preset value.

[0237] It should be noted that when the size of the second electrode fluctuates and the alignment fluctuates in the second direction, if h8 is small, in the second direction, if the fifth part is offset downward away from the edge of the third part, the fifth part may be offset to the first light-transmitting area and the edge of the fifth part away from the third part and the edge of the first light-shielding area closest to it may be greater than 0, which may cause the overlapping area between the second electrode and the first light-transmitting area to decrease, affecting the sub-pixel aperture ratio and thus affecting the light efficiency.

[0238] In the array substrate provided by the embodiment of the present disclosure, the third preset value is the minimum value that prevents the fourth portion from falling into the first shading area when the second electrode size fluctuates and the alignment fluctuates. h7 is greater than or equal to the third preset value to avoid affecting the sub-pixel aperture ratio and thus affecting the light efficiency when the second electrode size fluctuates and the alignment fluctuates in the second direction.

[0239] In the array substrate provided by the embodiment of the present disclosure, the fourth part and the fifth part are both located in the first shading area, that is, both ends of the second electrode extending in the second direction are located in the first shading area, and h7 and h8 are both greater than or equal to the third preset value, thereby avoiding the influence of the second electrode size fluctuation and alignment fluctuation in the second direction on the sub-pixel aperture ratio, further improving the sub-pixel aperture ratio and thus improving the light efficiency.

[0240] In some embodiments, as shown in FIG. 3 and FIG. 4 , in the first direction X, the width h9 of the first electrode 4 is substantially equal to the width h10 of the second electrode 6 .

[0241] In some embodiments, as shown in FIG3 and FIG4 , the edges of the first electrode 4 and the second electrode 6 located on the same side and extending along the second direction Y substantially overlap. That is, the difference between the edges of the first electrode 4 and the second electrode 6 located on the same side and extending along the second direction Y is less than or equal to a reasonable process error.

[0242] In some embodiments, as shown in FIG. 11 to FIG. 14 , the array substrate further includes:

[0243] A plurality of color resists 7 correspond one-to-one to the sub-pixel areas 101 and are located on a side of the planarization layer 3 close to the first base substrate 1 ; the orthographic projection of the color resist 7 on the first base substrate 1 at least covers the first light-transmitting area 1011 .

[0244] The array substrate provided by the embodiment of the present disclosure has color resistance set on the array substrate. When the array substrate is applied to a liquid crystal display panel with a high pixel density, the opposite substrate of the liquid crystal display panel does not need to be provided with color resistance, thereby avoiding the problem of color mixing and cross-coloring that is easily caused by setting color resistance on the opposite substrate, thereby improving the display effect.

[0245] In some embodiments, the multiple sub-pixel areas include multiple red sub-pixel areas, multiple blue sub-pixel areas, and multiple green sub-pixel areas; accordingly, the multiple color resists include: red color resists corresponding to the red sub-pixel areas, blue color resists corresponding to the blue sub-pixel areas, and green color resists corresponding to the green sub-pixel areas.

[0246] In some embodiments, as shown in FIG11 to FIG14 , the color resist 7 and the drain electrode D are located in the same layer;

[0247] The orthographic projection of the color resist 7 on the first base substrate 1 does not overlap with the orthographic projection of the drain electrode D on the first base substrate 1 , and the orthographic projection of the color resist 7 on the first base substrate 1 does not overlap with the orthographic projection of the first via hole 301 on the first base substrate 1 .

[0248] It should be noted that since the color resist and the drain electrode are located in the same layer, in order to ensure the filtering effect of the color resist, the thickness of the color resist is usually not too thin, so the thickness of the planarization layer covering the color resist will also be thicker. In order to avoid the risk of overlapping short lines of the first electrode at the first via hole, the side inclination angle of the planarization layer at the first via hole is larger, and thus the size of the second opening of the first via hole is larger. In the related art, the size of the light leakage risk area that needs to be blocked is also larger, which further affects the sub-pixel aperture ratio. However, the array substrate provided by the embodiment of the present disclosure, even if the color resist is provided on the array substrate, because the first filling portion is provided to fill at least the first via hole, the light leakage risk area of ​​the related art is avoided, so there is no need to block the light leakage risk area, which can improve the sub-pixel aperture ratio.

[0249] It should be noted that, as shown in FIG. 11 to FIG. 14 , the color resist 7 and the drain electrode D being located in the same layer means that they are disposed on the same film layer.

[0250] In some embodiments, as shown in Figures 11 to 14, the source S is located on the side of the drain D facing the first base substrate 1; the array substrate further includes a first interlayer insulating layer 8 located between the source S and the drain D; the color resist and the drain D are located between the first interlayer insulating layer 8 and the planarization layer 3.

[0251] In the array substrate provided by the embodiments of the present disclosure, the source and drain electrodes of the thin-film transistors are located in different film layers. Thus, even if the distance between the edge of the orthographic projection of the source electrode on the first substrate and the edge of the orthographic projection of the drain electrode on the first substrate is reduced, a short circuit between the source and drain electrodes will not occur, thereby simplifying the design of the array substrate layout. Furthermore, reducing the distance between the edge of the orthographic projection of the source electrode on the first substrate and the edge of the orthographic projection of the drain electrode on the first substrate can also reduce the size of the sub-pixel area, facilitating high pixel density, thereby improving resolution and facilitating high-resolution display.

[0252] In some embodiments, as shown in Figures 11 to 14, the array substrate further includes: a buffer layer 18 located between the second light-shielding pattern 25 and the first base substrate 1, a first insulating layer 19 located between the second light-shielding pattern 25 and the buffer layer 18, a second insulating layer 20 located between the second light-shielding pattern 25 and the active layer 201 of the thin film transistor 2, a third insulating layer 21 located between the active layer 201 and the gate G, a fourth insulating layer 22 located between the gate G and the source S, and a fifth insulating layer 23 located between the source S and the drain D; the color resist 7 and the drain D are both arranged on the fifth insulating layer 23.

[0253] In some embodiments, as shown in FIG. 5 to FIG. 8 and FIG. 11 to FIG. 14 , the third electrode includes a plurality of strip-shaped electrode portions 901 and slits 902 located between adjacent strip-shaped electrode portions 901 .

[0254] In some embodiments, as shown in FIG15 , the array substrate further includes: a plurality of third light-shielding patterns 28 ;

[0255] The third light shielding pattern 28 is located between the first protection layer 24 and the third electrode 9 .

[0256] In some embodiments, as shown in FIG. 16 , the orthographic projection of the third light-shielding pattern 28 on the first base substrate 1 is a strip extending along the second direction Y; a plurality of third light-shielding patterns 28 are arranged along the first direction X.

[0257] In some embodiments, as shown in FIG. 15 , the orthographic projection of the third light-shielding pattern 28 on the first base substrate 1 substantially coincides with the orthographic projection of the second signal line 30 on the first base substrate 1 .

[0258] The array substrate provided by the embodiment of the present disclosure is provided with a third light-shielding pattern that substantially overlaps with the orthographic projection of the second signal line, thereby preventing color mixing and cross-color problems between adjacent sub-pixels, improving display effects, and enhancing user experience.

[0259] Next, the light efficiency and light conversion efficiency improvement of the array substrate provided by the embodiment of the present disclosure when applied to a liquid crystal display panel are described. It has been verified that, if light leakage from the edge of the first via hole in the planarization layer is not considered, when the resolution and aperture ratio of the liquid crystal display panel provided by the embodiment of the present disclosure and the liquid crystal display panel of the related art are the same, the array substrate provided by the embodiment of the present disclosure uses a first filling portion to fill the first via hole and provides a second electrode, while the related art does not provide a first filling portion and a second electrode. The light efficiency of the liquid crystal display panel provided by the embodiment of the present disclosure can be improved by at least 3% compared to the light efficiency of the liquid crystal display panel of the related art. If light leakage from the edge of the first via hole in the planarization layer is considered, the first light shielding pattern of the opposing substrate of the liquid crystal display panel of the related art needs to shield the edge of the first via hole. When the resolution of the liquid crystal display panel provided by the embodiment of the present disclosure and the liquid crystal display panel of the related art are the same, the aperture ratio of the liquid crystal display panel provided by the embodiment of the present disclosure is greater than the aperture ratio of the resolution of the liquid crystal display panel of the related art, and the light conversion efficiency of the liquid crystal display panel provided by the embodiment of the present disclosure is improved by at least 12% compared to the light conversion efficiency of the liquid crystal display panel of the related art.

[0260] In some embodiments, as shown in FIG17 , the first signal line 10 includes: a first sub-signal line 1001 , a second sub-signal line 1002 , and a third sub-signal line 1003 , which are stacked;

[0261] The first sub-signal line 1001 is located on the side of the planarization layer 3 facing the first base substrate 1;

[0262] The second sub-signal line 1002 is provided in the same layer as the first electrode 4; the planarization layer 3 further includes a plurality of second via holes 302 extending through the thickness thereof, the second sub-signal line 1002 being electrically connected to the first sub-signal line 1001 via the second via holes 302, and the second sub-signal line 1002 having a first groove 12 at the second via holes 302;

[0263] The array substrate further includes: a plurality of second filling portions 11; the second filling portions 11 are located in the first groove 12;

[0264] The third sub-signal line 1003 is provided in the same layer as the second electrode 6 , and the third sub-signal line 1003 contacts the second sub-signal line 1002 on a side of the second sub-signal line 1002 and the second filling portion 11 facing away from the first base substrate 1 .

[0265] In the array substrate provided by the embodiment of the present disclosure, the first signal line includes a plurality of sub-signal lines that are stacked and electrically connected, i.e., multi-layer wiring of the first signal line. This can reduce the resistance and impedance of the first signal line while reducing the line width of each sub-signal line. When the line width of each sub-signal line is reduced, it is also beneficial to reduce the size of the peripheral area and realize a narrow-frame display.

[0266] In some embodiments, the first sub-signal line is disposed in the same layer as the source. Therefore, as shown in FIG17 , a fifth insulating layer 23 is further provided between the first signal line 1001 and the planarization layer 3 . The fifth insulating layer 23 includes a fourth via 2301 extending through the thickness of the fifth insulating layer 23 . The fourth via 2301 corresponds one-to-one with the second via 302 , and the fourth via 2301 partially exposes the first sub-signal line 1001 .

[0267] In some embodiments, the second via and the fourth via are formed in the same patterning process. As shown in FIG17 , the side surface of the planarization layer 3 at the second via 302 and the side surface of the fifth insulating layer 23 at the fourth via 2301 are located on the same inclined surface; that is, the second via 302 and the fourth via constitute the fifth via 32; thereby, the second sub-signal line 1002 is electrically connected to the first sub-signal line 1001 through the fifth via 32.

[0268] It should be noted that FIG17 is a cross-sectional view along JJ' in FIG2 . In FIG2 , the first signal line 10 includes portions located on the left and right sides and above the display area AA, and also includes a portion located below the display area AA. FIG2 takes the example of the first signal line 10 surrounding the display area on one side of the three edges of the display area AA as an example. The first signal line 10 extends from the peripheral area NA located below the display area AA to the peripheral area NA on the left side of the display area AA, passes through the peripheral area NA above the display area AA, and the peripheral area NA on the right side of the display area AA, and then returns to the peripheral area NA located below the display area AA. Of course, in a specific implementation, as shown in FIG18 , the first signal line 10 may also surround the display area AA in the orthographic projection of the first base substrate 1.

[0269] It should be noted that the number and positions of the fifth via holes can be set according to actual needs.

[0270] In some embodiments, as shown in FIG. 17 , the orthographic projection of the second filling portion 11 on the first base substrate 1 falls within the orthographic projections of the second sub-signal line 1002 and the third sub-signal line 1003 on the first base substrate 1 .

[0271] In some embodiments, as shown in FIG17 , the surface of the second filling portion 11 facing away from the first substrate 1 is substantially coplanar with the surface of the second sub-signal line 1002 outside the second via 302 facing away from the first substrate 1 . That is, the second filling portion 11 fills the first groove 12 .

[0272] The array substrate provided by the embodiment of the present disclosure uses a second filling portion to fill the groove formed by the second sub-signal line on the side of the second sub-signal line facing away from the first base substrate, which can improve the flatness of the film layer. In this way, the surface of the film layer below the subsequently formed third sub-signal line is flat, further improving the conductive performance of the sub-signal line.

[0273] In a specific implementation, the second filling portion and the first filling portion are formed in the same patterning process, that is, a filling portion material layer is formed first, and then a patterning process is performed to form the patterns of the first filling portion and the second filling portion.

[0274] The array substrate provided in the embodiment of the present disclosure has a second filling portion provided at the second via hole. This eliminates the need to remove the filling portion material at the second via hole while forming the first filling portion, thus reducing the manufacturing process. Furthermore, the array substrate provided in the embodiment of the present disclosure electrically connects the second and third sub-signal lines to the first sub-signal line, so the provision of the second filling portion does not affect the electrical connection of the multiple layers of sub-signal lines.

[0275] In some embodiments, as shown in FIG. 17 , the orthographic projection of the second filling portion 11 on the first base substrate 1 substantially coincides with the orthographic projection of the second via hole 302 on the first base substrate 1 .

[0276] In a specific implementation, the first via and the second via are formed in the same patterning process, and the second filling portion and the first filling portion are formed in the same patterning process. When the orthographic projection of the first filling portion on the first substrate coincides with the orthographic projection of the first via on the first substrate, and the orthographic projection of the second filling portion on the first substrate coincides with the orthographic projection of the second via on the first substrate, the second filling portion and the first filling portion can be formed using the mask plate for forming the first via and the second via, which can save costs.

[0277] In some embodiments, as shown in Figure 17, the second sub-signal line 1002 and the third sub-signal line 1003 are in contact in an area outside the second filling portion 11; and in the extension direction perpendicular to the first signal line 10 (the first direction X in Figure 17), the second sub-signal line 1002 and the third sub-signal line 1003 both include portions located on both sides of the second filling portion 11, and there are areas on both sides of the second filling portion 11 where the second sub-signal line 1002 and the third sub-signal line 1003 are in contact.

[0278] In some embodiments, as shown in FIG17 , the orthographic projection of the second sub-signal line 1002 on the first substrate 1 substantially overlaps with the orthographic projection of the third sub-signal line 1003 on the first substrate 1 , thereby increasing the contact area between the two and improving the conductive effect.

[0279] In some embodiments, as shown in FIG17 , the first signal line 10 further includes: a fourth sub-signal line 1004 provided in the same layer as the third electrode 9 ;

[0280] The array substrate further includes: a fourth sub-signal line 1004 electrically connected to the third sub-signal line 1003 through a via hole, ie, a sixth via hole 2401 penetrating the first protection layer 24 .

[0281] In some embodiments, as shown in FIG17 , the orthographic projection of the fourth sub-signal line 1004 on the first substrate 1 , the orthographic projection of the second sub-signal line 1002 on the first substrate 1 , and the orthographic projection of the third sub-signal line 1003 on the first substrate 1 substantially overlap.

[0282] In some embodiments, as shown in Figure 17, at the fifth via 32, the fifth insulating layer 23 has a third opening 2301 exposing the first sub-signal line 1001, and at the sixth via 2401, the first protective layer 24 has a fourth opening 24011 exposing the third sub-signal line 1003; the orthographic projection of the third opening 2301 on the first substrate 1 falls within the orthographic projection of the fourth opening 24011 on the first substrate 1.

[0283] In some embodiments, as shown in Figure 17, perpendicular to the extension direction of the first signal line 10 (the first direction X in Figure 17), the width h11 of the contact area between the second sub-signal line 1002 and the third sub-signal line 1003 is greater than the width h12 of the third opening 2301, and the width h13 of the fourth opening 24011 is greater than the width h12 of the third opening 2301.

[0284] In related art, the first signal line also uses a double-layer wiring pattern, including a fourth sub-signal line and a sub-signal line located below the planarization layer. The insulating film layer located between the two has vias to electrically connect the two. However, the insulating film layer includes at least a first protective layer and a planarization layer. Because the planarization layer is relatively thick, the thickness of the first protective layer plus the planarization layer is even thicker. The thicker the film layer between the sub-signal lines in the double-layer wiring pattern, the more likely it is to cause overlap and disconnection between the two. Furthermore, the vias in the first protective layer and the vias in the planarization layer are not formed in the same patterning process. The vias in the planarization layer are formed first, and then the first protective layer is formed, with the vias in the first protective layer formed inside the vias in the planarization layer. This means that the vias in the first protective layer are smaller than the vias in the planarization layer. This reduces the area of ​​electrical connection between the fourth sub-signal line and the sub-signal line below, thereby reducing the performance of the electrical connection between the two.

[0285] In the array substrate provided by the embodiment of the present disclosure, the first signal line includes a larger number of sub-signal lines, so that the fourth sub-signal line and the first sub-signal line are also overlapped through the second sub-signal line and the first sub-signal line to achieve electrical connection, which can avoid the overlap breakage caused by the large thickness of the film layer between the electrically connected sub-signal lines. When the size of the fifth via composed of the second via and the fourth via remains unchanged, the overlap area between the second sub-signal line and the first sub-signal line is larger than the overlap area between the fourth sub-signal line and the first sub-signal line in the related art, which is beneficial to improving the electrical connection performance between the sub-signal lines. In addition, the third sub-signal line and the second sub-signal line have overlapping areas on both sides of the second filling portion, and the overlapping area between the two is large, which can further improve the electrical connection performance. In addition, the size of the fourth opening, that is, the size of the electrical connection between the fourth sub-signal line and the third sub-signal line, is larger than the size of the third opening, and the area of ​​the electrical connection between the fourth sub-signal line and the third sub-signal line is larger. That is, compared to the prior art, where electrical connection is achieved through vias in the first protective layer, the electrical connection area between two adjacent layers of sub-signal lines is increased, thereby improving the electrical connection performance between each sub-signal line in the first signal line and the signal transmission capability of the first signal line. Furthermore, even if a second filling portion, a third sub-signal line, and a second sub-signal line are added, the second filling portion is provided on the same layer as the first filling portion, the second sub-signal line is provided on the same layer as the first electrode, and the third sub-signal line is provided on the same layer as the second electrode. The structure of the first signal line of the disclosed embodiment can be manufactured by simply changing the pattern of the mask used in the patterning process for each film layer, without adding to the array substrate manufacturing process, thus avoiding excessive cost increases.

[0286] In some embodiments, at the fifth via, the symmetry axis of the second filling portion parallel to the extension direction of the first signal line, the symmetry axis of the first sub-signal line parallel to the extension direction of the first signal line, the symmetry axis of the second sub-signal line parallel to the extension direction of the first signal line, the symmetry axis of the third sub-signal line parallel to the extension direction of the first signal line, and the symmetry axis of the fourth sub-signal line parallel to the extension direction of the first signal line roughly coincide with their orthographic projections on the first substrate.

[0287] In some embodiments, as shown in FIG2 , the peripheral area NA includes: a first binding area 13 located on one side of the display area AA in the second direction Y;

[0288] As shown in FIG19 , the array substrate further includes: a plurality of binding electrodes 14 located in the first binding area 13 , and a plurality of connecting leads 33 extending from the first binding area 13 toward one side of the display area (not shown);

[0289] As shown in FIG. 20 to FIG. 23 , the planarization layer 3 further includes a third via hole 303 , and the orthographic projection of the binding electrode 14 on the first base substrate 1 falls within the orthographic projection of the third via hole 303 on the first base substrate 1 .

[0290] It should be noted that FIG19 only shows a partial area of ​​the first binding region 13 , and FIG20 to FIG23 are all cross-sectional views along KK′ in FIG19 .

[0291] It should be noted that the multiple connecting leads, for example, include multiple first connecting leads, multiple second connecting leads, and multiple third connecting leads; and the multiple binding electrodes, for example, include: a first binding electrode electrically connected to multiple scan lines via the first connecting leads, a second binding electrode electrically connected to multiple second signal lines via the second connecting leads, and a third binding electrode electrically connected to the first signal line via the third connecting lead. When the array substrate is used in a liquid crystal display panel, it is bound to a drive unit in the first binding region, so that the drive unit provides corresponding signals to the scan lines, second signal lines, and first signal lines via the binding electrodes. The drive unit, for example, includes components such as a driver chip and a circuit board.

[0292] In some embodiments, as shown in FIG. 20 to FIG. 23 , the binding electrode 14 includes at least: a first sub-electrode 1401 , a fourth sub-electrode 1404 , and a fifth sub-electrode 1405 ;

[0293] The first sub-electrode 1401 is located on the side of the planarization layer 3 facing the first base substrate 1 , and the first sub-electrode 1401 is provided in the same layer as the source electrode (not shown);

[0294] The fourth sub-electrode 1404 is provided in the same layer as the third electrode (not shown); and the fourth sub-electrode 1404 is the uppermost sub-electrode in the binding electrode 14;

[0295] The fifth sub-electrode 1405 is located on the side of the first sub-electrode 1401 facing the first base substrate 1. The fifth sub-electrode 1405 is arranged on the same layer as the second shading pattern (not shown) and is electrically connected to the fourth sub-electrode 1404; the first sub-electrode 1401 is electrically connected to the fifth sub-electrode 1405 through a via hole penetrating the fourth insulating layer 22, the third insulating layer 21, and the second insulating layer 20.

[0296] During specific implementation, the driving unit is electrically connected to the fourth sub-electrode to achieve binding of the driving unit to the binding electrode.

[0297] In some embodiments, as shown in Figures 20 to 23, the fifth insulating layer 23 further includes a sixth via 2302, and the third via 303 corresponds to the sixth via 2302 one by one and is formed in a patterning process, that is, the third via 303 and the sixth via 2302 form a complete seventh via 34; the seventh via 34 exposes the first sub-electrode 1401.

[0298] The array substrate provided by the embodiment of the present disclosure has a third via hole set in the planarization layer and a sixth via hole set in the fifth insulating layer, so that electrical connection between at least some sub-electrodes in the binding electrode can be achieved at the third via hole and the sixth via hole.

[0299] In some embodiments, as shown in FIG20 , the binding electrode 14 further includes: a second sub-electrode 1402 and a third sub-electrode 1403 ;

[0300] The second sub-electrode 1402 is provided in the same layer as the first electrode 4 and is electrically connected to the first sub-electrode 1401;

[0301] The third sub-electrode 1403 is provided in the same layer as the second electrode 6 and is electrically connected to the second sub-electrode 1402;

[0302] The array substrate further includes: a third filling portion 15 located in the third via hole 303 and between the second sub-electrode 1402 and the third sub-electrode 1403 ;

[0303] The fourth sub-electrode 1404 contacts the third sub-electrode 1403 on a side of the third sub-electrode 1403 facing away from the first substrate 1 .

[0304] In some embodiments, as shown in FIG. 20 , the second sub-electrode 1402 overlaps the first sub-electrode 1401 in the seventh via hole 34 .

[0305] In some embodiments, as shown in Figure 20, the connecting lead 33 includes: a first sub-lead 3301 that is arranged in the same layer and integrally connected to the second sub-electrode 1402, and a second sub-lead 3302 that is arranged in the same layer and integrally connected to the third sub-electrode 1403; in the area outside the third filling portion 15, the first sub-lead 3301 is overlapped with the second sub-lead 3302, thereby realizing electrical connection between the second sub-electrode 1402 and the third sub-electrode 1403, and further realizing electrical connection between the sub-electrodes in the binding electrode 14.

[0306] It should be noted that the third filling portion is provided on the same layer as the first filling portion and the second filling portion. For example, the three are formed in one patterning process, that is, a filling layer that covers the entire surface and fills the vias in each part of the planarization layer is first formed, and then a patterning process is performed to remove the area where the filling portion is not required. In some embodiments, as shown in FIG20 , the orthographic projection of the third filling portion 15 on the first base substrate 1 coincides with the orthographic projection of the third via 303 on the first base substrate 1. In this way, when the orthographic projection of the first filling portion on the first base substrate coincides with the orthographic projection of the first via on the first base substrate and the orthographic projection of the second filling portion on the first base substrate coincides with the orthographic projection of the second via on the first base substrate, the third filling portion, the second filling portion, and the first filling portion can be formed using the mask plate that forms the first via, the second via, and the third via. Moreover, the binding electrode in the area of ​​the third via hole includes an electrically connected second sub-electrode and a third sub-electrode. In this way, electrical connection between the sub-electrodes in the binding electrode can be achieved without removing the third filling portion. Since the second sub-electrode is arranged on the same layer as the first electrode and the third sub-electrode is arranged on the same layer as the second electrode, the production of the array substrate does not require an additional mask plate, which can save costs.

[0307] In some embodiments, as shown in FIG. 21 , the connection lead 33 further includes: a third sub-lead 3303 , which is provided in the same layer as the fifth sub-electrode 1405 and is integrally connected thereto.

[0308] In some embodiments, the orthographic projections of the multiple binding electrodes on the first base substrate all fall within the orthographic projection of the same third via hole on the first base substrate. Specifically, in the first binding region, a third via hole is formed in the planarization layer, corresponding to the multiple binding electrodes. Correspondingly, a sixth via hole is formed in the fifth insulating layer, corresponding to the multiple binding electrodes. The array substrate includes a third filling portion.

[0309] In some embodiments, the orthographic projection of the seventh via on the first base substrate roughly coincides with the first binding area. That is, the planarization layer and the fifth insulating layer of the first binding area are completely removed. Correspondingly, the orthographic projection of the third via on the first base substrate roughly coincides with the first binding area. In the array substrate provided by the embodiment of the present disclosure, the planarization layer and the fifth insulating layer of the first binding area are completely removed, that is, the area of ​​the seventh via is relatively large. When the material of the coating filling layer forms a filling layer, it is beneficial for the material to flow smoothly at the seventh via, avoiding material accumulation and improving the flatness of the array substrate.

[0310] In some embodiments, as shown in FIG. 20 , the first protection layer 24 in the first binding region is also completely removed, and the fourth sub-electrode 1404 is in direct contact with the third sub-electrode 1403 .

[0311] It should be noted that, as shown in FIG19 , the multiple binding electrodes 14 are not located in the same row but are arranged in multiple rows, with some connecting leads 33 passing through the area between two adjacent binding electrodes 14. If a third filling portion is provided in the area corresponding to the third via, and the third via corresponds to multiple binding electrodes, for the structure shown in FIG20 , electrical connection between the multiple sub-electrodes in the binding electrode 14 can only be achieved by connecting the first sub-lead 3301 and the second sub-lead 3302 outside the third filling portion 15. However, the distance between adjacent connecting leads is generally small. If at least one of the second sub-lead and the first sub-lead is misaligned, a short circuit may occur during subsequent binding with the drive unit.

[0312] In some embodiments, as shown in Figures 22 and 23 , the distance between the surface of the binding electrode 14 facing away from the first substrate 1 and the first substrate 1 is less than the distance between the surface of the planarization layer 3 facing away from the first substrate 1 and the first substrate 1, and the surface of the binding electrode 14 facing away from the first substrate 1 is uncovered. That is, the uppermost sub-electrode of the binding electrode 14 is located within the third via 303.

[0313] In some embodiments, as shown in FIG. 22 and FIG. 23 , the fourth sub-electrode 1404 overlaps with the first sub-electrode 1401 in the seventh via hole 34 .

[0314] In the array substrate provided by the embodiment of the present disclosure, the fourth sub-electrode is directly overlapped with the first sub-electrode at the seventh via hole, and the third filling portion is not provided in the area between the two. Therefore, there is no need to provide a sub-electrode on the same layer as the first electrode and a sub-electrode on the same layer as the second electrode to achieve electrical connection between the fourth sub-electrode and the first sub-electrode, which can avoid the short circuit problem caused by the small distance between adjacent connecting leads when alignment deviation occurs.

[0315] In some embodiments, as shown in Figures 22 and 23, the binding electrode 14 includes only a first sub-electrode 1401, a fourth sub-electrode 1404, and a fifth sub-electrode 1405. The first sub-electrode 1401 is electrically connected to the fifth sub-electrode 1405 via a via hole that penetrates the fourth insulating layer 22, the third insulating layer 21, and the second insulating layer 20. At the seventh via hole 34, the first protective layer is completely removed, and the first sub-electrode 1401 is directly connected to the fourth sub-electrode 1404.

[0316] In some embodiments, as shown in FIG22 , the third filling portion is not included in the area corresponding to the third via hole 303. That is, after the filling layer is formed, the filling layer at the seventh via hole is completely removed.

[0317] In the array substrate provided by the embodiment of the present disclosure, a third filling portion is not provided at the third via hole in the first binding area, thereby eliminating the need to provide a sub-electrode on the same layer as the first electrode and a sub-electrode on the same layer as the second electrode to achieve electrical connection between the fourth sub-electrode and the first sub-electrode, thereby avoiding the short circuit problem caused by the small distance between adjacent connecting leads when alignment deviation occurs.

[0318] Alternatively, in some embodiments, as shown in Figure 23, the area corresponding to the third via 303 includes a third filling portion 15, and the orthographic projection of the third filling portion 15 on the first base substrate 1 and the orthographic projection of the surface of the binding electrode 14 on the side facing away from the first base substrate 1 on the first base substrate 1 do not overlap with each other, that is, the orthographic projection of the third filling portion 15 on the first base substrate 1 and the orthographic projection of the fourth sub-electrode 1404 on the first base substrate 1 do not overlap with each other.

[0319] That is, the filling layer in a partial area is removed at the seventh via hole, so that the third filling portion does not cover the overlapping portion between the fourth sub-electrode and the first sub-electrode.

[0320] In some embodiments, as shown in Figure 23, the third filling portion 15 has multiple first removal areas 1501, the first removal areas 1501 correspond one-to-one to the binding electrodes 14, and the orthographic projection of the fourth sub-electrode 1404 on the first base substrate 1 falls within the orthographic projection of the first removal area 1501 on the first base substrate 1.

[0321] In some embodiments, as shown in Figures 22 and 23 , the orthographic projections of the plurality of binding electrodes 14 on the first base substrate 1 all fall within the orthographic projection of the same third via 303 on the first base substrate 1. That is, the third via 303 included in the planarization layer 3 corresponds to the plurality of binding electrodes 14. Correspondingly, the sixth via 2302 included in the fifth insulating layer 23 corresponds to the plurality of binding electrodes 14.

[0322] In some embodiments, the orthographic projection of the seventh via on the first substrate substantially overlaps with the first binding region. That is, the planarization layer and the fifth insulating layer in the first binding region are completely removed. Accordingly, the orthographic projection of the third via on the first substrate substantially overlaps with the first binding region.

[0323] It should be noted that materials that can be patterned through exposure and development processes are typically used as the material for each filling portion. The planarization layer and the fifth insulating layer in the first bonding area are completely removed, meaning the seventh via has a larger area. When the material of the first filling portion is applied to form a filling layer, this facilitates material leveling in the seventh via, preventing material accumulation. This avoids the problem of residual material in the seventh via due to poor filling layer thickness uniformity, thus preventing the bonding electrode from being covered.

[0324] In some embodiments, as shown in FIG. 22 and FIG. 23 , the connection lead 33 and the fifth sub-electrode 1405 are provided in the same layer and are integrally connected.

[0325] Based on the same inventive concept, an embodiment of the present disclosure further provides a method for preparing an array substrate, as shown in FIG24 , comprising:

[0326] S101, providing a first substrate;

[0327] S102, forming a plurality of thin film transistors on one side of the first substrate; the thin film transistors include: a gate, a source, and a drain;

[0328] S103, forming a planarization layer on a side of the plurality of thin film transistors facing away from the first substrate and forming a plurality of first via holes in the planarization layer; the first via holes corresponding to the thin film transistors one by one, the first via holes exposing at least a portion of the surface of the drain electrode facing away from the first substrate;

[0329] S104, forming a pattern of a plurality of first electrodes on a side of the planarization layer away from the first base substrate; the first electrodes are connected to the drain electrode through a first via hole;

[0330] S105, forming a pattern of a first filling portion in a region of the first via hole on a side of the first electrode facing away from the first base substrate;

[0331] S106 , forming a pattern of a plurality of second electrodes on the side of the first electrode and the first filling portion facing away from the first base substrate; the second electrodes are in one-to-one contact with the first electrodes located outside the first via holes.

[0332] The method for preparing an array substrate provided in an embodiment of the present disclosure forms a first filling portion at the first via hole and on the side of the first electrode facing away from the drain electrode to fill the first via hole, thereby improving the flatness of the array substrate in the area of ​​the first via hole. When the array substrate is used in a liquid crystal display panel, the presence of a recessed area at the edge of the spacer at the first via hole, which could cause liquid crystal disorder and a light leakage risk area, is avoided. As a result, the light-shielding pattern does not need to block the light leakage risk area, which can reduce the size of the light-shielding pattern and thereby increase the sub-pixel aperture ratio. Especially for high-pixel density display products, even if the sub-pixel size is small, the sub-pixel aperture ratio is not compromised because the light leakage risk area does not need to be blocked. In other words, the array substrate provided in an embodiment of the present disclosure can be used in high-pixel density display products. Furthermore, the array substrate provided in an embodiment of the present disclosure further includes a second electrode outside the first via hole and in contact with the first electrode on the side of the first electrode facing away from the first base substrate. In other words, the second electrode is electrically connected to the drain electrode via the first electrode. When the array substrate is used in a liquid crystal display panel, the light efficiency of the liquid crystal display panel is determined by the second electrode. The size of the second electrode does not need to avoid the first via hole, which facilitates improving light efficiency by increasing the size of the second electrode.

[0333] In some embodiments, before forming a plurality of thin film transistors on one side of the first substrate, the method further includes:

[0334] A buffer layer, a first insulating layer, a plurality of second light shielding patterns, and a pattern of the second insulating layer are sequentially formed on one side of the first base substrate.

[0335] A plurality of thin film transistors are formed on one side of the first substrate, specifically comprising:

[0336] On the side of the second insulating layer away from the second light shielding pattern, multiple active layer patterns, a third insulating layer, multiple gate patterns, a fourth insulating layer, multiple source patterns, a fifth insulating layer and multiple drain patterns are sequentially formed.

[0337] In some embodiments, after forming a plurality of thin film transistors on one side of the first substrate, the method further includes:

[0338] A color resist pattern is formed on a side of the fifth insulating layer away from the source electrode and in an area outside the drain electrode.

[0339] In some embodiments, after forming a plurality of second electrode patterns on the first electrode and the first filling portion on a side facing away from the first substrate, the method further includes:

[0340] A first protection layer, a third light shielding pattern and a pattern of a third electrode are sequentially formed on a side of the second electrode away from the first electrode.

[0341] In some embodiments, forming a pattern of a first filling portion in a region of the first via hole on a side of the first electrode facing away from the first substrate specifically includes:

[0342] forming a filling layer;

[0343] The filling layer is patterned to form a pattern of a first filling portion in the region of the first via hole.

[0344] In a specific implementation, a patterning process is performed on the filling layer to form a pattern of the first filling portion in the region of the first via hole, specifically including:

[0345] The pattern of the first filling portion is formed by adopting exposure and development processes.

[0346] In some embodiments, the first base substrate includes a display area and a peripheral area surrounding the display area;

[0347] Before forming the planarization layer, it also includes:

[0348] forming a first sub-signal line of the first signal line;

[0349] While forming a plurality of first via holes, the method further includes:

[0350] forming a plurality of second via holes in the planarization layer that penetrate the thickness of the planarization layer;

[0351] While forming the patterns of the plurality of first electrodes, the method further comprises:

[0352] forming a pattern of a second sub-signal line of the first signal line; the second sub-signal line is electrically connected to the first sub-signal line through a second via hole;

[0353] The filling layer is patterned to form a pattern of a first filling portion in the region of the first via hole, and further includes:

[0354] forming a pattern of a second filling portion in a region of the second via hole;

[0355] While forming the patterns of the plurality of second electrodes, the method further comprises:

[0356] A pattern of a third sub-signal line of the first signal line is formed on a side of the second filling portion away from the first base substrate.

[0357] In some embodiments, forming a first sub-signal line of a first signal line specifically includes:

[0358] The pattern of the first sub-signal line is formed simultaneously with the pattern of the source electrode.

[0359] In some embodiments, while forming the third electrode, the method further includes:

[0360] A pattern of a fourth sub-signal line is formed; the fourth sub-signal line is electrically connected to the third sub-signal line.

[0361] In some embodiments, the first base substrate includes a display area and a peripheral area surrounding the display area; the peripheral area includes: a first binding area located on one side of the display area in the second direction;

[0362] Before forming the planarization layer, it also includes:

[0363] forming a first sub-electrode of the binding electrode;

[0364] While forming a plurality of first via holes, the method further includes:

[0365] forming a third via hole in the planarization layer to expose the first binding region;

[0366] While forming the patterns of the plurality of first electrodes, the method further comprises:

[0367] forming a pattern of a second sub-electrode of the binding electrode; the second sub-electrode is electrically connected to the first sub-electrode through a third via hole;

[0368] The filling layer is patterned to form a pattern of a first filling portion in the region of the first via hole, and further includes:

[0369] forming a pattern of a third filling portion in the region of the third via hole;

[0370] While forming the patterns of the plurality of second electrodes, the method further comprises:

[0371] A pattern of a third sub-electrode of the binding electrode is formed on a side of the third filling portion facing away from the first base substrate.

[0372] In some embodiments, forming the second sub-electrode further includes:

[0373] forming a pattern of a first sub-lead of a connection lead electrically connected to the second sub-electrode;

[0374] When forming the third sub-electrode, the method further includes:

[0375] A pattern of a second sub-lead that is a connection lead electrically connected to the third sub-electrode is formed; and the first sub-lead is in contact with the second sub-lead.

[0376] In some embodiments, while forming the second light shielding pattern, the method further includes:

[0377] A pattern of a fifth sub-electrode of the binding electrode is formed.

[0378] In some embodiments, forming the fifth sub-electrode further includes:

[0379] A pattern of a third sub-lead that is a connection lead electrically connected to the fifth sub-electrode is formed.

[0380] Next, the method for preparing the array substrate provided by the embodiment of the present disclosure is described by taking an array substrate including a first filling portion, a second filling portion, and a third filling portion, and a binding electrode including a first sub-electrode, a second sub-electrode, a third sub-electrode, a fourth sub-electrode, and a fifth sub-electrode as an example. As shown in FIG25 , the method for preparing the array substrate includes:

[0381] S201, forming a buffer layer 18, a first insulating layer 19, a pattern of a first conductive layer 36, a second insulating layer 20, a pattern of an active layer 201, a third insulating layer 21, a pattern of a second conductive layer 37, a fourth insulating layer 22, a pattern of a third conductive layer 38, a fifth insulating layer 23, a pattern of a fourth conductive layer 39, a pattern of a color resist 7, and a planarization layer 3 in sequence on one side of the first base substrate 11, and performing a patterning process to form a first via 301, a second via 302, and a third via 303 in the planarization layer 3, and simultaneously forming a fourth via 2301 corresponding to the second via 302 and a sixth via 2302 corresponding to the third via 303 in the fifth insulating layer 23; and then forming a pattern of the fourth conductive layer 39;

[0382] The first conductive layer 36 includes: a second light shielding pattern 25, a fifth sub-electrode 1405, and a third sub-lead 3303; the second conductive layer 37 includes: a gate G; the third conductive layer 38 includes: a source S, a first sub-signal line 1001, and a first sub-electrode 1401;

[0383] The fourth conductive layer 39 includes: a first electrode 4, a second sub-signal line 1002, a second sub-electrode 1402 and a first sub-lead 3301;

[0384] S202, forming a filling layer 35, and performing a patterning process on the filling layer to form a first filling portion 5, a second filling portion 11 and a third filling portion 15;

[0385] The patterning process of the filling layer includes, for example, exposure and development;

[0386] S203, sequentially forming the pattern of the fifth conductive layer 40, the pattern of the first protective layer 24, the pattern of the third shading pattern (not shown) and the pattern of the sixth conductive layer 41; wherein, the fifth conductive layer 40 includes: a second electrode 6, a third sub-signal line 1003, a third sub-electrode 1403 and a second sub-lead 3302; the sixth conductive layer 41 includes: a third electrode 9, a fourth sub-signal line 1004 and a fourth sub-electrode 1404.

[0387] Alternatively, in some embodiments, the first base substrate includes a display area and a peripheral area surrounding the display area; the peripheral area includes: a first binding area located on one side of the display area in the second direction;

[0388] While forming a plurality of first via holes, the method further includes:

[0389] forming a third via hole in the planarization layer; and causing the orthographic projection of the binding electrode on the first base substrate to fall within the orthographic projection of the third via hole on the first base substrate;

[0390] The filling layer is patterned to form a pattern of a first filling portion in the region of the first via hole, and further includes:

[0391] The filling layer at the third via hole is removed.

[0392] In some embodiments, after removing the filling layer at the third via hole, the method further includes:

[0393] It is detected whether a filling layer remains at the third via hole. If yes, the filling layer remaining at the third via hole is exposed and developed again to remove the remaining filling layer.

[0394] Next, the method for preparing the array substrate provided by the embodiment of the present disclosure is described by taking an array substrate including a first filling portion, a second filling portion, and a binding electrode including a first sub-electrode, a fourth sub-electrode, and a fifth sub-electrode as an example. The method for preparing the array substrate includes:

[0395] S301, sequentially forming a buffer layer, a first insulating layer, a pattern of a first conductive layer, a second insulating layer, a pattern of an active layer, a third insulating layer, a pattern of a second conductive layer, a fourth insulating layer, a pattern of a third conductive layer, a fifth insulating layer, a pattern of a fourth conductive layer, a pattern of a color resist, and a planarization layer on one side of a first base substrate, performing a patterning process to form a first via hole, a second via hole, and a third via hole in the planarization layer, and simultaneously forming a fourth via hole corresponding to the second via hole and a sixth via hole corresponding to the third via hole in the fifth insulating layer; and then forming a pattern of a fourth conductive layer;

[0396] The first conductive layer includes: a second light-shielding pattern, a fifth sub-electrode, and a connecting lead; the second conductive layer includes: a gate; the third conductive layer includes: a source, a first sub-signal line, and a first sub-electrode;

[0397] Wherein, the fourth conductive layer includes: a first electrode and a second sub-signal line;

[0398] S302, as shown in FIG26, forming a filling layer 35;

[0399] S303 , performing a patterning process on the filling layer 35 to form a first filling portion 5 at the first via hole 301 , a second filling portion 11 at the second via hole 302 , and removing the filling layer 35 at the third via hole 303 ;

[0400] The patterning process of the filling layer includes, for example, exposure and development;

[0401] S304, detecting whether there is a filling layer remaining at the third via hole; if yes, executing step S305, otherwise executing step S306;

[0402] S305 , as shown in FIG26 , performing exposure and development processes on all the filling layers 35 at the third via hole 303 again to remove the filling layers 35 ;

[0403] S306, sequentially forming a pattern of a fifth conductive layer, a first protective layer, a third light-shielding pattern, and a pattern of a sixth conductive layer; wherein the fifth conductive layer includes: a second electrode, a third sub-signal line; and the sixth conductive layer includes: a third electrode, a fourth sub-signal line, and a fourth sub-electrode.

[0404] In some embodiments, the first base substrate includes a display area and a peripheral area surrounding the display area; the peripheral area includes: a first binding area located on one side of the display area in the second direction;

[0405] While forming a plurality of first via holes, the method further includes:

[0406] forming a third via hole in the planarization layer; and causing the orthographic projection of the binding electrode on the first base substrate to fall within the orthographic projection of the third via hole on the first base substrate;

[0407] The filling layer is patterned to form a pattern of a first filling portion in the region of the first via hole, and further includes:

[0408] Part of the filling layer at the third via hole is removed to form a third filling portion and a plurality of first removal areas; the orthographic projection of the third filling portion on the first base substrate and the orthographic projection of the surface of the binding electrode on the side facing away from the first base substrate on the first base substrate do not overlap with each other, and the orthographic projection of the surface of the binding electrode on the side facing away from the first base substrate on the first base substrate falls within the orthographic projection of the first removal area on the first base substrate.

[0409] Next, the method for preparing the array substrate provided by the embodiment of the present disclosure is described by taking an array substrate including a first filling portion, a second filling portion, a third filling portion, a first removal area, and a binding electrode including a first sub-electrode, a fourth sub-electrode, and a fifth sub-electrode as an example. The method for preparing the array substrate includes:

[0410] S401, forming a buffer layer, a first insulating layer, a pattern of a first conductive layer, a second insulating layer, a pattern of an active layer, a third insulating layer, a pattern of a second conductive layer, a fourth insulating layer, a pattern of a third conductive layer, a fifth insulating layer, a pattern of a fourth conductive layer, a pattern of a color resist, and a planarization layer in sequence on one side of a first base substrate, and performing a patterning process to form a first via hole, a second via hole, and a third via hole in the planarization layer, and simultaneously forming a fourth via hole corresponding to the second via hole and a sixth via hole corresponding to the third via hole in the fifth insulating layer; and then forming a pattern of a fourth conductive layer;

[0411] The first conductive layer includes: a second light-shielding pattern, a fifth sub-electrode, and a connecting lead; the second conductive layer includes: a gate; the third conductive layer includes: a source, a first sub-signal line, and a first sub-electrode;

[0412] Wherein, the fourth conductive layer includes: a first electrode and a second sub-signal line;

[0413] S402, as shown in FIG27, forming a filling layer 35;

[0414] S403, as shown in FIG27, performing a patterning process on the filling layer 35 to form a first filling portion 5 at the first via hole 301, a second filling portion 11 at the second via hole 302, and a third filling portion 15 at the third via hole 303, as well as a first removal area 1501;

[0415] The patterning process of the filling layer includes, for example, exposure and development;

[0416] S404, sequentially forming a pattern of a fifth conductive layer, a first protective layer, a second light-shielding pattern, and a pattern of a sixth conductive layer; wherein the fifth conductive layer includes: a second electrode, a third sub-signal line; and the sixth conductive layer includes: a third electrode, a fourth sub-signal line, and a fourth sub-electrode.

[0417] In some embodiments, the filling layer is patterned using a first mask plate; wherein the first mask plate includes a light-transmitting area and a non-light-transmitting area, and the pattern of the non-light-transmitting area roughly coincides with the pattern of the first filling part, the second filling part, and the third filling part; when the filling layer is exposed using the first mask plate, the exposure amount of all light-transmitting areas is the same.

[0418] Alternatively, in some embodiments, a second mask plate is used to perform a patterning process on the filling layer; wherein the first mask plate includes a first light-transmitting area, a second light-transmitting area and a non-light-transmitting area, the pattern of the non-light-transmitting area roughly coincides with the pattern of the first filling part, the second filling part and the third filling part, and the pattern of the first light-transmitting area roughly coincides with the pattern of the first removal area; when the filling layer is exposed using the second mask plate, the exposure amount of the first light-transmitting area is greater than the exposure amount of the second light-transmitting area, thereby ensuring that the filling layer in the first removal area is completely removed, and preventing the filling layer from blocking the first sub-electrode.

[0419] It should be noted that, in the method for preparing the above-mentioned array substrate provided in the embodiment of the present disclosure, the patterns, positional relationships, etc. of the various film layers in the array substrate refer to the embodiment of the above-mentioned array substrate provided in the embodiment of the present disclosure, and will not be repeated here.

[0420] An embodiment of the present disclosure provides a display panel, as shown in FIG28 , comprising:

[0421] The array substrate 43 provided in the embodiment of the present disclosure;

[0422] The opposite substrate 44 is arranged opposite to the array substrate 43;

[0423] The liquid crystal layer 45 is located between the array substrate 43 and the opposite substrate 44 .

[0424] In some embodiments, the array substrate includes a first light-transmitting area; and the opposite substrate includes:

[0425] a second substrate;

[0426] The first light-shielding pattern is located on a side of the second base substrate facing the liquid crystal layer and includes a plurality of first opening areas. The orthographic projection of the first light-shielding pattern on the first base substrate covers the first light-shielding areas.

[0427] In some embodiments, the orthographic projection of the first opening area on the first substrate overlaps with the first light-transmitting area. In the display area, the orthographic projection of the first light-shielding pattern on the first substrate overlaps with all first light-shielding areas and all second light-shielding areas of the multiple sub-pixel areas.

[0428] In a specific implementation, an alignment layer is further provided on the side of the array substrate near the liquid crystal layer and on the side of the counter substrate near the liquid crystal layer. Spacers are further provided on the side of the array substrate near the liquid crystal layer and / or on the side of the counter substrate near the liquid crystal layer. The orthographic projection of the spacers on the second base substrate is located within the orthographic projection of the first light-shielding pattern on the second base substrate.

[0429] In the display panel provided by the embodiment of the present disclosure, in the array substrate, a first via is filled with a first filling portion on the side of the first electrode away from the drain electrode, thereby improving the flatness of the array substrate in the area of ​​the first via hole. This avoids the presence of a recessed area at the edge of the spacer at the first via hole, which causes liquid crystal disorder and the presence of a light leakage risk area. As a result, the light-shielding pattern does not need to block the light leakage risk area, and the size of the light-shielding pattern can be reduced, thereby increasing the sub-pixel aperture ratio. In particular, for display products with high pixel density, even if the size of the sub-pixel is very small, the sub-pixel aperture ratio will not be lost because there is no need to block the light leakage risk area. In addition, the first electrode also includes a second electrode in contact with the first via hole on the side away from the first base substrate, that is, the second electrode is electrically connected to the drain electrode through the first electrode. When the array substrate is applied to a liquid crystal display panel, the light efficiency of the liquid crystal display panel is determined by the second electrode. The size of the second electrode does not need to avoid the first via hole, which is conducive to improving the light efficiency by increasing the size of the second electrode.

[0430] An embodiment of the present disclosure provides a display device, as shown in FIG29 , which includes a display panel 46 provided by an embodiment of the present disclosure.

[0431] In some embodiments, the display device provided in the embodiments of the present disclosure may further include a backlight module 47 located on the light incident side of the array substrate 43, as shown in FIG29 . The backlight module may be a direct-lit backlight module or an edge-lit backlight module.

[0432] In a specific implementation, the side-entry backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet stacked on the light-emitting side of the matrix light source, a diffuser, and a brightening film, etc. The reflective sheet includes an opening arranged directly opposite the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.). Submillimeter or even micron-scale micro light-emitting diodes are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, it has a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. Moreover, when micro-light-emitting diodes are used as backlight sources, more sophisticated dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0433] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the aforementioned embodiments of the array substrate and display panel, and any repetitive details will not be repeated.

[0434] In summary, the array substrate and its manufacturing method, display panel, and display device provided by the embodiments of the present disclosure utilize a first filling portion to fill a first via hole on the side of the first electrode facing away from the drain electrode, thereby improving the flatness of the array substrate in the area of ​​the first via hole. When the array substrate is used in a liquid crystal display panel, this avoids the presence of a recessed area at the edge of the spacer at the first via hole, which could cause liquid crystal disorder and a light leakage risk area. As a result, the light-shielding pattern does not need to block the light leakage risk area, allowing the size of the light-shielding pattern to be reduced, thereby increasing the sub-pixel aperture ratio. Especially for high-pixel density display products, even if the sub-pixel size is small, the sub-pixel aperture ratio is not compromised because the light leakage risk area does not need to be blocked. In other words, the array substrate provided by the embodiments of the present disclosure can be used in high-pixel density display products. Furthermore, the array substrate provided by the embodiments of the present disclosure further includes a second electrode on the side of the first electrode facing away from the first base substrate, outside the first via hole and in contact therewith. In other words, the second electrode is electrically connected to the drain electrode via the first electrode. When the array substrate is used in a liquid crystal display panel, the light efficiency of the liquid crystal display panel is determined by the second electrode. The size of the second electrode does not need to avoid the first via hole, which facilitates improving light efficiency by increasing the size of the second electrode.

[0435] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0436] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: The array substrate comprises: a first substrate base plate; A plurality of thin film transistors are located on one side of the first substrate; the thin film transistors include: a gate, a source and a drain; a planarization layer, located on a side of the drain electrode away from the first substrate, and comprising first via holes corresponding to the thin film transistors one by one; the first via holes exposing at least a portion of a surface of the drain electrode away from the first substrate; A plurality of first electrodes are located on a side of the planarization layer away from the first substrate; the first electrodes are connected to the drain electrode through the first via holes; a plurality of first filling portions, at least located in the first via hole and located on a side of the first electrode away from the first substrate; A plurality of second electrodes are located on a side of the first electrode and the first filling portion away from the first substrate; the second electrodes are in contact with the first electrode outside the first via hole.

2. The array substrate according to claim 1, wherein: The first substrate includes a display area and a peripheral area surrounding the display area; the display area includes a plurality of sub-pixel areas arranged in an array along a first direction and a second direction; the sub-pixel area includes a first light-transmitting area and a first light-shielding area, and the first light-shielding area is located on one side of the first light-transmitting area in the second direction; The orthographic projection of the second electrode on the first substrate overlaps with the first light-transmitting area; The orthographic projection of the first via hole on the first substrate falls into the first light shielding area; The orthographic projection of the first filling portion on the first base substrate at least includes a portion falling into the first light shielding area.

3. The array substrate according to claim 2, wherein: The orthographic projection of the first electrode on the first substrate overlaps with the first light-transmitting area; In the first light-transmitting area and in the second direction, the width of the second electrode is greater than the width of the first electrode.

4. The array substrate according to claim 2 or 3, wherein: The orthographic projection of the second electrode on the first base substrate overlaps with the first light-shielding area.

5. The array substrate according to claim 4, wherein: In the second direction, the first electrodes and the second electrodes that are in contact with each other are arranged in a staggered manner.

6. The array substrate according to claim 5, wherein: The first electrode comprises: a first portion located outside the first via hole and a second portion located on one side of the first portion in the second direction and at least a portion of the second portion located in the first via hole; The second electrode comprises: a third portion located outside the first via hole and a fourth portion located on one side of the third portion in the second direction and at least a portion of the fourth portion located in the first via hole; In the second direction, the width of the first portion is smaller than the width of the third portion, and the width of the second portion is larger than the width of the fourth portion. 7 . The array substrate according to claim 6 , wherein the second portion completely covers the surface of the drain electrode exposed by the first via hole.

8. The array substrate according to any one of claims 6 to 7, wherein: In the second direction, the orthographic projection of the region between two adjacent second electrodes on the first base substrate overlaps with both the first light-transmitting region and the first light-shielding region.

9. The array substrate according to any one of claims 6 to 7, wherein: The second electrode further includes: a fifth portion located on a side of the third portion away from the fourth portion in the second direction; The orthographic projection of the fifth portion on the first substrate falls into the first light shielding area; In the second direction, an orthographic projection of a gap between two adjacent second electrodes on the first base substrate falls within an orthographic projection of the first filling portion on the first base substrate.

10. The array substrate according to any one of claims 6 to 9, wherein: A surface of the first filling portion facing away from the first base substrate and a surface of the first portion facing away from the first base substrate are substantially located in the same plane.

11. The array substrate according to any one of claims 2 to 10, wherein: In the first direction, the width of the first electrode is substantially equal to the width of the second electrode; The first electrode and the second electrode are located on the same side, and edges extending along the second direction substantially overlap.

12. The array substrate according to any one of claims 2 to 11, wherein: The array substrate further includes: A plurality of color resists correspond to the sub-pixel regions one by one and are located on a side of the planarization layer close to the first base substrate; the orthographic projection of the color resists on the first base substrate at least covers the first light-transmitting region.

13. The array substrate according to claim 12, wherein: The color resist and the drain electrode are located in the same layer; The orthographic projection of the color resist on the first base substrate does not overlap with the orthographic projection of the drain on the first base substrate, and the orthographic projection of the color resist on the first base substrate does not overlap with the orthographic projection of the first via on the first base substrate.

14. The array substrate according to claim 13, wherein: The source electrode is located on the side of the drain electrode facing the first base substrate; the array substrate further includes a first interlayer insulating layer located between the source electrode and the drain electrode; the color resist and the drain electrode are located between the first interlayer insulating layer and the planarization layer.

15. The array substrate according to any one of claims 2 to 14, wherein: The array substrate further comprises: a first signal line located in the peripheral area, and a plurality of second filling portions; the first signal line is electrically connected to the third electrode; The first signal line includes: a first sub-signal line, a second sub-signal line and a third sub-signal line which are stacked; The first sub-signal line is located on a side of the planarization layer facing the first substrate; The second sub-signal line is arranged in the same layer as the first electrode; the planarization layer further comprises a plurality of second via holes penetrating the thickness thereof, the second sub-signal line is electrically connected to the first sub-signal line through the second via holes, the second sub-signal line has a first groove at the second via holes; the second filling portion is located in the first groove; The third sub-signal line is disposed in the same layer as the second electrode. The second signal sub-line and the second filling portion are in contact with the second signal sub-line at a side facing away from the first substrate.

16. The array substrate according to claim 15, wherein: An orthographic projection of the second filling portion on the first base substrate falls within an orthographic projection of the second sub-signal line and the third sub-signal line on the first base substrate.

17. The array substrate according to claim 15 or 16, wherein: The first sub-signal line is arranged in the same layer as the source electrode.

18. The array substrate according to any one of claims 15 to 17, wherein: In the display area, the array substrate further includes: a third electrode located on a side of the second electrode away from the first base substrate; The first signal line further includes: a fourth sub-signal line disposed in the same layer as the third electrode; The array substrate further includes: a first protection layer located between the third sub-signal line and the fourth sub-signal line; the fourth sub-signal line is electrically connected to the third sub-signal line through a via hole penetrating the first protection layer.

19. The array substrate according to any one of claims 2 to 18, wherein: The peripheral area includes: a first binding area located at one side of the display area in the second direction; The array substrate further comprises: a plurality of binding electrodes located in the first binding area; The planarization layer further includes a third via hole, and the orthographic projection of the binding electrode on the first substrate falls within the orthographic projection of the third via hole on the first substrate.

20. The array substrate according to claim 19, wherein: The binding electrode includes: a first sub-electrode, a second sub-electrode, a third sub-electrode and a fourth sub-electrode; The first sub-electrode is located on a side of the planarization layer facing the first substrate; The second sub-electrode is disposed in the same layer as the first electrode and is electrically connected to the first sub-electrode; The third sub-electrode is disposed in the same layer as the second electrode and is electrically connected to the second sub-electrode; The array substrate further includes: a third filling portion, located in the third via hole and between the second sub-electrode and the third sub-electrode; The fourth sub-electrode is connected to the first sub-electrode on the side of the third sub-electrode away from the first substrate. The three electrodes are in contact.

21. The array substrate according to claim 20, wherein: The array substrate includes a third electrode; the fourth sub-electrode is arranged in the same layer as the third electrode.

22. The array substrate according to claim 19, wherein: The distance from the surface of the binding electrode away from the first substrate to the first substrate is smaller than the distance from the surface of the planarization layer away from the first substrate to the first substrate, and the surface of the binding electrode away from the first substrate is not covered.

23. The array substrate according to claim 22, wherein: The array substrate further includes: a third filling portion located in a partial area of ​​the third via hole; an orthographic projection of the third filling portion on the first substrate substrate and an orthographic projection of a surface of the third via hole exposing the binding electrode away from the first substrate substrate on the first substrate substrate do not overlap.

24. The array substrate according to any one of claims 19 to 23, wherein: The orthographic projections of the plurality of binding electrodes on the first substrate all fall within the orthographic projection of the same third via hole on the first substrate.

25. A method for preparing an array substrate, wherein: The method comprises: providing a first substrate; forming a plurality of thin film transistors on one side of the first substrate; The thin film transistor comprises: a gate, a source and a drain; A planarization layer is formed on a side of the plurality of thin film transistors away from the first substrate and a plurality of first via holes are formed in the planarization layer; the first via holes correspond to the thin film transistors one by one, and the first via holes expose at least a portion of the surface of the drain electrode away from the first substrate; A pattern of a plurality of first electrodes is formed on a side of the planarization layer away from the first substrate; the first electrodes are connected to the drain electrode through the first via holes; forming a pattern of a first filling portion on a side of the first electrode away from the first base substrate and in a region of the first via hole; A plurality of electrodes are formed on the first electrode and the first filling portion on the side facing away from the first base substrate. The second electrodes are in one-to-one contact with the first electrodes located outside the first via holes.

26. The method according to claim 25, wherein: Forming a pattern of a first filling portion on a side of the first electrode away from the first substrate and in a region of the first via hole specifically includes: forming a filling layer; The filling layer is subjected to a patterning process to form a pattern of a first filling portion in a region of the first via hole.

27. The method according to claim 26, wherein: The first substrate includes a display area and a peripheral area surrounding the display area; Before forming the planarization layer, the method further comprises: forming a first sub-signal line of the first signal line; While forming a plurality of first via holes, the method further includes: forming a plurality of second via holes penetrating the thickness of the planarization layer; While forming the patterns of the plurality of first electrodes, the method further comprises: forming a pattern of a second sub-signal line of the first signal line; the second sub-signal line is electrically connected to the first sub-signal line through the second via hole; The filling layer is subjected to a patterning process to form a pattern of a first filling portion in the region of the first via hole, and further comprises: forming a pattern of a second filling portion in a region of the second via hole; While forming a plurality of second electrode patterns, the method further comprises: A pattern of a third sub-signal line of the first signal line is formed on a side of the second filling portion away from the first base substrate.

28. The method according to claim 26 or 27, wherein: The first substrate includes a display area and a peripheral area surrounding the display area; the peripheral area includes: a first binding area located at one side of the display area in the second direction; Before forming the planarization layer, the method further comprises: forming a first sub-electrode of a binding electrode; While forming a plurality of first via holes, the method further includes: A third via hole is formed in the planarization layer; the orthographic projection of the binding electrode on the first substrate falls within the orthographic projection of the third via hole on the first substrate; While forming the patterns of the plurality of first electrodes, the method further comprises: forming a pattern of a second sub-electrode of the binding electrode; the second sub-electrode is electrically connected to the first sub-electrode through the third via hole; The filling layer is subjected to a patterning process to form a pattern of a first filling portion in the region of the first via hole, and further comprises: forming a pattern of a third filling portion in a region of the third via hole; While forming a plurality of second electrode patterns, the method further comprises: A pattern of a third sub-electrode of the binding electrode is formed on a side of the third filling portion away from the first base substrate.

29. The method according to claim 26 or 27, wherein: The first substrate includes a display area and a peripheral area surrounding the display area; the peripheral area includes: a first binding area located at one side of the display area in the second direction; While forming a plurality of first via holes, the method further includes: A third via hole is formed in the planarization layer; the orthographic projection of the binding electrode on the first substrate falls within the orthographic projection of the third via hole on the first substrate; The filling layer is subjected to a patterning process to form a pattern of a first filling portion in the region of the first via hole, and further comprises: The filling layer at the third via hole is removed.

30. The method of claim 29, wherein: After removing the filling layer at the third via hole, the method further includes: It is detected whether the filling layer remains at the third via hole. If yes, all the filling layers at the third via hole are exposed and developed again to remove the filling layers.

31. The method according to claim 26 or 27, wherein: The first substrate includes a display area and a peripheral area surrounding the display area; The peripheral area includes: a first binding area located at one side of the display area in the second direction; While forming a plurality of first via holes, the method further includes: A third via hole is formed in the planarization layer; the orthographic projection of the binding electrode on the first substrate falls within the orthographic projection of the third via hole on the first substrate; The filling layer is subjected to a patterning process to form a pattern of a first filling portion in the region of the first via hole, and further comprises: Part of the filling layer at the third via hole is removed to form a third filling portion and a plurality of first removal areas; an orthographic projection of the third filling portion on the first substrate substrate and an orthographic projection of a surface of the binding electrode on the side facing away from the first substrate substrate on the first substrate substrate do not overlap with each other, and an orthographic projection of a surface of the binding electrode on the side facing away from the first substrate substrate on the first substrate substrate falls within the orthographic projection of the first removal area on the first substrate substrate.

32. A display panel, wherein: The display panel comprises: The array substrate according to any one of claims 1 to 24; an opposite substrate, arranged opposite to the array substrate; The liquid crystal layer is located between the array substrate and the opposite substrate.

33. The display panel according to claim 32, wherein: The array substrate comprises a first light-transmitting area; the opposite substrate comprises: a second substrate base plate; The first light-shielding pattern is located on a side of the second base substrate facing the liquid crystal layer, and includes a plurality of first openings; the orthographic projection of the first light-shielding pattern on the first base substrate covers the first light-shielding area.

34. A display device, wherein: The display device comprises the display panel according to any one of claims 32 to 33.

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