Front-end-of-line (FEOL) and middle-end-of-line (MOL) for planar SCMOS manufacturing processes

Abstract

The invention relates to an integrated metal oxide semiconductor (MOS) transistor and a Schottky barrier diode (SBD). An integrated planar semiconductor device includes a substrate, an SBD joining an SBD semiconductor and a barrier metal on the substrate, and a MOS transistor formed on the substrate and including a gate, a source, and a drain. A portion of the gate of the MOS transistor extends from the MOS transistor to the SBD and is in semiconductor contact with the SBD. In some embodiments, the drain of the MOS transistor includes an extended drain structure. The SBD semiconductor includes a first semiconductor portion and a second semiconductor portion. A doping profile of the extended drain structure is substantially the same as a doping profile of the second semiconductor portion. A doping concentration of a channel region of the MOS transistor is substantially the same as a doping concentration of the first semiconductor portion.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 408,796, filed on September 21, 2022, entitled "Integration of Field Effect Transistors and Schottky Diodes on a Substrate", U.S. Provisional Application No. 63 / 494,362, filed on April 5, 2023, entitled "Front-End-Of-Line (FEOL) and Middle-of-Line (MOL) of Planar SCMOS Fabrication Processes", and U.S. Provisional Application No. 63 / 509,250, filed on June 20, 2023, entitled "Front-End-Of-Line (FEOL) and Middle-of-Line (MOL) of Planar SCMOS Fabrication Processes". Each of these applications is incorporated by reference in its entirety. Technical Field

[0003] This application generally relates to integrated circuit (IC) devices, and more particularly, to devices and methods for integrating field effect transistors (FETs) and Schottky barrier diodes (SBDs) on a semiconductor substrate. Background Art

[0004] Over the past few decades, the continuous maximum increase in the density of integrated circuit (IC) devices has driven the development of various industries in the high-tech sector. These high-tech industries include semiconductors, electronic devices, computers, communications, and their associated software fields used to build system platforms and software applications. This increase in IC device density is mainly attributed to new lithography techniques that utilize shorter light wavelengths and / or chemical and physical manufacturing processes with desired yield, reproducibility, and quality control.

[0005] IC development has gone through multiple technology nodes corresponding to different semiconductor manufacturing processes, design rules, generations of circuits, and / or system architectures. Each technology node is achieved by reducing the size of the IC, improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs), and increasing the levels and density of metal interconnects. As a result, each new technology node is more complex than the previous one and thus requires more expensive microfabrication technologies, facilities, and resources. At each new technology node, the tools, time, and manpower applied to implement very-large-scale integration (VLSI) circuits also become more complex and expensive. Before the 20nm technology node, MOSFETs were integrated on a substrate with a planar structure, while after the 20nm technology node, MOSFETs began to adopt a three-dimensional (3D) structure, adding height to their channel width and shortening the channel length. However, the use of technology nodes has been focused mainly on MOSFETs and has rarely or not at all involved other active semiconductor devices (e.g., diodes). It would be beneficial to introduce into integrated circuits different types of semiconductor devices from current practice. Summary of the Invention

[0006] This application relates to integrating planar field-effect transistors (FETs) and Schottky barrier diodes (SBDs) on a substrate in a monolithic manner (e.g., via a planar semiconductor microfabrication process). Specifically, this application describes an overall IC manufacturing method for P-type and N-type SBDs. These SBDs are used together with P-type and N-type MOSFETs (e.g., PMOS and NMOS transistors) provided in existing or upcoming planar complementary metal-oxide-semiconductor (CMOS) technology nodes for large-scale industrial production, thereby implementing Schottky-based complementary metal-oxide-semiconductor (SCMOS) ICs. Each part of the SBD is formed by existing semiconductor manufacturing operations of the semiconductor microfabrication process without adding any masks and thus corresponds to the corresponding part of the FET.

[0007] In various embodiments of this application, a part of the gate of a metal-oxide-semiconductor (MOS) transistor extends from the MOS transistor to the SBD and makes contact with the SBD semiconductor of the SBD. In some embodiments, the said part of the gate of the MOS transistor extends from the MOS transistor to the SBD along a first direction perpendicular to a second direction. The source, gate, and drain of the MOS transistor are arranged along the second direction, and both the first direction and the second direction are parallel to the surface of the substrate. The front-end-of-line (FEOL) is the first part of IC manufacturing, where individual components (e.g., transistors, SBDs) are patterned on the substrate, and the middle-of-line (MOL) of IC manufacturing uses a series of contact structures to connect individual transistors and interconnects.

[0008] In one aspect of the present application, a method of forming an integrated planar semiconductor device is implemented. The method includes forming a Schottky barrier diode (SBD) on a substrate. The SBD couples an SBD semiconductor and a blocking metal. The method further includes forming source and drain electrodes of a metal oxide semiconductor (MOS) transistor on the substrate, and forming a gate of the MOS transistor. A portion of the gate of the MOS transistor extends from the MOS transistor to the SBD and contacts the SBD semiconductor.

[0009] In another aspect, an integrated planar semiconductor device includes: a substrate, a Schottky barrier diode (SBD) that couples an SBD semiconductor and a blocking metal on the substrate, and a metal oxide semiconductor (MOS) transistor formed on the substrate and including a gate, a source, and a drain. A portion of the gate of the MOS transistor extends from the MOS transistor to the SBD and contacts the SBD semiconductor.

[0010] In some embodiments, the SBD includes an N-type SBD, and the SBD semiconductor includes an N-type semiconductor material. The MOS transistor includes a P-type MOS (PMOS) transistor. The SBD and the MOS transistor are located in a P-well and an N-well, respectively. Alternatively, in some embodiments, the SBD includes a P-type SBD, and the SBD semiconductor includes a P-type semiconductor material. The MOS transistor includes an N-type MOS (NMOS) transistor. The SBD and the MOS transistor are located in an N-well and a P-well, respectively. Alternatively, in some embodiments, the SBD includes an N-type SBD, and the SBD semiconductor includes an N-type semiconductor material. The MOS transistor includes an N-type MOS (NMOS) transistor. The N-type SBD and the NMOS transistor are located in the same P-well. Alternatively, in some embodiments, the SBD includes a P-type SBD, and the SBD semiconductor includes a P-type semiconductor material. The MOS transistor includes a P-type MOS (PMOS) transistor. The P-type SBD and the PMOS transistor are located in the same N-well.

[0011] The mention of these illustrative embodiments and implementations is not intended to limit or define the present disclosure, but rather to provide examples to assist in understanding the present disclosure. Additional embodiments are discussed in the detailed description, and further description is provided in the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To better understand the various embodiments described, reference should be made to the following embodiments in conjunction with the accompanying drawings below, in which like reference numerals refer to corresponding parts throughout the figures.

[0013] Figure 1A Schematic diagram of a three-input Schottky CMOS NAND logic gate of an integrated CMOS transistor and a Schottky barrier diode according to some embodiments.

[0014] Figure 1B The IC layout diagram of the three-input NAND logic gate shown in Figure 1A is for some embodiments.

[0015] Figure 2A The first cross-sectional view of an integrated planar semiconductor device including CMOS transistors (e.g., PMOS transistors) and complementary SBDs (e.g., N-type SBDs) is for some embodiments.

[0016] Figure 2B The second cross-sectional view of an integrated planar semiconductor device including CMOS transistors (e.g., NMOS transistors) and complementary SBDs (e.g., P-type SBDs) is for some embodiments.

[0017] Figure 2C The third cross-sectional view of an integrated planar semiconductor device including CMOS transistors (e.g., PMOS transistors) and complementary SBDs (e.g., P-type SBDs) is for some embodiments.

[0018] Figure 2D The fourth cross-sectional view of an integrated planar semiconductor device 200 including CMOS transistors (e.g., NMOS transistors) and complementary SBDs (e.g., N-type SBDs) is for some embodiments.

[0019] Figure 3A and 3B are two different cross-sectional views of an exemplary integrated semiconductor device including PMOS transistors and N-type SBDs for some embodiments.

[0020] Figure 3C and 3D are two different cross-sectional views of an exemplary integrated semiconductor device including NMOS transistors and P-type SBDs for some embodiments.

[0021] Figure 4A and 4B are two different cross-sectional views of another exemplary integrated semiconductor device including NMOS transistors and N-type SBDs in a P-well for some embodiments.

[0022] Figure 4C and 4D are two different cross-sectional views of another exemplary integrated semiconductor device including PMOS transistors and P-type SBDs in an N-well for some embodiments.

[0023] Figure 4E and 4FCross-sectional views of two example integrated semiconductor devices each including an NMOS transistor and an N-type SBD in a P-well, according to some embodiments.

[0024] Figure 4G and 4H Cross-sectional views of an example integrated semiconductor device including a PMOS transistor and a P-type SBD in an N-well, according to some embodiments.

[0025] Figure 5A Cross-sectional views of an example integrated semiconductor device including a PMOS transistor and an N-type SBD, according to some embodiments.

[0026] Figure 5B Cross-sectional views of an example integrated semiconductor device including an NMOS transistor and a P-type SBD, according to some embodiments.

[0027] Figure 5C Cross-sectional views of another example integrated semiconductor device including an NMOS transistor and an N-type SBD in a P-well, according to some embodiments.

[0028] Figure 5D Cross-sectional views of another example integrated semiconductor device including a PMOS transistor and a P-type SBD in an N-well 216, according to some embodiments.

[0029] Figure 6A and 6B Two different cross-sectional views of an integrated semiconductor device including CMOS transistors and complementary SBDs and processed to a first metal layer in the MOL, according to some embodiments.

[0030] Figure 7 Flowchart of a method for forming an integrated planar semiconductor device, according to some embodiments.

[0031] Throughout several views of the drawings, like reference numerals refer to corresponding parts. Detailed Description

[0032] This application relates to Schottky-based complementary metal oxide semiconductor (SCMOS) technology that integrates P-type and N-type Schottky barrier diodes (SBDs) in planar CMOS microfabrication processes. Each SBD is made by bonding a barrier metal and a semiconductor structure. The electrical behavior of the SBD stems from the electronic properties at the interface between these two materials. The correct operation of the SBD is very sensitive to the composition of the structure and its surface. Various surface preparation methods are used to control the SBD electrical characteristics. The surface preparation methods typically include surface oxidation and cleaning steps to introduce impurity atoms at the surface and deep within the semiconductor structure, either before or after depositing the barrier metal (e.g., Ni / Co / Ti / Pt). The barrier metal is deposited on the desired regions of the surface selected by lithography. Impurity atoms can also be doped into the barrier metal before deposition. In the case of a silicon surface, the barrier metal is typically silicided by a heating cycle, which has little impact on the electrical properties of other semiconductor devices, mainly MOSFETs. In other semiconductor process cases, the barrier metal may not undergo such a chemical reaction with the silicon surface. After appropriate surface preparation, a pure barrier metal film can produce the desired electrical characteristics. Additionally, an alternative approach is to deposit a silicide compound of the barrier metal, which can be used directly as the source material for such a deposition or can be produced through an in-situ chemical reaction in the metal deposition chamber. Instead of or in addition to the doping step after deposition, impurity atoms can be incorporated into the source. Although the formation process of SBDs on various semiconductor structures is complex, it has been developed and matured. The physical and chemical principles for producing SBDs are well known. However, for CMOS integrated circuits fabricated on a silicon substrate, prior to the present invention, SBDs were typically built in the wells of the CMOS integrated circuit. The most common well is the N-type well. However, the well can also be a P-type well. The technological advancement of the present invention lies in constructing and using SBDs formed on the diffusion pockets of transistors and possibly other devices, rather than SBDs formed on P-wells / N-wells (e.g., the P-wells / N-wells can share with the source and drain of CMOS transistors or be in their own individual pockets, and these pockets are used to build other semiconductor devices). Specifically, examples of the barrier metal include, but are not limited to, nickel silicide (NiSi / NiSi2) or cobalt silicide (CoSi2). When the surface is shallowly doped with impurity atoms of a metal material (e.g., nickel, nickel silicide, cobalt, cobalt silicide, etc.) or coated with a thin layer of a metal material, other materials can be optionally applied as the barrier metal. The silicided diffusion pockets are formed simultaneously with the source and drain of the CMOS transistor. In some embodiments, the photomask is adjusted to block or insert certain ions implanted into the silicided diffusion pockets of the SBD. In an example, the series resistance of the pocket is reduced to increase the diode current density.

[0033] Each SBD has a conductance characteristic that is determined by the material composition of the barrier metal and the silicided diffusion pocket, and more specifically, by the impurities and physical properties at the metal-silicon interface at the diode junction of the SBD. Example electronic properties of this metal-silicon interface include, but are not limited to, the barrier height associated with the on / off voltage of the SBD. In some embodiments, the combination of the barrier metal and the silicided diffusion pocket results in a relatively low value of the barrier height and on / off voltage of the Schottky barrier diode as compared to the threshold voltage of the MOSFET integrated in the SCMOS technology. Therefore, a Schottky barrier diode with a lower on / off voltage is also referred to as a low-threshold Schottky barrier diode (LtSBD).

[0034] In some embodiments, the integration of the SBD in a planar CMOS manufacturing process (e.g., at 28 nm or 65 nm technology nodes) is achieved by modifying the self-aligned silicidation module. A corresponding silicide definition photomask is involved in defining the SBD. The photomask has a first critical dimension that defines the feature size of the SBD. In contrast, when the silicide definition photomask is used in a planar CMOS manufacturing process that does not involve the SBD, it has a second critical dimension (e.g., defining the feature size of the silicide resistor). The second critical dimension is larger than the first critical dimension associated with the SBD. Although the silicide definition photomask is not critical in a planar CMOS manufacturing process, it becomes critical in a planar SCMOS manufacturing process that integrates the SBD. A computer-aided design (CAD) software tool is used to control the photomask manufacturing machine to print the features of the circuit and device layout onto the silicide definition photomask according to a logic formula. The parameters applied in the logic formula are modified to reflect the change in the critical dimension of the silicide definition photomask.

[0035] In some embodiments, MOS transistors are formed on a substrate and include a gate, a source, and a drain. A portion of the gate of the MOS transistor extends from the MOS transistor to the SBD and makes semiconductor contact with the SBD. Additionally, in some embodiments ( Figure 3A and 3B ), the SBD includes an N-type SBD, and the SBD semiconductor includes an N-type semiconductor material. The MOS transistor includes a P-type MOS (PMOS) transistor. The SBD and the MOS transistor are located in a P-well and an N-well optionally adjacent to the P-well, respectively. Alternatively, in some embodiments ( Figure 3C and 3D ), the SBD includes a P-type SBD, and the SBD semiconductor includes a P-type semiconductor material. The MOS transistor includes an N-type MOS (NMOS) transistor. The SBD and the MOS transistor are located in an N-well and a P-well optionally adjacent to the N-well, respectively. Alternatively, in some embodiments ( Figure 4A and 4B), the SBD includes an N-type SBD, and the SBD semiconductor includes an N-type semiconductor material. The MOS transistor includes an N-type MOS (NMOS) transistor. The N-type SBD and the NMOS transistor are located in the same P-well. Alternatively, in some embodiments ( Figure 4C and 4D ), the SBD includes a P-type SBD, and the SBD semiconductor includes a P-type semiconductor material. The MOS transistor includes a P-type MOS (PMOS) transistor. The P-type SBD and the PMOS transistor are located in the same N-well.

[0036] Figure 1A is a schematic diagram of a three-input Schottky CMOS NAND logic gate 100 of an integrated CMOS transistor and an SBD according to some embodiments, and Figure 1B is an IC layout diagram 150 of the three-input NAND logic gate shown in Figure 1A . The three-input Schottky CMOS NAND logic gate 100 includes three P-type SBDs 102, 104, and 106, a cross-coupled latch 108, and a control transistor 110. The cross-coupled latch 108 includes two CMOS inverters 108A and 108B, and the input and output of the CMOS inverter 108A are cross-coupled to the output and input of the CMOS inverter 108B, respectively. The CMOS inverter 108A includes a PMOS transistor 112A and an NMOS transistor 114A serially coupled to the PMOS transistor 112A. The CMOS inverter 108B includes a PMOS transistor 112B and an NMOS transistor 114B serially coupled to the PMOS transistor 112B. Input A0 is coupled to the cathode of the p-type SBD 102. Input A1 is coupled to the cathode of the p-type SBD 104. Input A2 is coupled to the cathode of the p-type SBD 106. The anodes of the SBDs 102, 104, and 106 are coupled to each other. The anodes of the SBDs 102 - 106 are also coupled to the input of the CMOS inverter 108A (i.e., the gates of the PMOS transistor 112A and the NMOS transistor 114A) and the output of the CMOS inverter 108B (i.e., the drains of the PMOS transistor 112B and the NMOS transistor 114B). Conversely, the output Y of the NAND logic gate 100 is coupled to the output of the CMOS inverter 108A (i.e., the drains of the PMOS transistor 112A and the NMOS transistor 114A) and the input of the CMOS inverter 108B (i.e., the gates of the PMOS transistor 112B and the NMOS transistor 114B).

[0037] The CMOS inverters 108A and 108B are coupled between a high supply voltage VDD (e.g., 1.8V, 0.9V) and a low supply voltage VSS (e.g., ground, -1.8V). The source of the pull-up transistor 112A is coupled to the high supply voltage VDD, and the drain of the pull-up transistor 112B is coupled to the input of the CMOS inverter 108A and the anodes of the P-type SBDs 102-106. The control transistor 110 is controlled by the input signal PCKN. When the input signal PCKN is at the low supply voltage VSS, the input of the CMOS inverter 108A is at the high supply voltage VDD, and the output of the NAND logic gate 100 is at the low supply voltage VSS. Conversely, when the input signal PCKN is at the high supply voltage VSS, the input of the CMOS inverter 108A is determined by the combination of the inputs A0, A1, and A2, and the output of the NAND logic gate 100 is also determined by the combination of the inputs A0, A1, and A2. Thus, the NAND logic gate 100 is a dynamic logic that is controlled to be refreshed with a positive duty cycle of the input signal PCKN.

[0038] Reference Figure 1A , the Schottky-based CMOS implementation of the three-input NAND logic gate 100 uses a P-type control transistor 110 coupled to the anodes of the three SBDs 102-106. Conversely, in some embodiments not shown, another Schottky CMOS implementation of the three-input NAND logic gate uses an n-type transistor 100' (instead of the PMOS control transistor 110) coupled to the anodes of the three SBDs 102-106. The n-type control transistor 110' is coupled between the anodes of the three SBDs 102-106 and the low supply voltage VSS. In some embodiments not shown, the three SBDs 102-106 are implemented by N-type SBDs that share a coupling to the anode of the control transistor 110 or 110'.

[0039] In some implementations not shown, the NAND logic gate 100 has a number of inputs (e.g., 2 inputs, 8 inputs), where the number is different from 3. Each input A of the NAND logic gate 100 i is coupled to the cathode of a corresponding P-type SBD, and the anode of the corresponding P-type SBD is coupled to the input of the CMOS inverter 108A. Each P-type SBD can be implemented by a PMOS or NMOS transistor in a corresponding planar CMOS manufacturing process that does not integrate SBDs. As the number of inputs and P-type SBDs increases, the efficiency enhancement obtained by replacing transistors with SBDs also increases. Reference Figure 1B, Inputs A0, A1, and A2 are disposed over regions forming P-type SBDs 102-106. Compared to transistors formed in a corresponding planar CMOS fabrication process without integrated SBDs, the P-type SBDs 102-106 do not contain any gate, channel, source, or drain structures and require a much smaller chip area.

[0040] In some embodiments, the P-type SBDs 102-106 are formed in an N-well. In some embodiments, at least one of the P-type SBDs 102-106 is formed in an N-well in common with a subset of PMOS transistors 110, 112A, and 112B. Additionally, in some embodiments, one or both of NMOS transistors 114A and 114B are formed in a P-well, which is optionally isolated from the N-well by a field oxide or trench. Additionally, in some embodiments, the gate of at least one of PMOS transistor 112A and NMOS transistor 114A extends to at least one of the P-type SBDs 102-106 and contacts the P-type semiconductor of at least one of the P-type SBDs 102-106.

[0041] As the feature size of integrated circuits (ICs) on silicon (Si) decreases, more complex and diverse electronic functions are integrated on a single silicon die. CMOS ICs are currently used as the main semiconductor technology for forming very large scale integration (VLSI) logic and static random access memory (SRAM) ICs. The increase in the density and complexity of VLSI is mainly attributed to the continuous stepwise reduction of the minimum feature size of both semiconductor functional circuits and the corresponding metal interconnects. Specifically, the continuous increase in IC density and the number of components is caused by the development of wafer fabrication plant equipment, tools, and methods, which enables the improvement of existing microfabrication technologies and transistor structures and the application of new microfabrication technologies and transistor structures. As the VLSI technology node changes from planar CMOS fabrication processes to vertical fin-based CMOS fabrication processes, such as from 2000 - 2010, the IC density and the number of components continue to increase.

[0042] Vertical fin-based CMOS manufacturing processes are widely used at the 16 - 22nm technology nodes, where CMOS transistors are already built on fins, increasing both integration density and complexity. The vertical fin-based CMOS manufacturing process is achieved by improving established as well as new types of semiconductor microfabrication equipment and processes. For example, self-aligned multiple patterning is applied to increase the effective resolution of lithography, and atomic layer deposition (ALD) is developed to control the thickness of various materials for nanoscale layer deposition. Plasma implantation is used to introduce semiconductor doping impurities. In some embodiments, two sets of improvements are desired for the technology node. First, one desired improvement for the technology node includes simultaneously increasing the operating speed and reducing the IC die area and power dissipation. Second, another desired improvement for the technology node includes using Schottky CMOS technology for both planar and vertical fin-based CMOS manufacturing processes.

[0043] In some embodiments, at least half of the transistors used to implement the logic circuit block are replaced by LtSBDs. The diode area of each LtSBD is optionally less than half of the minimum MOSFET size, and thus, the logic circuit block integrating LtSBDs has a smaller block area on the substrate. Additionally, the signal nets or interconnects of the SBD-based logic circuit block (e.g., using SBDs) are fewer than those of the transistor-based logic circuit block (e.g., using transistors without any SBDs). For example, the three-input NAND logic gate 100 has a device area of 1.05μm × 0.73μm ( Figure 1B ). When implemented entirely based on transistors, the area of the three-input NAND logic gate is greater than the device area of 1.05μm × 0.73μm.

[0044] The advantages of SCMOS technology extend to digital circuits, SRAM and non-volatile memories, and analog circuits. SCMOS provides a low-cost solution to keep up with the progress predicted by Moore's law. SCMOS technology does not rely on reducing the size of the patterns printed on the semiconductor substrate, nor on the improvement of microfabrication steps and equipment. SCMOS technology neither requires upgrading or adding microfabrication equipment, nor does it require implementing new and more complex silicon wafer processing steps. SCMOS reduces the operating expenses of IC manufacturing. In any existing technology node, the impact of adding LtSBDs on the existing reliability and quality assurance procedures is less than creating a new transistor structure in a new technology node. Additionally, SBD-based circuits employ a smaller number of MOSFET devices than transistor-based circuits, thereby eliminating the corresponding photomasks and lithography steps in some cases. Therefore, by integrating SBDs and modifying circuits using SBDs, the overall IC manufacturing cost of the established technology node is reduced. Various embodiments of the present application relate to integrating SBDs in planar silicon resin technology nodes with little or no change to the existing planar CMOS manufacturing process.

[0045] Figure 2A FIG. 1 is a first cross-sectional view of an integrated planar semiconductor device 200 including a CMOS transistor (e.g., PMOS transistor 202) and a complementary SBD (e.g., N-type SBD 204) according to some embodiments. Figure 2B FIG. 2 is a second cross-sectional view of an integrated planar semiconductor device including a CMOS transistor (e.g., NMOS transistor 206) and a complementary SBD (e.g., P-type SBD 208) according to some embodiments. The semiconductor device 200 includes a P-type substrate 212. In an example, the substrate 212 includes P-type bulk silicon (e.g., having a resistivity of 10 ohm·cm). In another example, the substrate 212 includes SOI, including an epitaxial silicon layer formed on a buried oxide. In some embodiments ( Figure 2A ), the integrated planar semiconductor device 200 includes at least a PMOS transistor 202 and an N-type SBD 204 formed on the substrate 212. The PMOS transistor 202 includes a gate 202G, a source 202S, and a drain 202D. The N-type SBD 204 joins an N-type semiconductor 222 and a barrier metal 224. The N-type semiconductor 222 includes a first portion 222A and a second portion 222B. In some embodiments ( Figure 2B ), the integrated planar semiconductor device 200 includes at least an NMOS transistor 206 and a P-type SBD 208 formed on the substrate 212. The NMOS transistor 206 includes a gate 206G, a source 206S, and a drain 206D. The P-type SBD 208 joins a P-type semiconductor 242 and a barrier metal 244. The P-type semiconductor 242 includes a first portion 242A and a second portion 242B.

[0046] Referring to Figure 2A , in some embodiments, the channel 202C of the PMOS transistor 202 is modulated with a P-type channel implant to reduce its threshold voltage value, and the channel has a first doping concentration. The P-type channel implant is applied to form the first portion 242A of the P-type semiconductor 242 of the P-type SBD208 ( Figure 2B ). The first doping concentration of the channel 202C of the PMOS transistor 202 is substantially the same as the first doping concentration of the first portion 242A of the P-type semiconductor 242 of the P-type SBD 208 ( Figure 2B ). The doping profile of the extended drain structure 202D of the PMOS transistor is the same as that of the P-type SBD 208 ( Figure 2B) is substantially the same as the doping profile of the second portion 242B of the P-type semiconductor 242. Alternatively, in some embodiments, the channel 202C of the PMOS transistor 202 is modulated with an N-type channel implant (e.g., with an N-type dopant) to increase its threshold voltage value. The channel implant is applied to form the first portion 222A of the N-type semiconductor 222 of the N-type SBD 204. The dopant concentration of the channel 202C is different from the dopant concentration of the first portion 222A of the N-type SBD 204.

[0047] Reference Figure 2B , in some embodiments, the channel 206C of the NMOS transistor 206 is modulated with an N-type channel implant to decrease its threshold voltage value, and the channel has a first doping concentration. The N-type channel implant is applied to form the first portion 222A of the N-type semiconductor 222 of the N-type SBD 204 ( Figure 2A ) of the N-type semiconductor 222 of the N-type SBD 204 ( Figure 2A ) of the N-type semiconductor 222 of the N-type SBD 204 ( Figure 2A ) of the N-type semiconductor 222 of the N-type SBD 204 (

[0048] ) of the N-type semiconductor 222 of the N-type SBD 204 (

[0049] Reference Figure 2A, a portion of the gate 202G of the PMOS transistor 202 extends from the PMOS transistor 202 to the N-type SBD 204 substantially parallel to the surface of the semiconductor device 200. The portion of the gate 202G of the PMOS transistor 202 contacts a first portion 222A of the N-type semiconductor 222 of the N-type SBD 204 and is physically and electrically coupled to the first portion. In some embodiments, the portion of the gate comprises a silicided gate layer 202G1, a P-type polysilicon portion 202GP, and an N-type polysilicon portion 202GN. The entire gate is formed of a single polysilicon layer. The P-type polysilicon portion 202GP and the N-type polysilicon portion 202GN share a bottom portion of the same polysilicon layer, except that the polysilicon portions 202GP and 202GN are implanted with P-type dopant and N-type dopant, respectively. The silicided gate layer 202G1 comprises a top portion of the polysilicon layer and covers both the polysilicon portions 202GP and 202GN. The silicided gate layer 202G1 is formed via a self-aligned silicide process, in which a metal film is deposited on the polysilicon layer composed of the gate 202G, the source 202S, and the drain 202D, and annealing and etching occur to form the silicided gate layer 202G1 of the gate 202G and the metal silicide contacts of the source 202S and the drain 202D. Thus, the silicided gate layer 202G1 and the P-type polysilicon portion 202GP together form the gate 202G of the PMOS transistor 202, and the silicided gate layer 202G1 extends over the N-type polysilicon portion 202GN and contacts the first portion 222A of the N-type semiconductor 222 via the N-type polysilicon portion 202GN.

[0050] Reference Figure 2B , a portion of the gate 206G of the NMOS transistor 206 extends from the NMOS transistor 206 to the P-type SBD 208. The portion of the gate 206G of the NMOS transistor 206 contacts a first portion 242A of the P-type semiconductor 242 of the P-type SBD 208 and is physically and electrically coupled to the first portion. In some embodiments, the portion of the gate comprises a silicided gate layer 206G1, a P-type polysilicon portion 206GP, and an N-type polysilicon portion 206GN. The P-type polysilicon portion 206GP and the N-type polysilicon portion 206GN are implanted with P-type dopant and N-type dopant, respectively. The silicided gate layer 206G1 is formed via a self-aligned silicide process. Thus, the silicided gate layer 206G1 and the N-type polysilicon portion 206GN together form the gate 206G of the NMOS transistor 206, and the silicided gate layer 206G1 extends over the P-type polysilicon portion 202GP and contacts the first portion 242A of the P-type semiconductor 242 via the P-type polysilicon portion 206GP.

[0051] In some embodiments (Figure 2A ), an N-type polysilicon portion 202GN extending from the gate 202G of the PMOS transistor 202 has a higher doping concentration than a first portion 222A of the N-type semiconductor 222. An N-type diffusion region 230 is formed between the N-type polysilicon portion 202GN and the first portion 222A of the N-type semiconductor 222. In some embodiments ( Figure 2B ), a P-type polysilicon portion 206GP extending from the gate 206G of the NMOS transistor 206 has a higher doping concentration than a first portion 242A of the P-type semiconductor 242. A P-type diffusion region 260 is formed between the P-type polysilicon portion 206GP and the first portion 242A of the P-type semiconductor 242.

[0052] In Figure 2A and 2B In some embodiments not shown in the first cross-sectional view and the second cross-sectional view, a metal thin film is deposited to cover at least a portion of the first portions 222A and 242A of the SBDs 204 and 208 together with the polysilicon gates 202G and 206G, and is patterned to form barrier metals 224 and 244 for the SBDs 204 and 208, respectively. Additionally, in some embodiments, a junction of the N-type SBD 204 is formed between the barrier metal 224 and the first portion 222A of the N-type semiconductor 222. A second portion 222B of the N-type semiconductor 222 is formed together with the extended drain structure 206D of the NMOS transistor 206 and has the same doping profile as the extended drain structure. During the same self-aligned silicide process for forming the polysilicon gate layer 202G1 of the gate 202G and the silicide contacts of the source 202S and the drain 202D, a silicide contact is formed on the second portion 222B of the N-type semiconductor 222. The metal thin film is deposited on the second portion 222B of the N-type semiconductor 222 while being deposited on the polysilicon layer composed of the gate 202G, the source 202S, and the drain 202D. The metal thin film is annealed and etched to form a silicide contact on the second portion 222B of the N-type semiconductor 222 while simultaneously forming the polysilicon gate layer 202G1 of the gate 202G and the silicide contacts of the source 202S and the drain 202D. In some embodiments, each of the source 202S and the drain 202D of the PMOS transistor 202 and the second portion 222B of the SBD semiconductor 222 has a different silicide contact surface.

[0053] In some embodiments, a P-well 218 and an N-well 216 are formed on the substrate 212. Refer to Figure 2A, in some embodiments, the P-well 218 is adjacent to the N-well 216, and the N-type SBD 204 and the PMOS transistor 202 are located in the P-well 218 and the N-well 216, respectively. Additionally, in some embodiments, the semiconductor device 200 further includes one or more isolation structures 216-1 or 216-2 disposed between the PMOS transistor 202 and the N-type SBD 204 and configured to isolate the PMOS transistor 202 and the N-type SBD 204. In some embodiments, the N-type SBD 204 is surrounded and isolated by the isolation structure 216-1, which optionally surrounds additional semiconductor devices formed in the P-well 218. In some embodiments, the PMOS transistor 202 is surrounded and isolated by the isolation structure 216-2, which optionally surrounds additional semiconductor devices formed in the N-well 216. In some embodiments, each isolation structure includes shallow trench isolation (STI). Alternatively, in some embodiments, each isolation structure 216-1 or 216-2 includes a field oxide region. The field oxide region optionally occupies a larger area than the corresponding STI structure 216-1 or 216-2.

[0054] Figure 2C A third cross-sectional view of an integrated planar semiconductor device 200 including a CMOS transistor (e.g., PMOS transistor 202) and a complementary SBD (e.g., P-type SBD 208) according to some embodiments. Figure 2D A fourth cross-sectional view of an integrated planar semiconductor device 200 including a CMOS transistor (e.g., NMOS transistor 206) and a complementary SBD (e.g., N-type SBD 204) according to some embodiments. In some embodiments, Figure 2C Each cross-sectional view in or 2D corresponds to Figure 2A A different portion of the substrate 212 in or 2B. Refer to Figure 2C , the integrated planar semiconductor device 200 includes at least a PMOS transistor 202 and a P-type SBD 208, and the PMOS transistor 202 and the P-type SBD 208 are formed in the N-well 216 on the substrate 212. In some embodiments, the extended drain structure 202D of the PMOS device 202 overlaps with a second portion 242B of the P-type semiconductor 242 of the P-type SBD 208. The PMOS transistor 202 is directly coupled to the P-type SBD 208. Refer to Figure 2C, the integrated planar semiconductor device 200 includes at least an NMOS transistor 206 and an N-type SBD 204, and the NMOS transistor 206 and the N-type SBD 204 are formed in a P-well 218 on a substrate 212. In some embodiments, the extended drain structure 206D of the NMOS device 206 overlaps with a second portion 222B of the N-type semiconductor 222 of the N-type SBD 204. The NMOS transistor 206 is directly coupled to the N-type SBD 204.

[0055] Reference Figure 2C , the P-type SBD 208 is formed by bonding a P-type semiconductor 242 and a barrier metal 244. The first doping concentration of the first portion 242A of the P-type semiconductor 242 of the P-type SBD 208 is substantially the same as the first doping concentration of the channel 202C of the PMOS transistor 202. The doping profile of the extended drain structure 202D of the PMOS transistor 202 is substantially the same as the doping profile of the second portion 242B of the P-type semiconductor 242 of the P-type SBD 208. In some embodiments, each of the extended drain structure 202D of the PMOS transistor 202 and the first portion 242A and the second portion 242B of the P-type semiconductor 242 has a different silicide contact surface. In some embodiments, the first portion 242A of the P-type semiconductor 242 has a first silicide contact surface, and the second portion 242B of the P-type semiconductor 242 has a second silicide contact surface that is laterally separated from the first silicide contact surface by a lateral distance. The lateral distance is greater than a predefined critical dimension CD of a silicide definition mask.

[0056] In some embodiments not shown, a silicide resistor is formed on the substrate 212. The silicide resistor is different from the extended drain structure 206D of the NMOS transistor 206 and the first portion 222A and the second portion 222B of the N-type semiconductor 222. The size of the silicide resistor is much larger than the critical dimension CD of the silicide definition mask and is thus not limited by it. The source 206S and the drain structure 206D of the NMOS transistor 206 are formed via self-aligned silicidation without being limited by the critical dimension CD of the silicide definition mask. Therefore, the predefined critical dimension CD of the silicide definition mask is controlled and defined based on the lateral distance of the N-type SBD 204, which makes the non-critical silicide definition mask in the CMOS manufacturing process a critical mask in the SCMOS manufacturing process for integrating MOS transistors and SBDs.

[0057] In Figure 2DIn the example shown, both the N-type SBD 204 and the NMOS transistor 206 are formed in the P-well 218. Alternatively, in the example, the N-type SBD 204 is located in the first P-well 218, and the NMOS transistor 206 is formed in a second P-well 236 ( Figure 3C ) different from the first P-well 218. Additionally, in some embodiments ( Figure 3D ), the P-type SBD 208 is formed in the N-well 238 and is formed by bonding a P-type semiconductor 242 and a blocking metal 244. The N-well 238 is isolated from at least one of the first P-well 218 and the second P-well 236 by an isolation structure 226A.

[0058] In some embodiments, the NMOS transistor 206 includes a first NMOS transistor. The integrated semiconductor device 200 further includes a second NMOS transistor configured to operate with a second N-type channel. The second N-type channel has an alternative doping concentration different from the first doping concentration, such that the first threshold voltage of the first NMOS transistor 206 is different from the second threshold voltage of the second NMOS transistor. By these means, multiple thresholds are available for forming the NMOS transistor, and multiple threshold doping concentrations can be selected to form the N-type semiconductor 222 of the N-type SBD 204.

[0059] In some embodiments, the second portion 222B of the N-type semiconductor 222 includes a second region (e.g., a lightly doped region) in which a third region (e.g., a heavily doped region) is formed and enclosed. According to the doping profile, the second region has a second doping concentration, and the third region has a third doping concentration greater than the second doping concentration. The second doping concentration of the second portion 222B is greater than the first doping concentration of the first portion 222A.

[0060] Figure 3A and 3B are two different cross-sectional views 310 and 320 of an exemplary integrated semiconductor device 200 including a PMOS transistor 202 and an N-type SBD 204 according to some embodiments. Figure 3C and 3D are two different cross-sectional views 340 and 350 of an exemplary integrated semiconductor device 200 including an NMOS transistor 206 and a P-type SBD 208 according to some embodiments. The cross-sectional views 310 and 320 correspond to two intersecting lines on the top surface of the corresponding substrate (e.g., Figure 1BThe two vertical lines 120 and 140 in), the cross-sectional views 340 and 350 also correspond to two intersecting lines on the top surface of the corresponding substrate. The integrated semiconductor device 200 integrates the PMOS transistor 202 and the N-type SBD 204 on the substrate 212, and the integrated semiconductor device 200 integrates the NMOS transistor 206 and the P-type SBD 208 on the substrate 214. In some embodiments, the gate of the NMOS transistor 206 (e.g., corresponding to Figure 1A the NMOS transistor 114A in) extends along the first line 120 to reach the P-type SBD 208 (e.g., corresponding to Figure 1A any one of the P-type SBDs 102-106 in), and the source 206S, gate 206G, and drain 206D of the NMOS transistor 206 are arranged along the second line 140.

[0061] In the integrated semiconductor device 200, the PMOS transistor 202 is formed in the first N-well 216, and the N-type SBD 204 is formed in the first P-well 218. The N-type SBD 204 joins the N-type semiconductor 222 and the blocking metal 224 (i.e., the anode). The first P-well 218 and the N-well 216 are optionally connected to each other. Optionally, an isolation structure 226 (e.g., 226A) is formed between the first P-well 218 and the N-well 216 to enhance the electrical isolation between the PMOS transistor 202 and the N-type SBD 204. The isolation structure 226A is located between the P-well 218 and the N-well 216 and includes a field oxide region or an STI trench. In some embodiments, the isolation structure 226 (e.g., 226B) is used at the edge of the N-well 216 or the P-well 218. In some embodiments, the isolation structure 226 (e.g., 226C) is used within a corresponding one of the N-well 216 and the P-well 218 to separate two electrical structures (e.g., the N-type SBD 204 and the well contact 228). Conversely, in the integrated semiconductor device 200, the NMOS transistor 206 is formed in the second P-well 236, and the P-type SBD 208 is formed in the second N-well 238. The P-type SBD 208 joins the P-type semiconductor 242 and the blocking metal 244 (i.e., the cathode). The second P-well 236 is different from the first P-well 218, and the second N-well 238 is different from the second N-well 216. The second P-well 236 and the N-well 238 are optionally connected to each other. An isolation structure 226A is formed in the connection region between the second P-well 236 and the N-well 238 to enhance the electrical isolation between the NMOS transistor 206 and the P-type SBD208.

[0062] The well contact 228 of the first P-well 218 is a combination of a first P-type portion 228A and a second P-type portion 228B, and the P-type portions 228A and 228B are formed together with a first portion 242A and a second portion 242B of the P-type semiconductor 242 of the P-type SBD 208, respectively. In other words, the P-type portions 228A and 228B are formed together with the P-type channel 202C and the extended drain structure of the PMOS transistor 202, respectively. The second portion 228B is formed in the first P-type portion 228A of the well contact 228 and has a different silicide contact surface. The well contact 248 of the second N-well 238 is a combination of a first N-type portion 248A and a second portion 248B, and the N-type portions 248A and 248B are formed together with a first portion 222A and a second portion 222B of the N-type semiconductor 222 of the N-type SBD 204, respectively. In other words, the N-type portions 248A and 248B are formed together with the N-type channel 206C and the extended drain structure 206D of the NMOS transistor 206, respectively. The second portion 248B is formed in the first N-type portion 248A of the well contact 248 and has a different silicide contact surface.

[0063] In some embodiments, substrates 212 and 214 are different portions of a silicon wafer processed by a common planar CMOS manufacturing process and separated from the silicon wafer after the planar CMOS manufacturing process is completed. Optionally, substrates 212 and 214 form a single substrate. Optionally, substrates 212 and 214 are separated from each other. The PMOS transistor 202 has a P-type channel 202C and an extended drain structure 202D. The NMOS transistor 206 has an N-type channel 206C and an extended drain structure 206D. The N-type semiconductor 222 of the N-type SBD 204 has a first portion 222A forming an N-type diffusion trench and a second portion 222B located in the N-type diffusion trench of the first portion 222A. The P-type semiconductor 242 of the P-type SBD 208 has a first portion 242A forming a P-type diffusion trench and a second portion 242B located in the P-type diffusion trench of the first portion 242A.

[0064] The first portion 242A of the P-type semiconductor 242 of the P-type SBD 208 is formed in common with the P-type channel 202C of the PMOS transistor 202 and has the same doping concentration as the P-type channel. The second portion 242B of the P-type semiconductor 242 of the P-type SBD 208 is formed in common with the extended drain structure 202D of the PMOS transistor 202. Different silicide contact surfaces of the extended drain structure 202D of the PMOS transistor 202 and the first portion 242A and the second portion 242B of the P-type semiconductor 242 of the P-type SBD 208 are formed simultaneously. Additionally, the first portion 222A of the N-type semiconductor 222 of the N-type SBD 204 is formed in common with the N-type channel 206C of the NMOS transistor 206 and has the same doping concentration as the N-type channel. The second portion 222B of the N-type semiconductor 222 of the N-type SBD 204 is formed in common with the extended drain structure 206D of the NMOS transistor 206. Different silicide contact surfaces of the extended drain structure 206D of the NMOS transistor 206 and the first portion 222A and the second portion 222B of the N-type semiconductor 222 of the N-type SBD 204 are formed simultaneously. In some embodiments, for example, using a single contact photomask (also referred to as a self-aligned silicide (salicide) definition mask), the extended drain structures of the PMOS transistor 202 and the NMOS transistor 206, the first and second portions of the N-type semiconductor 222 of the N-type SBD 204, and the different silicide contact surfaces of the first and second portions of the P-type semiconductor 242 of the P-type SBD 208 are patterned and formed simultaneously.

[0065] After using a single contact photomask to open the different silicide contact surfaces, a metal material layer is deposited to fill the contact holes formed on the different silicide contact surfaces of the PMOS transistor 202, the NMOS transistor 206, the P-type SBD 208, and / or the N-type SBD 204. In some embodiments, the metal material layer is patterned to provide a drain path 202DA coupled to the silicide contact surface of the extended drain structure 202D of the PMOS transistor 202, an anode path 242C coupled to the silicide contact surface of the second portion 242B of the P-type semiconductor 242 of the P-type SBD 208, and a barrier metal 244 coupled to the silicide contact surface of the first portion 242A of the P-type semiconductor 242 of the P-type SBD 208. The metal material layer is also patterned to provide a drain path 206DA coupled to the silicide contact surface of the extended drain structure 206D of the NMOS transistor 206, a cathode path 222C coupled to the silicide contact surface of the second portion 222B of the N-type semiconductor 222 of the N-type SBD 204, and a barrier metal 224 coupled to the silicide contact surface of the first portion 222A of the N-type semiconductor 222 of the N-type SBD 204.

[0066] Each functional part of the SBD 204 or 208 corresponds to the corresponding part in the transistor. Specifically, the first interconnect layer of the transistor corresponds to the metal layer of the SBD, and the transistor channel having a threshold voltage enhanced doping corresponds to the semiconductor part of the SBD (e.g., 222A and 242A), while the extended drain structure of the transistor is reconfigured to provide an ohmic contact with the semiconductor part of the SBD. Although the functional parts of the SBD 204 or 208 already exist in the CMOS manufacturing process, the CMOS technology node (e.g., 0.350 μm or lower) is implemented at least based on a self-aligned silicidation (SAS) photomask (i.e., a self-aligned silicide defining mask), and the SAS photomask is modified to integrate the SBD. In the CMOS manufacturing process, the SAS photomask is used to define one or more resistors and has a critical dimension that is the minimum feature size for defining one or more resistors. This critical dimension is larger than the critical dimensions of a group of other photomasks (e.g., those defining gates, metal contacts). The SAS photomask allows for relaxation of the tolerances of the feature widths and spacings to be printed on the semiconductor substrate. In an example, the critical dimension of the SAS photomask exceeds the critical line, such that the SAS photomask is labeled as non-critical. In various embodiments of the present application, in order to integrate the SBD in the CMOS manufacturing process, the SAS photomask is changed to a critical mask having a small critical dimension (e.g., less than a predefined critical threshold).

[0067] Each CMOS technology node has a most critical photomask, the critical dimension of which is the smallest among all the photomasks used in that technology node, and the most critical photomask is the gate photomask that defines the gate of the CMOS transistor formed at that technology node. The SCMOS technology integrates the LtSBD in the CMOS technology node and is applied to VLSI applications. The SCMOS technology constructs P-type and N-type LtSBDs, and each LtSBD occupies a smaller area than the corresponding diode-connected transistor. Each LtSBD is formed on the device active region (i.e., the diffusion trench), and the device active region is directly formed on the corresponding well according to the corresponding circuit function and electrical isolation requirements. Each LtSBD contains a barrier metal in contact with a lightly doped semiconductor surface having an impurity concentration of 10 15 -10 18 atoms / cm³. The lightly doped semiconductor surface is preferably doped with arsenic (As), phosphorus (P), or antimony (Sb), boron (B) according to a retrograde profile.

[0068] Examples of the barrier metals 224 and 244 include, but are not limited to, nickel silicide (NiSi), titanium silicide (TiSi), or cobalt silicide (CoSi2). When the surface is lightly doped with impurity atoms of a metallic material (e.g., nickel, nickel silicide, cobalt, cobalt silicide, etc.) or coated with a thin layer of a metallic material, other materials may optionally be applied as barrier metals. Specifically, the barrier metals (e.g., Co, Ti) are combined with well doping and transistor threshold adjustment implantation, thereby forming nickel silicide (NiSi), titanium silicide (TiSi), or cobalt silicide (CoSi2). The LtSBD can be constructed with the desired electrical characteristics to operate with a set of MOSFETs in SCMOS circuit applications. Additionally, in some embodiments, each P-type or N-type SBD has a corresponding Schottky barrier height voltage within the Schottky barrier height voltage range. The corresponding Schottky barrier height voltage varies with the temperature of the corresponding SBD. In some embodiments, the SBDs are separated from adjacent SBDs or transistors by trenches. Optionally, ion implantation is applied to adjust the doping concentration of the SBD diffusion tank or the device active region, thereby suppressing the reverse bias current of the SBD to below the leakage current tolerance.

[0069] Reference Figure 3B , in some embodiments, the PMOS transistor 202 is formed in the first N-well 216 and is configured to operate with the P-type channel 202C. Additionally, in some embodiments, the N-type SBD 204 is located in a P-well (e.g., Figure 3B 218 in) having a P-well access region 228 (also referred to as the well contact 228, optionally including portions 228A and 228B). The doping concentration of the P-type channel of the PMOS transistor 202 is equal to the doping concentration of the first portion 228A of the P-well access region 228. The doping profile of the extended drain structure of the PMOS transistor 202 matches the doping profile of the second P-type portion 228B of the P-well access region 228. The second P-type portion 228B of the P-well access region 228 is formed in the first portion 228A of the P-well access region 228 and has a different silicide contact surface. The first P-type portion 228A and the second P-type portion 228B of the P-well access region 228 together provide a low resistance path for the P-well 218.

[0070] In some embodiments, the integrated semiconductor device 200 further includes a P-type SBD 208 formed in the second N-well 238. The P-type SBD 208 is formed by bonding a P-type semiconductor 242 and a barrier metal 244. The first N-well 216 and the second N-well 238 are combined into a single N-well 216. Alternatively, in some embodiments, the integrated semiconductor device 200 further includes a P-type SBD 208 formed in the second N-well 238. The first N-well 216 is different from the second N-well 238.

[0071] Figure 4A and 4B are two different cross-sectional views 410 and 420 of another exemplary integrated semiconductor device 200 that includes an NMOS transistor 206 and an N-type SBD 204 in a P-well 218 according to some embodiments. The N-type SBD 204 joins an N-type semiconductor 222 and a barrier metal 224 (i.e., a metal anode). A first doping concentration of a first portion 222A of the N-type semiconductor 222 of the N-type SBD 204 is substantially the same as a first doping concentration of an N-type channel 206C of the NMOS transistor 206. A doping profile of an extended drain structure 206D of the NMOS transistor 206 is substantially the same as a doping profile of a second portion 222B of the N-type semiconductor 222. Each of the extended drain structure 206D of the NMOS transistor 206 and the first portion 222A and the second portion 222B of the N-type semiconductor 222 has a different silicide contact surface. In some embodiments, the N-type SBD 204 includes two SBDs having separate anodes 204A-1 and 204A-2 and a common cathode 204C. The barrier metal 224 is divided to be included in the two SBDs, and the first portion 222A of the N-type semiconductor 222 is also divided to be included in the two SBDs. Alternatively, in some embodiments, each of the barrier metal 224 and the first portion 222A of the N-type semiconductor 222 partially surrounds the second portion 222B of the N-type semiconductor 222, and the N-type SBD 204 includes a single SBD, regardless of whether the anodes 204A-1 and 204A-2 are separate or connected.

[0072] Figure 4C and 4D are two different cross-sectional views 440 and 450 of another exemplary integrated semiconductor device 200 that includes a PMOS transistor 202 and a P-type SBD 208 in an N-well 216 according to some embodiments. The cross-sectional views 440 and 450 correspond to two intersecting lines (e.g., Figure 1B two vertical lines 120 and 140 in Figure 1A ) on a top surface of a corresponding substrate. In some embodiments, a gate of the PMOS transistor 202 (e.g., corresponding to the PMOS transistor 112A in Figure 1A ) extends along a first line 120 to reach the P-type SBD 208 (e.g., corresponding to any one of the P-type SBDs 102-106 in

[0073] The P-type SBD 208 joins the P-type semiconductor 242 and the blocking metal 244 (e.g., metal cathode). The first doping concentration of the P-type channel 202C of the PMOS transistor 202 is substantially the same as the first doping concentration of the first portion 242A of the P-type semiconductor 242 of the P-type SBD 208. The doping profile of the extended drain structure 202D of the PMOS transistor 202 is substantially the same as the doping profile of the second portion 242B of the P-type semiconductor 242. Each of the extended drain structure 202D of the PMOS transistor 202 and the first portion 242A and the second portion 242B of the P-type semiconductor 242 has a different silicide contact surface. In some embodiments, the P-type SBD 208 includes two SBDs having separate cathodes 208C-1 and 208C-2 and a common anode 208A. The blocking metal 244 is divided to be included in the two SBDs, and the first portion 242A of the P-type semiconductor 242 is also divided to be included in the two SBDs. Alternatively, in some embodiments, each of the blocking metal 244 and the first portion 242A of the P-type semiconductor 242 partially surrounds the second portion 242B of the P-type semiconductor 242, and the P-type SBD 208 includes a single SBD, regardless of whether the cathodes 208C-1 and 208C-2 are separate or connected.

[0074] In some embodiments, the first portion 242A of the P-type semiconductor 242 has a first silicide contact surface, and the second portion 242B of the P-type semiconductor has a second silicide contact surface that is laterally separated from the first silicide contact surface by a lateral distance l2. The lateral distance l2 is greater than the predefined critical dimension CD of the silicide definition mask.

[0075] In some embodiments, the integrated semiconductor device 200 includes a silicide resistor that is formed on the substrate 212 and is different from the extended drain structure 202D of the PMOS transistor 202 and the first portion 242A and the second portion 242B of the P-type semiconductor 242. The size of the silicide resistor is much larger than the critical dimension CD of the silicide definition mask and is thus not limited by it. The source 202S and the drain structure 202D of the PMOS transistor 202 are formed by self-aligned silicidation without being limited by the critical dimension CD of the silicide definition mask. Therefore, the predefined critical dimension CD of the silicide definition mask is controlled and defined based on the lateral distance l1 or l2 of the P-type SBD 208, which makes the non-critical silicide definition mask in the CMOS manufacturing process a critical mask in the SCMOS manufacturing process for integrating MOS transistors and SBDs.

[0076] In some embodiments, PMOS transistor 202 includes a first PMOS transistor. Integrated semiconductor device 200 includes a second PMOS transistor configured to operate with a second P-type channel. The second P-type channel has an alternative doping concentration different from the first doping concentration such that a first threshold voltage of the first PMOS transistor 202 is different from a second threshold voltage of the second PMOS transistor.

[0077] In some embodiments, a second portion 242B of P-type semiconductor 242 includes a second region (e.g., a lightly doped region) in which a third region (e.g., a heavily doped region) is formed and enclosed. According to the doping profile, the second region has a second doping concentration and the third region has a third doping concentration greater than the second doping concentration. The second doping concentration of the second region is greater than the first doping concentration of the first portion 242A.

[0078] In Figure 4A - 4D In some embodiments shown, both P-type SBD 208 and PMOS transistor 202 are formed in N-well 216. Alternatively, in Figure 3A - 3D In some embodiments shown, P-type SBD 208 is located in a first N-well 238 and PMOS transistor 202 is formed in a second N-well 216 different from the first N-well 238. Additionally, in some embodiments, integrated semiconductor device 200 further includes an N-type SBD 204 formed in P-well 218 and formed by bonding N-type semiconductor 222 and barrier metal 224, wherein P-well 218 is isolated from at least one of the first N-well 238 and the second N-well 216 by an isolation structure 226A (e.g., a field oxide or an STI trench).

[0079] In some embodiments, referring to Figure 3A and 4C , P-type SBD 208 is located in N-well 216 having an N-well access region 248. The doping concentration of channel 206C of NMOS transistor 206 is equal to the doping concentration of a first N-type portion 248A of N-well access region 248. The doping profile of the extended drain structure 206D of NMOS transistor 206 matches the doping profile of a second portion 248B of N-well access region 248. The second portion 248B of N-well access region 248 is formed in the first N-type portion 248A of N-well access region 248 and has a different silicide contact surface. The first N-type portion 248A and the second N-type portion 248B of N-well access region 248 together provide a low-resistance path for N-well 216. In some embodiments not shown, N-well 238 has an N-well access region 248. In some embodiments, referring to Figure 3C and 4A, the P-well 236 or 216 has a P-well access region 228. The doping concentration of the channel 202C of the PMOS transistor 202 is equal to the doping concentration of the first P-type portion 228A of the P-well access region 228. The doping profile of the extended drain structure 202D of the PMOS transistor 202 matches the doping profile of the second portion 228B of the P-well access region 228. The second portion 228B of the P-well access region 228 is formed in the first P-type portion 228A of the P-well access region 228 and has a different silicide contact surface. The first P-type portion 228A and the second P-type portion 228B of the P-well access region 228 together provide a low-resistance path for the P-well 236 or 218.

[0080] Figure 4E and 4F are cross-sectional views 460 and 470 of two example integrated semiconductor devices 200 each including an NMOS transistor 206 and an N-type SBD 204-1 in a P-well 218 according to some embodiments. In some embodiments, the extended drain structure 206D of the NMOS device 206 overlaps with the second portion 222B of the N-type semiconductor 222 of the N-type SBD 204-1. The drain of the NMOS 206 is electrically coupled to the cathode of the N-type SBD 204-1. In some embodiments, the P-well 218 has a P-well access region 228 that provides a low-resistance path for the P-well 218. Additionally, in some embodiments, the NMOS transistor 206 and the P-well access region 228 are isolated by an isolation structure 226-1 (e.g., a field oxide region or an STI trench structure). Refer to Figure 4E , in some embodiments, the P-well includes two N-type SBDs 204-1 and 204-2 in the P-well 218. The N-type SBDs 204-1 and 204-2 are isolated by an isolation structure 226-2 (e.g., a field oxide region or an STI trench structure). Refer to Figure 4F , in some embodiments, the P-well 218 includes a single N-type SBD 204-1 in the P-well 218. The N-type SBD 204-1 includes two or more metal electrodes 204A-1 and 204A-2 that serve as the anode of the N-type SBD 204-1.

[0081] Figure 4G and 4HCross-sectional views 480 and 490 of an exemplary integrated semiconductor device 200 each including a PMOS transistor 202 and a P-type SBD 208-1 in an N-well 216, according to some embodiments. In some embodiments, an extended drain structure 202D of the PMOS device 202 overlaps a second portion 242B of a P-type semiconductor 242 of the P-type SBD 208-1. The drain of the PMOS 202 serves as the anode of the P-type SBD 208-1. The PMOS 202 corresponds to one of the PMOS transistors 110 and 112B, and the P-type SBD 208-1 corresponds to Figure 1A one of the SBDs 102-106 in Figure 4G . In some embodiments, the N-well 216 has an N-well access region 248 that provides a low-resistance path for the N-well 216. Additionally, in some embodiments, the PMOS transistor 202 and the N-well access region 248 are physically adjacent to each other, and a source 202S of the PMOS transistor 202 is physically connected to the N-well access region 248 via at least a first metal layer 482. In some cases, the first metal layer 482 is electrically coupled to a high power supply VDD. Referring to Figure 4H , in some embodiments, the N-well includes two P-type SBDs 208-1 and 208-2 in the N-well 216. The P-type SBDs 208-1 and 208-2 are isolated by an isolation structure 226-1 (e.g., a field oxide region or an STI trench structure). Referring to

[0082] Figure 5A Figure 5B Cross-sectional view 510 of an exemplary integrated semiconductor device 200 including a PMOS transistor 202 and an N-type SBD 204, according to some embodiments. Cross-sectional view 520 of an exemplary integrated semiconductor device 200 including an NMOS transistor 206 and a P-type SBD 208, according to some embodiments. Figure 5C Cross-sectional view 530 of another exemplary integrated semiconductor device 200 including an NMOS transistor 206 and an N-type SBD 204 in a P-well 218, according to some embodiments. Figure 5D Cross-sectional view 540 of another exemplary integrated semiconductor device 200 including a PMOS transistor 202 and a P-type SBD 208 in an N-well 216, according to some embodiments. In some embodiments, each of the gates 202G and 206G extends over a corresponding drain 202D or 206D or well access region 228 or 248, and is electrically insulated from the drain or the well access region.

[0083] Reference Figure 5A or 5D, a portion of the gate 202G of the PMOS transistor 202 extends substantially parallel to the surface of the semiconductor device 200 and extends from the PMOS transistor 202 to the SBD 204 or SBD 208. The portion of the gate 202G of the PMOS transistor 202 contacts a second portion of the SBD semiconductor 222 or 242 of the SBD 204 or 208, and is physically and electrically coupled to the second portion. In some embodiments, the portion of the gate comprises a silicided gate layer 202G1, a P-type polysilicon portion 202GP, and an N-type polysilicon portion 202GN. Alternatively, in some embodiments, the portion of the gate comprises a silicided gate layer 202G1 and an N-type polysilicon portion 202GN. The entire gate is formed of a single polysilicon layer. Reference Figure 5A , in some embodiments, the P-type polysilicon portion 202GP and the N-type polysilicon portion 202GN share a bottom portion of the same polysilicon layer, except that the polysilicon portions 202GP and 202GN are implanted with P-type and N-type dopants, respectively. Reference Figure 5D , in some embodiments, the P-type polysilicon portion 202GP extends from the PMOS 202 to the P-type SBD 208 together with the silicided gate layer 202G1. The silicided gate layer 202G1 comprises a top portion of the polysilicon layer and covers the polysilicon portion 202GP and / or 202GN.

[0084] Reference Figure 5B or 5C, a portion of the gate 206G of the NMOS transistor 206 extends substantially parallel to the surface of the semiconductor device 200 from the NMOS transistor 206 to the SBD 208 or 204. The portion of the gate 206G of the NMOS transistor 206 contacts a first portion of the SBD semiconductor 222 or 242 of the SBD 208 or 204, and is physically and electrically coupled to the first portion. In some embodiments, the portion of the gate comprises a silicided gate layer 206G1, an N-type polysilicon portion 206GN, and a P-type polysilicon portion 206GP. Alternatively, in some embodiments, the portion of the gate comprises a silicided gate layer 206G1 and a P-type polysilicon portion 206GP. The entire gate is formed of a single polysilicon layer. The entire gate is formed of a single polysilicon layer. Reference Figure 5B , the P-type polysilicon portion 206GP and the N-type polysilicon portion 206GN share a bottom portion of the same polysilicon layer, except that the polysilicon portions 206GP and 206GN are implanted with P-type and N-type dopants, respectively. Reference Figure 5C, in some embodiments, the N-type polysilicon portion 206GN extends from the NMOS 206 to the N-type SBD 204 together with the salicided gate layer 206G1. The salicided gate layer 206G1 includes the top portion of the polysilicon layer and covers the polysilicon portion 206GP and / or 206GN.

[0085] The salicided gate layers 202G1 and 206G1 are formed via a self-aligned silicide process, in which a metal thin film is deposited on the polysilicon layer composed of the gates 202G and 206G, the sources 202S and 206S, and the drains 202D and 206D, and annealing and etching occur to form the salicided gate layers of the gates 202G and 206G and the metal silicide contacts of the sources 202S and 206S and the drains 202D and 206D. Refer to Figure 5A and 5D , the salicided gate layer 202G1 and the P-type polysilicon portion 202GP together form the gate 206G of the PMOS transistor 202, and the salicided gate layer 202G1 extends onto the polysilicon portion 202GN or 202GP and contacts the first portions of the N-type semiconductor 222 or the P-type semiconductor 242 respectively. Refer to Figure 5B and 5C , the salicided gate layer 206G1 and the P-type polysilicon portion 206GP together form the gate 206G of the NMOS transistor 206, and the salicided gate layer 206G1 extends onto the polysilicon portion 206GP or 206GN and contacts the first portions of the N-type semiconductor 222 or the P-type semiconductor 242 respectively.

[0086] During the same self-aligned silicide process, the salicided gate layers of the gates 202G and 206G, and the metal silicide contacts of the sources 202S and 206S and the drains 202D and 206D are formed simultaneously with the metal silicide contacts of the second portions 222B of the N-type semiconductor 222 and the second portions 242B of the P-type semiconductor 242. A metal thin film is deposited on the second portions 222B of the N-type semiconductor 222 and the second portions 242B of the P-type semiconductor 242, while being deposited on the polysilicon layer composed of the gates 202G and 206G, the sources 202S and 206S, and the drains 202D and 206D. The metal thin film is annealed and etched so as to form not only the metal silicide contacts of the transistor sources, transistor drains, and SBD semiconductors, but also the salicided gate layers of the transistor gates for accessing the SBD semiconductors of the SBD.

[0087] In some embodiments ( Figure 5A and 5C), the N-type polysilicon portions 202GN or 206GN extending from the gates 202 or 206 have a higher doping concentration than the first portion 222A of the N-type semiconductor 222 of the N-type SBD 204. An N-type diffusion region 230 (not shown) is formed between the N-type polysilicon portion 202GN or 206GN and the first portion 222A of the N-type semiconductor 222. In some embodiments ( Figure 5B and 5D ), the P-type polysilicon portions 206GP or 202GP extending from the gates 206 or 202 have a higher doping concentration than the first portion 242A of the P-type semiconductor 242 of the P-type SBD 208. A P-type diffusion region 260 (not shown) is formed between the P-type polysilicon portion 206GP or 202GP and the first portion 242A of the P-type semiconductor 242.

[0088] Figure 6A and 6B are two different cross-sectional views 610 and 620 of an integrated semiconductor device 200 including CMOS transistors 202 and 206 and complementary SBDs 204 and 208 and processed in the MOL as a first metal layer according to some embodiments. After the FEOL, the surfaces of different silicide contact surfaces of the gate 202G, source structure 202S, and drain structure 202D of the PMOS transistor 202 are exposed, and the surfaces of different silicide contact surfaces of the gate 206G, source structure 206S, and drain structure 206D of the NMOS transistor 206 are also exposed. The surface of the barrier metal 244 of the P-type SBD 208 and the second portion 242B of the P-type semiconductor 242 are exposed, and the surface of the barrier metal 224 of the N-type SBD 204 and the second portion 222B of the N-type semiconductor 222 are also exposed. A first metal layer is deposited and multiple paths are provided to the exposed surfaces of the different silicide contact surfaces. The first metal layer is a combination of a barrier metal layer (e.g., nickel, nickel silicide, cobalt, cobalt silicide, etc.) and a conductive metal layer (e.g., copper). The barrier metal layer provides the barrier metals 224 and 244 for the N-type SBD 204 and the P-type SBD 208, and provides contact enhancement metals on the different silicide contact surfaces of the PMOS transistor 202, N-type SBD 204, NMOS transistor 206, and P-type SBD 208 respectively. The conductive metal layer is patterned into a first interconnect layer and provides paths to the exposed portions of the different silicide contact surfaces of the PMOS transistor 202, N-type SBD 204, NMOS transistor 206, and P-type SBD 208 respectively.

[0089] In some embodiments, refer to Figure 6A, the NMOS transistor 206 has a drain path 206DA coupled to the silicide contact surface of the extended drain structure 206D of the NMOS transistor 206. The N-type SBD 204 has an anode path 242C coupled to the silicide contact surface of the second portion 242B of the P-type semiconductor 242. The drain path 206DA, the cathode path 222C, and the barrier metal 224 are formed of a first metal layer. In some embodiments, the source path 206SA is also formed of the first metal layer. A subset of the source path 206SA, the drain path 206DA, the cathode path 222C, and the barrier metal 224 are electrically coupled via the first metal layer. Additionally, in some embodiments, the drain structure 206D of the NMOS transistor 206 and the second portion 222B of the N-type semiconductor 222 of the N-type SBD 204 optionally overlap each other, and the drain path 206DA and the cathode path 222C also optionally overlap each other. Conversely, in some embodiments, the drain structure 206D and the second portion 222B of the N-type semiconductor 222 overlap each other and are buried under the first metal layer without any drain or cathode path.

[0090] In some embodiments, referring to Figure 6B , the PMOS transistor 202 has a drain path 202DA coupled to the silicide contact surface of the extended drain structure 202D of the PMOS transistor 202. The P-type SBD 208 has an anode path 242C coupled to the silicide contact surface of the second portion 242B of the P-type semiconductor 242. The drain path 202DA, the anode path 242C, and the barrier metal 244 are formed of a first metal layer. In some embodiments, the source path 202SA is also formed of the first metal layer. A subset of the source path 202SA, the drain path 202DA, the anode path 242C, and the barrier metal 244 are electrically coupled via the first metal layer (e.g., via the interconnect 602). Additionally, in some embodiments, the drain structure 202D of the PMOS transistor 202 and the second portion 242B of the P-type semiconductor 242 of the P-type SBD 208 optionally overlap each other, and the drain path 202DA and the anode path 242C also optionally overlap each other. Conversely, in some embodiments, the drain structure 202D and the second portion 242B of the P-type semiconductor 242 overlap each other and are buried under the first metal layer without any drain or anode path.

[0091] In some embodiments, not shown, each of the silicide contact surfaces of the gate 206G of the NMOS transistor 206 and the gate 202G of the PMOS transistor 202 is at least partially covered by a first metal layer and accessed through a respective gate via. The respective gate vias are optionally coupled, for example, via the first metal layer and / or any other interconnect layer formed above the first metal layer, to a subset of the gates, sources, and drains of the CMOS transistors and / or a subset of the barrier metals and semiconductors of the complementary SBDs formed on the substrate 212 of the integrated semiconductor device 200.

[0092] Figure 7 FIG. 700 is a flow chart of a method 700 for forming an integrated planar semiconductor device 200 according to some embodiments. Method 700 includes forming (702) a Schottky barrier diode (SBD) on a substrate. The SBD joins an SBD semiconductor and a barrier metal. Method 700 further includes forming (704) sources and drains of metal oxide semiconductor (MOS) transistors on the substrate, and forming gates of the MOS transistors. A portion of the gate of the MOS transistor extends (706) to the SBD and contacts the SBD semiconductor. In some embodiments, the gate of the MOS transistor includes a polysiliconized gate layer.

[0093] In some embodiments, the drain of the MOS transistor includes (708) an extended drain structure. The SBD semiconductor includes (710) a first semiconductor portion and a second semiconductor portion, and the barrier metal contacts the first semiconductor portion. The doping profile of the extended drain structure is substantially the same (712) as the doping profile of the second semiconductor portion. The doping concentration of the channel region of the MOS transistor is substantially the same (714) as the doping concentration of the first semiconductor portion. Additionally, in some embodiments, each of the extended drain structure of the MOS transistor and the second semiconductor portion of the SBD semiconductor has a different silicide contact surface.

[0094] In some embodiments, method 700 includes forming source vias, drain vias, and SBD semiconductor vias from a metal layer. The source vias, drain vias, and SBD semiconductor vias contact the source, drain, and SBD semiconductor on the substrate, respectively.

[0095] In some embodiments ( Figure 3A and 3B) The SBD includes an N-type SBD, and the SBD semiconductor includes an N-type semiconductor material. The MOS transistor includes a P-type MOS (PMOS) transistor. The SBD and the MOS transistor are located in a P-well and an N-well adjacent to the P-well. Additionally, in some embodiments, the portion of the gate includes a (716) polysiliconized gate layer, a P-type polysilicon portion, and an N-type polysilicon portion. The polysiliconized gate layer and the P-type polysilicon portion together form the gate of the (718) PMOS transistor. The polysiliconized gate layer extends (720) over the N-type polysilicon portion and contacts the SBD semiconductor via the N-type polysilicon portion. Additionally, in some embodiments, the polysiliconized gate layer extends in a first direction perpendicular to a second direction, and the P-type polysilicon portion is disposed adjacent to the N-type polysilicon portion along the first direction. The source, gate, and drain of the MOS transistor are arranged along the second direction, and both the first direction and the second direction are parallel to the surface of the substrate.

[0096] In some embodiments, method 700 further includes forming an N-type MOS (NMOS) transistor in the P-well on the substrate, the NMOS transistor including a second gate, a second source, and a second drain. Additionally, in some embodiments, method 700 further includes extending the portion of the gate of the MOS transistor from the SBD to the NMOS transistor to merge with a corresponding portion of the second gate.

[0097] In some embodiments, the SBD includes a first SBD. Method 700 further includes forming a second SBD on the substrate that joins a second SBD semiconductor and a second barrier metal, and extending a portion of the gate of the MOS transistor from the first SBD to the second SBD to contact the second SBD semiconductor. The first SBD and the second SBD are of the same type and are formed in the same well.

[0098] In some embodiments ( Figure 3C and 3D) The SBD includes a P-type SBD, and the SBD semiconductor includes a P-type semiconductor material. The MOS transistor includes an N-type MOS (NMOS) transistor. The SBD and the MOS transistor are located in an N-well and a P-well adjacent to the N-well. Additionally, in some embodiments, the portion of the gate includes a silicided gate layer, a P-type polysilicon portion, and an N-type polysilicon portion. The silicided gate layer and the N-type polysilicon portion together form the gate of the NMOS transistor. The silicided gate layer extends over the P-type polysilicon portion and contacts the SBD semiconductor via the P-type polysilicon portion. Additionally, in some embodiments, the silicided gate layer extends in a first direction perpendicular to a second direction. The P-type polysilicon portion is disposed adjacent to the N-type polysilicon portion in the first direction. The source, gate, and drain of the MOS transistor are arranged in the second direction, and both the first direction and the second direction are parallel to the surface of the substrate. In some embodiments, method 700 includes forming a P-type MOS (PMOS) transistor on the substrate, the PMOS transistor being formed in the N-well and including a second gate, a second source, and a second drain. Additionally, in some embodiments, method 700 further includes extending the portion of the gate of the MOS transistor from the SBD to the PMOS transistor to merge with a corresponding portion of the second gate.

[0099] In some embodiments ( Figure 4A and 4B ), the SBD includes an N-type SBD, and the SBD semiconductor includes an N-type semiconductor material. The MOS transistor includes an N-type MOS (NMOS) transistor. The N-type SBD and the NMOS transistor are located in the same P-well. The portion of the gate includes a silicided gate layer and an N-type polysilicon portion. The silicided gate layer and the N-type polysilicon portion together form the gate of the NMOS transistor. The silicided gate layer and the N-type polysilicon portion extend over the SBD and contact the SBD semiconductor via the N-type polysilicon portion.

[0100] In some embodiments ( Figure 4C and 4D ), the SBD includes a P-type SBD, and the SBD semiconductor includes a P-type semiconductor material. The MOS transistor includes a P-type MOS (PMOS) transistor. The P-type SBD and the PMOS transistor are located in the same N-well. The portion of the gate includes a silicided gate layer and a P-type polysilicon portion. The silicided gate layer and the P-type polysilicon portion together form the gate of the PMOS transistor. The silicided gate layer and the P-type polysilicon portion extend over the SBD and contact the SBD semiconductor via the P-type polysilicon portion.

[0101] In some embodiments, the portion of the gate of the MOS transistor extends from the MOS transistor to the SBD along a first direction perpendicular to the second direction. The source, gate, and drain of the MOS transistor are arranged along the second direction, and both the first direction and the second direction are parallel to the surface of the substrate.

[0102] In some embodiments, method 700 further includes forming a field oxide region or a shallow trench isolation (STI) structure. The field oxide region or the STI structure is disposed between the SBD and the MOS transistor and is configured to isolate the SBD and the MOS transistor.

[0103] In some embodiments, the SBD and the MOS transistor belong to an X-input NAND logic gate, where X is a positive integer greater than 1.

[0104] It should be understood that the specific order of operations described for each of the above figures is merely exemplary and is not intended to indicate that the described order is the only order in which the operations can be performed. Those of ordinary skill in the art will recognize various ways of forming an integrated semiconductor device having a MOSFET device and an SBD device on the same substrate as described herein. Additionally, it should be noted that the details described with respect to one of the above processes also apply in a similar manner to any of the other processes described above. For the sake of brevity, similar details are not repeated.

[0105] It should also be understood that although the terms first, second, etc. are used herein in some cases to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various embodiments described, a first audio feature type may be referred to as a second audio feature type, and similarly, a second audio feature type may be referred to as a first audio feature type. The first audio feature type and the second audio feature type are both audio feature types, but they are not the same audio feature type.

[0106] The terms used in describing the various embodiments described herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It should be further understood that the terms "includes", "including", "comprises", and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0107] As used herein, depending on the context, the term "if" may optionally be construed to mean "when" or "after" or "in response to determining" or "in response to detecting" or "in accordance with determining". Similarly, depending on the context, the phrase "if determined" or "if detected [the stated condition or event]" may optionally be construed to mean "after determining" or "in response to determining" or "after detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]" or "in accordance with determining and detecting [the stated condition or event]".

[0108] Although the various figures show several logical stages in a particular order, stages that are not order-dependent can be reordered, and other stages can be combined or broken down. Although some reordering or other grouping is specifically mentioned, other reordering or grouping will be apparent to those of ordinary skill in the art, and thus the orderings and groupings presented herein are not an exhaustive list of alternatives. In addition, it should be recognized that the stages can be implemented in hardware, firmware, software, or any combination thereof.

[0109] For purposes of explanation, the foregoing description has been presented with reference to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Given the above teachings, many modifications and variations are possible. The embodiments were chosen to best explain the underlying principles of the claims and their practical application, thereby enabling others skilled in the art to best utilize the embodiments and make various modifications suitable for the particular uses contemplated.

Claims

1. An integrated planar semiconductor device, comprising: Substrate; A Schottky barrier diode (SBD) that bonds an SBD semiconductor and a blocking metal on the substrate; And A metal oxide semiconductor (MOS) transistor formed on the substrate and including a gate, a source, and a drain, wherein a portion of the gate of the MOS transistor extends from the MOS transistor to the SBD and contacts the SBD semiconductor.

2. The semiconductor device according to claim 1, wherein: The drain of the MOS transistor includes an extended drain structure; The SBD semiconductor includes a first semiconductor portion and a second semiconductor portion, and the blocking metal contacts the first semiconductor portion; The doping profile of the extended drain structure is substantially the same as the doping profile of the second semiconductor portion; And And The doping concentration of the channel region of the MOS transistor is substantially the same as the doping concentration of the first semiconductor portion.

3. The semiconductor device according to claim 2, wherein each of the extended drain structure of the MOS transistor and the second semiconductor portion of the SBD semiconductor has a different silicide contact surface.

4. The semiconductor device according to any one of claims 1 to 3, further comprising: A source path, a drain path, and an SBD semiconductor path, wherein the source path, the drain path, and the SBD semiconductor path are made of a metal layer and respectively contact the source, the drain, and the SBD semiconductor on the substrate.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The SBD includes an N-type SBD, and the SBD semiconductor includes an N-type semiconductor material; The MOS transistor includes a P-type MOS (PMOS) transistor; and The SBD and the MOS transistor are located in a P-well and an N-well adjacent to the P-well.

6. The semiconductor device according to claim 5, wherein: The portion of the gate includes a polysiliconized gate layer, a P-type polysilicon portion, and an N-type polysilicon portion; The polysiliconized gate layer and the P-type polysilicon portion together form the gate of the PMOS transistor; and The polysiliconized gate layer extends onto the N-type polysilicon portion and contacts the SBD semiconductor via the N-type polysilicon portion.

7. The semiconductor device according to claim 6, wherein: The polysiliconized gate layer extends along a first direction perpendicular to a second direction, and the P-type polysilicon portion is disposed adjacent to the N-type polysilicon portion along the first direction; And The source, the gate, and the drain of the MOS transistor are arranged along the second direction, and both the first direction and the second direction are parallel to the surface of the substrate.

8. The semiconductor device according to claim 5, further comprising: An N-type MOS (NMOS) transistor formed in the P-well on the substrate and including a second gate, a second source, and a second drain.

9. The semiconductor device according to claim 8, wherein the portion of the gate of the MOS transistor extends from the SBD to the NMOS transistor and merges with the corresponding portion of the second gate.

10. The semiconductor device according to any one of claims 1 to 9, the SBD includes a first SBD, the semiconductor device further comprising: A second SBD that bonds a second SBD semiconductor and a second blocking metal on the substrate, wherein the first SBD and the second SBD are of the same type and are formed in the same well; Wherein the portion of the gate of the MOS transistor extends from the first SBD to the second SBD and contacts the second SBD semiconductor.

11. The semiconductor device according to any one of claims 1 to 10, wherein: The SBD includes a P-type SBD, and the SBD semiconductor includes a P-type semiconductor material; The MOS transistor includes an N-type MOS (NMOS) transistor; and The SBD and the MOS transistor are located in an N-well and a P-well adjacent to the N-well.

12. The semiconductor device according to claim 11, wherein: The portion of the gate includes a polysiliconized gate layer, a P-type polysilicon portion, and an N-type polysilicon portion; The polysiliconized gate layer and the N-type polysilicon portion together form the gate of the NMOS transistor; and The polysiliconized gate layer extends over the P-type polysilicon portion and contacts the SBD semiconductor via the P-type polysilicon portion.

13. The semiconductor device according to claim 12, wherein: The polysiliconized gate layer extends along a first direction perpendicular to the second direction, and the P-type polysilicon portion is disposed adjacent to the N-type polysilicon portion along the first direction; And The source, gate, and drain of the MOS transistor are arranged along the second direction, and both the first direction and the second direction are parallel to the surface of the substrate.

14. The semiconductor device according to claim 11, further comprising: A P-type MOS (PMOS) transistor is formed in the N-well on the substrate and includes a second gate, a second source, and a second drain.

15. In the semiconductor device according to claim 14, the portion of the gate of the MOS transistor extends from the SBD to the PMOS transistor and merges with the corresponding portion of the second gate.

16. The semiconductor device according to any one of claims 1 to 15, wherein: The SBD includes a P-type SBD, and the SBD semiconductor includes a P-type semiconductor material; The MOS transistor includes a P-type MOS (PMOS) transistor; The P-type SBD and the PMOS transistor are located in the same N-well; The portion of the gate includes a polysiliconized gate layer and a P-type polysilicon portion; The polysiliconized gate layer and the P-type polysilicon portion together form the gate of the PMOS transistor; and The polysiliconized gate layer and the P-type polysilicon portion extend over the SBD and contact the SBD semiconductor via the P-type polysilicon portion.

17. The semiconductor device according to any one of claims 1 to 16, wherein: The SBD includes an N-type SBD, and the SBD semiconductor includes an N-type semiconductor material; The MOS transistor includes an N-type MOS (NMOS) transistor; The N-type SBD and the NMOS transistor are located in the same P-well; The portion of the gate includes a polysiliconized gate layer and an N-type polysilicon portion; The polysiliconized gate layer and the N-type polysilicon portion together form the gate of the NMOS transistor; and The polysiliconized gate layer and the N-type polysilicon portion extend over the SBD and contact the SBD semiconductor via the N-type polysilicon portion.

18. The semiconductor device according to any one of claims 1 to 17, wherein: The portion of the gate of the MOS transistor extends from the MOS transistor to the SBD along a first direction perpendicular to the second direction; And The source, gate, and drain of the MOS transistor are arranged along the second direction, and both the first direction and the second direction are parallel to the surface of the substrate.

19. The semiconductor device according to any one of claims 1 to 18, further comprising: A field oxide region or a shallow trench isolation (STI) structure, wherein the field oxide region or the STI structure is disposed between the SBD and the MOS transistor and is configured to isolate the SBD and the MOS transistor.

20. The semiconductor device according to any one of claims 1 to 19, wherein the SBD and the MOS transistor belong to an X-input NAND logic gate, where X is a positive integer greater than 1.

21. A method of forming an integrated planar semiconductor device, comprising: Form a Schottky barrier diode (SBD) on the substrate, and the SBD bonds the SBD semiconductor and the blocking metal; Form the source and drain of a metal oxide semiconductor (MOS) transistor on the substrate; And Form the gate of the MOS transistor, and a portion of the gate of the MOS transistor extends from the MOS transistor to the SBD and contacts the blocking metal.

22. The method according to claim 21, wherein: The drain of the MOS transistor includes an extended drain structure; The SBD semiconductor includes a first semiconductor portion and a second semiconductor portion; The doping profile of the extended drain structure is substantially the same as the doping profile of the second semiconductor portion; and and The doping concentration of the channel region of the MOS transistor is substantially the same as the doping concentration of the first semiconductor portion.

23. The method according to claim 22, wherein each of the extended drain structure of the MOS transistor and the first and second semiconductor portions of the SBD semiconductor has a different silicide contact surface.

24. The method according to any one of claims 21 to 23, further comprising: Source vias, drain vias, and SBD semiconductor vias are formed of a metal layer, wherein the source vias, the drain vias, and the SBD semiconductor vias are in contact with the source, the drain, and the SBD semiconductor on the substrate, respectively.

25. The method according to any one of claims 21 to 24, wherein: The SBD includes an N-type SBD, and the SBD semiconductor includes an N-type semiconductor material; The MOS transistor includes a P-type MOS (PMOS) transistor; and The SBD and the MOS transistor are located in a P-well and an N-well adjacent to the P-well.

26. The method according to claim 25, wherein: The portion of the gate includes a silicided gate layer, a P-type polysilicon portion, and an N-type polysilicon portion; The silicided gate layer and the P-type polysilicon portion together form the gate of the PMOS transistor; and The silicided gate layer extends over the N-type polysilicon portion and contacts the barrier metal via the N-type polysilicon portion.

27. The method according to claim 26, wherein: The silicided gate layer extends along a first direction perpendicular to a second direction, and the P-type polysilicon portion is disposed adjacent to the N-type polysilicon portion along the first direction; and The source, the gate, and the drain of the MOS transistor are arranged along the second direction, and both the first direction and the second direction are parallel to the surface of the substrate.

28. The method according to claim 25, further comprising: An N-type MOS (NMOS) transistor is formed in the P-well on the substrate, and the NMOS transistor includes a second gate, a second source, and a second drain.

29. The method according to claim 28, further comprising: The portion of the gate of the MOS transistor is extended from the SBD to the NMOS transistor to merge with a corresponding portion of the second gate.

30. The method according to any one of claims 21 to 29, wherein the SBD comprises a first SBD, and the method further comprises: A second SBD is formed on the substrate, and the second SBD joins a second SBD semiconductor and a second barrier metal. The first SBD and the second SBD are of the same type and are formed in the same well; and The portion of the gate of the MOS transistor is extended from the first SBD to the second SBD to contact the second barrier metal.

31. The method according to any one of claims 21 to 30, wherein: The SBD includes a P-type SBD, and the SBD semiconductor includes a P-type semiconductor material; The MOS transistor includes an N-type MOS (NMOS) transistor; and The SBD and the MOS transistor are located in an N-well and a P-well adjacent to the N-well.

32. The method according to claim 31, wherein: The portion of the gate includes a silicided gate layer, a P-type polysilicon portion, and an N-type polysilicon portion; The silicided gate layer and the N-type polysilicon portion together form the gate of the NMOS transistor; and The silicided gate layer extends over the P-type polysilicon portion and contacts the barrier metal via the P-type polysilicon portion.

33. The method according to claim 32, wherein: The polysiliconized gate layer extends along a first direction perpendicular to the second direction, and the P-type polysilicon portion is disposed adjacent to the N-type polysilicon portion along the first direction; And The source, the gate, and the drain of the MOS transistor are arranged along the second direction, and both the first direction and the second direction are parallel to the surface of the substrate.

34. The method according to claim 31, further comprising: A P-type MOS (PMOS) transistor is formed on the substrate, the PMOS transistor is formed in the N-well, and the PMOS transistor includes a second gate, a second source, and a second drain.

35. The method according to claim 34, further comprising: The portion of the gate of the MOS transistor extends from the SBD to the PMOS transistor to merge with a corresponding portion of the second gate.

36. The method according to any one of claims 21 to 35, wherein: The SBD includes a P-type SBD, and the SBD semiconductor includes a P-type semiconductor material; The MOS transistor includes a P-type MOS (PMOS) transistor; The P-type SBD and the PMOS transistor are located in the same N-well; The portion of the gate includes a polysiliconized gate layer and a P-type polysilicon portion; The polysiliconized gate layer and the P-type polysilicon portion together form the gate of the PMOS transistor; and The polysiliconized gate layer and the P-type polysilicon portion extend onto the SBD and contact the barrier metal via the P-type polysilicon portion.

37. The method according to any one of claims 21 to 36, wherein: The SBD includes an N-type SBD, and the SBD semiconductor includes an N-type semiconductor material; The MOS transistor includes an N-type MOS (NMOS) transistor; The N-type SBD and the NMOS transistor are located in the same P-well; The portion of the gate includes a polysiliconized gate layer and an N-type polysilicon portion; The polysiliconized gate layer and the N-type polysilicon portion together form the gate of the NMOS transistor; and The polysiliconized gate layer and the N-type polysilicon portion extend onto the SBD and contact the barrier metal via the N-type polysilicon portion.

38. The method according to any one of claims 21 to 37, wherein: The portion of the gate of the MOS transistor extends from the MOS transistor to the SBD along a first direction perpendicular to the second direction; and The source, the gate, and the drain of the MOS transistor are arranged along the second direction, and both the first direction and the second direction are parallel to the surface of the substrate.

39. The method according to any one of claims 21 to 38, further comprising: A field oxide region or a shallow trench isolation (STI) structure is formed, wherein the field oxide region or the STI structure is disposed between the SBD and the MOS transistor and is configured to isolate the SBD and the MOS transistor.

40. The method according to any one of claims 21 to 39, wherein the SBD and the MOS transistor belong to an X-input NAND logic gate, where X is a positive integer greater than 1.

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