Welding spot anomaly detection method, device and system, medium and equipment

Abstract

The invention discloses a welding spot anomaly detection method, device and system, a medium and equipment. The method comprises the steps that a high level and a low level are applied to a plurality of first chip pins and a plurality of second chip pins of a chip to be tested respectively, and the first chip pins and the second chip pins are distributed in a pairwise alternating mode; performing level detection on a first pin welding spot of each first chip pin and a second pin welding spot of each second chip pin of the chip to be detected so as to determine level values of each first pin welding spot and each second pin welding spot; in response to the fact that the level value of the first pin welding spot is different from the level value of the first chip pin, alarm information marking that the first pin welding spot is abnormal is output; and in response to the fact that the level value of the second pin welding spot is different from the level value of the second chip pin, outputting alarm information indicating that the second pin welding spot is abnormal. Through the method, the abnormal condition of the welding spot can be rapidly, accurately and comprehensively detected, and the production efficiency and quality of a production line are effectively improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular, to a method, device, system, medium and equipment for detecting solder joint abnormalities. Background Art

[0002] With the rapid development of integrated circuit technology, the trend of chip modularization, which integrates multiple complex chips in a product package, has become increasingly prominent. This modular design not only improves the integration of products but also greatly reduces the volume of products. However, with the miniaturization of module packaging, the requirements for the selected internal chips are becoming increasingly strict. Especially for chips with BGA (Ball Grid Array) packaging, which have a large number of pins and a small pitch between pin solder joints, it poses a great challenge to the welding of chips within the module.

[0003] At the same time, during the production of module products, welding abnormalities such as solder ball bridging, pillow effect, non-wetting open circuit, and voids often occur in chip pins. These problems are somewhat random, and there is currently no more comprehensive batch detection and processing method for these welding problems. Therefore, it is difficult to completely avoid them through simple sampling detection and feature recognition. Once these module products with welding defects flow out to the client, it may lead to customer complaints and even product recalls, causing huge economic losses and damage to the brand reputation of the enterprise.

[0004] Currently, there are mainly three common methods for detecting solder joint abnormalities in the industry: one is to use the diode range of a traditional multimeter to test the impedance between the chip pin and the ground; the second is to use an X-Ray (X-ray) optical microscope for observation; the third is to conduct a destructive physical test through the method of "sectioning + grinding + high-power microscope observation". However, these methods all have obvious limitations. Specifically, the multimeter test method can only test the impedance of a single pin of a single module at a time, with low test efficiency and unable to meet the requirements of mass production line detection; although the X-Ray observation method can achieve non-destructive detection, its ability to identify fine defects such as solder ball cracking and voids in pin solder joints is limited, and it relies on manual visual inspection, which is prone to missing defects; although the sectioning observation method can accurately identify welding defects, as a destructive test, it cannot be used for batch detection. In addition, these three existing methods do not have the function of intelligent detection and can only be used as an auxiliary analysis means and cannot be truly incorporated into the production plan. Summary of the Invention

[0005] The present application mainly provides a method, device, system, medium and equipment for detecting solder joint abnormalities, aiming to solve the technical problem that the existing welding abnormality detection methods are difficult to be incorporated into the module production process.

[0006] To solve the above technical problems, the technical solution adopted in this application is: to provide a solder joint abnormality detection method. The solder joint abnormality detection method includes: applying high and low levels to a plurality of first chip pins and a plurality of second chip pins of a chip to be tested, wherein the plurality of first chip pins and the plurality of second chip pins are alternately distributed in pairs; detecting the levels of the first pin solder joints of the respective first chip pins and the second pin solder joints of the respective second chip pins of the chip to be tested to determine the level values of the respective first pin solder joints and the respective second pin solder joints; in response to the level value of the first pin solder joint being different from the level value of the first chip pin, outputting an alarm message indicating that the first pin solder joint is abnormal; and in response to the level value of the second pin solder joint being different from the level value of the second chip pin, outputting an alarm message indicating that the second pin solder joint is abnormal.

[0007] In some embodiments, the plurality of first chip pins and the plurality of second chip pins of the chip to be tested are arranged in an array, and the plurality of first chip pins and the plurality of second chip pins are alternately distributed in pairs both horizontally and vertically in the array arrangement.

[0008] In some embodiments, before applying high and low levels to a plurality of first chip pins and a plurality of second chip pins of a chip to be tested, it includes: determining a plurality of parallel diagonal lines that diagonally cover all pin chips in the array arrangement; respectively determining the chip pins corresponding to adjacent parallel diagonal lines among the plurality of parallel diagonal lines as first chip pins and second chip pins, to obtain the plurality of first chip pins and the plurality of second chip pins.

[0009] In some embodiments, the solder joint abnormality detection method further includes: reporting the alarm message to a cloud server for the cloud server to adjust the production process of the production line of the test module corresponding to the chip to be tested based on the alarm message; and / or reporting the alarm message to a host computer for the host computer to perform visual processing on the alarm message.

[0010] To solve the above technical problems, another technical solution adopted by this application is: to provide a solder joint abnormality detection device, which includes: a module to be tested, including a chip to be tested and a circuit board, chip pins of the chip to be tested are soldered to the circuit board, and pin solder joints are formed at each of the chip pins on the circuit board. The chip to be tested is configured to divide each of the chip pins into first chip pins and second chip pins that are alternately distributed in pairs, and apply a high level and a low level to each of the first chip pins and the second chip pins respectively; a detection circuit, connected to each of the pin solder joints, for performing a level detection on each of the pin solder joints to determine the level value of each of the pin solder joints; a control unit, connected to the detection circuit and the module to be tested respectively, for feeding back the level value of each of the pin solder joints to the chip to be tested; wherein, the chip to be tested is further configured to output an alarm message indicating that the first pin solder joint is abnormal in response to the level value of the first chip pin being different from the level value of the corresponding first pin solder joint; and output an alarm message indicating that the second pin solder joint is abnormal in response to the level value of the second chip pin being different from the level value of the corresponding second pin solder joint.

[0011] In some embodiments, the detection circuit includes a triode or a MOS transistor, and the triode or the MOS transistor is configured to perform a level conversion on the level value of each of the pin solder joints to obtain a status flag level; the control unit determines whether to feed back the level value of the corresponding pin solder joint to the chip to be tested based on the status flag level.

[0012] In some embodiments, the solder joint abnormality detection device further includes a first communication module, and a second communication module and / or a third communication module; wherein, the first communication module is connected between the module to be tested and the control unit for feeding back the level value of each of the pin solder joints to the chip to be tested; the second communication module is configured to connect the chip to be tested to a cloud server and report the corresponding alarm message to the cloud server; the third communication module is configured to connect the chip to be tested to a host computer and report the corresponding alarm message to the host computer.

[0013] To solve the above technical problems, another technical solution adopted by this application is: to provide an abnormal solder joint processing system, which includes: the solder joint abnormality detection device as described above, for outputting an alarm message indicating that the pin solder joint of the chip to be tested in the module to be tested is abnormal when an abnormality is detected; a cloud server, connected to the solder joint abnormality detection device, for performing production process adjustment on the production line of the module to be tested based on the alarm message; a host computer, connected to the solder joint abnormality detection device, for performing visualization processing on the alarm message.

[0014] To solve the above technical problems, another technical solution adopted in this application is: to provide a storage medium, on which program data is stored, characterized in that when the program data is executed by a processor, the steps of the solder joint anomaly detection method as described above are implemented.

[0015] To solve the above technical problems, another technical solution adopted in this application is: to provide a computer device, which includes a processor and a memory connected to each other, the memory stores a computer program, and when the processor executes the computer program, the steps of the solder joint anomaly detection method as described above are implemented.

[0016] The beneficial effects of this application are as follows: Different from the prior art, this application discloses a solder joint anomaly detection method, device, system, medium and device. By applying high and low levels to multiple first chip pins and multiple second chip pins of the chip to be tested respectively and detecting the levels of each pin solder joint, this application realizes comprehensive, efficient and accurate detection of solder joint anomalies, can automatically complete the detection, alarm and subsequent processing of solder joint anomalies without manual participation, greatly improves the detection efficiency and accuracy, can be effectively put into production line production, meets the requirements of batch detection in the production line, accurately identifies the abnormal state of the pin solder joint for corresponding alarm, reporting and subsequent processing, avoids the quality problems of module products caused by welding defects, effectively reduces the risks of customer complaints and product recalls, and thus protects the economic interests and brand reputation of the enterprise. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings, where:

[0018] Figure 1 is a schematic flowchart of an embodiment of the solder joint anomaly detection method provided by this application;

[0019] Figure 2 is Figure 1 a schematic diagram of an embodiment of the chip pins arranged in an array in the chip to be tested in the embodiment;

[0020] Figure 3 is Figure 2 a schematic diagram of an embodiment of determining the chip pins as the first chip pins and the second chip pins in the embodiment;

[0021] Figure 4 is a schematic structural diagram of an embodiment of the solder joint anomaly detection device provided by this application;

[0022] Figure 5 It is a schematic structural diagram of another embodiment of the solder joint abnormality detection device provided by this application;

[0023] Figure 6 It is a schematic structural diagram of an embodiment of the solder joint abnormality processing system provided by this application;

[0024] Figure 7 It is a schematic structural diagram of an embodiment of the storage medium provided by this application;

[0025] Figure 8 It is a schematic structural diagram of an embodiment of the computer device provided by this application. Specific Embodiments

[0026] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0027] The terms "first", "second", and "third" in the embodiments of this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of this application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes unlisted steps or units, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0028] Referring to "embodiment" in this context means that the specific features, structures, or characteristics described in connection with the embodiment may be included in at least one embodiment of this application. The phrase appears in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0029] This application provides a method for detecting solder joint abnormalities. Refer to Figure 1 , Figure 1It is a schematic flowchart of an embodiment of the solder joint anomaly detection method provided by this application. The solder joint anomaly detection method includes:

[0030] Step 10: Apply high level and low level to multiple first chip pins and multiple second chip pins of the chip to be tested respectively, where the multiple first chip pins and the multiple second chip pins are alternately distributed in pairs.

[0031] Step 20: Perform level detection on the first pin solder joints of each first chip pin and the second pin solder joints of each second chip pin of the chip to be tested, so as to determine the level values of each first pin solder joint and each second pin solder joint.

[0032] Step 30: In response to the level value of the first pin solder joint being different from the level value of the first chip pin, output an alarm message indicating that the first pin solder joint is abnormal.

[0033] Step 40: In response to the level value of the second pin solder joint being different from the level value of the second chip pin, output an alarm message indicating that the second pin solder joint is abnormal.

[0034] In this embodiment, the chip to be tested is a chip for solder joint anomaly detection, and the chip to be tested can be chips of different chip types under different packaging processes. Among them, in the packaging process, due to its miniaturization and high integration characteristics, the chip with BGA packaging is the current mainstream chip packaging trend. And due to its large number of pins and small pitch of pin solder joints, it also increases the difficulty of corresponding solder joint detection, resulting in problems of low detection efficiency and insufficient detection quality. Therefore, the solution adopted in this scheme is mainly aimed at the chip with rectangular array distribution of chip pins under BGA packaging, so as to improve the efficiency and accuracy of solder joint anomaly detection for this type of chip. The chip to be tested can specifically be chip types such as communication chips, processor chips, or memory chips, etc. This application does not make specific limitations on this, as long as its pins adopt the BGA packaging method.

[0035] In this embodiment, the chip to be tested has multiple chip pins, and these chip pins are divided into first chip pins and second chip pins that are alternately distributed in pairs. The first chip pins and the second chip pins are alternately distributed in pairs and are applied with voltages of different levels. Among them, the specific way of alternating in pairs can be in a single dimension. For example, for the chip pins in a single dimension, high, low, high, low, high... alternating levels are applied respectively. The way of alternating in pairs can also be multi-dimensional alternating distribution. Refer to Figure 2 , in Figure 2In the example, multiple first chip pins and multiple second chip pins of the chip under test are arranged in an array. The multiple first chip pins and the multiple second chip pins are alternately distributed in pairs both horizontally and vertically in the array distribution. Specifically, the black circular areas such as a, b, c, d, and the white circular areas such as x are the first chip pins and the second chip pins respectively, and high and low levels are applied to them respectively. Each first chip pin has second chip pins as its adjacent chip pins both horizontally and vertically. Similarly, each second chip pin has first chip pins as its adjacent chip pins both horizontally and vertically. In addition, this alternating distribution can also be more dimensional, such as a three-dimensional array or other complex array distribution forms, as long as the first chip pins and the second chip pins can be alternately distributed in pairs. This way of alternating distribution makes the electrical level of each pin solder joint different from that of its adjacent pin solder joints, facilitating subsequent electrical level detection and judgment of solder joint abnormalities.

[0036] In this embodiment, the pin solder joint is a contact point for electrically connecting and fixing the chip pin to the circuit board, and is usually formed by soldering methods such as soldering, plugging, hot pressing, or surface mounting to solder the chip pin to the corresponding pad on the circuit board. Specifically, the first chip pin corresponds to the first pin solder joint, and the second chip pin corresponds to the second pin solder joint. The pin solder joints may face various soldering defects, such as poor soldering, cold solder joints, open circuits, or short circuits. These defects may cause the electrical connection between the pin solder joint and the chip pin to be unstable or ineffective, affecting the normal operation of the chip. Therefore, it is necessary to first perform electrical level detection on the first pin solder joints of each first chip pin and the second pin solder joints of each second chip pin of the chip under test to determine the electrical level values of each first pin solder joint and each second pin solder joint.

[0037] In this embodiment, after determining the electrical level values of each first pin solder joint and each second pin solder joint, these electrical level values can be compared with the electrical level values of the corresponding first chip pins and second chip pins. If the electrical level value of the first pin solder joint is inconsistent with the electrical level value of the first chip pin, it indicates that the first pin solder joint may be abnormal. At this time, an alarm message will be output to mark the abnormality of the first pin solder joint. Similarly, if the electrical level value of the second pin solder joint is inconsistent with the electrical level value of the second chip pin, it also indicates that the second pin solder joint may be abnormal, and an alarm message will also be output to mark the abnormality of the second pin solder joint. Such a comparison and alarm mechanism can achieve a quick response and accurate identification of solder joint abnormalities, providing strong support for subsequent processing.

[0038] In this embodiment, the abnormalities of the pin soldering joints include short - circuit abnormalities and open - circuit abnormalities. Among them, a short - circuit abnormality refers to an unexpected electrical connection formed between a pin soldering joint and an adjacent pin soldering joint or a circuit part that should not be connected, resulting in the current being able to flow directly without passing through the expected path. This kind of abnormality usually causes the electrical performance of the chip to decline and may even cause damage to the chip. The occurrence of a short - circuit abnormality may be due to excessive solder, too high soldering temperature, or too long soldering time during the soldering process, which causes the solder to flow, resulting in a connection formed between pin soldering joints that should originally be isolated. An open - circuit abnormality refers to an unstable or completely ineffective electrical connection between a pin soldering joint and a chip pin or a circuit board, resulting in the current being unable to flow normally. This kind of abnormality usually causes the chip to fail to work properly or only work partially. The occurrence of an open - circuit abnormality may be due to poor soldering, mechanical damage to the pin soldering joint, poor contact between the pin soldering joint and the pad, etc., resulting in problems such as pillow effect and non - wetting open - circuit.

[0039] This embodiment can effectively distinguish between short - circuit abnormalities and open - circuit abnormalities. Specifically, when a short - circuit abnormality occurs, the original level difference that should be maintained between a first chip pin and its corresponding first pin soldering joint, or between a second chip pin and its corresponding second pin soldering joint, will disappear. For example, when there is solder bridging, it will cause an electrical connection to be formed between two adjacent pin soldering joints, so that the level values of these two originally staggered pin soldering joints are the same. When an open - circuit abnormality occurs, normal level transmission cannot be carried out between a first chip pin and its corresponding first pin soldering joint, or between a second chip pin and its corresponding second pin soldering joint, resulting in the level value of the pin soldering joint being inconsistent with the level value of the corresponding chip pin. By detecting and comparing the level values of each pin soldering joint with the level values of the chip pins, the solder - joint abnormality detection method of this application can accurately identify these two common types of solder - joint abnormalities, namely short - circuit and open - circuit. By distinguishing between short - circuit abnormalities and open - circuit abnormalities, corresponding treatment measures can be taken for different types of abnormalities in the follow - up. For example, for a short - circuit abnormality, measures such as re - soldering or isolating the abnormal solder joint may be required; for an open - circuit abnormality, measures such as strengthening the soldering connection or replacing the pin soldering joint may be required. Such an abnormality - distinguishing and treatment mechanism can further improve the accuracy and efficiency of solder - joint abnormality detection, providing more comprehensive and reliable support for the chip production and testing processes.

[0040] Optionally, before applying high levels and low levels to multiple first chip pins and multiple second chip pins of the chip to be tested, it further includes: determining multiple parallel oblique lines that diagonally cover all the pins of the chip in the array distribution; respectively determining the chip pins corresponding to adjacent parallel oblique lines in the multiple parallel oblique lines as the first chip pins and the second chip pins, obtaining multiple first chip pins and multiple second chip pins.

[0041] In this alternative embodiment, a method for distinguishing between the first chip pins and the second chip pins is specified. Here, the diagonal direction is defined with respect to the horizontal and vertical directions of the array distribution of the pins to be measured on the chip. That is, the diagonal line does not extend along the horizontal or vertical direction, but spans multiple rows and columns. In this way, it can be ensured that when high and low levels are applied, the distribution of the first chip pins and the second chip pins in the array is more uniform, thereby improving the accuracy and comprehensiveness of level detection. After determining multiple parallel diagonal lines, the chip pins corresponding to adjacent parallel diagonal lines are respectively determined as the first chip pins and the second chip pins. In this way, the chip pins on the same diagonal line will be given the same level, while the chip pins on adjacent diagonal lines will be given opposite levels, so that the first chip pins and the second chip pins are alternately distributed in pairs in the horizontal and vertical directions.

[0042] This alternative embodiment can be specifically referred to Figure 7 , when determining the first chip pins and the second chip pins by means of diagonal lines, specifically, the chip pins are divided into two groups, such as S1 and S2 in the illustration. In order to ensure comprehensive coverage of the detection of the corresponding pins and avoid the problems of missed detection and repeated detection of chip pins, this application can Figure 7 group the chip pins during the testing process by the S-shaped selection method shown in Figure 7 . S1 and S2 respectively represent the groups determined as the first chip pins and the second chip pins. In the Figure 7 example, the diagonal line starts from the upper right of the chip, extends to the lower left, covering a part of the chip pin array, and then turns at a parallel diagonal line at intervals below and extends to the upper right, covering another part of the chip pin array, and so on, forming multiple parallel diagonal lines. The chip pins on each diagonal line are divided into the same group, while the chip pins on adjacent diagonal lines are divided into another group, and the S-shaped connection method connects the first chip pins and the second chip pins in series respectively, making it easier to intuitively and quickly detect missed or repeated detections. In this way, through the method of grouping by diagonal lines, it can be ensured that the first chip pins and the second chip pins are evenly distributed in the chip pin array, while avoiding the problems of missed detection and repeated detection. Moreover, this S-shaped selection method can also form a standard to ensure that the path of each solder joint detection is the same, facilitating quick reproduction and positioning of chip abnormalities, improving the consistency and accuracy of detection, reducing detection deviations caused by irregular pin layouts, and further enhancing the accuracy and reliability of detection.

[0043] Optionally, the solder joint abnormality detection method further includes: reporting the alarm information to the cloud server for the cloud server to adjust the production process of the production line of the test module corresponding to the chip to be tested based on the alarm information; and / or reporting the alarm information to the host computer for the host computer to perform visual processing on the alarm information.

[0044] In this alternative embodiment, the alarm information can be reported to the cloud server. Herein, the cloud server refers to a computing service that stores data on a remote server via the Internet. The cloud server can analyze and process the received alarm information to identify possible problems that may exist in the DUT module corresponding to the DUT chip during the production process. For example, the cloud server can determine whether a failure has occurred in a certain production link or whether the process parameters of the entire production line need to be adjusted based on the type and frequency of the alarm information. Based on these analysis results, the cloud server can automatically adjust the production process or send adjustment suggestions to the staff on the production line to improve production efficiency and product quality.

[0045] In this embodiment, the alarm information can also be reported to the host computer. Herein, the host computer refers to a computer that can directly issue control commands and is usually located in the control room or testing center of the production line. After receiving the alarm information, the host computer can perform visual processing on it, such as intuitively displaying information such as the location, type, and severity of the solder joint abnormality through charts, animations, or sounds. In this way, the staff on the production line can quickly understand the situation of the solder joint abnormality and take corresponding handling measures, such as stopping the production line, checking the equipment, or retesting the chip, etc., to ensure the quality of the product and the smooth progress of production.

[0046] Through the above two ways of reporting alarm information, this alternative embodiment can further enhance the practicability and flexibility of the solder joint abnormality detection method. In practical applications, according to different requirements and scenarios, it is possible to choose to report the alarm information to the cloud server for remote analysis and processing, or report it to the host computer for local visualization and quick response. These two methods complement each other and jointly constitute a complete solder joint abnormality detection and processing system, enabling the solder joint abnormality detection method of this embodiment to better adapt to the needs of different users and actual application scenarios, not only improving the accuracy and efficiency of solder joint abnormality detection, but also providing more comprehensive and reliable support for the production and testing process of the chip.

[0047] Refer to Figure 4 , Figure 4 which is a schematic structural diagram of an embodiment of the solder joint abnormality detection device provided by this application.

[0048] The solder joint abnormality detection device 50 includes: a module under test 51, including a chip under test and a circuit board. The chip pins of the chip under test are soldered to the circuit board, and pin solder joints are formed at each chip pin of the circuit board. The chip under test is configured to divide the chip pins into first chip pins and second chip pins that are alternately distributed in pairs, and apply high and low levels to each first chip pin and second chip pin respectively; a detection circuit 52, connected to each pin solder joint, for performing level detection on each pin solder joint to determine the level value of each pin solder joint; a control unit 53, connected to the detection circuit 52 and the module under test 51 respectively, for feeding back the level value of each pin solder joint to the chip under test; wherein, the chip under test is further configured to output an alarm message indicating the abnormality of the first pin solder joint in response to the level value of the first chip pin being different from the level value of the corresponding first pin solder joint; and output an alarm message indicating the abnormality of the second pin solder joint in response to the level value of the second chip pin being different from the level value of the corresponding second pin solder joint.

[0049] In this embodiment, the module under test 51 is a chip modularized product and is also the object to be detected for solder joint abnormalities in this embodiment. It includes a chip under test and a circuit board, and the chip under test is electrically connected to the circuit board by soldering. The chip pins of the chip under test are divided into first chip pins and second chip pins that are alternately distributed in pairs, and high and low levels are respectively applied to the first chip pins and the second chip pins. For the specific details, reference can be made to the introduction of the aforementioned solder joint abnormality detection method, which will not be elaborated here.

[0050] In this embodiment, the detection circuit 52 is a component for performing level detection on each pin solder joint. It is connected to each pin solder joint in the module under test 51 through an electrical connection method, and can obtain the level status of each pin solder joint in real time and accurately, thereby ensuring the accuracy of solder joint abnormality detection. The detection circuit can be established in various ways. For example, it can be implemented by a dedicated level detection chip or integrated circuit. These chips or circuits have the characteristics of high precision and low noise, and can accurately measure the level value of each pin solder joint. In addition, the detection circuit 52 can also include circuit elements such as analog switches and buffers to realize the acquisition, transmission, and processing of level signals, ensuring the stability and reliability of the detection results.

[0051] Optionally, in one embodiment, the detection circuit 52 includes a triode or a MOS transistor, and the triode or MOS transistor is used to perform level conversion on the level value of each pin solder joint to obtain a status flag level; the control unit determines whether to feed back the level value of the corresponding pin solder joint to the chip under test based on the status flag level.

[0052] In this alternative embodiment, a bipolar junction transistor (BJT) and a metal-oxide-semiconductor field-effect transistor (MOSFET) have the functions of level conversion and amplification in the detection circuit 52. In this embodiment, the BJT or MOSFET is used as a level conversion element, which can convert the level values of each pin solder joint to obtain a status flag level. The status flag level is a signal used to represent the level status of the pin solder joint. It can be a high level or a low level, depending on the actual level value of the pin solder joint and the characteristics of the BJT or MOSFET. Based on this status flag level, the control unit can determine whether it is necessary to feedback the level value of the corresponding pin solder joint to the chip under test. If the status flag level indicates an abnormality in the pin solder joint, the control unit will feedback the level value of this pin solder joint and the abnormality information to the chip under test, and the chip under test will further process it and output an alarm message. Such a level conversion mechanism not only simplifies the level detection process and improves the detection efficiency, but also ensures the accuracy and stability of the level signal, providing strong support for subsequent abnormality judgment and processing.

[0053] In this embodiment, the control unit 53 is responsible for coordinating and managing the entire detection process. It is connected to the detection circuit 52 and the module under test 51 through electrical connection, and can receive the level values of each pin solder joint transmitted by the detection circuit 52 in real time, and send control instructions to the module under test 51. The control unit 53 can be implemented based on a microcontroller unit (MCU), which has powerful data processing and logical judgment capabilities, and can quickly and accurately judge the level status of each pin solder joint and make corresponding processing decisions.

[0054] In this embodiment, after receiving the level values of the pin solder joints feedback by the microcontroller, the chip under test of the module under test 51 will further analyze these level values and compare them with the expected level values. If it is detected that the level value of a certain pin solder joint does not match the expectation, that is, this pin solder joint is abnormal, the chip under test will immediately generate a corresponding alarm message. The alarm message contains key information such as the specific location of the abnormal pin solder joint, the type of abnormality (such as short circuit or open circuit), and the degree of abnormality. For details, please refer to the introduction of the solder joint abnormality detection method mentioned above, which will not be elaborated here.

[0055] Optionally, refer to Figure 5, in one embodiment, the solder joint anomaly detection device 50 further includes a first communication module 541, and a second communication module 542 and / or a third communication module 543; wherein, the first communication module 541 is connected between the module under test 51 and the control unit 53, and is configured to feed back the level values of the pin solder joints to the chip under test; the second communication module 542 is configured to connect the chip under test to a cloud server and report the corresponding alarm information to the cloud server; the third communication module 543 is configured to connect the chip under test to a host computer and report the corresponding alarm information to the host computer.

[0056] In this alternative embodiment, through the setting of these multiple communication modules, the solder joint anomaly detection device 50 can implement multiple ways of reporting alarm information. Among them, the first communication module 541 serves as an internal communication module, responsible for transmitting the level values of the pin solder joints between the module under test 51 and the control unit 53 to ensure the real-time and accuracy of the detection data. This module can adopt a high-speed and low-latency communication protocol to ensure the efficient transmission and processing of data; the second communication module 542 is responsible for reporting the alarm information to the cloud server. Through this module, the solder joint anomaly detection device 50 can establish a stable communication connection with the remote cloud server and upload the detected solder joint anomaly information in real time. After receiving these information, the cloud server can use its powerful data processing and analysis capabilities to deeply mine and process the alarm information, thereby providing strong support for the process adjustment and optimization of the production line; the third communication module 543 is used to report the alarm information to the host computer. Through this module, the solder joint anomaly detection device 50 can achieve seamless docking with the host computer on the production line and display the alarm information to the staff on the production line in an intuitive and easy-to-understand manner. In this way, the staff can quickly understand the situation of the solder joint anomaly and take corresponding treatment measures to ensure the smooth progress of production and the quality of products.

[0057] In this embodiment, the first communication module 541 may specifically be implemented using different communication protocols such as Universal Asynchronous Receiver / Transmitter (UART), Inter-Integrated Circuit (I2C), or Serial Peripheral Interface (SPI), etc. These communication protocols are adapted to the communication interface types in the module under test, so as to effectively feedback the test results detected by the processor to each module under test. The second communication module 542 may specifically include a radio frequency unit and an antenna. Among them, part of the radio frequency unit is a radio frequency antenna matching circuit, which provides a path for the radio frequency to stably transmit data up and down. The antenna is used to connect to a radio frequency instrument and provide a physical interface for the radio frequency to transmit and receive data up and down. The radio frequency unit can convert the alarm information output by the chip under test into an electromagnetic wave signal and transmit it through the antenna, thereby establishing a communication connection with the cloud server. The third communication module usually uses wired communication methods such as USB (Universal Serial Bus), Ethernet interface, or RS-232 interface to transmit the alarm information to the host computer at the product detection station in the form of digital signals. These communication interfaces have characteristics such as fast transmission speed, high stability, and strong anti-interference ability, which can ensure the accurate and timely transmission of alarm information and provide a strong guarantee for the rapid response and fault handling of the production line. At the same time, the solder joint abnormality detection device 50 can also flexibly select a suitable communication module and communication method according to the actual application scenario and requirements to meet the customized needs of different users.

[0058] In this embodiment, by integrating multiple communication modules, the solder joint abnormality detection device 50 not only improves the flexibility and diversity of alarm information reporting, but also provides more possibilities for subsequent detection data processing and analysis. For example, the alarm information can be correlated and analyzed with other data on the production line to further explore potential problems in the production process and provide strong data support for continuous improvement and optimization. At the same time, the device also supports multiple communication protocols and interfaces, and can be easily integrated and interconnected with other detection devices and systems to achieve more comprehensive and efficient solder joint abnormality detection and processing. For the specific details, reference can be made to the introduction of the aforementioned solder joint abnormality detection method, which will not be elaborated here.

[0059] Optionally, in some embodiments, the multiple first chip pins and multiple second chip pins of the chip under test are arranged in an array, and the multiple first chip pins and multiple second chip pins are alternately distributed in pairs both horizontally and vertically in the array distribution.

[0060] Optionally, in some embodiments, the module 51 to be measured is further specifically configured to: determine multiple parallel oblique lines that obliquely cover all the pin chips in the array distribution; and respectively determine the chip pins corresponding to adjacent parallel oblique lines among the multiple parallel oblique lines as the first chip pins and the second chip pins, so as to obtain multiple first chip pins and multiple second chip pins.

[0061] Since the embodiments of the device part correspond to the embodiments of the above method, for the introduction of the solder joint anomaly detection device provided in the embodiments of the present invention, please refer to the above method embodiments, and the embodiments of the present invention will not be elaborated herein again, and it has the same beneficial effects as the above solder joint anomaly detection method.

[0062] Refer to Figure 6 , Figure 6 which is a schematic structural diagram of an embodiment of the solder joint anomaly processing system provided in the present application.

[0063] The solder joint anomaly processing system 60 includes: the solder joint anomaly detection device 50 as described above, which is configured to output an alarm message indicating the anomaly of the pin solder joint when detecting an anomaly in the pin solder joint of the chip to be measured in the module to be measured; a cloud server 61, connected to the solder joint anomaly detection device, which is configured to adjust the production process of the production line of the module to be measured based on the alarm message; and a host computer 62, connected to the solder joint anomaly detection device, which is configured to perform visualization processing on the alarm message.

[0064] In this embodiment, by connecting the solder joint anomaly detection device 50 to the cloud server 61, the cloud server 61 can receive the alarm message reported by the solder joint anomaly detection device and perform in-depth analysis and processing on it. The cloud server 61 has powerful data processing and storage capabilities, and can classify, count, and analyze the alarm message, so as to discover possible systematic problems or trend changes in the production line. The cloud server 61 can be a specific production line module welding management platform, which provides scientific basis and suggestions for the process adjustment and optimization of the production line by analyzing and statistically analyzing the long-term batch welding conditions of the modules to be measured in the solder joint anomaly detection device in real time, so as to dynamically adjust the production line processes such as the furnace temperature curve and the nitrogen-assisted process, avoid batch failures, improve the production line production first-pass rate, and improve production efficiency and production quality.

[0065] In this embodiment, by connecting the solder joint anomaly device 50 to the host computer 52, the host computer 62 can receive the alarm information reported by the solder joint anomaly detection device 50 in real time and perform visual processing on it. The host computer 62 is usually equipped with professional visualization software or interfaces, which can intuitively display the alarm information to users in various forms such as charts, animations, and color changes, helping users quickly understand the solder joint anomaly situation. At the same time, the host computer 62 can also store and manage the alarm information to form historical alarm records, facilitating users to trace and analyze the solder joint anomaly situation. Such a design not only improves the readability and comprehensibility of the alarm information but also provides strong support for fault troubleshooting and continuous improvement of the production line.

[0066] In this embodiment, the solder joint anomaly processing system 60 constructs a complete and efficient solder joint anomaly detection and processing process by integrating the solder joint anomaly detection device 50, the cloud server 61, and the host computer 62. This process not only realizes the real-time detection and alarm of solder joint anomalies but also provides scientific basis and suggestions for process adjustment and optimization of the production line through the data processing and visualization functions of the cloud server and the host computer. Such a system not only improves the accuracy and efficiency of solder joint anomaly detection but also provides more comprehensive and reliable support for the chip production and testing processes, helping to improve the overall production efficiency and product quality of the production line. In addition, the solder joint anomaly processing system 60 also has good scalability and flexibility. For example, more detection devices, communication modules, or data processing units can be added according to actual needs to further improve the detection ability and data processing efficiency of the system. At the same time, the system can also be integrated and interconnected with other production management systems or devices to achieve more comprehensive and intelligent production line management and control. Such a design enables the solder joint anomaly processing system 60 to better adapt to the needs of different users and actual application scenarios and provides more comprehensive and efficient support for the chip production and testing processes.

[0067] Since the embodiments of the system part include the device embodiments as described above and adopt some of the method embodiments as described above, the introduction of the solder joint anomaly processing system provided by the embodiments of the present invention can refer to the above method embodiments and device embodiments, and the embodiments of the present invention will not be elaborated herein. It has the same beneficial effects as the above solder joint anomaly detection method and the above solder joint anomaly detection device.

[0068] Referring to the figure, Figure 7 is a schematic structural diagram of an embodiment of the storage medium provided by this application.

[0069] The storage medium 70 stores program data 71, which, when executed by a processor, implements the solder joint anomaly detection method as Figures 1 to 3 described.

[0070] The program data 71 is stored in a storage medium 70, including a number of instructions for causing a network device (such as a router, a personal computer, a server, etc.) or a processor to execute all or part of the steps of the methods in the various embodiments of the present application.

[0071] Optionally, the storage medium 70 may be a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk, or other media that can store the program data 71.

[0072] Refer to Figure 8 , Figure 8 which is a schematic structural diagram of an embodiment of the computer device provided by the present application.

[0073] The computer device 80 includes a processor 82 and a memory 81 that are interconnected. The memory 81 stores a computer program. When the processor 82 executes the computer program, it implements the solder joint anomaly detection method as Figures 1 to 3 described. Among them, the memory 81 may include the storage medium 70 or may be other separately developed memories.

[0074] Different from the prior art, the present application discloses a solder joint anomaly detection method, device, system, medium, and device. By applying high and low levels to multiple first chip pins and multiple second chip pins of a chip under test respectively and detecting the levels of the solder joints of each pin, a comprehensive, efficient, and accurate detection of solder joint anomalies is achieved. It can automatically complete the detection, warning, and subsequent processing of solder joint anomalies without manual participation, greatly improving the detection efficiency and accuracy. It can be effectively put into production line production, meeting the needs of batch detection in the production line, accurately identifying the abnormal states of pin solder joints for corresponding warning, reporting, and subsequent processing, avoiding quality problems of module products caused by welding defects, effectively reducing the risks of customer complaints and product recalls, and thus protecting the economic interests and brand reputation of the enterprise.

[0075] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the device embodiments, system embodiments, medium embodiments, and device embodiments, since they are basically similar to the method embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the partial descriptions of the method embodiments.

[0076] This application can be used in numerous general-purpose or special-purpose computing system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multi-processor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and so on.

[0077] In several embodiments provided by this application, it should be understood that the disclosed methods, devices, systems, storage media, and computer devices can be implemented in other ways. For example, the embodiments of the solder joint anomaly detection device described above are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0078] In addition, in each embodiment of this application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0079] The above are only the embodiments of this application, and do not limit the patent scope of this application accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of this application.

Claims

1. A method for detecting abnormal welding spots, characterized in that: include: Applying a high level and a low level to a plurality of first chip pins and a plurality of second chip pins of the chip to be tested, respectively, wherein the plurality of first chip pins and the plurality of second chip pins are alternately distributed in pairs; Performing level detection on the first pin solder joints of each of the first chip pins and the second pin solder joints of each of the second chip pins of the chip to be tested to determine the level values ​​of each of the first pin solder joints and each of the second pin solder joints; In response to the level value of the first pin solder joint being different from the level value of the first chip pin, outputting alarm information indicating that the first pin solder joint is abnormal; In response to the level value of the second pin solder joint being different from the level value of the second chip pin, outputting alarm information indicating that the second pin solder joint is abnormal.

2. The method for detecting abnormal welding points according to claim 1, characterized in that: The plurality of first chip pins and the plurality of second chip pins of the chip to be tested are distributed in an array, and the plurality of first chip pins and the plurality of second chip pins are distributed alternately in pairs in the transverse and longitudinal directions of the array distribution.

3. The method for detecting abnormal welding points according to claim 2, characterized in that: Before respectively applying high level and low level to the plurality of first chip pins and the plurality of second chip pins of the chip to be tested, the method comprises: Determining a plurality of parallel oblique lines that obliquely cover all the pin chips in the array distribution; The chip pins corresponding to adjacent parallel oblique lines among the plurality of parallel oblique lines are respectively determined as first chip pins and second chip pins to obtain the plurality of first chip pins and the plurality of second chip pins.

4. The method for detecting abnormal welding points according to claim 1, characterized in that: The solder joint abnormality detection method further comprises: Reporting the alarm information to a cloud server, so that the cloud server can adjust the production process of the production line of the module to be tested corresponding to the chip to be tested based on the alarm information; and / or The alarm information is reported to a host computer so that the host computer can perform visualization processing on the alarm information.

5. A welding spot abnormality detection device, characterized in that: include: A module to be tested, comprising a chip to be tested and a circuit board, wherein the chip pins of the chip to be tested are welded on the circuit board, and pin solder joints are formed at each of the chip pins on the circuit board, and the chip to be tested is used to divide each of the chip pins into first chip pins and second chip pins that are alternately distributed in pairs, and apply a high level and a low level to each of the first chip pins and the second chip pins respectively; A detection circuit connected to each of the pin solder joints, and used to perform level detection on each of the pin solder joints to determine the level value of each of the pin solder joints; A control unit, connected to the detection circuit and the module to be tested, respectively, and used to feed back the level value of each pin solder joint to the chip to be tested; Among them, the chip to be tested is also used to output an alarm message indicating that the solder joint of the first pin is abnormal in response to the level value of the first chip pin being different from the level value of the corresponding first pin solder joint; and to output an alarm message indicating that the solder joint of the second pin is abnormal in response to the level value of the second chip pin being different from the level value of the corresponding second pin solder joint.

6. The device for detecting abnormal welding points according to claim 5, characterized in that: The detection circuit includes a triode or a MOS tube, and the triode or the MOS tube is used to perform level conversion on the level value of each pin solder joint to obtain a status mark level; The control unit determines whether to feed back the level value corresponding to the pin solder joint to the chip under test based on the state flag level.

7. The device for detecting abnormal welding spots according to claim 5, characterized in that: The welding point abnormality detection device further includes a first communication module, and a second communication module and / or a third communication module; Wherein, the first communication module is connected between the module to be tested and the control unit, and is used to feed back the level value of each pin solder point to the chip to be tested; The second communication module is used to connect the chip under test to a cloud server and report the corresponding alarm information to the cloud server; The third communication module is used to connect the chip under test to a host computer and report the corresponding alarm information to the host computer.

8. A welding point abnormality processing system, characterized in that: include: The solder joint anomaly detection device according to any one of claims 5 to 7 is used to output an alarm message indicating an abnormality in a pin solder joint of a chip to be tested in a module to be tested when an abnormality is detected in the pin solder joint of the chip to be tested in the module to be tested; A cloud server connected to the solder joint anomaly detection device, and configured to adjust the production process of the production line of the module to be tested based on the alarm information; A host computer is connected to the welding point abnormality detection device and is used for visualizing the alarm information.

9. A storage medium having program data stored thereon, characterized in that: When the program data is executed by a processor, the steps of the welding spot abnormality detection method according to any one of claims 1 to 4 are implemented.

10. A computer device, characterized in that: The method comprises a processor and a memory connected to each other, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the welding spot abnormality detection method according to any one of claims 1 to 4 are implemented.

Images