A control circuit based on a deformable mirror device driver

Abstract

The present invention provides a control circuit based on a deformable mirror device driver, comprising a multi-stage power supply architecture, a drive channel module, a monitoring module, and an FPGA control module. The multi-stage power supply architecture includes an external main power supply, an FPGA power supply module, and a drive channel power supply module. The external main power supply has a 12V power output, which is used to provide power input for the FPGA power supply module and the drive channel power supply module. There are N drive channel power supply modules, respectively denoted as the first drive channel power supply module to the Nth drive channel power supply module. Each drive channel power supply module includes a voltage reference source, a buck regulator, a boost regulator, and a D / A voltage reference source. The present invention utilizes the coordinated feedback of multiple monitoring modules to ensure the quality of circuit operation, and then integrates the FPGA algorithm for dynamic compensation to reduce crosstalk between drive voltage channels, ensure the synchronization and consistency of large-scale arrays, and reduce the cumulative error of optical images.

Description

Technical Field

[0001] The present invention relates to the field of adaptive optics and precision drive control technology, and in particular to a control circuit based on a deformable mirror device driver. Background Art

[0002] Deformable mirrors, as active optical devices capable of real-time adjustment of mirror deformation, offer advantages such as fast response speed, high deformation accuracy, and multi-channel coordinated control. They are widely used in wavefront correction for astronomical telescopes, beam shaping for laser communications, and aberration compensation for biomedical imaging. However, existing deformable mirror drive circuits still suffer from slow dynamic response, insufficient multi-channel consistency, and insufficient noise suppression. Their control accuracy and system stability also fail to meet the requirements of specific scenarios. Therefore, further improving the overall performance of deformable mirror drivers remains a research priority in this field. The output data from the FPGA can dynamically adjust the voltage amplitude of the drive channel, significantly improving the response speed and control accuracy of the deformable mirror. The multi-module drive channels work in parallel to ensure synchronization across large-scale drive arrays of deformable mirrors. The individual module power supplies ensure that the voltage amplifier provides precise and stable power to each unit. Traditional analog circuits are susceptible to interference from factors like temperature and electromagnetic fields, and require a large number of components to implement even simple data integration and algorithm processing. However, using an FPGA control module to digitize the control loop allows data extracted from the drive channel via the monitoring module to be transferred to the FPGA for processing. Leveraging its parallel computing capabilities, filtering or control algorithms can be added to appropriate modules to achieve multi-channel real-time closed-loop control. External interference can also be suppressed through digital isolation and synchronous sampling techniques. Therefore, this control circuit based on the deformable mirror device driver has significant technical potential for improving deformable mirror performance and expanding its application scenarios. Summary of the Invention

[0003] Purpose of the invention: The technical problem to be solved by the present invention is to address the deficiencies of the existing technology and provide a control circuit based on a deformable mirror device driver, comprising a multi-stage power supply architecture, a drive channel module, a monitoring module, and an FPGA control module;

[0004] The multi-stage power supply architecture includes an external main power supply, an FPGA power supply module and a drive channel power supply module. The external main power supply is a 12V power supply output, which is used to provide power input for the FPGA power supply module and the drive channel power supply module;

[0005] There are N driving channel power supply modules, which are respectively recorded as the first driving channel power supply module to the Nth driving channel power supply module. Each driving channel power supply module includes a voltage reference source, a buck regulator, a boost regulator, and a D / A voltage reference source;

[0006] There are N buck regulators, denoted as the first buck regulator to the Nth buck regulator; each buck regulator has the same structure; the first buck regulator is composed of a first buck converter, a second buck converter, a third buck converter, a fourth buck converter, a first low-dropout (LDO) regulator, and a second low-dropout (LDO) regulator;

[0007] There are N voltage reference sources, denoted as the first voltage reference source to the Nth voltage reference source; each voltage reference source has the same structure;

[0008] The first voltage reference source is composed of a first reference voltage, a second reference voltage and a fifth BUCK converter;

[0009] There are N D / A voltage reference sources, which are denoted as the first D / A voltage reference source to the Nth D / A voltage reference source; each D / A voltage reference source has the same structure.

[0010] The first buck regulator and the first voltage reference source are the first buck regulator and the first voltage reference source of the first drive channel. The first buck regulator and the first voltage reference source not only power the first drive channel module, but also power the FPGA control module. The external total power supply voltage is stepped down by the first buck regulator. The first voltage reference source provides a reference voltage for the first buck regulator and provides power for the FPGA control module.

[0011] There are N driving channel modules, respectively denoted as the first driving channel module to the Nth driving channel module. Each driving channel module includes a decoder, a digital-to-analog converter, an analog switch matrix, a voltage follower, and a multi-channel voltage amplifier. The decoder and the digital-to-analog converter receive the FPGA digital signal, use the decoder to open the analog switch, and transmit the analog signal of the digital-to-analog converter to the voltage follower through the analog switch for signal buffering. The voltage follower inputs the buffered analog signal into the corresponding channel of the multi-channel voltage amplifier.

[0012] There are Z digital-to-analog converters, which are respectively denoted as the first digital-to-analog converter to the Nth digital-to-analog converter;

[0013] The analog switch matrix includes Z analog switches, denoted as the first analog switch to the Zth analog switch, wherein the Z analog switches have a total of N groups, each group having A analog switches, and the input channels of each group of A analog switches are connected to the A analog output channels of each analog-to-digital converter, and the relationship N*A=Z is satisfied;

[0014] There are Z voltage followers, which are respectively denoted as the first voltage follower to the Zth voltage follower;

[0015] There are N decoders, which are respectively denoted as the first decoder to the Nth decoder. The decoders convert the digital signal output by the FPGA control module into an enable signal for driving the analog switch to open.

[0016] The digital-to-analog converter has A analog signal output channels, which converts the digital signal output by the FPGA control module into an initial analog signal for driving the deformable mirror device, and the analog signal is transmitted to the voltage follower through the analog switch;

[0017] Each analog switch has the same structure and function. The analog switch receives the enable signal output by the decoder and bidirectionally opens the analog switch of the corresponding channel, allowing the analog signal of the digital-to-analog converter to be input to the analog switch of the corresponding channel. The analog switch then outputs the analog signal to the bound voltage follower.

[0018] There are A voltage followers, each having the same structure and function, for buffering and electrically isolating the analog signal output by the analog switch to ensure signal stability, and outputting the buffered analog signal to the multi-channel voltage amplifier;

[0019] The multi-channel voltage amplifier amplifies the analog voltage signal output by the voltage follower and outputs a high voltage signal for driving the corresponding unit of the deformable mirror;

[0020] The number of modules can be flexibly adjusted based on the number of deformable mirror drive ceramic units. For example, if there are 64 deformable mirror drive ceramic units, an 8-channel drive channel module can be used. Each drive channel module uses a 3-8 decoder to activate 8 analog switches. The analog signals from the 8-channel digital-to-analog converter are transmitted to 8 voltage followers via the activated analog switches for signal buffering. The signals from the voltage followers are then transmitted to 8 voltage amplifiers for voltage amplification. Finally, the 8 drive channel modules generate 64 amplified voltage signals to drive 64 ceramic unit deformable mirrors.

[0021] The drive channel power supply module steps down the external total power supply through a step-down regulator to convert it into a stable power supply for the monitoring module and the drive channel module; the external total power supply voltage is stepped up through a step-up regulator to convert it into a stable power supply for the multi-channel voltage amplifier of the drive channel module; the voltage reference source provides a reference voltage for the step-down regulator, and the D / A voltage reference source provides a reference voltage for the digital-to-analog converter of the drive channel module;

[0022] The FPGA control module includes a clock synchronization module, a digital-analog mixed signal processing module, a bus data interface, a data control module, and a monitoring control module;

[0023] The clock synchronization module is used to reduce the frequency of the 50MHZ clock input by the FPGA control module and output the SPI_CLK clock used by each module of the FPGA control module; the SYS_RST signal input by the clock synchronization module is a global reset signal, and the SYS_RST signal will be transmitted to each module of the FPGA control module;

[0024] The digital-analog mixed signal processing module includes an SPI protocol 1 module, an SPI protocol data control module and a read-write FIFO module; the SPI protocol 1 module is used to transmit data via the SPI protocol, and the SPI protocol data control module is used to integrate the data transmitted by the SPI protocol 1 module; the read-write FIFO module is used to process the data to be written into the digital-to-analog converter by the buffer data control module and the channel feedback data of the digital-to-analog converter transmitted from the SPI protocol data control module;

[0025] The digital-analog mixed signal processing module buffers, integrates and processes the digital signal and enable signal output by the data control module, and then outputs the processed data to the digital-to-analog converter; when inputting, it sends a digital signal of a specified channel to the digital-to-analog converter, reads the digital signal of the specified channel output by the digital-to-analog converter, and then processes, integrates and buffers the output data to the data control module;

[0026] The data control module includes a channel data allocation module and an enable module; the channel data allocation module sends an enable signal to the enable module, the enable module receives and integrates the enable signals from the total data interface and the digital-analog mixed signal processing module, and sends an enable signal to drive the decoder of the channel module;

[0027] The data control module receives the channel data and enable signal outputted from the bus data interface as input, and receives the digital signal and enable signal processed by the digital-analog mixed signal processing module as input. When outputting, the closed-loop signal is processed and read out to the bus data interface, and the digital signal and enable signal for driving the analog switch matrix to operate are outputted to the decoder.

[0028] The bus data interface includes a total data module, an SPI protocol 2 and an EEPROM storage module;

[0029] The bus data interface transmits the data of the monitoring control module and the data of the data control module to the total data module using SPI protocol 2 for input and processing, and outputs the channel data and enable signal to the data control module during output; the EEPROM storage module is used to store the channel feedback data of the digital-to-analog converter transmitted from the data control module, and can also store the data to be written to the digital-to-analog converter in the past and present;

[0030] There are N groups of monitoring modules, denoted as the first monitoring module to the Nth monitoring module, each monitoring module includes a distributed digital temperature sensor and a current monitor;

[0031] The monitoring and control module is used to integrate the digital signals read by the distributed digital temperature sensor and the current monitor and transmit them to the bus data interface for processing;

[0032] The monitoring and control module includes a temperature processing module, a current processing module and a detection data fusion module; the temperature processing module processes the sensor temperature data and then transmits it to the detection data fusion module, and the current processing module processes the sensor current data and then transmits it to the detection data fusion module; the monitoring and control module and the FPGA control module perform data fusion processing to realize the distribution of multi-channel data and closed-loop feedback control;

[0033] The distributed digital temperature sensor is powered by the first buck regulator, detects the temperature coefficient of the multi-channel voltage amplifier, and transmits the digital signal to the FPGA control module through the register;

[0034] The current monitor is powered by the buck regulator of the driving channel power supply module, monitors the current of the high-voltage line output by the boost regulator of the driving channel power supply module, and transmits the digital signal generated by the current monitor to the FPGA control module through the SPI protocol; the deformable mirror device is a planar array system composed of piezoelectric ceramic units, and the deformable mirror device controls the deformation of the piezoelectric ceramic by dynamically adjusting the voltage applied to each ceramic unit, thereby achieving high-precision correction of the light beam wavefront; the voltage control signal output by the multi-channel voltage amplifier of the driving channel is distributed to each ceramic unit in a vector form.

[0035] The first step-down regulator is powered by a 12V main power supply, and the 12V power supply is stepped down to a 7V output through a first buck converter of the first step-down regulator; the second buck converter steps down to a 5V output; the 12V output power supply is stepped down to a 1.2V output through a fourth buck converter; the 5V output power supply is stepped down to a 3.3V output through a third buck converter, the 3.3V output power supply is stepped down to a 1.5V output through a first low-dropout (LDO) regulator; and the 3.3V output power supply is stepped down to a 2.5V output through a second LDO regulator.

[0036] After the first step-down regulator steps down the voltage, the second BUCK converter steps down the voltage to provide the power supply voltage input to the FPGA control module;

[0037] The third BUCK converter and the first LDO voltage regulator are used in conjunction with each other to become the I / O port voltage input of the FPGA control module;

[0038] The second LDO voltage regulator is the FPGA control module PLL analog voltage input;

[0039] The fourth BUCK converter is the core voltage input of the FPGA control module;

[0040] After the first buck regulator steps down the voltage, the output voltage of the first buck converter is used as the power supply input of the first multi-channel voltage amplifier of the first driving channel;

[0041] The second BUCK converter is the input of the first digital-to-analog converter power supply of the first driving channel;

[0042] The second BUCK converter supplies power to the decoder, analog switch and voltage follower of the first driving channel module;

[0043] The second BUCK converter outputs a 5V power supply which is converted to -5V by the first flyback converter and is used as the -5V power supply input for the first multi-channel voltage amplifier of the first driving channel module;

[0044] The second BUCK converter of the first step-down regulator also provides 5V power to the first digital temperature sensor and the first current monitor of the first monitoring module.

[0045] The first voltage reference source is powered by a 12V main power supply, and the 12V power supply is converted to a 3.3V output through a fifth BUCK converter; the 3.3V power supply is converted to a 1.2V output and a 2.5V output through the first reference voltage and the second reference voltage, the 1.2V output is used as a voltage reference source for the fourth BUCK converter, and the 2.5V output is used as a voltage reference source for the second LDO regulator;

[0046] The first D / A voltage reference source is powered by the main power supply 12V, and the 12V power supply is converted into a 5V output through the second BUCK converter. The 5V power supply is converted into a 2.5V output through the third reference voltage. The 2.5V output is used as the reference voltage of the first digital-to-analog conversion chip of the first drive channel to provide a reference voltage for the analog output signal.

[0047] The N groups of boost regulators have the same structure and function. The first boost regulator is powered by a 12V main power supply and boosts the 12V power supply to a 250V output voltage via a first BOOST conversion circuit, providing a 250V power input for the first multi-channel voltage amplifier. The output voltage-side current of the first boost regulator is monitored by a first current detector of a first monitoring module.

[0048] The digital-analog mixed signal processing module of the FPGA control module passes the digital signal and enable signal output by the data control module into a write FIFO (First Input First Out) for buffering, then passes the buffered data of the FIFO into the SPI protocol data control module for integration, and finally writes the control data into the first digital-to-analog converter of the first drive channel through the SPI protocol 1 module;

[0049] The mixed digital-analog signal processing module processes the digital signal read by the first digital-analog converter to the channel and transmits it to SPI protocol 1 through SPI protocol, transmits the digital signal to the SPI protocol data control module for data integration, then transmits it to the read FIFO for buffering, and finally sends it to the data control module.

[0050] The data control module transmits the digital signal and enable signal processed by the bus data interface to the data distribution module and the enable module for distribution, transmits the distributed channel data and enable signal to the write FIFO, and transmits the signal to the decoder;

[0051] The data control module transmits the data and enable signal output from the read FIFO to the data distribution module and the enable module for processing, and then reads the processed data and enable signal to the bus data interface.

[0052] The bus data interface transmits the signal output from the monitoring control module and the data and enable signal output from the data control module to the total data module for sorting, and outputs the data and enable signal to the data control module for processing;

[0053] The total data module can maintain the input and output data, and divide the EEPROM storage module as the storage end into two storage areas for input and output data. The data to be saved is transmitted to the storage end through SPI protocol 2, and then looped back to the total data module for signal closed-loop processing.

[0054] The monitoring and control module transmits the data read by the first digital temperature sensor through the register to the temperature processing module for processing;

[0055] The monitoring control module reads data from the first current monitor through the SPI protocol and transmits the data to the current processing module for processing;

[0056] The information processed by the temperature processing module and the current processing module are sent to the detection data fusion module for data processing and integration, and finally the data is output to the bus data interface.

[0057] The detection data fusion module of the monitoring and control module includes: a temperature control module, a current control module and an output conditioning module. The temperature control module includes a temperature data integration module, a temperature signal filtering module and a temperature PI module, and the current control module includes a current data integration module, a current signal filtering module and a current PI module.

[0058] The data from the temperature PI module and the current PI module are put into the output conditioning module of the detection data fusion module for signal processing, and then the processed signals are sent to the bus data interface.

[0059] The detection data fusion module uses discretization to implement the incremental PI control algorithm, including: calculating the deviation between the input signal and the reference signal to generate the current error signal e(n):

[0060] e(n)=r(n)-y(n),

[0061] Where r(n) is the reference input at time n, and y(n) is the actual system output at time n;

[0062] The error signal e(n) is processed in parallel via two channels: one channel is multiplied by the integral coefficient KI to generate the integral adjustment value; the other channel is stored in a register and serves as the historical error input e(n-1) for the proportional term calculation in the next control cycle. The proportional term is obtained by multiplying the historical error e(n-1) in the register by the proportional coefficient KP. The integral and proportional terms are then vector-synthesized to obtain the incremental adjustment value ΔU(n) for the current control cycle:

[0063] ΔU(n)=K P ·[e(n-1)]+K I ·e(n),

[0064] where K P is the proportionality coefficient, K I is the integration coefficient;

[0065] The output control quantity is obtained by algebraically superposing the incremental adjustment quantity and the control quantity U(n-1) at the previous moment:

[0066] U(n)=U(n-1)+ΔU(n),

[0067] Where U(n) is the control quantity output at the current moment;

[0068] Update the error register:

[0069] e(n-1)←e(n),

[0070] The current error, e(n), is stored in a register for use in the next cycle; the symbol ← indicates that the value of e(n) is assigned to e(n-1). This algorithm eliminates the integral accumulation effect of traditional position-based algorithms through a recursive iterative mechanism, significantly improving the system's dynamic response and steady-state robustness while maintaining control accuracy.

[0071] Beneficial effects: (1) The present invention uses a collaborative design of multi-module distributed independent power supplies and high-precision voltage reference sources to provide isolated stable voltage and low noise requirements for each operating module;

[0072] (2) The present invention can adapt to deformable mirror arrays of different sizes by flexibly expanding N drive channels and coordinating and parallelizing multiple modules and drive channels;

[0073] (3) The present invention utilizes the collaborative feedback of multiple monitoring modules to ensure the quality of circuit operation, and then integrates the FPGA algorithm into dynamic compensation to reduce the crosstalk between driving voltage channels, ensure the synchronization and consistency of large-scale arrays, and reduce the cumulative error of optical images;

[0074] (4) The drive channel of the present invention uses a high-precision digital-to-analog converter, which is combined with an analog switch and a decoder to increase the flexibility of the drive circuit. The multi-channel voltage amplifier combined with a boost regulator and a voltage follower makes the control of the deformable mirror more precise, significantly improving the correction resolution of the optical system.

[0075] (5) The present invention uses FPGA digital closed-loop control to achieve multi-channel parallel control, and combines communication protocols to improve the system's response speed and control accuracy, meeting the wavefront correction requirements of astronomical observations or laser communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 It is a schematic diagram of the overall structure of the present invention.

[0077] Figure 2 This is a structural diagram of the FPGA power supply module.

[0078] Figure 3 This is a structural diagram of the first drive channel power supply module.

[0079] Figure 4 It is a structural diagram of the first monitoring module.

[0080] Figure 5 Figure 2 is a schematic diagram of the FPGA control module.

[0081] Figure 6 Schematic diagram of the detection data fusion module.

[0082] Figure 7 A side view of a deformable mirror. DETAILED DESCRIPTION

[0083] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and other advantages of the present invention will become more apparent.

[0084] like Figure 1 As shown, an embodiment of the present invention provides a control circuit based on a deformable mirror device driver, comprising: a multi-stage power supply architecture, a drive channel array, a monitoring unit, and an FPGA control core. The multi-stage power supply architecture comprises an external main power input (12V), a dedicated FPGA low-voltage power supply circuit, and N groups of drive channel high-voltage power supply circuits; the drive channel array includes a cascaded decoder, a digital-to-analog converter group, an analog switch matrix, a voltage follower group, and a multi-channel high-voltage amplifier; the monitoring unit comprises N groups of distributed digital temperature sensors and a current monitoring device; and the FPGA control core integrates a clock synchronization module, a mixed-signal processor, a bus data interface, and a closed-loop monitoring controller to achieve multi-channel data distribution and closed-loop feedback control.

[0085] In the power module of this example, the external power input 12V is transmitted to the FPGA power module and the N groups of drive channel power modules. The first buck regulator in the FPGA power module converts the 12V voltage into four voltage sources suitable for the FPGA chip based on the reference voltage provided by the first voltage reference source. The buck regulators in the N groups of drive channel power modules convert the 12V voltage into voltage sources suitable for the supply of each module chip in the drive channel based on the reference voltage provided by the voltage reference source. The boost regulator provides a 250V power supply for the multi-channel voltage amplifier specified by the drive channel. The D / A voltage reference source provides an external reference voltage source for the high-precision requirements of the analog-to-digital converter.

[0086] The FPGA control module reads data from the amplifier temperature monitored by the digital temperature sensor in the monitoring module and the high-voltage line current output by the boost regulator, monitored by the current detector. This data is then processed by internal modules, and the decoder drive data and the digital signal from the analog-to-digital converter are input into two chips. After receiving the information, the decoder outputs an enable signal to open the specified analog switch. The analog-to-digital converter then transmits the analog signal in and out of the analog switch within a single clock cycle. The voltage follower buffers and electrically isolates the analog signal output by the analog switch before outputting it to a multi-channel voltage amplifier. The multi-channel voltage amplifier amplifies the weak analog signal by a specified multiple based on its gain requirements, generating a voltage sufficient to drive the unit array of the deformable mirror, causing it to deform and achieve optical wavefront correction.

[0087] The FPGA control module can send read commands, which transmit the command data to the DAC. The DAC then outputs the specified channel data requested in the command to the FPGA control module. The FPGA control module performs feedback processing based on the monitoring module and the read channel voltage data. It then outputs the appropriate channel data to the DAC, forming a closed-loop control. The read channel voltage feedback signal, the monitoring module sensor feedback signal, and the input drive digital signal can be stored in the EEPROM memory module. This is then looped back to the internal module for signal processing.

[0088] Figure 2 This is a schematic diagram of the FPGA power supply module. The power supply system, centered around a 12V input, generates different voltage rails through multi-stage voltage conversion, providing precise power to devices within the FPGA control module. The system uses a first step-down regulator and a second buck converter to convert the 12V input into 7V and 5V power rails. The 5V output provides the FPGA's power supply, while the 7V provides power for the multi-channel voltage amplifier. A third buck converter and a first low-dropout (LDO) regulator generate 3.3V and 1.5V power rails for the FPGA's I / O ports, enabling flexible FPGA circuit configuration. A second LDO regulator generates a 2.5V PLL analog voltage for the FPGA, as well as a 1.2V core voltage rail generated by a fourth buck converter. The first voltage reference source uses a fifth buck converter to generate a 3.3V supply from an external 12V power supply to power the reference voltage chip. The 1.2V and 2.5V voltages generated by the first and second reference voltages provide reference voltages for the FPGA's critical analog and core voltage conversion chips. By designing a power sequencing chip or circuit, the power supply power-up sequence is 1. core voltage, 2. analog voltage, 3. I / O port, and 4. supply voltage. This sequence must meet power-up timing requirements to avoid latch-up, ensure stable I / O states, and ensure reliable FPGA startup and long-term stable operation.

[0089] Figure 3 This is a schematic diagram of the structure of the first drive channel power supply module. The power supply system is based on 12V input and generates different voltage rails through multi-level voltage conversion to provide precise power supply for the devices in the drive channel module. The principle of the buck regulator and voltage reference source is as follows Figure 2The above description is unnecessary. The 7V and 5V power supplies output by the first buck converter are passed through a first flyback converter to generate a -5V power supply, which powers the first voltage amplifier. Furthermore, the 5V power supply also powers the first analog-to-digital converter, decoder, analog switch, voltage follower, and external first monitoring module of the driver channel. The first D / A voltage reference source generates a 5V power supply through a second buck converter, which is then reduced to a 2.5V reference voltage using a third reference voltage reference chip, providing an external reference voltage for the mode converter. The first boost regulator uses a first boost converter circuit to boost the input 12V power supply to 250V, providing the drive voltage for the first multi-channel voltage amplifier. The current in its 250V voltage line is also monitored by the first current monitor of the first monitoring module. The first driver channel power supply module is the same as the other driver channel power supply modules.

[0090] Figure 4 This is a schematic diagram of the structure of the first monitoring module. The main 12V power supply supplies power to the first drive channel power module, which in turn supplies power to the first digital temperature sensor and first current monitor of the first monitoring module via a buck circuit. The first digital temperature sensor monitors the temperature coefficient of the first multi-channel voltage amplifier, and the FPGA control module reads the temperature value through register configuration. The first current monitor monitors the current in the 250V line, and the FPGA control module reads the current value via the SPI protocol. The first temperature sensor monitors device temperature to prevent overheating damage. A temperature compensation algorithm is integrated into the FPGA control module, adjusting the drive voltage or signal gain based on temperature data to improve system stability. The first current monitor detects the output current of the first multi-channel voltage amplifier in real time to prevent device damage caused by overcurrent. The output power of the power module is adjusted based on the current data, reducing system power consumption and improving energy efficiency. These data provide critical feedback to the FPGA control module, supporting dynamic adjustment, fault protection, and energy efficiency optimization, making it an indispensable core component in the deformable mirror drive system. The first monitoring module is similar to the monitoring modules in other channels.

[0091] Figure 5This is a schematic diagram of the FPGA control module. The clock synchronization module converts the system clock input SYS_CLK_50Hz into the global clock SPI_CLK suitable for running other modules. Its SYS_RST is the system's global reset and is associated with the pushbutton switch. The temperature processing module in the monitoring and control module reads sensor register data, processes it, and then transmits it to the detection data fusion module for integration. The current processing module in the monitoring and control module uses the SPI protocol to read the first current monitor data, processes it, and then transmits it to the detection data fusion module for integration. The detection data fusion module outputs the integrated data to the bus data interface. The temperature and current data, after algorithmic processing, serve as the output reference for the closed-loop voltage output data of the drive channel. The bus data interface outputs the drive channel data of the deformable mirror array to the data control module and the SPI-supported EEPROM storage module. The data control module uses the data distribution module and the EN module to combine the data and enable signal output from the bus data interface into two channels. One channel contains the 3-bit data signal and enable signal of the drive encoder. The other channel contains the 24-bit data signal and enable signal that are transmitted to the mixed-signal processing module. The mixed-signal processing module buffers the two incoming signals into a read FIFO. The read FIFO buffered data is then output to the SPI protocol data control module, which processes the data into serial data suitable for SPI operation. The SPI protocol data control module then transmits the data to the SPI protocol 1 module, which outputs the data to the first digital-to-analog converter using the SPI protocol.

[0092] When the FPGA wants to read data from a specific channel, it sends a read message to the first DAC. The first DAC outputs the data to the SPI Protocol 1 module via the SPI protocol. The SPI protocol data control processes the data from the SPI Protocol 1 module and buffers it in the read FIFO. The read FIFO sends the read data and an enable signal to the data distribution module and enable module in the data control module. The data distribution module and enable module process the data and output the channel data and enable signal to the total data module for split reading. The read channel data can be stored in the EEPROM storage module using the SPI protocol.

[0093] The master data module in the bus data interface interacts with data stored in the EEPROM storage module, reading and storing past and current channel write data and channel readout information. This data is then placed in the master data module for algorithmic processing in conjunction with the sensor coefficients read by the monitoring module. This provides more accurate numerical and temperature operation for the unit drivers of the deformable mirror array. The EEPROM storage module's storage can be divided into two areas: one for read data and the other for write data. The EEPROM storage module's stored data can also be exchanged with an external host computer for convenient host control. It reads or writes 24-bit data transmission, including default register bits, read / write enable bits, channel select read / write bits, register type configuration bits, and channel data read / write bits. A checksum or parity bit can be used to ensure data integrity.

[0094] Figure 6 This is a schematic diagram of the detection data fusion module. The temperature and current data generated by the monitoring module's temperature sensor and current monitor are fed into the detection data fusion module's temperature and current signals. The temperature signal is filtered and then fed into the temperature PI for control. The current signal is filtered and then fed into the current PI for control. The temperature PI and current PI values are fed into the output conditioning module for signal fusion. The processed signals are then fed into the master data module of the bus data interface.

[0095] Figure 7 A side view of a deformable mirror; on the left is the drive array, and on the right is the mirror surface. These units adjust the mirror's shape, which in turn compensates for wavefront distortion and improves image quality.

[0096] The present invention provides a control circuit based on a deformable mirror device driver. There are numerous methods and approaches for implementing this technical solution. The foregoing merely represents a preferred embodiment of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention. Components not specified in this embodiment may be implemented using existing technologies.

Claims

1. A control circuit based on a deformable mirror device driver, characterized in that: Includes multi-level power supply architecture, drive channel module, monitoring module and FPGA control module; The multi-stage power supply architecture includes an external main power supply, an FPGA power supply module and a drive channel power supply module. The external main power supply is a 12V power supply output, which is used to provide power input for the FPGA power supply module and the drive channel power supply module; There are N driving channel power supply modules, which are respectively recorded as the first driving channel power supply module to the Nth driving channel power supply module. Each driving channel power supply module includes a voltage reference source, a buck regulator, a boost regulator, and a D / A voltage reference source; There are N buck regulators, denoted as the first buck regulator to the Nth buck regulator; each buck regulator has the same structure; the first buck regulator is composed of a first buck converter, a second buck converter, a third buck converter, a fourth buck converter, a first low-dropout (LDO) regulator, and a second low-dropout (LDO) regulator; There are N voltage reference sources, which are denoted as the first voltage reference source to the Nth voltage reference source; Each voltage reference source has the same structure; The first voltage reference source is composed of a first reference voltage, a second reference voltage and a fifth BUCK converter; There are N D / A voltage reference sources, which are denoted as the first D / A voltage reference source to the Nth D / A voltage reference source; each D / A voltage reference source has the same structure; The first buck regulator and the first voltage reference source are the first buck regulator and the first voltage reference source of the first drive channel. The first buck regulator and the first voltage reference source not only power the first drive channel module, but also power the FPGA control module. The external total power supply voltage is stepped down by the first buck regulator. The first voltage reference source provides a reference voltage for the first buck regulator and provides power for the FPGA control module. There are N driving channel modules, respectively denoted as the first driving channel module to the Nth driving channel module. Each driving channel module includes a decoder, a digital-to-analog converter, an analog switch matrix, a voltage follower, and a multi-channel voltage amplifier. The decoder and the digital-to-analog converter receive the FPGA digital signal, use the decoder to open the analog switch, and transmit the analog signal of the digital-to-analog converter to the voltage follower through the analog switch for signal buffering. The voltage follower inputs the buffered analog signal into the corresponding channel of the multi-channel voltage amplifier. There are N digital-to-analog converters, which are respectively denoted as the first digital-to-analog converter to the Nth digital-to-analog converter; The analog switch matrix includes Z analog switches, denoted as the first analog switch to the Zth analog switch, wherein the Z analog switches have a total of N groups, each group having A analog switches, and the input channels of each group of A analog switches are connected to the A analog output channels of each analog-to-digital converter, and the relationship N*A=Z is satisfied; There are Z voltage followers, which are respectively denoted as the first voltage follower to the Zth voltage follower; There are N decoders, which are respectively denoted as the first decoder to the Nth decoder. The decoders convert the digital signal output by the FPGA control module into an enable signal for driving the analog switch to open. The digital-to-analog converter has A analog signal output channels, which converts the digital signal output by the FPGA control module into an initial analog signal for driving the deformable mirror device, and the analog signal is transmitted to the voltage follower through the analog switch; Each analog switch has the same structure and function. The analog switch receives the enable signal output by the decoder and bidirectionally opens the analog switch of the corresponding channel, allowing the analog signal of the digital-to-analog converter to be input to the analog switch of the corresponding channel. The analog switch then outputs the analog signal to the bound voltage follower. There are A voltage followers in each drive channel module. Each voltage follower has the same structure and function and is used to buffer and electrically isolate the analog signal output by the analog switch to ensure signal stability, and output the buffered analog signal to the multi-channel voltage amplifier. The multi-channel voltage amplifier amplifies the analog voltage signal output by the voltage follower and outputs a high voltage signal for driving the corresponding unit of the deformable mirror; The drive channel power supply module steps down the external total power supply through a step-down regulator to convert it into a stable power supply for the monitoring module and the drive channel module; the external total power supply voltage is stepped up through a step-up regulator to convert it into a stable power supply for the multi-channel voltage amplifier of the drive channel module; the voltage reference source provides a reference voltage for the step-down regulator, and the D / A voltage reference source provides a reference voltage for the digital-to-analog converter of the drive channel module; The FPGA control module includes a clock synchronization module, a digital-analog mixed signal processing module, a bus data interface, a data control module, and a monitoring control module; The clock synchronization module is used to reduce the frequency of the 50MHZ clock input by the FPGA control module and output the SPI_CLK clock used by each module of the FPGA control module; the SYS_RST signal input by the clock synchronization module is a global reset signal, and the SYS_RST signal will be transmitted to each module of the FPGA control module; The digital-analog mixed signal processing module includes an SPI protocol 1 module, an SPI protocol data control module and a read-write FIFO module; the SPI protocol 1 module is used to transmit data via the SPI protocol, and the SPI protocol data control module is used to integrate the data transmitted by the SPI protocol 1 module; the read-write FIFO module is used to process the data to be written into the digital-to-analog converter by the buffer data control module and the channel feedback data of the digital-to-analog converter transmitted from the SPI protocol data control module; The digital-analog mixed signal processing module buffers, integrates and processes the digital signal and enable signal output by the data control module, and then outputs the processed data to the digital-to-analog converter; when inputting, it sends a digital signal of a specified channel to the digital-to-analog converter, reads the digital signal of the specified channel output by the digital-to-analog converter, and then processes, integrates and buffers the output data to the data control module; The data control module includes a channel data allocation module and an enable module; the channel data allocation module sends an enable signal to the enable module, the enable module receives and integrates the enable signals from the total data interface and the digital-analog mixed signal processing module, and sends an enable signal to drive the decoder of the channel module; The data control module receives the channel data and enable signal outputted from the bus data interface as input, and receives the digital signal and enable signal processed by the digital-analog mixed signal processing module as input. When outputting, the closed-loop signal is processed and read out to the bus data interface, and the digital signal and enable signal for driving the analog switch matrix to operate are outputted to the decoder. The bus data interface includes a total data module, an SPI protocol 2 and an EEPROM storage module; The bus data interface transmits the data of the monitoring control module and the data of the data control module to the total data module using SPI protocol 2 for input and processing, and outputs the channel data and enable signal to the data control module during output; the EEPROM storage module is used to store the channel feedback data of the digital-to-analog converter transmitted from the data control module, and can also store the data to be written to the digital-to-analog converter in the past and present; There are N groups of monitoring modules, denoted as the first monitoring module to the Nth monitoring module, each monitoring module includes a distributed digital temperature sensor and a current monitor; The monitoring and control module is used to integrate the digital signals read by the distributed digital temperature sensor and the current monitor and transmit them to the bus data interface for processing; The monitoring and control module includes a temperature processing module, a current processing module and a detection data fusion module; the temperature processing module processes the sensor temperature data and then transmits it to the detection data fusion module, and the current processing module processes the sensor current data and then transmits it to the detection data fusion module; the monitoring and control module and the FPGA control module perform data fusion processing to realize the distribution of multi-channel data and closed-loop feedback control; The distributed digital temperature sensor is powered by the first buck regulator, detects the temperature coefficient of the multi-channel voltage amplifier, and transmits the digital signal to the FPGA control module through the register; The current monitor is powered by the buck regulator of the driving channel power supply module, monitors the current of the high-voltage line output by the boost regulator of the driving channel power supply module, and transmits the digital signal generated by the current monitor to the FPGA control module through the SPI protocol; the deformable mirror device is a planar array system composed of piezoelectric ceramic units, and the deformable mirror device controls the deformation of the piezoelectric ceramic by dynamically adjusting the voltage applied to each ceramic unit, thereby achieving high-precision correction of the light beam wavefront; the voltage control signal output by the multi-channel voltage amplifier of the driving channel is distributed to each ceramic unit in a vector form.

2. A control circuit based on a deformable mirror device driver according to claim 1, characterized in that: The first step-down regulator is powered by a 12V main power supply, and the 12V power supply is stepped down to a 7V output through a first buck converter of the first step-down regulator; the second buck converter steps down to a 5V output; the 12V output power supply is stepped down to a 1.2V output through a fourth buck converter; the 5V output power supply is stepped down to a 3.3V output through a third buck converter, the 3.3V output power supply is stepped down to a 1.5V output through a first low-dropout (LDO) regulator; and the 3.3V output power supply is stepped down to a 2.5V output through a second LDO regulator. After the first step-down regulator steps down the voltage, the second BUCK converter steps down the voltage to provide the power supply voltage input to the FPGA control module; The third BUCK converter and the first LDO voltage regulator are used in conjunction with each other to become the I / O port voltage input of the FPGA control module; The second LDO voltage regulator is the FPGA control module PLL analog voltage input; The fourth BUCK converter is the core voltage input of the FPGA control module; After the first buck regulator steps down the voltage, the output voltage of the first buck converter is used as the power supply input of the first multi-channel voltage amplifier of the first driving channel; The second BUCK converter is the input of the first digital-to-analog converter power supply of the first driving channel; The second BUCK converter supplies power to the decoder, analog switch and voltage follower of the first driving channel module; The second BUCK converter outputs a 5V power supply which is converted to -5V by the first flyback converter and is used as the -5V power supply input for the first multi-channel voltage amplifier of the first driving channel module; The second BUCK converter of the first step-down regulator also provides 5V power to the first digital temperature sensor and the first current monitor of the first monitoring module.

3. A control circuit based on a deformable mirror device driver according to claim 2, characterized in that: The first voltage reference source is powered by a 12V main power supply, and the 12V power supply is converted to a 3.3V output through a fifth BUCK converter; the 3.3V power supply is converted to a 1.2V output and a 2.5V output through the first reference voltage and the second reference voltage, the 1.2V output is used as a voltage reference source for the fourth BUCK converter, and the 2.5V output is used as a voltage reference source for the second LDO regulator; The first D / A voltage reference source is powered by the main power supply 12V, and the 12V power supply is converted into a 5V output through the second BUCK converter. The 5V power supply is converted into a 2.5V output through the third reference voltage. The 2.5V output is used as the reference voltage of the first digital-to-analog conversion chip of the first drive channel to provide a reference voltage for the analog output signal.

4. A control circuit based on a deformable mirror device driver according to claim 3, characterized in that: The N groups of boost regulators have the same structure and function; the first boost regulator is powered by a total power supply of 12V, and boosts the 12V power supply to a 250V output through a first BOOST conversion circuit, providing a 250V power input for the first multi-channel voltage amplifier; the output voltage side current of the first boost regulator is detected by a first current detector of a first monitoring module.

5. A control circuit based on a deformable mirror device driver according to claim 4, characterized in that: The digital-analog mixed signal processing module of the FPGA control module transmits the digital signal and enable signal output by the data control module into the write FIFO for buffering, then transmits the buffered data of the FIFO to the SPI protocol data control module for integration, and finally writes the control data into the first digital-to-analog converter of the first drive channel through the SPI protocol 1 module; The mixed digital-analog signal processing module processes the digital signal read by the first digital-analog converter to the channel and transmits it to SPI protocol 1 through SPI protocol, transmits the digital signal to the SPI protocol data control module for data integration, then transmits it to the read FIFO for buffering, and finally sends it to the data control module.

6. The control circuit based on the deformable mirror device driver according to claim 5, characterized in that: The data control module transmits the digital signal and enable signal processed by the bus data interface to the data distribution module and the enable module for distribution, transmits the distributed channel data and enable signal to the write FIFO, and transmits the signal to the decoder; The data control module transmits the data and enable signal output from the read FIFO to the data distribution module and the enable module for processing, and then reads the processed data and enable signal to the bus data interface.

7. A control circuit based on a deformable mirror device driver according to claim 6, characterized in that: The bus data interface transmits the signal output from the monitoring control module and the data and enable signal output from the data control module to the total data module for sorting, and outputs the data and enable signal to the data control module for processing; The total data module can maintain the input and output data, and divide the EEPROM storage module as the storage end into two storage areas for input and output data. The data to be saved is transmitted to the storage end through SPI protocol 2, and then looped back to the total data module for signal closed-loop processing.

8. The control circuit based on the deformable mirror device driver according to claim 7, characterized in that: The monitoring and control module transmits the data read by the first digital temperature sensor through the register to the temperature processing module for processing; The monitoring control module reads data from the first current monitor through the SPI protocol and transmits the data to the current processing module for processing; The information processed by the temperature processing module and the current processing module are sent to the detection data fusion module for data processing and integration, and finally the data is output to the bus data interface.

9. The control circuit based on the deformable mirror device driver according to claim 8, characterized in that: The detection data fusion module of the monitoring and control module includes: a temperature control module, a current control module and an output conditioning module; The temperature control module includes a temperature data integration module, a temperature signal filtering module and a temperature PI module, and the current control module includes a current data integration module, a current signal filtering module and a current PI module; The data from the temperature PI module and the current PI module are put into the output conditioning module of the detection data fusion module for signal processing, and then the processed signals are sent to the bus data interface.

10. The control circuit based on the deformable mirror device driver according to claim 9, characterized in that: The detection data fusion module uses discretization to implement the incremental PI control algorithm, including: calculating the deviation between the input signal and the reference signal to generate the current error signal e(n): e(n)=r(n)-y(n), Where r(n) is the reference input at time n, and y(n) is the actual system output at time n; The error signal e(n) is processed in parallel via two channels: one channel is multiplied by the integral coefficient KI to generate the integral adjustment value; the other channel is stored in a register and serves as the historical error input e(n-1) for the proportional term calculation in the next control cycle. The proportional term is obtained by multiplying the historical error e(n-1) in the register by the proportional coefficient KP. The integral and proportional terms are then vector-synthesized to obtain the incremental adjustment value ΔU(n) for the current control cycle: ΔU(n)=K P [e(n-1)]+K I ·e(n), where K P is the proportionality coefficient, K I is the integration coefficient; The output control quantity is obtained by algebraically superposing the incremental adjustment quantity and the control quantity U(n-1) at the previous moment: U(n)=U(n-1)+ΔU(n), Where U(n) is the control quantity output at the current moment; Update the error register: e(n-1)←e(n), The current error e(n) is stored in a register for use in the next cycle; the symbol ← indicates that the value of e(n) is assigned to e(n-1).

Images