LDO (Low Dropout Regulator) loop compensation circuit with wide output capacitance range

Abstract

The embodiment of the invention discloses an LDO (Low Dropout Regulator) loop compensation circuit with a wide output capacitance range, a sampling circuit and a transconductance amplifier circuit are additionally arranged at the output end of an LDO, and the output end of the sampling circuit and the output end of the LDO are respectively connected to the in-phase end and the anti-phase end of a transconductance amplifier; the output end of the transconductance amplifier is connected to the feedback end of the LDO through a feedback resistor. A zero point related to output capacitance is generated by adding the feedback path, loop compensation is carried out on an output pole, and stability of an LDO loop is achieved. Compared with a method for performing loop compensation through a left half plane zero point obtained through parasitic ESR resistance of an output capacitor, the LDO loop compensation circuit has the advantages that stability of wide-range output capacitance can be guaranteed, transient overshoot cannot be increased, and meanwhile the LDO loop has good stability and consistency.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of analog integrated circuits, and particularly to an LDO loop compensation circuit with a wide output capacitance range. Background Art

[0002] Low dropout regulators (LDOs) are very important in the field of power management circuits. They have the characteristics of low voltage dropout and low output noise, and have broad application prospects in the field of power supply for portable electronic products.

[0003] To achieve LDO loop stability, a left half-plane zero is generated by using the parasitic ESR resistance of the output capacitor to perform pole loop compensation on the output pole. However, the parasitic ESR resistance has two problems: on the one hand, the ESR resistance will increase the transient overshoot, resulting in performance degradation; on the other hand, the parasitic ESR resistance is uncontrollable, resulting in poor consistency of LDO loop stability. Summary of the Invention

[0004] Therefore, the embodiments of the present invention provide an LDO loop compensation circuit with a wide output capacitance range to solve the technical problems that the method of performing pole loop compensation through the parasitic ESR resistance in the prior art will increase the transient overshoot, resulting in performance degradation and poor loop stability.

[0005] To achieve the above object, the embodiments of the present invention provide the following technical solutions:

[0006] According to the first aspect of the embodiments of the present invention, an LDO loop compensation circuit with a wide output capacitance range is provided. The LDO loop compensation circuit is composed of an LDO loop, a sampling circuit, and a transconductance amplifier circuit, and specifically includes:

[0007] The sampling circuit is composed of a power transistor, a sampling transistor, a current mirror, and a capacitor. The output end of the sampling circuit and the output end of the LDO loop are respectively connected to the non-inverting end and the inverting end of the transconductance amplifier. The output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor, forming a feedback path;

[0008] A zero related to the output capacitance is generated through the feedback path to perform loop compensation on the output pole;

[0009] Among them, the transconductance amplifier circuit is a rail-to-rail folded cascode structure. The rail-to-rail structure is composed of an input pair transistor and a current mirror, and the output stage is composed of a load transistor and a cascode transistor.

[0010] Further, the sampling circuit is composed of a power transistor, a sampling transistor, a current mirror, and a capacitor, and specifically includes:

[0011] The sampling tubes MN1 and MN2 are the sampling tubes of the power tube MN0. The power tube MN0 is respectively connected to the sampling tube MN1 and the sampling tube MN2. The sampling tube MN1 is connected to the current mirror MN3, and the sampling tube MN2 is connected to the current mirror MN4. The other ends of the current mirror MN3 and the current mirror MN4 are respectively connected to the capacitor C1 and grounded. The other end of the capacitor C1 is respectively connected to the voltage-dividing resistor R1 and the output terminal VO0 of the LDO loop.

[0012] Further, the sampling tubes MN1 and MN2 have the same aspect ratio, and the current mirrors MN3 and MN4 have the same aspect ratio.

[0013] Further, the output terminal of the sampling circuit and the output terminal of the LDO loop are respectively connected to the non-inverting input terminal and the inverting input terminal of the transconductance amplifier, specifically including:

[0014] The output terminal VO1 of the sampling circuit is connected to the non-inverting input terminal of the transconductance amplifier Gm, and the output terminal VO0 of the LDO loop is also connected to the inverting input terminal of the transconductance amplifier Gm.

[0015] Further, the output terminal of the transconductance amplifier is connected to the feedback terminal of the LDO loop through a feedback resistor to form a feedback path, specifically including:

[0016] The output terminal of the transconductance amplifier is connected to the common terminal of the LDO voltage-dividing resistor R1 and the voltage-dividing resistor R2 through a feedback resistor R3.

[0017] Further, the output terminal of the transconductance amplifier is connected to the feedback terminal of the LDO loop through a feedback resistor to form a feedback path, and further includes:

[0018] By adding a feedback path, a zero point z1 related to the output capacitor is generated;

[0019] Adjusting the resistance R3 and the transconductance g m3 of the size can adjust the position of the zero point to perform phase compensation on the LDO loop.

[0020] Further, the transconductance amplifier circuit is a rail-to-rail folded cascode structure. The rail-to-rail structure is composed of an input pair of transistors and a current mirror, and the output stage is composed of a load transistor and a cascode transistor, specifically including:

[0021] The gates of the input pair of transistors MN10 and the input pair of transistors MP5 are the inverting input terminals of the transconductance amplifier Gm, and are connected to the voltage VO0. The gates of the input pair of transistors MN11 and the input pair of transistors MP6 are the non-inverting input terminals of the transconductance amplifier Gm, and are connected to the voltage VO1;

[0022] The gate of current mirror MN5 is connected to bias voltage VBIAS1, and the gate of current mirror MP0 is connected to bias voltage VBIAS2.

[0023] Furthermore, the transconductance amplifier circuit is a rail-to-rail folded cascode structure. The rail-to-rail structure consists of an input pair of transistors and a current mirror, and the output stage consists of a load transistor and a cascode transistor. Specifically, it further includes:

[0024] The output stage consists of load transistors MP1, MP2, load transistors MN6, MN7 and cascode transistors MP3, MP4, cascode transistors MN8, MN9. The gates of load transistors MP1 and MP2 are connected to bias voltage VBIAS2, the gates of cascode transistors MP3 and MP4 are connected to bias voltage VBIAS4, and the gates of cascode transistors MN8 and MN7 are connected to bias voltage VBIAS3;

[0025] The drains of cascode transistors MP4 and MN9 are the output terminals of transconductance amplifier Gm and are connected to voltage VFB.

[0026] The embodiments of the present invention have the following advantages:

[0027] In the embodiments of the present invention, a sampling circuit and a transconductance amplifier circuit are added at the output end of the LDO. The output terminal of the sampling circuit and the output terminal of the LDO are respectively connected to the non-inverting and inverting terminals of the transconductance amplifier; the output terminal of the transconductance amplifier is connected to the feedback terminal of the LDO through a feedback resistor. By adding the above feedback path, a zero point related to the output capacitance is generated to perform loop compensation on the output pole, realizing the stability of the LDO loop. Compared with the method of performing loop compensation by obtaining a left-half plane zero point through the parasitic ESR resistance of the output capacitance, the embodiments of the present invention can ensure the stability of a wide range of output capacitances, will not increase the transient overshoot, and at the same time the LDO loop has good stability and consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only exemplary, and for those of ordinary skill in the art, without creative efforts, other implementation drawings can also be obtained according to the provided drawings.

[0029] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the implementation conditions of the present invention. Therefore, they do not have substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention.

[0030] Figure 1 is the circuit structure diagram of the existing LDO loop circuit;

[0031] Figure 2 is the circuit structure diagram of an LDO loop compensation circuit with a wide output capacitance range provided by an embodiment of the present invention;

[0032] Figure 3 is the circuit structure diagram of the transconductance amplifier Gm of an LDO loop compensation circuit with a wide output capacitance range provided by an embodiment of the present invention;

[0033] Figure 4 is the schematic diagram of the amplitude-frequency and phase-frequency curves of the LDO output pole (without compensation zero) in an LDO loop compensation circuit with a wide output capacitance range provided by an embodiment of the present invention;

[0034] Figure 5 is the schematic diagram of the amplitude-frequency and phase-frequency curves of the LDO output pole (with compensation zero) in an LDO loop compensation circuit with a wide output capacitance range provided by an embodiment of the present invention. Detailed implementation manners

[0035] The following specific embodiments illustrate the implementation manners of the present invention. Those familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0036] For a low dropout linear regulator (LDO) using an NMOS transistor as a power transistor, a main pole P1 is generated at the output end of the error amplifier, and a secondary pole P2 is generated at the output end of the power transistor. When the load is light, if the output capacitance is large, the secondary pole will be located within the unity gain bandwidth, affecting the loop stability and even causing output oscillation.

[0037] Reference Figure 1, to achieve the stability of the LDO loop, the parasitic ESR resistance of the output capacitor is utilized to generate a left-half plane zero to perform pole loop compensation on the output pole. However, there are two problems with the parasitic ESR resistance. On the one hand, the ESR resistance will increase the transient overshoot, resulting in performance degradation. On the other hand, the parasitic ESR resistance is uncontrollable, resulting in poor consistency of the LDO loop stability.

[0038] To solve the above technical problems that the method of pole loop compensation through the parasitic ESR resistance will increase the transient overshoot, resulting in performance degradation and poor loop stability.

[0039] Reference Figure 2 , an embodiment of the present invention discloses an LDO loop compensation circuit with a wide output capacitor range. The LDO loop compensation circuit is composed of an LDO loop, a sampling circuit, and a transconductance amplifier circuit, and specifically includes:

[0040] The sampling circuit is composed of a power transistor, a sampling transistor, a current mirror, and a capacitor. The output end of the sampling circuit and the output end of the LDO loop are respectively connected to the non-inverting end and the inverting end of the transconductance amplifier. The output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor, forming a feedback path;

[0041] A zero related to the output capacitor is generated through the feedback path to perform loop compensation on the output pole.

[0042] Among them, the transconductance amplifier circuit is a rail-to-rail folded cascode structure. The rail-to-rail structure is composed of an input pair transistor and a current mirror, and the output stage is composed of a load transistor and a cascode transistor.

[0043] Further, the sampling circuit is composed of a power transistor, a sampling transistor, a current mirror, and a capacitor, and specifically includes: The sampling transistors MN1 and MN2 are the sampling transistors of the power transistor MN0. The power transistor MN0 is respectively connected to the sampling transistors MN1 and MN2. The sampling transistor MN1 is connected to the current mirror MN3, and the sampling transistor MN2 is connected to the current mirror MN4. The other ends of the current mirrors MN3 and MN4 are respectively connected to the capacitor C1 and grounded. The other end of the capacitor C1 is respectively connected to the voltage dividing resistor R1 and the output end VO0 of the LDO loop.

[0044] Further, the sampling transistors MN1 and MN2 have the same aspect ratio, and the current mirrors MN3 and MN4 have the same aspect ratio.

[0045] Further, the output end of the sampling circuit and the output end of the LDO loop are respectively connected to the non-inverting end and the inverting end of the transconductance amplifier, and specifically include:

[0046] The output terminal VO1 of the sampling circuit is connected to the non-inverting terminal of the transconductance amplifier Gm, and the output terminal VO0 of the LDO loop is also connected to the inverting terminal of the transconductance amplifier Gm.

[0047] Further, the output terminal of the transconductance amplifier is connected to the feedback terminal of the LDO loop through a feedback resistor, forming a feedback path, specifically including: the output terminal of the transconductance amplifier is connected to the common terminal of the LDO voltage-dividing resistors R1 and R2 through a feedback resistor R3.

[0048] The LDO output terminal sampling circuit consists of MN1, MN2, MN3, MN4, current mirror I1, and capacitor C C and. Among them, MN1 and MN2 are the sampling tubes of the power tube MN0. MN1 and MN2 have the same aspect ratio, and the transconductance of MN2 is g m2 . MN3 and MN4 are current mirrors, and MN3 and MN4 have the same aspect ratio. The output terminal VO1 of the sampling circuit and the output terminal VO0 of the LDO are respectively connected to the non-inverting and inverting terminals of the transconductance amplifier Gm, and the transconductance of the transconductance amplifier Gm is g m3 . The output terminal of the transconductance amplifier is connected to the common terminal of the LDO voltage-dividing resistors R1 and R2 through a feedback resistor R3.

[0049] V EA2 to V FB The transfer function is as follows:

[0050]

[0051] Analyzing the above transfer function, a left-half plane zero z1 related to the output capacitance can be obtained:

[0052]

[0053] By adding the above feedback path, a zero z1 related to the output capacitance is generated to perform loop compensation on the output pole. By adjusting the magnitudes of R3 and g m3 , the position of the zero can be adjusted to perform phase compensation on the loop, achieving the stability of the LDO loop.

[0054] For example, when C O = 10 uF, g mp = 1 mS, g m3 = 25 uS, R3 = 4 kΩ, R1 = R2 = 10 kΩ, the output pole at this time is:

[0055]

[0056] The amplitude-frequency and phase-frequency curves of the output pole when the LDO has no zero z1 are as Figure 4 shown, and the maximum phase shift is -89.43°.

[0057] When the LDO includes the zero z1, the amplitude-frequency and phase-frequency curves of the output pole and the zero z1 are as follows Figure 5 shown. The maximum phase shift is -41.76°. The zero z1 compensates the output pole for the loop.

[0058] Furthermore, the output terminal of the transconductance amplifier is connected to the feedback terminal of the LDO loop through a feedback resistor to form a feedback path. It also includes: generating a zero z1 related to the output capacitor by adding a feedback path; adjusting the resistor R3 and the transconductance g m3 to adjust the position of the zero and perform phase compensation on the LDO loop.

[0059] Furthermore, referring to Figure 3 , the transconductance amplifier circuit is a rail-to-rail folded cascode structure. The rail-to-rail structure consists of input pairs and current mirrors, and the output stage consists of load transistors and cascode transistors. Specifically, it includes: the gates of the input pair transistors MN10 and MP5 are the inverting input terminals of the transconductance amplifier Gm and are connected to the voltage VO0. The gates of the input pair transistors MN11 and MP6 are the non-inverting input terminals of the transconductance amplifier Gm and are connected to the voltage VO1. The gate of the current mirror MN5 is connected to the bias voltage VBIAS1, and the gate of the current mirror MP0 is connected to the bias voltage VBIAS2.

[0060] Furthermore, the transconductance amplifier circuit is a rail-to-rail folded cascode structure. The rail-to-rail structure consists of input pairs and current mirrors, and the output stage consists of load transistors and cascode transistors. Specifically, it also includes: the output stage consists of load transistors MP1, MP2, MN6, MN7 and cascode transistors MP3, MP4, MN8, MN9. The gates of the load transistors MP1 and MP2 are connected to the bias voltage VBIAS2. The gates of the cascode transistors MP3 and MP4 are connected to the bias voltage VBIAS4. The gates of the cascode transistors MN8 and MN7 are connected to the bias voltage VBIAS3.

[0061] The drains of the cascode transistors MP4 and MN9 are the output terminals of the transconductance amplifier Gm and are connected to the voltage VFB.

[0062] The transconductance amplifier Gm adopts a rail-to-rail folded cascode structure to achieve rail-to-rail input to meet the low dropout requirement of the low dropout linear regulator. The rail-to-rail input structure consists of input pair transistors MN10, MN11, MP5 and MP6, and current mirrors MN5 and MP0. The gates of MN10 and MP5 are the inverting input terminals of the transconductance amplifier Gm and are connected to the voltage VO0. The gates of MN11 and MP6 are the non-inverting input terminals of the transconductance amplifier Gm and are connected to the voltage VO1. The gate of the current mirror MN5 is connected to the bias voltage VBIAS1. The gate of the current mirror MP0 is connected to the bias voltage VBIAS2.

[0063] The output stage consists of load transistors MP1, MP2, MN6 and MN7, and cascode transistors MP3, MP4, MN8 and MN9. The gates of the load transistors MP1 and MP2 are connected to the bias voltage VBIAS2. The gates of the cascode transistors MP3 and MP4 are connected to the bias voltage VBIAS4. The gates of the cascode transistors MN8 and MN7 are connected to the bias voltage VBIAS3.

[0064] The drains of MP4 and MN9 are the output terminals of the transconductance amplifier Gm and are connected to the voltage VFB.

[0065] Although the present invention has been described in detail with general descriptions and specific embodiments above, based on the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of protection of the present invention.

Claims

1. A LDO loop compensation circuit with a wide output capacitance range, characterized in that: The LDO loop compensation circuit is composed of an LDO loop, a sampling circuit and a transconductance amplifier circuit, and specifically includes: The sampling circuit is composed of a power tube, a sampling tube, a current mirror and a capacitor. The output end of the sampling circuit and the output end of the LDO loop are respectively connected to the in-phase end and the inverting end of the transconductance amplifier. The output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path. A zero point related to the output capacitor is generated through the feedback path and loop compensation is performed on the output pole; Wherein, the transconductance amplifier circuit is a rail-to-rail folded common source and common gate structure, the rail-to-rail structure is composed of an input pair of tubes and a current mirror, and the output stage is composed of a load tube and a common source and common gate tube.

2. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 1, characterized in that: The sampling circuit is composed of a power tube, a sampling tube, a current mirror and a capacitor, and specifically includes: The sampling tube MN1 and the sampling tube MN2 are sampling tubes of the power tube MN0. The power tube MN0 is connected to the sampling tube MN1 and the sampling tube MN2 respectively. The sampling tube MN1 is connected to the current mirror MN3, and the sampling tube MN2 is connected to the current mirror MN4. The other ends of the current mirror MN3 and the current mirror MN4 are respectively connected to the capacitor C1 and grounded. The other end of the capacitor C1 is respectively connected to the voltage divider resistor R1 and the output end VO0 of the LDO loop.

3. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 2, characterized in that: The sampling tube MN1 and the sampling tube MN2 have the same width-to-length ratio, and the current mirror MN3 and the current mirror MN4 have the same width-to-length ratio.

4. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 3, characterized in that: The output end of the sampling circuit and the output end of the LDO loop are respectively connected to the in-phase end and the inverting end of the transconductance amplifier, specifically comprising: The output terminal VO1 of the sampling circuit is connected to the non-inverting terminal of the transconductance amplifier Gm, and the output terminal VO0 of the LDO loop is also connected to the inverting terminal of the transconductance amplifier Gm.

5. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 4, characterized in that: The output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path, which specifically includes: The output end of the transconductance amplifier is connected to the common end of the LDO voltage divider resistor R1 and the voltage divider resistor R2 through a feedback resistor R3.

6. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 5, characterized in that: The output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path, and further includes: By adding a feedback path, a zero point z1 related to the output capacitor is generated; Adjust the resistor R3 and transconductance g m3 The size of can adjust the position of the zero point and perform phase compensation on the LDO loop.

7. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 6, characterized in that: The transconductance amplifier circuit is a rail-to-rail folded common source and common gate structure, the rail-to-rail structure is composed of an input pair of tubes and a current mirror, and the output stage is composed of a load tube and a common source and common gate tube, specifically including: The gates of the input pair tubes MN10 and MP5 are the inverting input terminals of the transconductance amplifier Gm, connected to the voltage VO0, and the gates of the input pair tubes MN11 and MP6 are the non-inverting input terminals of the transconductance amplifier Gm, connected to the voltage VO1; The gate of the current mirror MN5 is connected to the bias voltage VBIAS1 , and the gate of the current mirror MP0 is connected to the bias voltage VBIAS2 .

8. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 7, characterized in that: The transconductance amplifier circuit is a rail-to-rail folded common source and common gate structure, the rail-to-rail structure is composed of an input pair of tubes and a current mirror, and the output stage is composed of a load tube and a common source and common gate tube, and specifically also includes: The output stage is composed of load tube MP1, load tube MP2, load tube MN6, load tube MN7 and cascode tube MP3, cascode tube MP4, cascode tube MN8, cascode tube MN9. The gates of load tubes MP1 and MP2 are connected to bias voltage VBIAS2, the gates of cascode tubes MP3 and MP4 are connected to bias voltage VBIAS4, and the gates of cascode tubes MN8 and MN7 are connected to bias voltage VBIAS3. The drains of the cascode transistors MP4 and MN9 are output terminals of the transconductance amplifier Gm, and are connected to the voltage VFB.

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