An LDO loop compensation circuit with a wide output capacitance range

Abstract

An embodiment of the present invention discloses an LDO loop compensation circuit with a wide output capacitance range. The embodiment of the present invention adds a sampling circuit and a transconductance amplifier circuit to the LDO output end, and the sampling circuit output end and the LDO output end are respectively connected to the in-phase and inverting ends of the transconductance amplifier; the output end of the transconductance amplifier is connected to the LDO feedback end through a feedback resistor. By adding the above-mentioned feedback path, a zero point related to the output capacitance is generated, and the output pole is loop-compensated to achieve the stability of the LDO loop. Compared with the loop compensation method of the left half plane zero point obtained by the parasitic ESR resistance of the output capacitor, the embodiment of the present invention can ensure the stability of a wide range of output capacitance without increasing transient overshoot. At the same time, the LDO loop has good stability and consistency.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of analog integrated circuits, and in particular to an LDO loop compensation circuit with a wide output capacitance range. Background Art

[0002] Low-dropout linear regulators (LDOs) are very important in the field of power management circuits. They have the characteristics of low voltage drop and low output noise, and have broad application prospects in the field of power supply for portable electronic products.

[0003] To achieve LDO loop stability, the output capacitor's parasitic ESR resistance creates a left-half-plane zero to compensate for the output pole. However, parasitic ESR presents two problems: first, it increases transient overshoot, degrading performance; second, it's uncontrollable, resulting in poor LDO loop stability consistency. Summary of the Invention

[0004] To this end, an embodiment of the present invention provides an LDO loop compensation circuit with a wide output capacitance range to solve the technical problem that the existing technology of performing pole loop compensation through parasitic ESR resistance will increase transient overshoot, resulting in performance degradation and poor loop stability.

[0005] In order to achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0006] According to a first aspect of an embodiment of the present invention, a LDO loop compensation circuit with a wide output capacitance range is provided. The LDO loop compensation circuit is composed of an LDO loop, a sampling circuit, and a transconductance amplifier circuit, and specifically includes:

[0007] The sampling circuit is composed of a power tube, a sampling tube, a current mirror and a capacitor. The output end of the sampling circuit and the output end of the LDO loop are respectively connected to the non-inverting end and the inverting end of the transconductance amplifier. The output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path.

[0008] A zero point related to the output capacitor is generated through the feedback path and loop compensation is performed on the output pole;

[0009] The transconductance amplifier circuit is a rail-to-rail folded cascode structure, the rail-to-rail structure is composed of an input pair of tubes and a current mirror, and the output stage is composed of a load tube and a cascode tube.

[0010] Furthermore, the sampling circuit is composed of a power tube, a sampling tube, a current mirror and a capacitor, and specifically includes:

[0011] Sampling tubes MN1 and MN2 are sampling tubes for power tube MN0. Power tube MN0 is connected to sampling tubes MN1 and MN2, respectively. Sampling tube MN1 is connected to current mirror MN3, and sampling tube MN2 is connected to current mirror MN4. The other ends of current mirrors MN3 and MN4 are respectively connected to capacitor C1 and grounded. The other end of capacitor C1 is respectively connected to voltage divider resistor R1 and output end VO0 of the LDO loop.

[0012] Furthermore, the sampling tube MN1 and the sampling tube MN2 have the same width-to-length ratio, and the current mirror MN3 and the current mirror MN4 have the same width-to-length ratio.

[0013] Furthermore, the output end of the sampling circuit and the output end of the LDO loop are respectively connected to the non-inverting end and the inverting end of the transconductance amplifier, specifically comprising:

[0014] The output terminal VO1 of the sampling circuit is connected to the non-inverting terminal of the transconductance amplifier Gm, and the output terminal VO0 of the LDO loop is also connected to the inverting terminal of the transconductance amplifier Gm.

[0015] Furthermore, the output end of the transconductance amplifier is connected to the feedback end of the LDO loop via a feedback resistor to form a feedback path, specifically including:

[0016] The output of the transconductance amplifier is connected to the common end of the LDO voltage divider resistors R1 and R2 through a feedback resistor R3.

[0017] Furthermore, the output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path, and further includes:

[0018] By adding a feedback path, a zero point z1 related to the output capacitor is generated;

[0019] Adjust the resistor R3 and transconductance g m3 The size of can be used to adjust the position of the zero point and perform phase compensation on the LDO loop.

[0020] Furthermore, the transconductance amplifier circuit is a rail-to-rail folded cascode structure, the rail-to-rail structure is composed of an input pair of transistors and a current mirror, and the output stage is composed of a load transistor and a cascode transistor, specifically including:

[0021] The gates of the input pair transistors MN10 and MP5 are the inverting input terminals of the transconductance amplifier Gm, and are connected to the voltage VO0. The gates of the input pair transistors MN11 and MP6 are the non-inverting input terminals of the transconductance amplifier Gm, and are connected to the voltage VO1.

[0022] The gate of the current mirror MN5 is connected to the bias voltage VBIAS1 , and the gate of the current mirror MP0 is connected to the bias voltage VBIAS2 .

[0023] Furthermore, the transconductance amplifier circuit is a rail-to-rail folded cascode structure, the rail-to-rail structure is composed of an input pair of transistors and a current mirror, and the output stage is composed of a load transistor and a cascode transistor, and specifically also includes:

[0024] The output stage is composed of load transistors MP1, MP2, MN6, MN7 and cascode transistors MP3, MP4, MN8, and MN9. The gates of load transistors MP1 and MP2 are connected to bias voltage VBIAS2, the gates of cascode transistors MP3 and MP4 are connected to bias voltage VBIAS4, and the gates of cascode transistors MN8 and MN7 are connected to bias voltage VBIAS3.

[0025] The drains of the cascode transistors MP4 and MN9 are output terminals of the transconductance amplifier Gm, and are connected to the voltage VFB.

[0026] The embodiments of the present invention have the following advantages:

[0027] In an embodiment of the present invention, a sampling circuit and a transconductance amplifier circuit are added to the output of the LDO. The output of the sampling circuit and the output of the LDO are connected to the in-phase and inverting terminals of the transconductance amplifier, respectively. The output of the transconductance amplifier is connected to the feedback terminal of the LDO via a feedback resistor. By adding the above-mentioned feedback path, a zero point related to the output capacitance is generated, and loop compensation is performed on the output pole, thereby achieving stability of the LDO loop. Compared with the loop compensation method using the left half plane zero point obtained by the parasitic ESR resistance of the output capacitor, the embodiment of the present invention can ensure the stability of a wide range of output capacitance without increasing transient overshoot. At the same time, the LDO loop has better stability and consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other implementation drawings based on the provided drawings without inventive effort.

[0029] The structures, proportions, sizes, etc. illustrated in this specification are intended only to complement the contents disclosed herein and to facilitate understanding and reading by persons familiar with the art. They are not intended to limit the conditions under which the present invention may be implemented and therefore have no substantive technical significance. Any structural modifications, changes in proportions, or adjustments in sizes, without affecting the efficacy and objectives of the present invention, shall still fall within the scope of the technical contents disclosed herein.

[0030] Figure 1 It is a circuit structure diagram of an existing LDO loop circuit;

[0031] Figure 2 A circuit structure diagram of an LDO loop compensation circuit with a wide output capacitance range provided by an embodiment of the present invention;

[0032] Figure 3 A circuit structure diagram of a transconductance amplifier Gm of an LDO loop compensation circuit with a wide output capacitance range provided by an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of the amplitude-frequency and phase-frequency curves of the LDO output pole (without compensation zero) in an LDO loop compensation circuit with a wide output capacitance range provided by an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of the amplitude-frequency and phase-frequency curves of the LDO output pole (with compensation zero point) in an LDO loop compensation circuit with a wide output capacitance range provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following describes the implementation of the present invention using specific embodiments. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. Obviously, the embodiments described are only a portion of the present invention, not all of it. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are intended to fall within the scope of protection of the present invention.

[0036] A low-dropout linear regulator (LDO) using an NMOS transistor as the power transistor generates a primary pole, P1, at the error amplifier output and a secondary pole, P2, at the power transistor output. Under light loads, if the output capacitance is large, the secondary pole will fall within the unity-gain bandwidth, affecting loop stability and even causing output oscillation.

[0037] refer to Figure 1To achieve LDO loop stability, the output capacitor's parasitic ESR resistance creates a left-half-plane zero to compensate for the output pole. However, parasitic ESR presents two problems. First, it increases transient overshoot, degrading performance. Second, parasitic ESR resistance is uncontrollable, resulting in poor LDO loop stability consistency.

[0038] In order to solve the technical problem that the above-mentioned method of performing pole loop compensation through parasitic ESR resistance will increase transient overshoot, resulting in performance degradation and poor loop stability.

[0039] refer to Figure 2 The embodiment of the present invention discloses an LDO loop compensation circuit with a wide output capacitance range. The LDO loop compensation circuit is composed of an LDO loop, a sampling circuit, and a transconductance amplifier circuit, and specifically includes:

[0040] The sampling circuit is composed of a power tube, a sampling tube, a current mirror and a capacitor. The output end of the sampling circuit and the output end of the LDO loop are respectively connected to the non-inverting end and the inverting end of the transconductance amplifier. The output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path.

[0041] The feedback path generates a zero related to the output capacitance and performs loop compensation on the output pole.

[0042] The transconductance amplifier circuit is a rail-to-rail folded cascode structure, the rail-to-rail structure is composed of an input pair of tubes and a current mirror, and the output stage is composed of a load tube and a cascode tube.

[0043] Furthermore, the sampling circuit is composed of a power tube, a sampling tube, a current mirror and a capacitor, specifically including: sampling tube MN1 and sampling tube MN2 are sampling tubes of the power tube MN0, the power tube MN0 is connected to the sampling tube MN1 and the sampling tube MN2 respectively, the sampling tube MN1 is connected to the current mirror MN3, the sampling tube MN2 is connected to the current mirror MN4, the other ends of the current mirror MN3 and the current mirror MN4 are respectively connected to the capacitor C1 and grounded, and the other end of the capacitor C1 is respectively connected to the voltage divider resistor R1 and the output end VO0 of the LDO loop.

[0044] Furthermore, the sampling tube MN1 and the sampling tube MN2 have the same width-to-length ratio, and the current mirror MN3 and the current mirror MN4 have the same width-to-length ratio.

[0045] Furthermore, the output end of the sampling circuit and the output end of the LDO loop are respectively connected to the non-inverting end and the inverting end of the transconductance amplifier, specifically comprising:

[0046] The output terminal VO1 of the sampling circuit is connected to the non-inverting terminal of the transconductance amplifier Gm, and the output terminal VO0 of the LDO loop is also connected to the inverting terminal of the transconductance amplifier Gm.

[0047] Furthermore, the output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path, specifically including: the output end of the transconductance amplifier is connected to the common end of the LDO voltage divider resistor R1 and the voltage divider resistor R2 through a feedback resistor R3.

[0048] The LDO output sampling circuit consists of MN1, MN2, MN3, MN4, current mirror I1 and capacitor C C Among them, MN1 and MN2 are sampling tubes of power tube MN0. MN1 and MN2 have the same width-to-length ratio. The transconductance of MN2 is g m2 MN3 and MN4 are current mirrors, and their width to length ratio is the same. The sampling circuit output terminal VO1 and the LDO output terminal VO0 are connected to the in-phase and inverting terminals of the transconductance amplifier Gm respectively. The transconductance of the transconductance amplifier Gm is g m3 The output of the transconductance amplifier is connected to the common terminal of the LDO voltage divider resistors R1 and R2 through a feedback resistor R3.

[0049] V EA2 to V FB The transfer function is shown below:

[0050]

[0051] Analyzing the above transfer function, we can obtain a left-half-plane zero z1 related to the output capacitance:

[0052]

[0053] By adding the above feedback path, a zero point z1 related to the output capacitor is generated, which compensates the output pole. m3 The size of can adjust the position of the zero point, perform phase compensation on the loop, and achieve the stability of the LDO loop.

[0054] For example, when C O =10uF,g mp =1mS,g m3 =25uS, R3=4kΩ, R1=R2=10kΩ, the output pole is:

[0055]

[0056] When LDO has no zero point z1, the output extreme amplitude-frequency and phase-frequency curves are as follows: Figure 4 As shown, the maximum phase shift is -89.43°.

[0057] When LDO contains zero point z1, the output pole and zero point z1 amplitude-frequency and phase-frequency curves are as follows: Figure 5 As shown in Figure 1, the maximum phase shift is -41.76°, and the zero point z1 performs loop compensation on the output pole.

[0058] Furthermore, the output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path, and further comprises: generating a zero point z1 related to the output capacitance by adding a feedback path; adjusting the resistor R3 and the transconductance g m3 The size of can be used to adjust the position of the zero point and perform phase compensation on the LDO loop.

[0059] Further, refer to Figure 3 The transconductance amplifier circuit is a rail-to-rail folded cascode structure. The rail-to-rail structure consists of an input pair of transistors and a current mirror. The output stage consists of a load transistor and a cascode transistor. Specifically, the gates of the input pair of transistors MN10 and MP5 are the inverting input terminals of the transconductance amplifier Gm and are connected to the voltage VO0. The gates of the input pair of transistors MN11 and MP6 are the non-inverting input terminals of the transconductance amplifier Gm and are connected to the voltage VO1. The gate of the current mirror MN5 is connected to the bias voltage VBIAS1, and the gate of the current mirror MP0 is connected to the bias voltage VBIAS2.

[0060] Furthermore, the transconductance amplifier circuit is a rail-to-rail folded cascode structure, the rail-to-rail structure is composed of an input pair of tubes and a current mirror, and the output stage is composed of a load tube and a cascode tube. Specifically, the output stage is composed of a load tube MP1, a load tube MP2, a load tube MN6, a load tube MN7 and a cascode tube MP3, a cascode tube MP4, a cascode tube MN8, and a cascode tube MN9, the gates of the load tubes MP1 and MP2 are connected to a bias voltage VBIAS2, the gates of the cascode tubes MP3 and MP4 are connected to a bias voltage VBIAS4, and the gates of the cascode tubes MN8 and MN7 are connected to a bias voltage VBIAS3.

[0061] The drains of the cascode transistors MP4 and MN9 are output terminals of the transconductance amplifier Gm, and are connected to the voltage VFB.

[0062] The transconductance amplifier Gm uses a rail-to-rail folded cascode structure to achieve rail-to-rail input, meeting the low-dropout voltage requirements of low-dropout linear regulators. This rail-to-rail input structure consists of the input transistors MN10, MN11, MP5, and MP6, and the current mirrors MN5 and MP0. The gates of MN10 and MP5 serve as the inverting inputs of the transconductance amplifier Gm and are connected to voltage VO0. The gates of MN11 and MP6 serve as the non-inverting inputs of the transconductance amplifier Gm and are connected to voltage VO1. The gate of current mirror MN5 is connected to bias voltage VBIAS1. The gate of current mirror MP0 is connected to bias voltage VBIAS2.

[0063] The output stage consists of load transistors MP1, MP2, MN6, and MN7, and cascode transistors MP3, MP4, MN8, and MN9. The gates of load transistors MP1 and MP2 are connected to bias voltage VBIAS2. The gates of cascode transistors MP3 and MP4 are connected to bias voltage VBIAS4. The gates of cascode transistors MN8 and MN7 are connected to bias voltage VBIAS3.

[0064] The drains of MP4 and MN9 are the output terminals of the transconductance amplifier Gm, and are connected to the voltage VFB.

[0065] Although the present invention has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications and improvements may be made thereto. Therefore, such modifications and improvements, without departing from the spirit of the present invention, are intended to be within the scope of protection claimed herein.

Claims

1. An LDO loop compensation circuit with a wide output capacitance range, characterized in that: The LDO loop compensation circuit is composed of an LDO loop, a sampling circuit, and a transconductance amplifier circuit, and specifically includes: The sampling circuit is composed of a power tube, a sampling tube, a current mirror and a capacitor. The output end of the sampling circuit and the output end of the LDO loop are respectively connected to the non-inverting end and the inverting end of the transconductance amplifier. The output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path. A zero point related to the output capacitor is generated through the feedback path and loop compensation is performed on the output pole; The transconductance amplifier circuit is a rail-to-rail folded cascode structure, the rail-to-rail structure is composed of an input pair of tubes and a current mirror, and the output stage is composed of a load tube and a cascode tube.

2. The LDO loop compensation circuit with a wide output capacitance range according to claim 1, wherein: The sampling circuit is composed of a power tube, a sampling tube, a current mirror and a capacitor, and specifically includes: Sampling tubes MN1 and MN2 are sampling tubes for power tube MN0. Power tube MN0 is connected to sampling tubes MN1 and MN2, respectively. Sampling tube MN1 is connected to current mirror MN3, and sampling tube MN2 is connected to current mirror MN4. The other ends of current mirrors MN3 and MN4 are respectively connected to capacitor C1 and grounded. The other end of capacitor C1 is respectively connected to voltage divider resistor R1 and output end VO0 of the LDO loop.

3. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 2, wherein: The sampling tube MN1 and the sampling tube MN2 have the same width-to-length ratio, and the current mirror MN3 and the current mirror MN4 have the same width-to-length ratio.

4. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 3, wherein: The output end of the sampling circuit and the output end of the LDO loop are respectively connected to the non-inverting end and the inverting end of the transconductance amplifier, specifically comprising: The output terminal VO1 of the sampling circuit is connected to the non-inverting terminal of the transconductance amplifier Gm, and the output terminal VO0 of the LDO loop is also connected to the inverting terminal of the transconductance amplifier Gm.

5. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 4, wherein: The output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path, which specifically includes: The output of the transconductance amplifier is connected to the common end of the LDO voltage divider resistors R1 and R2 through a feedback resistor R3.

6. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 5, wherein: The output end of the transconductance amplifier is connected to the feedback end of the LDO loop through a feedback resistor to form a feedback path, and further includes: By adding a feedback path, a zero point z1 related to the output capacitor is generated; Adjust the resistor R3 and transconductance g m3 The size of can be used to adjust the position of the zero point and perform phase compensation on the LDO loop.

7. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 6, wherein: The transconductance amplifier circuit is a rail-to-rail folded cascode structure, which is composed of an input pair of transistors and a current mirror, and an output stage composed of a load transistor and a cascode transistor, specifically including: The gates of the input pair transistors MN10 and MP5 are the inverting input terminals of the transconductance amplifier Gm, and are connected to the voltage VO0. The gates of the input pair transistors MN11 and MP6 are the non-inverting input terminals of the transconductance amplifier Gm, and are connected to the voltage VO1. The gate of the current mirror MN5 is connected to the bias voltage VBIAS1 , and the gate of the current mirror MP0 is connected to the bias voltage VBIAS2 .

8. The LDO loop compensation circuit with a wide output capacitance range as claimed in claim 7, wherein: The transconductance amplifier circuit is a rail-to-rail folded cascode structure, which is composed of an input pair of transistors and a current mirror, and an output stage composed of a load transistor and a cascode transistor, and specifically includes: The output stage is composed of load transistors MP1, MP2, MN6, MN7 and cascode transistors MP3, MP4, MN8, and MN9. The gates of load transistors MP1 and MP2 are connected to bias voltage VBIAS2, the gates of cascode transistors MP3 and MP4 are connected to bias voltage VBIAS4, and the gates of cascode transistors MN8 and MN7 are connected to bias voltage VBIAS3. The drains of the cascode transistors MP4 and MN9 are output terminals of the transconductance amplifier Gm, and are connected to the voltage VFB.

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