Low-voltage-difference linear voltage stabilizing circuit

Abstract

The invention belongs to the technical field of LDO circuits, and particularly relates to a low-voltage-difference linear voltage stabilizing circuit which comprises a voltage division circuit connected with a VEE end, a phase inverter, a current stabilizing circuit and a Q12 tube connected with a Vreg end. Compared with a traditional low-voltage linear voltage stabilizing circuit, the stability that the output voltage changes along with the input voltage is improved; an anti-phase structure and NMOS tube output are adopted, so that the impedance of a radio frequency signal is infinite, and the characteristics of rectification and stabilization are also achieved; at high and low temperatures, the voltage output of the circuit is very stable, and the stability of the output voltage is further guaranteed when the circuit is matched with a specific radio frequency circuit. According to the low-voltage linear voltage stabilizing circuit, the problem that the output voltage changes greatly along with the input voltage is solved under the small static working current; when the radio frequency power amplifier works normally, the problem that the output voltage is unstable due to temperature change is solved, and the stability of the low-voltage linear voltage stabilizing circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of LDO circuits, and particularly to a low dropout linear voltage regulator circuit. Background Art

[0002] As Figure 2 shown, the basic composition structure of a traditional LDO. The circuit adopts the closed-loop feedback principle of an operational amplifier to maintain the stability of the output voltage under different loads. This structure consists of a bandgap reference voltage source, an error amplifier, a power transistor, and feedback. The working principle is that when the load changes, the output voltage decreases, the feedback voltage decreases, the gate voltage of the power transistor decreases, but the source-gate voltage increases, and the drain current increases accordingly to increase the output voltage, suppress the decrease of the output voltage, and ensure the stability of the output voltage.

[0003] With the rapid development of semiconductor technology, the integration degree of chips is getting higher and higher, and the requirements for the volume and performance of the power management module are also getting higher and higher. Companies at home and abroad are becoming more and more focused on the research of high-performance low dropout linear voltage regulator circuits without external capacitors. By comparing data, it can be found that there is a large gap between domestic LDO products without external capacitors and foreign ones. Summary of the Invention

[0004] The purpose of the present invention is to provide a low dropout linear voltage regulator circuit to solve the problems raised in the above background art.

[0005] To achieve the above purpose, the present invention provides the following technical solution: A low dropout linear voltage regulator circuit, comprising:

[0006] A voltage dividing circuit, an inverter, a current stabilizing circuit connected to the VEE terminal, and a Q12 transistor connected to the Vreg terminal;

[0007] Wherein, the voltage dividing circuit is connected to the inverter, the inverter is connected to the current stabilizing circuit, and the current stabilizing circuit is connected to the Vreg terminal based on the Q12 transistor.

[0008] Preferably, the voltage dividing circuit includes resistors R1, R2, and R3. One end of the resistor R1 is connected to the VEE terminal, the other end of the resistor R1 is connected to the resistors R2 and R3, the other end of the resistor R3 is grounded, and the other end of the resistor R2 is connected to the inverter.

[0009] Preferably, the inverter includes transistors Q1 and Q2. The other end of the resistor R2 is connected to the transistor Q1, the transistor Q1 is connected to the transistor Q2, and resistors R4 and R5 are respectively connected to the transistors Q1 and Q2. The other ends of the resistors R4 and R5 are connected to the VDD terminal, the transistors Q1 and Q2 are grounded, and the transistors Q1, Q2 are connected to the transistor Q3.

[0010] Preferably, the steady current circuit includes transistors Q4, Q5, Q6, Q7 and Q8. Transistor Q3 is connected to one end of resistor R6, one end of resistor R7, one end of resistor R8, one end of resistor R9 and transistor Q9. Transistor Q9 is connected to transistor Q12, and transistor Q12 is externally connected to the Vreg terminal. The other end of resistor R6 is connected to transistor Q4, and transistor Q4 is connected to transistor Q7, one end of resistor R7, one end of resistor R8, one end of resistor R9 and transistor Q9. Transistor Q7 is connected to transistor Q5, one end of resistor R10 and transistor Q8. The other end of resistor R10 is grounded. Transistor Q5 is connected to resistors R7 and R8. The other end of resistor R9 is connected to transistor Q6 and transistor Q9. Transistor Q6 is connected to transistor Q8, and transistor Q8 is connected to resistor R10.

[0011] Preferably, it further includes diodes D1 and D2. The positive electrode of diode D1 is connected to resistor R6, and the positive electrode of diode D2 is connected to transistor Q4. The negative electrodes of diodes D1 and D2 are grounded.

[0012] Preferably, transistor Q8 is externally connected to resistors R11 and R12. The other end of resistor R12 is grounded, and the other end of resistor R11 is connected to transistor Q9.

[0013] Preferably, a resistor R12 is connected in parallel between resistors R1 and R2. Resistor R12 is connected to transistor Q10, and transistor Q10 is connected to resistors R13 and R15. The other end of resistor R13 is connected to transistor Q12, and the other end of resistor R15 is connected to transistor Q11. Transistor Q11 is connected to resistor R14, and the other end of resistor R14 is connected to transistor Q12.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0015] Compared with the traditional low-voltage linear voltage regulator circuit, the present invention increases the stability of the output voltage with respect to the change in the input voltage; by adopting an inverting structure and an NMOS transistor output, it not only has an infinite impedance for radio frequency signals but also exhibits rectifying and stabilizing characteristics; at high and low temperatures, the voltage output of this circuit is also very stable, and when cooperating with a specific radio frequency circuit, the stability of the output voltage is further ensured.

[0016] The present invention is a low-voltage linear voltage regulator circuit, which overcomes the problem of large variation in the output voltage with respect to the change in the input voltage at a relatively small quiescent current; when the radio frequency power amplifier is operating normally, it solves the problem of unstable output voltage caused by temperature changes, and improves the stability of the low-voltage linear voltage regulator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is the low-dropout linear voltage regulator circuit diagram of the present invention;

[0018] Figure 2 It is a circuit diagram of a traditional LDO;

[0019] Figure 3 It is the current simulation diagram of the present invention;

[0020] Figure 4 It is the simulation diagram of the output voltage of the present invention varying with the input voltage;

[0021] Figure 5 It is the simulation diagram of the output voltage of the present invention varying with temperature. Specific embodiments

[0022] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0024] Analysis of the existing LDO circuit: The bandgap reference source is generally a reference voltage, which is not affected by factors such as power supply voltage, temperature, and process; this circuit uses the base-emitter voltage V of a bipolar transistor with a negative temperature coefficient BE and the base-emitter voltage difference ΔV with a positive temperature coefficient BE to form.

[0025] The main function of the error amplifier is negative feedback. It compares the feedback voltage VFB with the bandgap reference voltage VREF, and transmits the output to the gate terminal of the power transistor to change the magnitude of the drain current of the power transistor, thereby achieving the function of stabilizing the voltage.

[0026] The feedback network is mainly resistor voltage division, which determines the ratio between the output voltage and the reference voltage value of the LDO.

[0027] The challenges faced in the design of a low-dropout linear voltage regulator circuit are to maintain the stability of the loop under different load conditions and achieve fast transient response without a large capacitor on the chip. A smaller static current means a longer service life, but it will slow down the transient response speed of the circuit. These are closely related to the characteristics of the basic building blocks of the LDO.

[0028] Embodiment 1:

[0029] Please refer to Figures 1-5 , the present invention provides a technical solution: a low dropout linear voltage regulator circuit, including: a voltage dividing circuit connected to the VEE terminal, an inverter, a current stabilizing circuit, and a Q12 transistor connected to the Vreg terminal; wherein, the voltage dividing circuit is connected to the inverter, the inverter is connected to the current stabilizing circuit, and the current stabilizing circuit is connected to the Vreg terminal based on the Q12 transistor.

[0030] The voltage dividing circuit includes resistors R1, R2, and R3. One end of the resistor R1 is connected to the VEE terminal, the other end of the resistor R1 is connected to the resistors R2 and R3, the other end of the resistor R3 is grounded, and the other end of the resistor R2 is connected to the inverter. The inverter includes transistors Q1 and Q2. The other end of the resistor R2 is connected to the transistor Q1, the transistor Q1 is connected to the transistor Q2, and resistors R4 and R5 are respectively connected to the transistors Q1 and Q2. The other ends of the resistors R4 and R5 are connected to the VDD terminal, the transistors Q1 and Q2 are grounded, and the transistors Q1, Q2 are connected to the transistor Q3. The current stabilizing circuit includes transistors Q4, Q5, Q6, Q7, and Q8. The transistor Q3 is connected to one end of a resistor R6, one end of a resistor R7, one end of a resistor R8, one end of a resistor R9, and a transistor Q9. The transistor Q9 is connected to the transistor Q12. The transistor Q12 is externally connected to the Vreg terminal. The other end of the resistor R6 is connected to the transistor Q4. The transistor Q4 is connected to the transistor Q7, one end of the resistor R7, one end of the resistor R8, one end of the resistor R9, and the transistor Q9. The transistor Q7 is connected to the transistor Q5, one end of a resistor R10, and the transistor Q8. The other end of the resistor R10 is grounded. The transistor Q5 is connected to the resistors R7 and R8. The other end of the resistor R9 is connected to the transistors Q6 and Q9. The transistor Q6 is connected to the transistor Q8. The transistor Q8 is connected to the resistor R10. It also includes diodes D1 and D2. The positive electrode of the diode D1 is connected to the resistor R6. The positive electrode of the diode D2 is connected to the transistor Q4. The negative electrodes of the diodes D1 and D2 are grounded. The transistor Q8 is externally connected to resistors R11 and R12. The other end of the resistor R12 is grounded. The other end of the resistor R11 is connected to the transistor Q9.

[0031] A resistor R12 is connected in parallel between the resistors R1 and R2. The resistor R12 is connected to a transistor Q10. The transistor Q10 is connected to resistors R13 and R15. The other end of the resistor R13 is connected to the transistor Q12. The other end of the resistor R15 is connected to a transistor Q11. The transistor Q11 is connected to a resistor R14. The other end of the resistor R14 is connected to the transistor Q12.

[0032] Input section: Input from the VEE on the left side, passing through the voltage-dividing network composed of R1, R2, and R3 and Q1, may be a signal input and preprocessing circuit for adjusting the input signal to an appropriate level range for subsequent circuit processing.

[0033] Intermediate processing section: Multiple transistors (such as Q3 - Q8) in the intermediate part are interconnected with resistors and diodes to form a complex amplification and processing circuit. Q3, Q4, etc. are used to increase the signal gain and suppress common-mode interference; while Q5 - Q8 provide a stable current or voltage reference for the subsequent circuit.

[0034] Output section: The circuit composed of components such as Q9 - Q12 on the right side finally outputs a stable voltage Vreg to provide a stable power supply for other circuit modules.

[0035] Analysis of the above content: The specific circuit connection method of this solution, as Figure 1 shown, overcomes the instability of the output voltage and balances the static current and transient response time. VEE is the logic control voltage with a supply magnitude of 1.6V, and VDD is the supply voltage of 1.8V;

[0036] Resistor R1 and resistor R3 are in a voltage-dividing structure to control the output magnitude of the logic voltage;

[0037] An inverter structure composed of Q1 tube and Q2 tube is adopted. The Gate terminal voltage of Q2 tube is relatively low, and the Drain terminal voltage is at a high potential. NMOS Q3 outputs a stable voltage.

[0038] Two diodes, diode D1 and diode D2, play the roles of rectification and voltage stabilization.

[0039] Q5 tube and Q6 tube, Q7 tube and Q8 tube are symmetrically distributed to provide a stable current output.

[0040] In addition, resistor R10 has an impact on the output voltage by voltage division. The smaller its resistance value, the smaller the output voltage of VREG, and the smaller the change in the output voltage with the change of VDD voltage; conversely, the voltage stability will be affected. Therefore, a balance needs to be made between the two.

[0041] The voltage division of resistor R11 and resistor R12 affects the magnitude of the output voltage. In order to make the working current of this circuit smaller, not only the sizes of all nmos tubes are selected to be smaller, but also the resistance values of the resistors should be in the high resistance range of kiloohms.

[0042] The output voltage is finally converted from Q9 tube to Q12 tube output. It is a voltage stabilization structure composed of Q10 tube, Q11 tube, resistor R13, resistor R14, and resistor R15, which further stabilizes the voltage output.

[0043] As Figure 3As shown, it is a current simulation diagram. In the figure, m2 is the mark point 2. When VDD is 1.8V and the temperature is 25°C, the measured value of I_VDD is 439.2uA.

[0044] As Figure 4 shown, it is a simulation diagram of the output voltage varying with the input voltage. In the figure, m1 is the mark point 1. When the temperature is 25°C and the input voltage changes from 2V - 1.8V - 1.6V in sequence, the magnitudes of the output voltage Vreg are 0.884V, 0.873V, and 0.846V respectively. When the input voltage changes to 0.4V, the change in the output voltage difference is only less than 40mV.

[0045] As Figure 5 shown, it is a simulation diagram of the output voltage varying with the temperature. In the figure, it is a simulation diagram of the output voltage varying with the temperature when the input voltage is constant. From the low temperature of -40°C to the high temperature of 150°C, the change in the output voltage is only 1mV.

[0046] Compared with the traditional low - voltage linear voltage - regulating circuit, this solution improves the stability of the output voltage varying with the input voltage; adopting an inverting structure and NMOS - tube output not only has an infinite impedance for radio - frequency signals but also has rectifying and stabilizing characteristics; at high and low temperatures, the voltage output of this circuit is also very stable. When cooperating with a specific radio - frequency circuit, the stability of the output voltage is further guaranteed. This solution overcomes the problem that the output voltage varies greatly with the input voltage at a relatively small quiescent current; when the radio - frequency power amplifier is working normally, it solves the problem of unstable output voltage caused by temperature changes and improves the stability of the low - voltage linear voltage - regulating circuit.

[0047] The above shows and describes the basic principles, main features, and advantages of the present invention. For those skilled in the art, it is obvious that the present invention is not limited to the details of the above - mentioned exemplary embodiments, and without departing from the spirit or basic features of the present invention, the present invention can be implemented in other specific forms; therefore, from any point of view, the embodiments should be regarded as exemplary and non - restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed within the present invention, and any reference signs in the claims should not be regarded as limiting the claims involved.

[0048] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A low voltage difference linear voltage regulator circuit, characterized in that: include: A voltage divider circuit, an inverter, a current stabilization circuit connected to the VEE terminal, and a Q12 tube connected to the Vreg terminal; The voltage divider circuit is connected to an inverter, the inverter is connected to a current stabilizing circuit, and the current stabilizing circuit is connected to a Vreg terminal based on a Q12 tube.

2. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The voltage divider circuit includes resistors R1, R2, and R3. One end of the resistor R1 is connected to the VEE end, the other end of the resistor R1 is connected to resistors R2 and R3, the other end of the resistor R3 is grounded, and the other end of the resistor R2 is connected to the inverter.

3. The low voltage difference linear voltage regulator circuit according to claim 2, characterized in that: The inverter includes a Q1 tube and a Q2 tube, the other end of the resistor R2 is connected to the Q1 tube, the Q1 tube is connected to the Q2 tube, and the Q1 tube and the Q2 tube are respectively connected to resistors R4 and R5, the other ends of the resistors R4 and R5 are connected to the VDD end, the Q1 tube and the Q2 tube are grounded, and the Q1 tube, the Q2 tube and the Q3 tube are connected.

4. The low voltage difference linear voltage regulator circuit according to claim 3, characterized in that: The current stabilization circuit includes Q4, Q5, Q6, Q7 and Q8. The Q3 is connected to one end of the resistor R6, one end of the resistor R7, one end of the resistor R8, one end of the resistor R9 and the Q9. The Q9 is connected to the Q12. The Q12 is externally connected to the Vreg end. The other end of the resistor R6 is connected to the Q4. The Q4 is connected to the Q7, one end of the resistor R7, one end of the resistor R8, one end of the resistor R9 and the Q9. The Q7 is connected to the Q5, one end of the resistor R10 and the Q8. The other end of the resistor R10 is grounded. The Q5 is connected to the resistors R7 and R8. The other end of the resistor R9 is connected to the Q6 and Q9. The Q6 is connected to the Q8. The Q8 is connected to the resistor R10.

5. The low voltage difference linear voltage regulator circuit according to claim 4, characterized in that: It also includes diodes D1 and D2, wherein the anode of the diode D1 is connected to the resistor R6, the anode of the diode D2 is connected to the Q4 tube, and the cathodes of the diodes D1 and D2 are grounded.

6. The low voltage difference linear voltage regulator circuit according to claim 4, characterized in that: The Q8 tube is externally connected to resistors R11 and R12, the other end of the resistor R12 is grounded, and the other end of the resistor R11 is connected to the Q9 tube.

7. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: A resistor R12 is connected in parallel between the resistors R1 and R2, the resistor R12 is connected to the Q10 tube, the Q10 tube is connected to the resistors R13 and R15, the other end of the resistor R13 is connected to the Q12 tube, the other end of the resistor R15 is connected to the Q11 tube, the Q11 tube is connected to the resistor R14, and the other end of the resistor R14 is connected to the Q12 tube.

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