Read-write conversion circuit and memory
By designing a read-write conversion circuit with variable read-write operation speed in DRAM, the problem of fixed read-write operation speed of existing DRAM is solved, and flexible performance adjustment and power consumption optimization are achieved.
Patent Information
- Application Number
- CN202510273956.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2020-06-05
- Publication Date
- 2025-06-20
AI Technical Summary
The read and write operation speed of existing DRAM is fixed, which is difficult to meet the read and write performance requirements in different scenarios, and it consumes a lot of power during high-speed read and write operations.
A read-write conversion circuit is designed, including a read-write conversion module and a control module. The control module outputs variable read-write control signals in response to the read-write speed configuration signal, so that the read-write operation speed of the read-write conversion module is variable.
It realizes the configurability of read and write operation speed, is suitable for scenarios with different performance requirements, avoids unnecessary power consumption and improves memory performance.
Smart Images
Figure CN120179172A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor technologies, and in particular, to a read-write conversion circuit and a memory. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in a computer and consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor through the bit line for storage.
[0003] DRAM can be divided into Double Data Rate (DDR) dynamic random access memory, GDDR (Graphics Double Data Rate) dynamic random access memory, and Low Power Double Data Rate (LPDDR) dynamic random access memory. As DRAM is applied in more and more fields, such as more and more applications in the mobile field, users' requirements for the power consumption index of DRAM are getting higher and higher.
[0004] However, the current performance of DRAM still needs to be improved. Summary of the Invention
[0005] The technical problem solved by the embodiments of the present invention is to provide a read-write conversion circuit and a memory, so that the speed of the read-write operation of the read-write conversion circuit is variable, thereby improving the performance of the memory.
[0006] To solve the above problems, an embodiment of the present invention provides a read-write conversion circuit, which is characterized by including: a read-write conversion module that responds to a read-write control signal to perform a read-write operation; a control module that responds to a read-write speed configuration signal to output the variable read-write control signal to control the speed of the read-write operation of the read-write conversion module to be variable.
[0007] In addition, it further includes: a speed configuration module connected to the control module for outputting the read-write speed configuration signal to the control module.
[0008] In addition, the read-write control signal includes a read control signal and a write control signal. The read-write conversion module responds to the read control signal to perform a read operation and responds to the write control signal to perform a write operation. The speed configuration module includes: a read speed configuration unit for outputting the read speed configuration signal in the read-write speed configuration signal to the control module, so that the control module outputs a variable read control signal in response to the read speed configuration signal to control the variable speed of the read operation; a write speed configuration unit for outputting the write speed configuration signal in the read-write speed configuration signal to the control module, so that the control module outputs a variable write control signal in response to the read speed configuration signal to control the variable speed of the write operation.
[0009] In addition, it further includes: a local data line, a local complementary data line, and a global data line. During the read-write operation, data is transmitted between the local data line and the local complementary data line and the global data line, and the data signals of the local data line and the local complementary data line are opposite in phase.
[0010] In addition, the read-write conversion module includes: a local read-write unit that responds to the local read-write control signal in the read-write control signal to perform a local read-write operation; the control module includes: a local control unit that responds to the local read-write speed configuration signal in the read-write speed configuration signal to output a variable local read-write control signal to control the variable speed of the local read-write operation of the local read-write unit.
[0011] In addition, the read-write conversion circuit further includes: a local speed configuration module connected to the local control unit for outputting the local read-write speed configuration signal to the local control unit.
[0012] In addition, the read-write conversion circuit further includes: a sense amplifier. The sense amplifier is connected to the local read-write unit via the local data line and the local complementary data line for sensing the bit line voltage.
[0013] In addition, the same local read-write unit is connected to a plurality of the sense amplifiers via the local data line and the local complementary data line.
[0014] In addition, the write data path includes: from the local read-write unit through the local data line and the local complementary data line to the sense amplifier, and then via the sense amplifier to the bit line; the read data path includes: from the bit line through the sense amplifier to the local data line and the local complementary data line, and then via the local data line and the local complementary data line to the local read-write unit.
[0015] In addition, the read-write conversion module includes: a global read-write unit that responds to the global read-write control signal in the read-write control signal to perform global read-write operations; the control module includes: a global control unit that responds to the global read-write speed configuration signal in the read-write speed configuration signal to output the variable global read-write control signal to control the variable speed of the global read-write operations of the global read-write unit.
[0016] In addition, the read-write conversion circuit further includes: a global speed configuration module connected to the global control unit for outputting the global read-write speed configuration signal to the global control unit.
[0017] In addition, the local read-write unit includes: a local amplifier connected between the local data line and the local complementary data line for amplifying the data on the local data line and the data on the local complementary data line.
[0018] In addition, the local amplifier includes: a first inverter, the input terminal of the first inverter is electrically connected to the local data line, and the output terminal of the first inverter is electrically connected to the local complementary data line; a second inverter, the input terminal of the second inverter is electrically connected to the output terminal of the first inverter and the local complementary data line, and the output terminal of the second inverter is electrically connected to the input terminal of the first inverter and the local data line.
[0019] In addition, the first inverter includes: a first PMOS transistor and a first NMOS transistor, the gates of the first PMOS transistor and the first NMOS transistor are connected and used as the input terminal of the first inverter, the source of the first PMOS transistor is connected to the working power supply, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and used as the output terminal of the first inverter; the second inverter includes: a zero-th PMOS transistor and a zero-th NMOS transistor, the gates of the zero-th PMOS transistor and the zero-th NMOS transistor are connected and used as the input terminal of the second inverter, the source of the zero-th PMOS transistor is connected to the working power supply, and the drain of the zero-th PMOS transistor is connected to the drain of the zero-th NMOS transistor and used as the output terminal of the second inverter.
[0020] In addition, the local read / write unit includes a local read conversion circuit, which is configured to transfer the data on the local data line and the local complementary data line to the global data line in response to the local read control signal in the local read / write control signal; the local read conversion circuit includes: a third NMOS transistor and a fourth NMOS transistor; the drain of the third NMOS transistor is connected to the global data line, the gate of the third NMOS transistor is connected to the local complementary data line, and the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; the gate of the fourth NMOS transistor receives the local read signal in the local read / write control signal, and the source is grounded.
[0021] In addition, the read / write conversion circuit further includes: a global complementary data line, and during the read operation, the data signal phases of the global complementary data line and the global data line are opposite; the local read conversion circuit further includes: an eighth NMOS transistor and a ninth NMOS transistor; the drain of the eighth NMOS transistor is connected to the global complementary data line, the gate of the eighth NMOS transistor is connected to the local data line, and the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; the gate of the ninth NMOS transistor receives the local read signal, and the source is grounded.
[0022] In addition, the local read / write unit includes: a local write conversion circuit, which is configured to transfer the data on the global data line to the local data line and the local complementary data line in response to the local write control signal in the local read / write control signal; the local write conversion circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; the drain of the fifth NMOS transistor is connected to the local complementary data line, the gate of the fifth NMOS transistor is connected to the source of the seventh NMOS transistor, and the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor receives the local write signal in the local read / write control signal, and the source is grounded; the drain of the seventh NMOS transistor is connected to the local data line, and the gate receives the local write signal.
[0023] In addition, the read / write conversion circuit further includes: a global complementary data line, and during the read / write operation, the data signal phase of the global complementary data line is opposite to that of the global data line; the local write conversion circuit further includes: a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; the drain of the tenth NMOS transistor is connected to the local data line, the gate of the tenth NMOS transistor is connected to the source of the twelfth NMOS transistor and is connected to the global complementary data line, and the source of the tenth NMOS transistor is connected to the drain of the eleventh NMOS transistor; the gate of the eleventh NMOS transistor receives the local write signal, and the source is grounded; the drain of the twelfth NMOS transistor is connected to the local complementary data line, and the gate receives the local write signal.
[0024] In addition, the local read / write unit further includes: a precharge circuit, which is connected between the local data line and the local complementary data line and is used to precharge the local data line and the local complementary data line in response to a precharge control signal.
[0025] In addition, the precharge circuit includes: a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor. The gates of the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor receive the precharge control signal; the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the working power supply. The drain of the third PMOS transistor is electrically connected to the local data line; the drain of the fourth PMOS transistor is electrically connected to the local complementary data line; the fifth PMOS transistor electrically connects the local data line and the local complementary data line in response to the precharge control signal.
[0026] Correspondingly, an embodiment of the present invention further provides a memory, including the above-mentioned read / write conversion circuit.
[0027] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:
[0028] An embodiment of the present invention provides a read-write conversion circuit with excellent structural performance, including a read-write conversion module that performs read-write operations in response to a read-write control signal, and a control module that outputs a variable read-write control signal in response to a read-write speed configuration signal to control the variable speed of the read-write operations of the read-write conversion module. Since the read-write control signal output by the control module is variable, the speed of the read-write operations performed by the read-write conversion module receiving this variable read-write control is also variable, so that the speed of the read-write operations of the read-write conversion circuit can be configured. Compared with the case where the speed of the read-write operations of the read-write conversion circuit is fixed, the read-write conversion circuit provided by the embodiment of the present invention can adjust the speed of the read-write operations according to actual needs, so that the read-write conversion circuit can be more widely applied, such as being able to be applied not only to scenarios of low-speed read-write operations but also to scenarios of high-speed read-write operations; in addition, by using the read-write conversion circuit provided by the embodiment of the present invention, when high-speed read-write operations are not required, it can be adjusted to low-speed read-write operations, thus avoiding the problem of high power consumption caused by high-speed read-write operations. Therefore, the performance of the read-write conversion circuit provided by the embodiment of the present invention is improved.
[0029] In addition, the read-write conversion module includes a local read-write unit, and the control module includes a local control unit, which outputs a variable local read-write control signal in response to the local read-write speed configuration signal in the read-write speed configuration signal to control the variable speed of the local read-write operations of the local read-write unit. In this way, the speed of the local read-write operations of the read-write conversion circuit provided by the embodiment of the present invention can be configured.
[0030] In addition, the read-write conversion module includes a global read-write unit, and the control module includes a global control unit, which outputs a variable global read-write control signal in response to the global read-write speed configuration signal in the read-write speed configuration signal to control the variable speed of the global read-write operations of the global read-write unit. In this way, the speed of the global read-write operations of the read-write conversion circuit provided by the embodiment of the present invention can be configured.
[0031] In addition, the local read-write unit includes a local amplifier connected between a local data line and a local complementary data line for amplifying the data on the local data line and the data on the local complementary data line. The local amplifier is beneficial to accelerating the distinction between the local data line and the local complementary data line, which is not only beneficial to improving the speed of local read-write operations but also beneficial to reducing the driving requirements of the local data line and the local complementary data line on the sense amplifier, thereby reducing the design difficulty of the sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the figures in the drawings do not constitute a proportional limitation.
[0033] Figure 1 A read-write conversion circuit provided in an embodiment of the present invention;
[0034] Figure 2 A read-write conversion circuit provided in another embodiment of the present invention;
[0035] Figure 3 Another read-write conversion circuit provided in another embodiment of the present invention;
[0036] Figure 4 A timing diagram of read-write control signals corresponding to high-speed write operations and low-speed write operations during the write operation of the read-write conversion circuit provided in another embodiment of the present invention;
[0037] Figure 5 A timing diagram of read-write control signals corresponding to high-speed read operations and low-speed read operations during the read operation of the read-write conversion circuit provided in another embodiment of the present invention;
[0038] Figure 6 A schematic circuit diagram of a local read-write unit in the read-write conversion circuit provided in another embodiment of the present invention;
[0039] Figure 7 Another schematic circuit diagram of a local read-write unit in the read-write conversion circuit provided in another embodiment of the present invention. Detailed implementation manners
[0040] As can be seen from the background art, the performance of the existing DRAM still needs to be improved.
[0041] The inventors of the present invention found that for the same DRAM in the prior art, the speed of its read-write operations (including read speed and write speed) is fixed. Since the speed of the read-write operations of the DRAM has been fixed, it is difficult to meet the requirement of having a high read-write operation speed for the DRAM at a certain period; if the DRAM is designed to have a fixed high read-write operation speed, then for the case where the DRAM has a low read-write operation speed at a certain period and can meet the requirement, the high read-write operation speed will bring the problem of high power consumption of the DRAM. That is to say, currently, there are problems of fixed read-write operation speed and high power consumption of the memory.
[0042] To solve the above problems, an embodiment of the present invention provides a read-write conversion circuit, including a read-write conversion module and a control module. The control module responds to a read-write speed configuration signal to output a variable read-write control signal, thereby controlling the variable speed of the read-write operation of the read-write conversion module. Thus, the embodiment of the present invention can achieve the configuration of the speed of the read-write operation, so as to adjust the speed of the read-write operation of the read-write conversion circuit to meet the expectation, and avoid unnecessary power consumption of the read-write conversion circuit, thereby improving the performance of the read-write conversion circuit.
[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will elaborate on the embodiments of the present invention with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present invention, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.
[0044] Figure 1 The read-write conversion circuit provided by an embodiment of the present invention.
[0045] Refer to Figure 1 , in this embodiment, the read-write conversion circuit includes: a read-write conversion module 101 that responds to a read-write control signal to perform a read-write operation; a control module 102 that responds to a read-write speed configuration signal to output a variable read-write control signal to control the variable speed of the read-write operation of the read-write conversion module 101.
[0046] The following will elaborate on the read-write conversion circuit provided in this embodiment with reference to the accompanying drawings.
[0047] In this embodiment, the read-write conversion circuit further includes: a local data line Ldat, a local complementary data line Ldat#, and a global data line Gdat. During the read-write operation, data is transmitted between the local data line Ldat and the local complementary data line Ldat# and the global data line Gdat#, and the data signals of the local data line Ldat and the local complementary data line Ldat# are opposite in phase.
[0048] In this embodiment, the data read by the read / write conversion circuit or the data signal written are all in pairs. Each pair of data signals includes two data. During the read / write operation, one of the two data is a high-level signal and the other data is a low-level signal. Therefore, the read / write conversion circuit includes at least a pair of local data lines Ldat and local complementary data lines Ldat#. Specifically, during the read operation, the data is transmitted to the global data line Gdat via the local data line Ldat and the local complementary data line Ldat#; during the write operation, the data is transmitted to the local data line Ldat and the local complementary data line Ldat# via the global data line Gdat.
[0049] The local data line Ldat is also called the local data line (local data line), and the local complementary data line Ldat# is also called the complementary local data line; the global data line Gdat is also called the global data line.
[0050] In this embodiment, the global data line Gdat of the read / write conversion circuit is in a single-ended transmission mode, that is, there is no global complementary data line in the read / write conversion circuit whose data signal phase is complementary to that of the global data line Gdat.
[0051] It should be noted that in other embodiments, the global data line of the read / write conversion circuit can also be in a differential transmission mode, that is, the read / write conversion circuit further includes a global complementary data line, and during the read / write operation, the data signal of the global complementary data line is opposite in phase to that of the global data line.
[0052] Specifically, the read / write conversion circuit is applied to a memory. The memory includes a column selection module 100. The local data line Ldat is connected to the bit line BL through the column selection module 100, and the local complementary data line Ldat# is connected to the complementary bit line BL# through the column selection module 100. The memory cell selected for the read operation or the write operation is selected through the column selection module 100. Correspondingly, a signal is transmitted between the bit line BL connected to the selected memory cell and the local data line Ldat, and a signal is transmitted between the complementary bit line BL# connected to the selected memory cell and the local complementary data line Ldat#.
[0053] During the read operation, the read / write conversion module 101 transmits the data of the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat; during the write operation, the read / write conversion module 101 transmits the data of the global data line Gdat to the local data line Ldat and the local complementary data line Ldat#.
[0054] The read / write control signals include: column selection signals, local read / write control signals, and global read / write control signals. The local read / write control signals are used to control the local read / write operations of the read / write conversion module 101, and the global read / write control signals are used to control the global read / write operations of the read / write conversion module 101.
[0055] The rate of the read / write control signals affects the speed of the read / write operations of the read / write conversion circuit. For example, the faster the rate of the read / write control signals, the faster the corresponding read / write operation speed; the slower the rate of the read / write control signals, the slower the corresponding read / write operation speed.
[0056] The read / write control signals are provided by the control module 102, and the read / write control signals output by the control module 102 are variable. Specifically, the rate of the read / write control signals is variable. The read / write speed configuration signals are related to the desired speed of the read / write operations. When the speed of the read / write operations is not the desired speed, the read / write control signals output by the control module 102 change, that is, the rate of the read / write control signals changes, so that the speed of the read / write operations performed by the read / write conversion module 101 in response to the changed read / write control signals changes, thus ensuring that the read / write speed of the read / write operations is the desired speed.
[0057] For example, when the speed of the read / write operations performed by the read / write conversion module 101 in response to the first read / write control signal is lower than the desired speed, the control module 102 outputs the second read / write control signal in response to the read / write speed configuration signals, so that the read / write operation speed of the read / write conversion module 101 increases to the desired speed; when the speed of the read / write operations performed by the read / write conversion module 101 in response to the third read / write control signal is higher than the desired speed, the control module 102 outputs the fourth read / write control signal in response to the read / write speed configuration signals, so that the read / write operation speed of the read / write conversion module 101 decreases to the desired speed.
[0058] Since the speed of the read / write operations of the read / write conversion module 101 is variable, the speed of the read / write operations of the read / write conversion module 101 can be adjusted according to the actual performance requirements, such as increasing the data transmission speed in the read / write operations or decreasing the data transmission speed in the read / write operations. While meeting different read / write performance requirements, unnecessary power consumption can be reduced.
[0059] In this embodiment, the read / write conversion circuit may further include: a speed configuration module 103, connected to the control module 102, for outputting read / write speed configuration signals to the control module 102. In this way, integrating the speed configuration module 103 into the read / write conversion circuit is beneficial to reducing the transmission path of the read / write speed configuration signals to the control module 102, further improving the response speed of the control module 102, so that the control module 102 can output the adjusted read / write control signals more timely, and thus the purpose of changing the speed of the read / write operations of the read / write conversion module 101 can be achieved faster.
[0060] The read-write control signal includes a read control signal and a write control signal. The read-write conversion module 101 responds to the read control signal to perform a read operation and responds to the write control signal to perform a write operation. In this embodiment, the control module 102 responds to the read-write speed configuration signal to output a variable read control signal to control the variable speed of the read operation of the read-write conversion module 101; the control module 102 also responds to the read-write speed configuration signal to output a variable write control signal to control the variable speed of the write operation of the read-write conversion module 101.
[0061] Correspondingly, the read-write speed configuration signal includes a read speed configuration signal and a write speed configuration signal; the speed configuration module 103 includes: a read speed configuration unit 113 for outputting the read speed configuration signal in the read-write speed configuration signal to the control module 102, so that the control module 102 responds to the read speed configuration signal to output a variable read control signal to control the variable speed of the read operation; a write speed configuration unit 123 for outputting the write speed configuration signal in the read-write speed configuration signal to the control module 102, so that the control module responds to the read speed configuration signal to output a variable write control signal to control the variable speed of the write operation.
[0062] It should be noted that the speed configuration module may further include a local speed configuration module and a global speed configuration module. The local speed configuration module is used to output a local read-write speed configuration signal to the control module to control the variable speed of the local read-write operation of the read-write conversion module; the global speed configuration module is used to output a global read-write speed configuration signal to the control module to control the variable speed of the global read-write operation of the read-write conversion module.
[0063] It should also be noted that in other embodiments, the speed configuration module may also be provided by other circuits outside the read-write conversion circuit.
[0064] For the read-write conversion circuit provided in this embodiment, the control module 101 outputs a variable read-write control signal, so that the speeds of the read and write operations of the read-write conversion module 101 are variable, thereby making the application scenarios of the read-write conversion circuit wider, such as being able to perform both high-speed and low-speed read and write operations, and avoiding the problem of high power consumption caused by being in the high-speed read and write operation state for a long time.
[0065] Another embodiment of the present invention also provides a read-write conversion circuit, which is substantially the same as the read-write conversion circuit provided in the previous embodiment, except that: in this embodiment, the read-write conversion module and the control module are described in more detail. The following will describe the read-write conversion circuit provided in this embodiment in detail with reference to the accompanying drawings. For the same or corresponding parts as those in the previous embodiment, reference may be made to the detailed description of the previous embodiment.
[0066] Figure 2 A read-write conversion circuit provided for another embodiment of the present invention.
[0067] Refer to Figure 2 , the read-write conversion circuit includes: a local data line Ldat, a local complementary data line Ldat#, a global data line Gdat, and a global complementary data line Gdat#; a read-write conversion module 201 and a control module 202. The read-write conversion module 201 responds to a read-write control signal to perform read-write operations, so as to perform data transmission between the local data line Ldat and the local complementary data line Ldat# and the global data line Gdat and the global complementary data line Gdat#. And during the read-write operation, the data signal phases of the local data line Ldat and the local complementary data line Ldat# are opposite, and the data signal phases of the global data line Gdat and the global complementary data line Gdat# are opposite.
[0068] It should be noted that in other embodiments, the read-write conversion circuit may not be provided with a global complementary data line.
[0069] In this embodiment, the read-write conversion module 201 includes: a local read-write unit 211, which responds to the local read-write control signal in the read-write control signal to perform local read-write operations. Among them, the local read-write control signal includes a local read signal Rd and a local amplification enable signal.
[0070] Correspondingly, the control module 202 includes: a local control unit 212, which responds to the local read-write speed configuration signal in the read-write speed configuration signal to output a variable local read-write control signal to control the variable speed of the local read-write operation of the local read-write unit 211.
[0071] In this way, the speed of the local read-write operation in the read-write conversion circuit is variable. Specifically, the speed of the local read operation in the local read-write operation is variable, and the speed of the local write operation in the local read-write operation is variable. For example, the local read operation can be reduced from a high-speed read to a low-speed read, or increased from a low-speed read to a high-speed read; the local write operation can be reduced from a high-speed write to a low-speed write, or increased from a low-speed write to a high-speed write. Since the speed of the local read-write operation is variable, the speed of the local read-write operation can be adjusted according to actual needs, so as to ensure that the read-write conversion circuit has the advantage of low power consumption while meeting the data transmission speed requirements.
[0072] In this embodiment, the read-write conversion circuit may further include: a local speed configuration module 213, which is connected to the local control unit 212 and is used to output a local read-write speed configuration signal to the local control unit 212 to make the local read-write control signal output by the local control unit 212 adjustable.
[0073] It should be noted that in other embodiments, a local read / write speed configuration signal may also be provided to the local control unit by an external circuit, that is, the read / write conversion circuit does not require a local speed configuration module.
[0074] The read / write conversion circuit may further include: a sense amplifier 214, which is connected to the local read / write unit 211 via a local data line Ldat and a local complementary data line Ldat# for sensing the voltages of a bit line BL and a complementary bit line BL#.
[0075] The bit line BL is connected to the local data line Ldat via the sense amplifier 214, and the complementary bit line BL# is connected to the local complementary data line Ldat# via the sense amplifier 214.
[0076] In this embodiment, the sense amplifier 214 receives a column select signal CSL. The sense amplifier 214 includes two NMOS transistors (not labeled), and the gates of the NMOS transistors receive the column select signal CSL. One NMOS transistor connects the bit line BL to the local data line Ldat in response to the column select signal CSL, and the other NMOS transistor connects the complementary bit line BL# to the local complementary data line Ldat# in response to the column select signal CSL.
[0077] It can be understood that in other embodiments, the sense amplifier may include any number of transistors, such as multiple NMOS transistors and / or multiple PMOS transistors. Any device that can implement the sense amplification function can be used as the sense amplifier.
[0078] Among them, the bit line BL is connected to a storage transistor (not labeled), the gate of the storage transistor is connected to a word line WL, one end of the storage transistor is connected to the bit line BL, and the other end is connected to a voltage Vplate via a capacitor (not labeled). The complementary bit line BL# is connected to a control transistor (not labeled), one end of the control transistor is connected to the complementary bit line BL#, and the other end is connected to the voltage Vplate.
[0079] In addition, the same local read / write unit 211 may be connected to multiple sense amplifiers 214 via the local data line Ldat and the local complementary data line Ldat#. For the convenience of illustration and description, Figure 2 only one sense amplifier 214 is shown in the figure.
[0080] In this embodiment, the read-write conversion circuit is applied to a memory. The write data path includes: from the local read-write unit 211 through the local data line Ldat and the local complementary data line Ldat# to the sense amplifier, and then through the sense amplifier 214 to the bit line BL and the complementary bit line BL#; the read data path includes: from the bit line through the sense amplifier 214 to the local data line Ldat and the local complementary data line Ldat#, and then through the local data line Ldat and the local complementary data line Ldat# to the local read-write unit 211.
[0081] In this embodiment, the read-write conversion module 201 further includes: a global read-write unit 221, which responds to the global read-write control signal in the read-write control signal to perform global read-write operations.
[0082] The control module 202 includes: a global control unit 222, which responds to the global read-write speed configuration signal in the read-write speed configuration signal to output a variable global read-write control signal to control the variable speed of the global read-write operation of the global read-write unit 221. In this way, the speed of the global read-write operation in the read-write conversion circuit is variable. Specifically, the speed of the global read operation in the global read-write operation is variable, and the speed of the global write operation in the global read-write operation is variable.
[0083] That is to say, in this embodiment, not only the speed of the local read-write operation is variable, but also the speed of the global read-write operation is variable.
[0084] It should be noted that in other embodiments, the control module may only include one of the local control unit or the global control unit. Correspondingly, only the speed of the local read-write operation is variable or only the speed of the global read-write operation is variable.
[0085] Correspondingly, the read-write conversion circuit may further include: a global speed configuration module 223, which is connected to the global control unit 222 and is used to output a global read-write speed configuration signal to the global control unit 222.
[0086] Among them, the local speed configuration module 213 and the global speed configuration module 223 may be integrated into the same speed configuration module 203. This speed configuration module 203 is used to output a local read-write speed configuration signal to the local control unit 212 and is also used to output a global read-write speed configuration signal to the global control unit 222.
[0087] It can be understood that in other embodiments, the global read-write speed configuration signal may also be provided to the global control unit by an external circuit, that is, the read-write conversion circuit does not require a global speed configuration module.
[0088] Figure 3 Another read-write conversion circuit provided for another embodiment. As Figure 3As shown, in another example, the read / write conversion circuit may further include: a read speed configuration unit 243, configured to output a read speed configuration signal in the read / write speed configuration signal to the local control unit 212 and the global control unit 222, so that the local control unit 212 outputs a variable local read control signal in response to the read speed configuration signal to control the variable speed of the local read operation, and so that the global control unit 222 outputs a variable global read control signal in response to the read speed configuration signal to control the variable speed of the global read operation; a write speed configuration unit 253, configured to output a write speed configuration signal in the read / write speed configuration signal to the local control unit 212 and the global control unit 222, so that the local control unit 212 outputs a variable local write control signal in response to the write speed configuration signal to control the variable speed of the local write operation, and so that the global control unit 222 outputs a variable global write control signal in response to the write speed configuration signal to control the variable speed of the global write operation. The read speed configuration unit 243 and the write speed configuration unit 253 may be integrated into the same speed configuration module 203, and the description of the speed configuration module 203 may refer to the foregoing embodiments.
[0089] For a read / write conversion circuit having a global read / write unit 221, the write data path includes: via the global read / write unit 221 to the global data line Gdat and the global complementary data line Gdat#, and then transmitted to the local read / write unit 211 via the global data line Gdat and the global complementary data line Gdat#; from the local read / write unit 211 through the local data line Ldat and the local complementary data line Ldat# to the sense amplifier 214, and then via the sense amplifier 214 to the bit line BL and the complementary bit line BL#.
[0090] For a read / write conversion circuit having a global read / write unit 221, the read data path includes: from the bit line BL and the complementary bit line BL# through the sense amplifier 214 to the local data line Ldat and the local complementary data line Ldat#, and then via the local data line Ldat and the local complementary data line Ldat# to the local read / write unit 211; then via the local read / write unit 211 to the global data line Gdat and the global complementary data line Gdat#; via the global data line Gdat and the global complementary data line Gdat# to the global read / write unit 221.
[0091] In this embodiment, the local read / write unit 211 includes a local read conversion circuit 2111, configured to transmit the data of the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat and the global complementary data line Gdat# in response to the local read control signal in the local read / write control signal.
[0092] The control module 202 outputs a local read control signal, and the control module 202 outputs a variable local read control signal in response to the read / write speed configuration signal to adjust the read speed of the local read conversion circuit 2111, thereby making the speed of the local read operation of the read / write conversion module 201 variable.
[0093] The local read / write unit 211 further includes: a local write conversion circuit 2112, configured to transfer the data of the global data line Gdat and the global complementary data line Gdat# to the local data line Ldat and the local complementary data line Ldat# in response to the local write control signal in the local read / write control signal.
[0094] The control module 202 outputs a local write control signal, and the control module 202 outputs a variable local write control signal in response to the read / write speed configuration signal to adjust the write speed of the local write conversion circuit 2112, thereby making the speed of the local write operation of the read / write conversion module 201 variable.
[0095] The local read / write unit 211 further includes: a local amplifier 2113, connected between the local data line Ldat and the local complementary data line Ldat#, for amplifying the data of the local data line Ldat and the data of the local complementary data line Ldat#.
[0096] The control module 202 outputs a variable local read control signal or a local write control signal, making the amplification speed of the local amplifier 2113 variable, thereby also being able to change the speed of the local read operation and the local write operation of the read / write conversion module 201 to a certain extent.
[0097] The local amplifier 2113 constitutes a circuit for amplifying the signal of the local data line Ldat and the signal of the local complementary data line Ldat#, which helps to accelerate the distinction between the local data line Ldat and the local complementary data line Ldat#, thereby improving the speed of data signal transmission and the data read / write speed. In addition, since the data signals of the local data line Ldat and the local complementary data line Ldat# are amplified, the requirements for the driving ability of the sense amplifier in the memory for the local data line Ldat and the local complementary data line Ldat# are reduced. Therefore, even if the area of the sense amplifier gradually decreases, the sense amplifier still has sufficient driving ability for the local data line Ldat and the local complementary data line Ldat#, so as to ensure good electrical performance of the read / write conversion circuit while meeting the development trend of device miniaturization, and further improve the storage performance of the memory including the read / write conversion circuit.
[0098] The global read / write unit 221 includes a sense amplifier 2211, a precharge unit 2212, and a write driver unit 2213. The sense amplifier 2211 can amplify the data signals of the global data line Gdat and the global complementary data line Gdat#, and the precharge unit 2212 can precharge the global data line Gdat and the global complementary data line Gdat#.
[0099] The control module 202 outputs a variable global read control signal to adjust the speed of the global read operation or the global write operation of the global read / write unit 221, such as adjusting the amplification speed of the sense amplifier 2211, the precharge speed of the precharge unit 2212, and the driving speed of the write driver unit 2213, so as to achieve the purpose of changing the speed of the global read / write operation of the read / write conversion module 201.
[0100] In this embodiment, the read / write conversion circuit may further include: a precharge circuit (not shown), which is connected between the local data line Ldat and the local complementary data line Ldat# and is used to precharge the local data line Ldat and the local complementary data line Ldat# in response to a precharge control signal.
[0101] Figure 4 is the timing diagram of the read / write control signals corresponding to the high-speed write operation and the low-speed write operation during the write operation of the read / write conversion circuit provided in this embodiment; Figure 5 is the timing diagram of the read / write control signals corresponding to the high-speed read operation and the low-speed read operation during the read operation of the read / write conversion circuit provided in this embodiment; Figure 4 and Figure 5 also shows the bit line / complementary bit line signal (BL / BL#), the global data line / global complementary data line signal (Gdat / Gdat#), and the local data line / local complementary data line signal (Ldat / Ldat#). It can be understood that high speed and low speed are relative.
[0102] Refer to Figure 4 , during the write operation, the read / write control signals include: a global write control signal, a column selection signal CSL, a local write signal Wr, and a local amplification enable. It can be understood that during the low-speed write operation, the level of the local amplification enable can be 0, so the timing diagram of the local amplification enable is not shown corresponding to the low-speed write operation.
[0103] From Figure 4It is not difficult to find that when changing from a high-speed write operation to a low-speed write operation, the rate of the read-write control signal slows down, the data transfer rates of the global data line Gdat and the global complementary data line Gdat# slow down, and the data transfer rates of the local data line Ldat and the local complementary data line Ldat# slow down. When changing from a low-speed write operation to a high-speed write operation, the rate of the read-write control signal speeds up, the data transfer rates of the global data line Gdat and the global complementary data line Gdat# speed up, and the data transfer rates of the local data line Ldat and the local complementary data line Ldat# speed up.
[0104] In addition, Figure 4 only shows the timing diagrams of each read-write control signal within a single clock cycle. Looking at the entire clock cycle, when changing from a low-speed write operation to a high-speed write operation, the rate of the write control signal in the corresponding read-write control signal speeds up, and when changing from a high-speed write operation to a low-speed write operation, the rate of the write control signal in the corresponding read-write control signal slows down.
[0105] Referring to Figure 5 , when entering the read operation, the read-write control signals include: column select signal CSL, local read signal Rd, global amplification enable, global precharge signal, and local amplification enable. It can be understood that when performing a low-speed read operation, the level of the local amplification enable can be 0, so the timing diagram of the local amplification enable is not shown for the low-speed read operation. From Figure 5 It is not difficult to find that when changing from a high-speed read operation to a low-speed read operation, the rate of the read-write control signal slows down, the data transfer rates of the local data line Ldat and the local complementary data line Ldat# slow down, and the data transfer rates of the global data line Gdat and the global complementary data line Gdat# slow down; when changing from a low-speed read operation to a high-speed read operation, the rate of the read-write control signal speeds up, the data transfer rates of the local data line Ldat and the local complementary data line Ldat# speed up, and the data transfer rates of the global data line Gdat and the global complementary data line Gdat# speed up.
[0106] Figure 5 only shows the timing diagrams of each read-write control signal within a single clock cycle. Looking at the entire clock cycle, when changing from a low-speed read operation to a high-speed read operation, the rate of the read control signal in the corresponding read-write control signal speeds up, and when changing from a high-speed read operation to a low-speed write operation, the rate of the read control signal in the corresponding read-write control signal slows down.
[0107] It should be noted that Figure 4 and Figure 5 only show several common read-write control signals that affect the read-write operation speed. In an actual circuit, depending on the circuit design, there may be other read-write control signals that affect the read-write operation speed.
[0108] The circuit structure of the local read / write unit in the read / write conversion single path provided in this embodiment will be specifically described below in conjunction with the accompanying drawings.
[0109] Figure 6 It is a schematic diagram of a circuit structure of the local read / write unit in the read / write conversion circuit provided in this embodiment; Figure 7 It is another schematic diagram of a circuit structure of the local read / write unit in the read / write conversion circuit provided in this embodiment.
[0110] Refer to Figure 6 , the global data line Gdat is in a single transmission mode, that is, the read / write conversion circuit does not include global complementary data lines. The local read / write unit 211 includes a local read conversion circuit 2111, which is used to transmit the data of the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat in response to the local read control signal in the local read / write control signal.
[0111] In this embodiment, the local read conversion circuit 2111 includes: a third NMOS transistor MN3 and a fourth NMOS transistor MN4; the drain of the third NMOS transistor MN3 is connected to the global data line Gdat, the gate of the third NMOS transistor MN3 is connected to the local complementary data line Ldat#, and the source of the third NMOS transistor MN3 is connected to the drain of the fourth NMOS transistor MN4; the gate of the fourth NMOS transistor MN4 receives the local read signal Rd in the local read control signal, and the source is grounded.
[0112] It can be understood that the local read conversion circuit 2111 can also be other suitable deformed circuits. For example, the gate of the fourth NMOS transistor is connected to the local complementary data line, and the gate of the third NMOS transistor receives the local read signal.
[0113] In another example, as Figure 7 shown, the global data line Gdat can also be in a dual transmission mode, that is, the read / write conversion circuit includes the global data line Gdat and the global complementary data line Gdat#, and during the read operation, the data signals of the global complementary data line Gdat and the global data line Gdat# are opposite in phase. Correspondingly, in addition to the above-mentioned third NMOS transistor MN3 and fourth NMOS transistor MN4, the local read conversion circuit 2111 further includes: an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9; the drain of the eighth NMOS transistor MN8 is connected to the global complementary data line Gdat#, the gate of the eighth NMOS transistor MN8 is connected to the local data line Ldat, and the source of the eighth NMOS transistor MN8 is connected to the drain of the ninth NMOS transistor MN9; the gate of the ninth NMOS transistor MN9 receives the local read signal Rd, and the source is grounded.
[0114] The local read / write unit 211 includes: a local write conversion circuit 2112, configured to transfer the data of the global data line Gdat to the local data line Ldat and the local complementary data line Ldat# in response to the local write control signal in the local read / write control signal.
[0115] In this embodiment, the local write conversion circuit 2112 includes: a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7; the drain of the fifth NMOS transistor MN5 is connected to the local complementary data line Ldat#; the gate of the fifth NMOS transistor MN5 is connected to the source of the seventh NMOS transistor MN7; the source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6; the gate of the sixth NMOS transistor MN6 receives the local write signal Wr in the local write control signal, and the source is grounded; the drain of the seventh NMOS transistor MN7 is connected to the local data line Ldat, and the gate receives the local write signal Wr.
[0116] In another example, as Figure 7 shown, the read / write conversion circuit 211 further includes: a global complementary data line Gdat#. During a read operation, the data signal phase of the global complementary data line Gdat# is opposite to that of the global data line Gdat; in addition to the above-mentioned fifth NMOS transistor MN5, sixth NMOS transistor MN6, and seventh NMOS transistor MN7, the local write conversion circuit 2112 further includes: a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12; the drain of the tenth NMOS transistor MN10 is connected to the local data line Ldat; the gate of the tenth NMOS transistor MN10 is connected to the source of the twelfth NMOS transistor MN12 and is connected to the global complementary data line Gdat#; the source of the tenth NMOS transistor MN10 is connected to the drain of the eleventh NMOS transistor MN11; the gate of the eleventh NMOS transistor MN11 receives the local write signal Wr, and the source is grounded; the drain of the twelfth NMOS transistor MN12 is connected to the local complementary data line Ldat#, and the gate receives the local write signal Wr.
[0117] The local amplifier 2113 includes: a first inverter, the input terminal of the first inverter is electrically connected to the local data line, and the output terminal of the first inverter is electrically connected to the local complementary data line; a second inverter, the input terminal of the second inverter is electrically connected to the output terminal of the first inverter and the local complementary data line, and the output terminal of the second inverter is electrically connected to the input terminal of the first inverter and the local data line.
[0118] Specifically, the first inverter includes a first PMOS transistor MP1 and a first NMOS transistor MN1. The gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 are electrically connected and serve as the input terminal in1 of the first inverter. The source of the first PMOS transistor MP1 is connected to the operating power supply VDD, and the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 and serves as the output terminal out1 of the first inverter.
[0119] The second inverter includes a zero PMOS transistor MP0 and a zero NMOS transistor MN0. The gates of the zero PMOS transistor MP0 and the zero NMOS transistor MN0 are connected and serve as the input terminal in2 of the second inverter. The source of the zero PMOS transistor MP0 is connected to the operating power supply VDD, and the drain of the zero PMOS transistor MP0 is connected to the drain of the zero NMOS transistor MN0 and serves as the output terminal out2 of the second inverter.
[0120] The first PMOS transistor MP1, the first NMOS transistor MN1, the zero PMOS transistor MP0, and the zero NMOS transistor MN0 constitute a local amplifier 2113.
[0121] In addition, the local amplifier 2113 further includes an enable NMOS transistor mn. The first inverter and the second inverter are also connected to the drain of the enable NMOS transistor mn, and the drain of the enable NMOS transistor mn is grounded, and the gate receives a local enable signal En. Specifically, the source of the first NMOS transistor MN1 and the source of the zero NMOS transistor MN0 are connected to the drain of the sixth NMOS transistor MN6.
[0122] Due to the setting of the local amplifier 2113, the transmission speed of data from the bit line BL to the local data line Ldat is increased, the transmission speed of data from the complementary bit line BL# to the local complementary data line Ldat# is increased, and the driving requirement of the memory for the sense amplifier is reduced. Specifically, taking the data on the bit line BL as high level and the data on the complementary bit line BL# as low level as an example, since the first input terminal in1 of the first inverter is connected to the second output terminal out2 of the second inverter, and the first output terminal out1 of the first inverter is connected to the second input terminal in2 of the second inverter, during the transmission of the bit line BL and the complementary bit line BL# to the local data line Ldat and the local complementary data line Ldat#, the setting of the local amplifier 2113 will cause the local complementary data line Ldat# with a lower voltage to be pulled down to "0" more quickly, or cause the local data line Ldat with a higher voltage to be pulled up to "1" more quickly. Therefore, the speed of pulling up the local data line Ldat is increased, and the speed of pulling down the local complementary data line Ldat# is also increased, so the driving requirements of the local data line Ldat and the local complementary data line Ldat# for the sense amplifier are reduced.
[0123] Meanwhile, since the local data line Ldat and the local complementary data line Ldat# can reach a high level or a low level more quickly, the local data line Ldat and the local complementary data line Ldat# can be transferred to the global data line Gdat and the global complementary data line Gdat# earlier, so that when reading data, the speed of transferring data from the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat and the global complementary data line Gdat# is increased.
[0124] Correspondingly, during the writing period, the local amplifier 2113 can also amplify the local data line Ldat and the local complementary data line Ldat#, improving the speed of transferring data from the global data line Gdat and the global complementary data line Gdat# to the local data line Ldat and the local complementary data line Ldat#.
[0125] In this embodiment, the pre-charge circuit includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5; the gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 receive a pre-charge control signal Eq; the sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the working power supply VDD, the drain of the third PMOS transistor MP3 is electrically connected to the local data line Ldat; the drain of the fourth PMOS transistor MP4 is electrically connected to the local complementary data line Ldat#; the fifth PMOS transistor MN5 electrically connects the local data line Ldat and the local complementary data line Ldat# in response to the pre-charge control signal Eq. The control module 202 outputs a read / write control signal in response to the read / write speed configuration signal to change the data read rate of the local read conversion circuit 2111 or the data write rate of the local write conversion circuit 2112, etc., so as to adjust the speed of the read / write operation of the read / write conversion circuit.
[0126] The read / write conversion circuit provided in this embodiment can not only adjust the speed of local read / write operations, but also adjust the speed of global read / write operations, thus further improving the convenience of adjusting the read / write operation speed of the read / write conversion circuit.
[0127] Correspondingly, an embodiment of the present invention provides a memory, including the above-mentioned read / write conversion circuit.
[0128] This memory can be a DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND, NOR, etc. As can be seen from the foregoing analysis, the memory provided in this embodiment has the advantage of variable data transfer speed and low requirements for the driving ability of the sense amplifier, which is conducive to meeting the development trend of device miniaturization.
[0129] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present invention. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present invention. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A read-write conversion circuit, characterized in that, Comprising: A read-write conversion module that responds to a read-write control signal to perform read-write operations; wherein, the read-write operations include a read operation and a write operation; A local data line, a local complementary data line, and a global data line; wherein, data signals of the local data line and the local complementary data line are opposite in phase; Wherein, the read-write conversion module is configured to: during the read operation, transfer inverted data of the local complementary data line to the global data line, during the write operation, transfer data of the global data line to the local data line, and write inverted data of the global data line to the local complementary data line; Wherein, the read-write conversion module includes: a local read-write unit that responds to a local read-write control signal in the read-write control signal to perform local read-write operations; Wherein, the local read-write unit includes a local read conversion circuit for responding to a local read control signal in the local read-write control signal to transfer inverted data of the local complementary data line to the global data line; the local read conversion circuit includes: A third NMOS transistor and a fourth NMOS transistor; a drain of the third NMOS transistor is connected to the global data line, a gate of the third NMOS transistor is connected to the local complementary data line, a source of the third NMOS transistor is connected to a drain of the fourth NMOS transistor; a gate of the fourth NMOS transistor receives a local read signal in the local read-write control signal, and a source is grounded.
2. A read-write conversion circuit, characterized in that, Comprising: A read-write conversion module that responds to a read-write control signal to perform read-write operations; wherein, the read-write operations include a read operation and a write operation; A local data line, a local complementary data line, and a global data line; wherein, data signals of the local data line and the local complementary data line are opposite in phase; Wherein, the read-write conversion module is configured to: during the read operation, transfer inverted data of the local complementary data line to the global data line, during the write operation, transfer data of the global data line to the local data line, and write inverted data of the global data line to the local complementary data line; Wherein, the read-write conversion module includes: a local read-write unit that responds to a local read-write control signal in the read-write control signal to perform local read-write operations; Wherein, the local read-write unit includes: a local write conversion circuit for responding to a local write control signal in the local read-write control signal to transfer inverted data of the local complementary data line to the global data line; the local write conversion circuit includes: A fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; a drain of the fifth NMOS transistor is connected to the local complementary data line, a gate of the fifth NMOS transistor is connected to a source of the seventh NMOS transistor, a source of the fifth NMOS transistor is connected to a drain of the sixth NMOS transistor; a gate of the sixth NMOS transistor receives a local write signal in the local read-write control signal, and a source is grounded; a drain of the seventh NMOS transistor is connected to the local data line, and a gate receives the local write signal.
3. The read-write conversion circuit according to claim 1 or 2, characterized in that, The read / write control signal includes a read control signal and a write control signal. The read / write conversion module responds to the read control signal to perform a read operation and responds to the write control signal to perform a write operation.
4. The read-write conversion circuit according to claim 3, characterized in that, The read / write conversion circuit further includes: a sense amplifier, which is connected to the local read / write unit via the local data line and the local complementary data line and is used to sense the bit line voltage.
5. The read-write conversion circuit according to claim 4, characterized in that, The same local read / write unit is connected to a plurality of the sense amplifiers via the local data line and the local complementary data line.
6. The read-write conversion circuit according to claim 4, characterized in that, The write data path includes: from the local read / write unit through the local data line and the local complementary data line to the sense amplifier, and then through the sense amplifier to the bit line; the read data path includes: from the bit line through the sense amplifier to the local data line and the local complementary data line, and then through the local data line and the local complementary data line to the local read / write unit.
7. The read-write conversion circuit according to claim 1 or 2, characterized in that, The local read / write unit includes: a local amplifier, which is connected between the local data line and the local complementary data line and is used to amplify the data on the local data line and the data on the local complementary data line.
8. The read-write conversion circuit according to claim 7, characterized in that, The local amplifier includes: a first inverter, the input end of the first inverter is electrically connected to the local data line, and the output end of the first inverter is electrically connected to the local complementary data line; a second inverter, the input end of the second inverter is electrically connected to the output end of the first inverter and the local complementary data line, and the output end of the second inverter is electrically connected to the input end of the first inverter and the local data line.
9. The read-write conversion circuit according to claim 8, characterized in that, The first inverter includes: a first PMOS transistor and a first NMOS transistor, the gates of the first PMOS transistor and the first NMOS transistor are connected and serve as the input end of the first inverter, the source of the first PMOS transistor is connected to the working power supply, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and serves as the output end of the first inverter; the second inverter includes: a zero PMOS transistor and a zero NMOS transistor, the gates of the zero PMOS transistor and the zero NMOS transistor are connected and serve as the input end of the second inverter, the source of the zero PMOS transistor is connected to the working power supply, and the drain of the zero PMOS transistor is connected to the drain of the zero NMOS transistor and serves as the output end of the second inverter.
10. The read-write conversion circuit according to claim 1 or 2, characterized in that, The read / write conversion circuit further includes: a global complementary data line, and during a read operation, the data signal on the global complementary data line is opposite in phase to the data signal on the global data line; the local read conversion circuit further includes: an eighth NMOS transistor and a ninth NMOS transistor; the drain of the eighth NMOS transistor is connected to the global complementary data line, the gate of the eighth NMOS transistor is connected to the local data line, and the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; the gate of the ninth NMOS transistor receives the local read signal and the source is grounded.
11. The read-write conversion circuit according to claim 2, characterized in that, The read-write conversion circuit further includes: a global complementary data line, and during the read-write operation, the data signal phases of the global complementary data line and the global data line are opposite; the local write conversion circuit further includes: a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; the drain of the tenth NMOS transistor is connected to the local data line, the gate of the tenth NMOS transistor is connected to the source of the twelfth NMOS transistor and is connected to the global complementary data line, and the source of the tenth NMOS transistor is connected to the drain of the eleventh NMOS transistor; the gate of the eleventh NMOS transistor receives the local write signal, and the source is grounded; the drain of the twelfth NMOS transistor is connected to the local complementary data line, and the gate receives the local write signal.
12. A memory, characterized in that, Comprising: The read-write conversion circuit according to any one of claims 1-11.