A high-level Montgomery modular multiplication circuit and its parallel operation method

Abstract

This application discloses a high-level Montgomery modular multiplication circuit and its parallel operation method. The circuit includes: a loop control module, comprising m sets of loop control units for parallel operation of loop calculations to complete k+1 rounds of loop calculations, and for buffering intermediate data during the loop calculation process, reading data required for loop calculations from a storage module, and transmitting the corresponding data to the operation module according to the loop calculation steps; a core state machine module, responsible for controlling the start and end of each first-level loop calculation in the k+1 rounds of loop calculations run by the m sets of loop control units in the loop control module; an operation module, for receiving data transmitted by the loop control module, and performing multiplication and addition operations based on the received data; and a storage module, for storing data required for loop calculations for the loop control device to read and call. This application achieves a reduction in circuit area while maintaining high efficiency in loop calculations based on the parallel operation of m sets of loop control units.

Description

Technical Field

[0001] This application relates to the field of modular multiplication circuits, specifically to a high-level Montgomery modular multiplication circuit and its parallel operation method. Background Technology

[0002] The Montgomery modular multiplication algorithm is one of the most widely used methods for implementing modular multiplication. As a fundamental unit of asymmetric encryption and decryption algorithms such as RAS and ECC, the Montgomery modular multiplication algorithm's computational speed determines its overall computational efficiency. With the development and application of information technology, the security of encryption and decryption algorithms has become increasingly important to improve information security. Currently, most encryption and decryption algorithms are implemented in hardware to avoid data theft due to software vulnerabilities, which could cause serious adverse effects. Most modular multiplication circuits are currently designed based on the Montgomery algorithm and its variations. However, in hardware implementation, a good balance between circuit performance and circuit area is not achieved; there is a problem where improved circuit performance requires a larger circuit area, or a smaller circuit area results in poorer circuit performance. Summary of the Invention

[0003] This application provides a high-level Montgomery modular multiplication circuit and its parallel operation method, the specific technical solution of which is as follows:

[0004] A high-level Montgomery modular multiplication circuit specifically includes: a loop control module, comprising m sets of loop control units for parallel operation of loop calculations to complete k+1 rounds of loop calculations, and for caching intermediate data during the loop calculation process, reading data required for loop calculations from a storage module, and transmitting the corresponding data to the calculation module according to the loop calculation steps; a core state machine module, responsible for controlling the start and end of each first-level loop calculation in the k+1 rounds of loop calculations run by the m sets of loop control units in the loop control module; a calculation module, for receiving data transmitted by the loop control module, and performing multiplication and addition operations based on the received data; and a storage module, for storing data required for loop calculations for the loop control device to read and call; wherein, the k+1 rounds of loop calculations include k+1 rounds of first-level loop calculations, and each round of first-level loop calculations includes a pre-start loop calculation and k rounds of second-level loop calculations; the loop control device runs at most m rounds of loop calculations in parallel simultaneously; k and m are both positive integers, and k is a positive integer multiple of m.

[0005] Furthermore, the storage module includes three single-port random access static memory (RAM), one dual-port RAM, and two registers. The three single-port RAMs include a first single-port RAM for storing k+1 sets of multipliers A, a second single-port RAM for storing k+1 sets of multipliers B, and a third single-port RAM for storing k+1 sets of modulo N. The dual-port RAM stores k+1 sets of initial results S and also stores the results of each round of secondary loop operations. The k+1 sets of initial results S are used for the first round of loop operations. The two registers include a constant q register for storing one set of constants q and a result S register for storing the results of each round of primary loop operations.

[0006] Further, the arithmetic module includes a first multiplier, a second multiplier, and an adder; the first multiplier includes a first input terminal, a second input terminal, and a first output terminal; the second multiplier includes a third input terminal, a fourth input terminal, and a second output terminal; the adder includes a fifth input terminal, a sixth input terminal, a seventh input terminal, an eighth input terminal, and a third output terminal; wherein, the first, second, third, fourth, fifth, and sixth input terminals serve as input ports of the arithmetic module for receiving data transmitted by the loop control device; the first output terminal of the first multiplier is connected to the seventh input terminal of the adder, for transmitting the data after multiplication by the first multiplier to the adder for addition; the second output terminal of the second multiplier is connected to the eighth input terminal of the adder, for transmitting the data after multiplication by the second multiplier to the adder for addition; the third output terminal of the adder serves as the output port of the arithmetic module for outputting the data after addition.

[0007] Furthermore, the arithmetic module further includes: a first register, a second register, and a third register; wherein, the first register is located between the first multiplier and the adder, the first output terminal is connected to the input terminal of the first register, and the output terminal of the first register is connected to the seventh input terminal of the adder; the second register is located between the second multiplier and the adder, the second output terminal is connected to the input terminal of the second register, and the output terminal of the second register is connected to the eighth input terminal of the adder; the input terminal of the third register is connected to the third output terminal of the adder, and the output terminal of the third register serves as the output port of the arithmetic module.

[0008] Furthermore, the first register also includes a fourth output terminal, which serves as the output port of the arithmetic module for outputting the data that has undergone multiplication by the first multiplier.

[0009] Furthermore, each group of loop control units includes a loop controller, which is used to read the data stored in the storage module in response to the start control signal of the first-level loop operation of the core state machine module, and to perform the first-level loop operation based on the first multiplier, second multiplier and adder in the operation module in a time-division multiplexing manner based on the data stored in the storage module. It is also used to control the start and end of each round of the second-level loop operation.

[0010] Furthermore, each loop control unit also includes: an intermediate data cache module, used to cache data read from the storage module and intermediate calculation data fed back by the calculation module during the loop operation, and for the loop control unit to read and call; wherein, the intermediate data cache module includes: a first calculation result t register, used to cache the first calculation result t fed back by the calculation module; a second calculation result u register, used to cache the second calculation result u fed back by the calculation module; a third calculation result d register, used to cache the third calculation result d fed back by the calculation module; a multiplier A register, used to cache the multiplier A read by the loop control module from the first single-port random static memory of the storage module; a multiplier B register, used to cache the multiplier B read by the loop control module from the second single-port random static memory of the storage module; a modulus N register, used to cache the modulus N read by the loop control module from the third single-port random static memory of the storage module; and an intermediate result S register, used to cache the result S read by the loop control module from the dual-port random static memory of the storage module.

[0011] Furthermore, the high-performance Montgomery modular multiplication circuit further includes: a first input terminal of the first multiplier connected to a multiplier A register in each group of loop control units to receive the multiplier A cached in the multiplier A register transmitted by the loop control module; a second input terminal of the first multiplier also connected to a first calculation result t register in each group of loop control units to receive the first calculation result t cached in the first calculation result t register transmitted by the loop control module; a third input terminal of the second multiplier connected to a multiplier B register in each group of loop control units to receive the multiplier B cached in the multiplier B register transmitted by the loop control module; and a fourth input terminal of the second multiplier connected to a multiplier B register in each group of loop control units. The second calculation result u register is connected to receive the second calculation result u cached in the second calculation result u register transmitted by the loop control module; the fourth input of the second multiplier is connected to the modulus N register in each group of loop control units to receive the modulus N cached in the modulus N register transmitted by the loop control module; the fifth input of the adder is connected to the intermediate result S register in each group of loop control units to receive the result S cached in the intermediate result S register transmitted by the loop control module; the sixth input of the adder is connected to the third calculation result d register in each group of loop control units to receive the third calculation result d cached in the third calculation result d register transmitted by the loop control module.

[0012] This application also provides a parallel operation method for a high-level Montgomery modular multiplication circuit, specifically including: when the r-th group of loop control units completes the first round of the second-level loop operation in the first-level loop operation, the core state machine controls the (r+1)-th group of loop control units to start executing the next round of the first-level loop operation when the core state machine is in an idle state; wherein, when r equals m, when the r-th group of loop control units completes the first round of the second-level loop operation in the first-level loop operation, the core state machine controls the first group of loop control units to start executing the next round of the first-level loop operation; when the loop control unit starts executing a round of the first-level loop operation, it changes from the idle state to the working state, and correspondingly, when the loop control unit finishes a round of the first-level loop operation, it changes from the working state to the idle state.

[0013] Furthermore, a set of loop control units performs one round of first-level loop operation, specifically including: Step 1: Perform a pre-start loop operation and obtain the pre-start loop operation result; Step 2: Perform k rounds of second-level loop operation based on the pre-start loop operation result.

[0014] Further, the method for performing the pre-start loop operation and obtaining the result of the pre-start loop operation described in step 1 specifically includes: Step 11: The loop control unit reads the multiplier A(i) stored in the first single-port random static memory, the multiplier B(1) stored in the second single-port random static memory, and the result S(1) stored in the dual-port random static memory and transmits them to the operation module to obtain the first calculation result t of the pre-start loop operation; Step 12: The loop control unit reads the constant q stored in the constant q register and combines it with the first calculation result t of the pre-start loop operation and transmits it to the operation module to obtain the second calculation result u of the pre-start loop operation; Step 13: The loop control unit reads the modulus N(1) stored in the third single-port random static memory, combines it with the multiplier A(i) stored in the first single-port random static memory, the multiplier B(1) stored in the second single-port random static memory, the result S(1) stored in the dual-port random static memory, and the second calculation result u of the pre-start loop operation and transmits it to the operation module to obtain the third calculation result d of the pre-start loop operation.

[0015] Further, step 11 specifically includes: the loop control unit initiates a multiplier A(i) read operation to the first single-port random static memory of the storage module and a multiplier B(1) read operation to the second single-port random static memory of the storage module based on the number of first-level loop rounds it executes; the loop control unit caches the read multiplier A(i) in the multiplier A register and caches the read multiplier B(1) in the multiplier B register. At the same time, the loop control unit initiates a result S(1) read operation to the dual-port random static memory; the loop control unit caches the read result S(1) in the intermediate result S register, and at the same time, the loop control unit transmits the multiplier A(i) cached in the multiplier A register to the first multiplier through the first input terminal. The multiplier B(1) cached in the multiplier B register is transmitted to the first multiplier through the second input terminal, so that the first multiplier performs the multiplication operation of multiplier A(i) and multiplier B(1); the first multiplier transmits the product of multiplier A(i) and multiplier B(1) to the adder, and the loop control unit transmits the result S(1) cached in the intermediate result S register to the adder through the fifth input terminal, so that the adder performs the addition operation of the product of multiplier A(i) and multiplier B(1) and result S(1) and transmits the addition operation result as the first calculation result t to the corresponding set of loop control units, and the loop control unit caches the first calculation result t in the first calculation result t register; where i is a positive integer less than or equal to k+1.

[0016] Further, step 12 specifically includes: the loop control unit transmits the first calculation result t cached in the first calculation result t register to the first multiplier through the first input terminal; the loop control unit reads the constant q from the constant q register and transmits it to the first multiplier through the second input terminal, so that the first multiplier performs the multiplication operation of the first calculation result t and the constant q; and the first multiplier transmits the result of the multiplication operation of the first calculation result t and the constant q as the second calculation result u to the corresponding set of loop control units.

[0017] Further, step 13 specifically includes: the loop control unit caches the second calculation result u into the second calculation result u register, and at the same time, the loop control unit initiates a modulus N (1) read operation to the third single-port random static memory of the storage module; the loop control unit caches the read modulus N (1) into the modulus N register; the loop control unit transmits the multiplier A (i) cached in the multiplier A register to the first multiplier through the first input terminal, and transmits the multiplier B (1) cached in the multiplier B register to the first multiplier through the second input terminal, so that the first multiplier performs the multiplication operation of multiplier A (i) and multiplier B (1); the loop control unit transmits the second calculation result u cached in the second calculation result u register to the second multiplier through the third input terminal; the loop control unit transmits the modulus N (1) cached in the modulus N register to the first multiplier through the fourth input terminal. The second multiplier performs a multiplication operation between the second calculation result u and the modulus N(1). The loop control unit transmits the result S(1) cached in the intermediate result S register to the adder through the fifth input terminal. At the same time, the first multiplier transmits the product of multiplier A(i) and multiplier B(1) to the adder through the seventh input terminal. The second multiplier transmits the product of modulus N(1) and the second calculation result u to the adder through the eighth input terminal. This allows the adder to perform an addition operation between the result S(1), the product of multiplier A(i) and multiplier B(1), and the product of modulus N(1) and the second calculation result u. The addition operation result is then transmitted as the third calculation result d to the corresponding loop control unit. The loop control unit caches the third calculation result d in the third calculation result d register and obtains the third calculation result d as the result of the pre-start loop operation.

[0018] Furthermore, step 2, which involves performing k rounds of second-level loop operations based on the pre-starting loop operation results, specifically includes:

[0019] The loop control unit initiates a multiplier B(j+1) read operation to the second single-port random static memory of the storage module based on the second-level loop operation and a modulus N(j+1) read operation to the third single-port random static memory of the storage module. The loop control unit caches the read multiplier B(j+1) in the multiplier B register and the read modulus N(j+1) in the modulus N register. The loop control unit then initiates a result S(j+1) read operation to the dual-port random static memory. The loop control unit caches the read result S(j+1) in the intermediate result S register. The loop control unit transmits the multiplier A(i) cached in the multiplier A register to the first multiplier through the first input terminal, and transmits the multiplier B(j+1) cached in the multiplier B register to the first multiplier through the second input terminal, so that the first multiplier performs the multiplication operation of multiplier A(i) and multiplier B(j+1). The loop control unit transmits the second calculation result u cached in the second calculation result u register to the second multiplier through the third input terminal, and transmits the modulus N(j+1) cached in the modulus N register to the second multiplier through the fourth input terminal, so that the second multiplier performs the second calculation. The result u is multiplied by the modulus N(j+1); the loop control unit transmits the result S(j+1) cached in the intermediate result S register to the adder through the fifth input terminal, the loop control unit transmits the third calculation result d cached in the third calculation result d register to the adder through the sixth input terminal, and at the same time, the first multiplier transmits the product of multiplier A(i) and multiplier B(j+1) to the adder through the seventh input terminal, and the second multiplier transmits the product of modulus N(j+1) and the second calculation result u to the adder through the eighth input terminal, so that the adder performs the multiplication operation of result S(1) and multiplier B(j+1). The product of A(i) and multiplier B(j+1), the product of modulus N(j+1) and the second calculation result u, and the third calculation result d of the pre-starting loop operation are added together. The result of the addition operation is cached as the result S(j) in the dual-port random static memory for the next round of loop operation to be read, thus completing one round of two-level loop operation. It is then determined whether the number of rounds j of the second-level loop operation is equal to k. If yes, step 2 ends; otherwise, the value of the number of rounds j of the second-level loop operation is incremented by 1, and the next round of the second-level loop operation begins. Here, j is a positive integer less than or equal to k.

[0020] Furthermore, step 2, which involves performing k rounds of secondary loop operations based on the pre-start loop operation result, further includes: when the number of rounds j of the secondary loop operation is equal to k, the loop control unit transmits the addition operation result as the result of the current round of primary loop operation to the result S register of the storage module for caching.

[0021] The high-level Montgomery modular multiplication circuit and its parallel operation method described in this application achieve the technical effect of reducing circuit area while maintaining high efficiency in circuit cyclic operation by having multiple sets of cyclic control units in the cyclic control module call the same storage module and implement parallel operation of multiple rounds of cyclic operation based on the same operation module. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a high-level Montgomery modular multiplication circuit according to one embodiment of this application.

[0023] Figure 2 This is a schematic diagram of the computing module according to one embodiment of this application.

[0024] Figure 3 This is a schematic diagram of the computation module according to another embodiment of this application.

[0025] Figure 4 This is a schematic diagram of a loop control unit according to one embodiment of this application. Implementation

[0026] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described below are for illustrative purposes only and are not intended to limit the scope of this application.

[0027] Most current modular multiplication circuits are designed based on the Montgomery algorithm and its variations. However, in hardware implementation, a good balance between circuit performance and circuit area is not achieved; there are issues where improved circuit performance requires a larger circuit area, or a smaller circuit area results in poorer performance. To improve the balance between circuit area and performance in high-primary Montgomery modular multiplication circuits, this application provides a high-primary Montgomery modular multiplication circuit. This circuit aims to achieve parallel operation of multiple rounds of loop operations by having multiple loop control units in the loop control module call the same storage module and operate based on the same arithmetic module. This reduces the circuit area while maintaining high efficiency in loop operations.

[0028] Specifically, such as Figure 1 As shown, the high-base Montgomery modular multiplication circuit, as Figure 1 As shown, it specifically includes:

[0029] The loop control module includes m sets of loop control units, which are used to run loop operations in parallel to complete k+1 rounds of loop operations, and to cache intermediate data during the loop operation process. They read the data required for the loop operation from the storage module and transmit the corresponding data to the operation module according to the loop operation steps. The m sets of loop control units in the loop control module can run at most m rounds of loop operations simultaneously. The cached intermediate data refers to the data transmitted to the operation module by the loop control unit according to the loop operation steps, and the data fed back to the corresponding loop control unit by the operation module based on the operation results. This intermediate data can be used for subsequent loop operation steps.

[0030] The core state machine module is responsible for controlling the start and end of each first-level loop operation in the k+1 rounds of loop operations run by the m groups of loop control units in the loop control module. Specifically, in order to enable the k+1 rounds of loop operations to be performed smoothly and in parallel within the m groups of loop control units, the core state machine module controls the node at which each group of loop control units begins to execute a round of loop operations. The node at which the core state machine module controls the start of a new round of loop operations can be, but is not limited to, controlling the first group of loop control units to begin the first round of loop operations after the high-level Montgomery modular multiplication circuit is powered on, or controlling the next group of loop control units to begin the next round of loop operations after a specified intermediate data operation is completed during a round of loop operations. The completion of the specified intermediate data operation can be, but is not limited to, the completion of the first second-level loop operation during a round of loop operations.

[0031] The arithmetic module receives data transmitted from the loop control module and performs multiplication and addition operations based on the received data. The arithmetic module includes at least a multiplier and an adder to perform multiplication and addition operations, with the number of multipliers and adders configured according to actual computational requirements. The loop control module uses time-division multiplexing of the arithmetic module to achieve the technical effect of enabling a simple arithmetic module to perform complex computations, thus optimizing the algorithmic computation efficiency of the high-sigma Montgomery modular multiplication circuit.

[0032] The storage module is used to store the data required for loop operations, which can be read and called by the loop control device. The storage module is also used by the m groups of loop control units in the loop control device to perform parallel loop operations, thereby realizing data reuse in the storage space, improving the utilization rate of storage space, and reducing the required circuit area while ensuring circuit performance.

[0033] The high-radical Montgomery modular multiplication circuit described in this application is used to implement the high-radical Montgomery modular multiplication algorithm. The high-radical Montgomery modular multiplication algorithm is an efficient modular multiplication algorithm that can perform modular multiplication operations without division and is widely used in the field of cryptography. Here, k equals the radix of the high-radical Montgomery modular multiplication algorithm, achieving 22... k Modular multiplication of bits. The k+1 rounds of loop operation consist of k+1 rounds of first-level loop operation, and each round of first-level loop operation includes a pre-starting loop operation and k rounds of second-level loop operation. k and m are both positive integers, and k is a positive integer multiple of m.

[0034] As a preferred embodiment of this application, such as Figure 1 As shown, the storage module includes three single-port random access static retrieval systems (RAMs), one dual-port RAM, and two registers; wherein the three single-port RAMs include:

[0035] The first single-port static random access memory is used to store k+1 sets of multipliers A, each set consisting of 2... k The bit multiplier A, wherein the lower k groups of multipliers A are valid data, and the (k+1)th group of multipliers A is 0; the first single-port random static memory is used for each group of loop control units to read and call the corresponding group of multipliers A when executing the above-mentioned pre-start loop operation and second-level loop operation; the number of groups of multipliers A called by the loop control unit from the first single-port random static memory is determined based on the number of rounds of first-level loop operation and the number of rounds of second-level loop operation; preferably, the loop control unit calls the same number of groups of multipliers A from the first single-port random static memory based on the number of rounds of its first-level loop operation, for example, when the loop control unit executes the first round of first-level loop operation, it calls the first group of multipliers A from the first single-port random static memory for the first round of first-level loop operation.

[0036] The second single-port random static memory is used to store k+1 sets of multipliers B, each set consisting of 2 kThe bit multiplier B has the following structure: the lower k groups of multipliers B are valid data, and the (k+1)th group of multipliers B is 0. The second single-port random static memory is used for each group of loop control units to read and call the corresponding group of multipliers B when performing pre-start loop operation and secondary loop operation. When the loop control unit calls the number of groups of multipliers B from the second single-port random static memory to perform pre-start loop operation, it calls the first group of multipliers B. When the loop control unit calls the number of groups of multipliers B from the second single-port random static memory to perform secondary loop operation, it is determined based on the number of secondary loop operation rounds it performs. Preferably, the loop control unit calls the number of groups of multipliers B from the second single-port random static memory that is 1 more than the number of secondary loop operation rounds based on the number of execution rounds of its secondary loop operation. For example, when the loop control unit performs the first round of secondary loop operation, it calls the second group of multipliers B from the second single-port random static memory for the first round of secondary loop operation.

[0037] The third single-port static random access memory is used to store k+1 sets of modulo N, each set including 2 k The bit modulus N has the following parameters: the lower k groups of modulus N are valid data, and the (k+1)th group of modulus N is 0. The third single-port random static memory is used for each group of loop control units to read and call the corresponding group of modulus N when performing the above-mentioned pre-start loop operation and secondary loop operation. When the loop control unit calls the modulus N from the third single-port random static memory to perform the pre-start loop operation, it calls the first group of modulus N. When the loop control unit calls the modulus N from the third single-port random static memory to perform the secondary loop operation, the number of groups of modulus N to be called is determined based on the number of execution rounds of the secondary loop operation of the loop control unit. Preferably, the loop control unit calls the modulus N from the third single-port random static memory with a number of groups that is 1 greater than the number of execution rounds of the secondary loop operation based on the number of execution rounds of its secondary loop operation. For example, when the loop control unit performs the first round of the secondary loop operation, it calls the second group of modulus N from the third single-port random static memory for the first round of the secondary loop operation.

[0038] A dual-port random static memory is used to store k+1 sets of initial results S, and also to store the results of each round of secondary loop operation; wherein, the k+1 sets of initial results S are used by the loop control unit to execute the first round of primary loop operation; when the loop control unit executes the second to k+1 rounds of primary loop operation, it is based on the results of each round of secondary loop operation stored in the dual-port random static memory in the previous round of loop operation.

[0039] The two registers include a constant q register and a result S register; wherein, the constant q register is used to store a set of k bits of constant q, and the constant q is calculated as: q = -N -1 mod2 kThe result S register is used to store the result S(i) of each round of first-level loop operation. In this embodiment, the memory used to store the result S of each round of second-level loop operation is a dual-port random static memory, which ensures that the memory storing the result S has the ability to execute reading and storing in parallel. This is so that when multiple sets of loop control units are stored in parallel in the loop control module, the initial result S can be called and the second-level loop operation result can be written to the dual-port random static memory at the same time.

[0040] As a preferred embodiment of this application, such as Figure 2 As shown, the arithmetic module includes a first multiplier, a second multiplier, and an adder. Specifically, the first multiplier includes a first input terminal, a second input terminal, and a first output terminal; the second multiplier includes a third input terminal, a fourth input terminal, and a second output terminal; and the adder includes a fifth input terminal, a sixth input terminal, a seventh input terminal, an eighth input terminal, and a third output terminal. The first, second, third, fourth, fifth, and sixth input terminals serve as input ports of the arithmetic module, connected to the loop control device, and are used to receive data transmitted by the loop control device.

[0041] Specifically, the first output of the first multiplier is connected to the seventh input of the adder, enabling the first multiplier to transmit data to the adder. This is typically used to transmit data after multiplication by the first multiplier to the adder for addition. The second output of the second multiplier is connected to the eighth input of the adder, enabling the second multiplier to transmit data to the adder. This is typically used to transmit data after multiplication by the second multiplier to the adder for addition. The third output of the adder serves as the output port of the arithmetic module, used to output the data after addition. This embodiment limits the arithmetic module to include two multipliers and one adder, allowing the two multipliers to perform multiplication operations in parallel.

[0042] Preferably, in some embodiments of this application, in order to improve parallel computing capabilities, the high-performance Montgomery modular multiplication circuit can be configured with multiple operation modules including two multipliers and one adder. The m groups of loop operation units are configured with one operation module corresponding to each group according to a preset number of groups. For example, every 4 groups of loop operation units are configured with one operation module including two multipliers and one adder, so as to improve the parallel computing efficiency of multiple groups of loop operations in the loop control device.

[0043] As a preferred embodiment of this application, such as Figure 3As shown, the arithmetic module further includes a first register, a second register, and a third register. The first register is located between the first multiplier and the adder, with its first output connected to its input and its output connected to the seventh input of the adder. The second register is located between the second multiplier and the adder, with its second output connected to its input and its output connected to the eighth input of the adder. The third register's input is connected to the adder's third output, and its output serves as the output port of the arithmetic module. This embodiment, by setting a first register between the first multiplier and the adder, a second register between the second multiplier and the adder, and a third register between the adder's output and the loop arithmetic unit, effectively improves the arithmetic module's execution efficiency by interrupting the connection between the first / second multiplier and the adder using registers.

[0044] As a preferred embodiment of this application, such as Figure 3 As shown, the first register also includes a fourth output terminal, which serves as the output port of the arithmetic module for outputting the data multiplied by the first multiplier. This embodiment addresses the operational steps in the pre-startup loop of the high-level Montgomery modular multiplication algorithm that do not require addition. By setting a fourth output terminal on the first register, the fourth output terminal directly outputs the data multiplied by the first multiplier to the outside of the arithmetic module, bypassing the adder and directly feeding it back to the loop arithmetic device. This improves the feedback efficiency of intermediate results and reduces unnecessary occupation of computational resources.

[0045] As a preferred embodiment of this application, such as Figure 4As shown, each group of loop control units includes a loop controller, which is used to read the data stored in the storage module in response to the start control signal of the first-level loop operation of the core state machine module, and to perform the first-level loop operation based on the first multiplier, second multiplier and adder in the operation module in a time-division multiplexing manner based on the data stored in the storage module. It is also used to control the start and end of each round of the second-level loop operation. Specifically, when the loop controller responds to the start control signal of the first-level loop operation of the core state machine module, it controls the group of loop control units to execute the corresponding round of the first-level loop operation. The loop controller reads and calls the corresponding data from the storage module based on the execution progress of the first-level loop operation. For example, when executing the pre-start loop operation, it reads the first group result S (1) from the dual-port random static memory, reads the multiplier A (i) of the corresponding group number from the first single-port random static memory according to the execution round number i of the first-level loop operation, and reads the first group multiplier B (1) from the second single-port random static memory. The loop controller controls the start and end of each round of secondary loop operations based on the execution progress of the pre-start loop operation performed by the loop control unit. When the pre-start loop operation is completed, the loop controller starts the first round of secondary loop operations. When the result of a round of secondary loop operations is obtained, the loop controller ends that round and starts the next round. When the result of the kth round of secondary loop operations is obtained, the loop controller ends the kth round of secondary loop operations. In the loop control unit provided in this embodiment, the control of data transmission and reception between the loop control unit and the storage module, core state machine, and operation module is implemented.

[0046] As a preferred embodiment of this application, such as Figure 4 As shown, each group of loop control units also includes: an intermediate data cache module, used to cache data read from the storage module and intermediate calculation data fed back by the calculation module during the loop operation, and for the loop controller to read and call; wherein, the intermediate data cache module includes:

[0047] The first calculation result t register is used to cache the first calculation result t fed back by the operation module; wherein, the first calculation result t refers to the first calculation result t obtained by the loop operation unit in performing the first calculation step of a pre-start loop operation.

[0048] The second calculation result u register is used to cache the second calculation result u fed back by the operation module; wherein, the second calculation result u refers to the second calculation result u obtained by the loop operation unit performing a round of pre-start loop operation in the second calculation step;

[0049] The third calculation result d register is used to cache the third calculation result d fed back by the operation module; wherein, the third calculation result d refers to the third calculation result d obtained by the loop operation unit in performing the third calculation step of a round of pre-start loop operation; the third calculation result d is used in the k rounds of second-level loop operation in the same round of first-level loop operation.

[0050] The multiplier A register is used to cache the multiplier A read by the loop control unit from the first single-port random access static memory of the storage module. The multiplier B register is used to cache the multiplier B read by the loop control unit from the second single-port random access static memory of the storage module. The modulus N register is used to cache the modulus N read by the loop control unit from the third single-port random access static memory of the storage module. The intermediate result S register is used to cache the result S read by the loop control unit from the dual-port random access static memory of the storage module. This embodiment, by setting an intermediate data cache module in each group of loop control units, achieves two aspects: firstly, it caches the first calculation result t, the second calculation result u, and the third calculation result d fed back from the operation module, so as to facilitate the calling of subsequent loop operation steps; secondly, it caches the multiplier A, multiplier B, modulus N, and result S in the storage module, so that the data stored in the storage module can be read and called by multiple groups of loop control units running in parallel. Based on the caching of the data required in the loop operation process by the intermediate data cache module, the parallel operation efficiency of m groups of loop control units is improved.

[0051] Preferably, the intermediate data caching module includes a first calculation result t register, a second calculation result u register, a third calculation result d register, a multiplier A register, a multiplier B register, a modulus N register, and an intermediate result S register, all of which are registers capable of caching k-bit data; when new k-bit data is read or written, the new data is overwritten by the old data for caching.

[0052] In a preferred embodiment of this application, the high-level Montgomery modular multiplication circuit further includes:

[0053] The first input terminal of the first multiplier is connected to the multiplier A register in each group of loop control units to receive the multiplier A cached in the multiplier A register transmitted by the loop control unit; the first input terminal of the first multiplier is also connected to the first calculation result t register in each group of loop control units to receive the first calculation result t cached in the first calculation result t register transmitted by the loop control unit; the second input terminal of the first multiplier is connected to the multiplier B register in each group of loop control units to receive the multiplier B cached in the multiplier B register transmitted by the loop control unit.

[0054] The third input of the second multiplier is connected to the second calculation result u register in each group of loop control units to receive the second calculation result u cached in the second calculation result u register transmitted by the loop control unit; the fourth input of the second multiplier is connected to the modulus N register in each group of loop control units to receive the modulus N cached in the modulus N register transmitted by the loop control unit.

[0055] The fifth input of the adder is connected to the intermediate result S register in each group of loop control units to receive the result S cached in the intermediate result S register transmitted by the loop control unit; the sixth input of the adder is connected to the third calculation result d register in each group of loop control units to receive the third calculation result d cached in the third calculation result d register transmitted by the loop control unit. This embodiment, by limiting the registers in the loop control units to which the inputs of the first multiplier, the second multiplier, and the adder are connected, ensures that the first multiplier is only used to perform the multiplication operation of multiplier A and multiplier B, and the multiplication operation of the first calculation result t and the constant q, and that the second multiplier is only used to perform the multiplication operation of the second calculation result u and the modulus N. This distinguishes the multiplication operation steps performed by the first multiplier and the second multiplier in the loop operation, avoiding the confusion between the execution of the first multiplier and the second multiplier due to the parallel operation of multiple groups of loop control units.

[0056] As a preferred embodiment of this application, a parallel computation method for high-sigma Montgomery modular multiplication is provided, specifically including: when the r-th group of loop control units completes the first round of the second-level loop operation in the first-level loop operation, the core state machine controls the (r+1)-th group of loop control units to start executing the next round of the first-level loop operation when the r-th group of loop control units is in an idle state; wherein, when r equals m, when the r-th group of loop control units completes the first round of the second-level loop operation in the first-level loop operation, the core state machine controls the first group of loop control units to start executing the next round of the first-level loop operation. Specifically, when a loop control unit starts executing a round of the first-level loop operation, it transitions from an idle state to a working state; correspondingly, when a loop control unit finishes a round of the first-level loop operation, it transitions from a working state to an idle state. Since the pre-starting loop operation in a single-round loop requires the result of the first round of the second-level loop from the previous round, and the second-level loop operation requires the results of the second to kth rounds of the previous round, this implementation uses the completion of the first round of the second-level loop operation in the first-round loop operation as the node to trigger the start of the next round of the first-round loop operation. This ensures that when the next round of the loop operation starts, it can at least provide the data required to perform the pre-starting loop operation on the result of the third calculation d. This improves the efficiency of parallel computing while ensuring that the single-round loop operation can be executed smoothly.

[0057] In a preferred embodiment of this application, the logic for the core state machine module to control the loop control unit to start executing the first-level loop operation is based on whether the first round of the second-level loop operation in the first-level loop operation is completed. Specifically, the core state machine module controls the first group of loop control units to start executing the first round of the first-level loop operation. When the first group of loop control units completes the first round of the second-level loop operation in the first round of the first-level loop operation, the core state machine module controls the second group of loop control units to start executing the second round of the first-level loop operation. When the second group of loop control units completes the first round of the second-level loop operation in the second round of the first-level loop operation, the core state machine module controls the third group of loop control units to start executing the second round of the first-level loop operation, and so on. When the (m-1)th group of loop control units completes the first round of the second-level loop operation in the (m-1)th round of the first-level loop operation, the core state machine controls the mth group of loop control units to start executing the mth round of the first-level loop operation.

[0058] In a preferred embodiment of this application, a set of loop control units performs one round of first-level loop operation, specifically including: Step 1: Performing a pre-start loop operation and obtaining the pre-start loop operation result; Step 2: Performing k rounds of second-level loop operation based on the pre-start loop operation result. The pre-start loop operation result refers to the obtained third calculation result d. This embodiment divides one round of first-level loop operation into a pre-start loop operation and k rounds of second-level loop operation. The execution of the k rounds of second-level loop operation is based on the pre-start loop operation result, thus achieving nested k rounds of second-level loop operation within each round of first-level loop operation.

[0059] As a preferred embodiment of this application, the method for performing a pre-starting loop operation and obtaining the result of the pre-starting loop operation in step 1 specifically includes:

[0060] Step 11: The loop control unit reads the multiplier A(i) stored in the first single-port random static memory, the multiplier B(1) stored in the second single-port random static memory, and the result S(1) stored in the dual-port random static memory and transmits them to the arithmetic module to obtain the first calculation result t of the pre-start loop operation;

[0061] Step 12: The loop control unit reads the constant q stored in the constant q register and combines it with the first calculation result t of the pre-start loop operation to transmit it to the operation module to obtain the second calculation result u of the pre-start loop operation;

[0062] Step 13: The loop control unit reads the modulus N (1) stored in the third single-port random static memory, combines it with the multiplier A (i) stored in the first single-port random static memory, the multiplier B (1) stored in the second single-port random static memory, the result S (1) stored in the dual-port random static memory, and the second calculation result u of the pre-start loop operation, and transmits it to the operation module to obtain the third calculation result d of the pre-start loop operation.

[0063] Specifically, in the multiplier A(i), i refers to the number of the first-level loop operation currently being executed by the loop control unit; the multiplier A(i) refers to the i-th group of multipliers A pre-stored in the first single-port random static memory; the multiplier B(1) refers to the first group of multipliers B pre-stored in the second single-port random static memory; the result S(1) refers to the result of the first round of the second-level loop operation in the previous loop operation. In particular, if the current operation is the first round of loop operation, the result S(1) is the first group of initial results S pre-stored in the dual-port random static memory.

[0064] In a preferred embodiment of this application, step 11 specifically includes:

[0065] The loop control unit initiates a multiplier A(i) read operation to the first single-port random static memory of the storage module based on the number of first-level loops i it executes, and initiates a multiplier B(1) read operation to the second single-port random static memory of the storage module; wherein, the multiplier A(i) refers to the i-th group of multipliers A pre-stored in the first single-port random static memory; the multiplier B(1) refers to the 1-th group of multipliers B pre-stored in the second single-port random static memory.

[0066] The loop control unit caches the read multiplier A(i) into the multiplier A register and caches the read multiplier B(1) into the multiplier B register. At the same time, the loop control unit initiates a read operation on the result S(1) to the dual-port random static memory. The result S(1) refers to the result of the first round of the second-level loop operation in the previous loop operation. In particular, if the current operation is the first round of the loop operation, the result S(1) is the first set of initial results S pre-stored in the dual-port random static memory.

[0067] The loop control unit caches the read result S(1) into the intermediate result S register. At the same time, the loop control unit transmits the multiplier A(i) cached in the multiplier A register to the first multiplier through the first input terminal, and transmits the multiplier B(1) cached in the multiplier B register to the first multiplier through the second input terminal, so that the first multiplier performs the multiplication operation of multiplier A(i) and multiplier B(1).

[0068] The first multiplier transmits the product of multiplier A(i) and multiplier B(1) to the adder through the seventh input terminal. The loop control unit transmits the result S(1) cached in the intermediate result S register to the adder through the fifth input terminal, so that the adder performs the addition operation of the product of multiplier A(i) and multiplier B(1) and the result S(1) and transmits the addition operation result as the first calculation result t to the corresponding set of loop control units. The loop control unit caches the first calculation result t in the first calculation result t register; where i is a positive integer less than or equal to k+1. In this embodiment, the calculation step of the first calculation result of the pre-starting loop in the high-level Montgomery modular multiplication algorithm is split into two steps. The first step is to calculate the product of multiplier A(i) and multiplier B(1). The second step is to calculate the sum of the product of multiplier A(i) and multiplier B(1) and the result S(1) based on the product of multiplier A(i) and multiplier B(1), thereby realizing the acquisition of the first calculation result t.

[0069] In a preferred embodiment of this application, step 12 specifically includes: the loop control unit transmits the first calculation result t cached in the first calculation result t register to the first multiplier through the first input terminal; the loop control unit reads the constant q from the constant q register and transmits it to the first multiplier through the second input terminal, so that the first multiplier performs the multiplication operation of the first calculation result t and the constant q; and the first multiplier transmits the result of the multiplication operation of the first calculation result t and the constant q as the second calculation result u to the corresponding set of loop control units.

[0070] In a preferred embodiment of this application, step 13 specifically includes:

[0071] The loop control unit caches the second calculation result u into the second calculation result u register. At the same time, the loop control unit initiates a modulus N(1) read operation to the third single-port random static memory of the storage module. The loop control unit caches the read modulus N(1) into the modulus N register. The modulus N(1) refers to the first set of modulus N pre-stored in the third single-port random static memory.

[0072] The loop control unit transmits the multiplier A(i) cached in the multiplier A register to the first multiplier through the first input terminal, and transmits the multiplier B(1) cached in the multiplier B register to the first multiplier through the second input terminal, so that the first multiplier performs the multiplication operation of multiplier A(i) and multiplier B(1). The loop control unit transmits the second calculation result u cached in the second calculation result u register to the second multiplier through the third input terminal, and transmits the modulus N(1) cached in the modulus N register to the second multiplier through the fourth input terminal, so that the second multiplier performs the multiplication operation of the second calculation result u and modulus N(1).

[0073] The loop control unit transmits the result S(1) cached in the intermediate result S register to the adder through the fifth input terminal. At the same time, the first multiplier transmits the product of multiplier A(i) and multiplier B(1) to the adder through the seventh input terminal. The second multiplier transmits the product of modulus N(1) and second calculation result u to the adder through the eighth input terminal. This allows the adder to perform the addition operation of the result S(1), the product of multiplier A(i) and multiplier B(1), the product of modulus N(1) and second calculation result u, and transmits the addition operation result as the third calculation result d to the corresponding set of loop control units. The loop control unit caches the third calculation result d in the third calculation result d register and obtains the third calculation result d as the result of the pre-start loop operation.

[0074] As a preferred embodiment of this application, step 2, which involves performing k rounds of secondary loop operations based on the pre-starting loop operation results, specifically includes:

[0075] The loop control unit initiates a multiplier B(j+1) read operation to the second single-port random access static memory of the storage module based on the second-level loop operation execution round number j, and initiates a modulus N(j+1) read operation to the third single-port random access static memory of the storage module; where j is a positive integer less than or equal to k. The j+1 is determined based on the second-level loop operation execution round number j of the loop control unit, the multiplier B(j+1) refers to the (j+1)th set of multipliers B pre-stored in the second single-port random access static memory, and the modulus N(j+1) refers to the (j+1)th set of modulos N pre-stored in the third single-port random access static memory.

[0076] The loop control unit caches the read multiplier B(j+1) in the multiplier B register and the read modulus N(j+1) in the modulus N register. The loop control unit initiates a read operation on the result S(j+1) from the dual-port random static memory. Here, the result S(j+1) refers to the (j+1)th set of results S stored in the dual-port random static memory. Specifically, when the loop control unit executes the first round of first-level loop operation, the result S(j+1) refers to the (j+1)th set of initial results S pre-stored in the dual-port random static memory. Conversely, when the loop control unit does not execute the first round of first-level loop operation, the result S(j+1) refers to the (j+1)th set of results S in the k sets of results S stored in the dual-port random static memory based on the results of the second-level loop operation in the previous round of loop operation.

[0077] The loop control unit buffers the read result S(j+1) into the intermediate result S register. The loop control unit transmits the buffered multiplier A(i) in the multiplier A register to the first multiplier through the first input terminal, and transmits the buffered multiplier B(j+1) in the multiplier B register to the first multiplier through the second input terminal, so that the first multiplier performs the multiplication operation of multiplier A(i) and multiplier B(j+1) to obtain the product of multiplier A(i) and multiplier B(j+1). The loop control unit transmits the second calculation result u buffered in the second calculation result u register to the second multiplier through the third input terminal, and transmits the buffered modulus N(j+1) in the modulus N register to the second multiplier through the fourth input terminal, so that the second multiplier performs the multiplication operation of the second calculation result u and modulus N(j+1) to obtain the product of the second calculation result u and modulus N(j+1).

[0078] The loop control unit transmits the result S(j+1) cached in the intermediate result S register to the adder through the fifth input terminal. The loop control unit transmits the third calculation result d cached in the third calculation result d register to the adder through the sixth input terminal. At the same time, the first multiplier transmits the product of multiplier A(i) and multiplier B(j+1) to the adder through the seventh input terminal. The second multiplier transmits the product of modulus N(j+1) and second calculation result u to the adder through the eighth input terminal. This allows the adder to perform the addition operation of the result S(1), the product of multiplier A(i) and multiplier B(j+1), the product of modulus N(j+1) and second calculation result u, and the third calculation result d of the pre-starting loop operation. The addition operation result is cached as the result S(j) in the dual-port random static memory for the next round of loop operation to be read, thus completing one round of two-level loop operation.

[0079] The system determines whether the number of execution rounds j in the secondary loop operation is equal to k. If yes, step 2 ends; otherwise, the number of execution rounds j is incremented by 1, and the next round of the secondary loop operation begins. In this embodiment, the loop controller determines whether the number of execution rounds j in the secondary loop operation is equal to k to control the end of the secondary loop operation based on the number of execution rounds. If the number of execution rounds in the secondary loop operation has not reached k, the loop control unit continues to execute the secondary loop operation.

[0080] As a preferred embodiment of this application, step 2, which involves performing k rounds of secondary loop operations based on the pre-start loop operation result, further includes: when the number of rounds j of the secondary loop operation is equal to k, the loop control unit transmits the addition operation result as the result of the current round of primary loop operation to the result S register of the storage module for caching.

[0081] In a preferred embodiment of this application, an upper limit is defined on the number of first-level loop operations that each group of loop control units can complete. Specifically, the number of first-level loop operations that the first group of loop control units can complete is equal to 1 + k / m rounds; the number of first-level loop operations that the remaining groups of loop control units can complete is equal to k / m rounds, where k / m is a positive integer. For example, in some embodiments, the loop control module is configured with 4 groups of loop control units, i.e., m=4, and the radix-32 Montgomery modular multiplication algorithm is implemented based on these 4 groups of loop control units, i.e., k=32. In this loop control module, the first group of loop control units is used to implement 9 rounds of first-level loop operations, and the second to fourth groups of loop control units are used to implement 8 rounds of first-level loop operations.

[0082] In a preferred embodiment of this application, to ensure that the reading, writing, and calling of the storage module and the arithmetic module do not interfere with each other during the parallel operation of multiple sets of loop control units, the timing of the first multiplier, the second multiplier, and the adder in the arithmetic module is time-division multiplexed among the m sets of loop control units in the loop control module; the timing of reading the first single-port random access memory, the second single-port random access memory, the third single-port random access memory, the dual-port random access memory, and the constant q in the storage module is time-division multiplexed; and the timing of writing the result S register in the storage module is time-division multiplexed. This ensures that only one loop control module performs read operations on the first single-port random access memory / the second single-port random access memory / the third single-port random access memory in each clock cycle, and that only one loop control module performs read and write operations on the dual-port random access memory in each clock cycle. The specific limiting logic can be, but is not limited to: grouping the timing sequence into four time units. In each group, the first time unit allows read operations on the dual-port random access static memory; the second time unit allows calls to the multiplier; the third time unit allows calls to the adder; and the fourth time unit allows read operations on the first, second, and third single-port random access static memory, and write operations on the dual-port random access static memory. This implementation improves the reuse efficiency of storage and arithmetic modules when multiple groups of loop control units are operating in parallel by controlling the loop control unit to perform read calls and transfer operations on each memory and register in a time-sharing manner.

[0083] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. These programs can be stored in computer-readable storage media (such as ROM, RAM, magnetic disks, or optical disks, and other media capable of storing program code). When executed, the program performs the steps of the above-described method embodiments.

[0084] It should be noted that the aforementioned loop control modules, arithmetic modules, and storage modules can all be, but are not limited to, digital circuit modules described by the designer using the hardware description language Verilog HDL, or digital circuit modules drawn or compiled by the designer using software with circuit drawing or compilation capabilities. Furthermore, the functional units in the various embodiments of this invention can be integrated into a single processing module, or each unit can exist physically separately, or two or more units can be integrated into a single module.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A high radix Montgomery modular multiplication circuit, comprising: The high Montgomery modular multiplication circuit comprises: a cycle control module comprising m sets of cycle control units, which are used to perform cycle operations in parallel to complete k+1 rounds of cycle operations, and are used to buffer intermediate data in the cycle operation process, read data required for the cycle operation from a storage module, and transmit corresponding data to an operation module according to a cycle operation step; a core state machine module, which is used to control the start and end of each round of primary cycle operation in the k+1 rounds of cycle operation performed by the m sets of cycle control units in the cycle control module; the operation module, which is used to receive data transmitted by the cycle control module, and perform multiplication and addition operations based on the received data; the storage module, which is used to store data required for the cycle operation, and is used to read and call the data by the cycle control device; wherein the k+1 rounds of cycle operation comprise k+1 rounds of primary cycle operation, each round of primary cycle operation comprises a pre-start cycle operation and k rounds of secondary cycle operation, and the cycle control device performs at most m rounds of cycle operation in parallel; k and m are positive integers, and k is a positive integer multiple of m.

2. The high-radix Montgomery modular multiplication circuit of claim 1, wherein, The storage module comprises three single-port random static memories, one double-port random static memory and two registers. The three single-port random static memories comprise a first single-port random static memory for storing k+1 sets of multipliers A, a second single-port random static memory for storing k+1 sets of multipliers B, and a third single-port random static memory for storing k+1 sets of moduli N. The double-port random static memory is used to store k+1 sets of initial results S, and is also used to store the result of each round of secondary cycle operation; the k+1 sets of initial results S are used for the first round of cycle operation. The two registers comprise a constant q register for storing one set of constants q, and a result S register for storing the result of each round of primary cycle operation.

3. The high-radix Montgomery modular multiplication circuit of claim 1, wherein, The operation module comprises a first multiplier, a second multiplier and an adder. The first multiplier comprises a first input end, a second input end and a first output end. The second multiplier comprises a third input end, a fourth input end and a second output end. The adder comprises a fifth input end, a sixth input end, a seventh input end, an eighth input end and a third output end. The first input end, the second input end, the third input end, the fourth input end, the fifth input end and the sixth input end serve as input ports of the operation module and are used to receive data transmitted by the cycle control device. The first output end of the first multiplier is connected to the seventh input end of the adder, and is used to transmit data subjected to multiplication operation by the first multiplier to the adder for addition operation. The second output end of the second multiplier is connected to the eighth input end of the adder, and is used to transmit data subjected to multiplication operation by the second multiplier to the adder for addition operation. The third output end of the adder serves as an output port of the operation module and is used to output data subjected to addition operation.

4. The high-radix Montgomery modular multiplication circuit of claim 3, wherein, The operation module further comprises a first register, a second register and a third register; the first register is arranged between the first multiplier and the adder, the first output end is connected with the input end of the first register, and the output end of the first register is connected with the seventh input end of the adder; the second register is arranged between the second multiplier and the adder, the second output end is connected with the input end of the second register, and the output end of the second register is connected with the eighth input end of the adder; the input end of the third register is connected with the third output end of the adder, and the output end of the third register is used as the output port of the operation module.

5. The high-radix Montgomery modular multiplication circuit of claim 4, wherein, The first register further comprises a fourth output end, which is used as the output port of the operation module to output the data subjected to the multiplication operation of the first multiplier.

6. The high-radix Montgomery modular multiplication circuit of claim 3, wherein, Each group of the loop control units comprises a loop controller, which is configured to read the data stored in the storage module in response to the start control signal of the primary loop operation of the core state machine module, time-division multiplex the first multiplier, the second multiplier and the adder in the operation module based on the read data stored in the storage module to perform the primary loop operation, and control the start and end of each round of the secondary loop operation.

7. The high-radix Montgomery modular multiplication circuit of claim 6, wherein, Each group of the loop control units further comprises an intermediate data cache module, which is configured to cache the data read from the storage module and the intermediate operation data fed back by the operation module in the loop operation process, and provide the loop control unit with the read and call; the intermediate data cache module comprises: a first calculation result t register, configured to cache the first calculation result t fed back by the operation module; a second calculation result u register, configured to cache the second calculation result u fed back by the operation module; a third calculation result d register, configured to cache the third calculation result d fed back by the operation module; a multiplier A register, configured to cache the multiplier A read by the loop control module from the first single-port random static memory of the storage module; a multiplier B register, configured to cache the multiplier B read by the loop control module from the second single-port random static memory of the storage module; a modulus N register, configured to cache the modulus N read by the loop control module from the third single-port random static memory of the storage module; an intermediate result S register, configured to cache the result S read by the loop control module from the double-port random static memory of the storage module.

8. The high-radix Montgomery modular multiplication circuit of claim 7, wherein, The high-base Montgomery modular multiplication circuit further comprises: the first input end of the first multiplier is connected with the multiplier A register in each group of the loop control units respectively, so as to receive the multiplier A cached in the multiplier A register and transmitted by the loop control module; the first input end of the first multiplier is further connected with the first calculation result t register in each group of the loop control units respectively, so as to receive the first calculation result t cached in the first calculation result t register and transmitted by the loop control module; the second input end of the first multiplier is connected with the multiplier B register in each group of the loop control units respectively, so as to receive the multiplier B cached in the multiplier B register and transmitted by the loop control module; the third input end of the second multiplier is connected with the second calculation result u register in each group of the loop control units respectively, so as to receive the second calculation result u cached in the second calculation result u register and transmitted by the loop control module; and the fourth input end of the second multiplier is connected with the third calculation result d register in each group of the loop control units respectively, so as to receive the third calculation result d cached in the third calculation result d register and transmitted by the loop control module. The fourth input end of the second multiplier is connected with the modulus N register in each group of the loop control units respectively to receive the modulus N register cached by the loop control module; The fifth input end of the adder is connected with the intermediate result S register in each group of the loop control units respectively to receive the result S cached by the loop control module; The sixth input end of the adder is connected with the third calculation result d register in each group of the loop control units respectively to receive the third calculation result d cached by the loop control module.

9. A parallel operation method of a high radix Montgomery modular multiplication circuit, characterized by, The parallel operation method of the high-radix Montgomery modular multiplication circuit, specifically comprises: When the rth group of the loop control units completes the first round of the secondary loop operation in the primary loop operation, the core state machine module controls the r+1th group of the loop control units to start the next round of the primary loop operation in the idle state; When r is equal to m, the core state machine module controls the first group of the loop control units to start the next round of the primary loop operation when the rth group of the loop control units completes the first round of the secondary loop operation in the primary loop operation; when the loop control unit starts a round of the primary loop operation, it is converted from the idle state to the working state, and correspondingly, when the loop control unit ends a round of the primary loop operation, it is converted from the working state to the idle state.

10. The parallel operation method of the high-radix Montgomery modular multiplication circuit according to claim 9, wherein, The one group of the loop control units performs a round of the primary loop operation, specifically comprising: Step 1: performing a pre-starting loop operation to obtain a pre-starting loop operation result; Step 2: performing k rounds of the secondary loop operation based on the pre-starting loop operation result to obtain a primary loop operation result, and ending a round of the primary loop operation.

11. The parallel operation method of the high-radix Montgomery modular multiplication circuit according to claim 10, wherein The method for performing the pre-starting loop operation to obtain the pre-starting loop operation result in step 1, specifically comprising: Step 11: the loop control unit reads the multiplier A(i) stored in the first single-port random static memory, the multiplier B(1) stored in the second single-port random static memory, and the result S(1) stored in the double-port random static memory, and transmits them to the operation module to obtain the first calculation result t of the pre-starting loop operation; Step 12: the loop control unit reads the constant q stored in the constant q register, combines the first calculation result t of the pre-starting loop operation, and transmits them to the operation module to obtain the second calculation result u of the pre-starting loop operation; Step 13: the loop control unit reads the modulus N(1) stored in the third single-port random static memory, combines the multiplier A(i) stored in the first single-port random static memory, the multiplier B(1) stored in the second single-port random static memory, the result S(1) stored in the double-port random static memory, and the second calculation result u of the pre-starting loop operation, and transmits them to the operation module to obtain the third calculation result d of the pre-starting loop operation.

12. The parallel operation method of the high-radix Montgomery modular multiplication circuit according to claim 11, wherein, The step 11, specifically comprising: The cycle control unit initiates a multiplier A(i) read operation to the first single-port random static memory of the storage module and a multiplier B(1) read operation to the second single-port random static memory of the storage module based on the number of cycles of the primary loop executed by the cycle control unit; The cycle control unit caches the read multiplier A(i) to a multiplier A register and caches the read multiplier B(1) to a multiplier B register, and simultaneously initiates a result S(1) read operation to the dual-port random static memory; The cycle control unit caches the read result S(1) to an intermediate result S register, and simultaneously transmits the multiplier A(i) cached in the multiplier A register to the first multiplier through a first input terminal and transmits the multiplier B(1) cached in the multiplier B register to the first multiplier through a second input terminal, so that the first multiplier performs a multiplication operation on the multiplier A(i) and the multiplier B(1); The first multiplier transmits the product of the multiplier A(i) and the multiplier B(1) to the adder, the cycle control unit transmits the result S(1) cached in the intermediate result S register to the adder through a fifth input terminal, so that the adder performs an addition operation on the product of the multiplier A(i) and the multiplier B(1) and the result S(1) and transmits the addition operation result as a first calculation result t to a corresponding group of cycle control units, and the cycle control unit caches the first calculation result t of the pre-started cycle operation to a first calculation result t register; wherein i is a positive integer less than or equal to k+1.

13. The parallel operation method of the high-radix Montgomery modular multiplication circuit according to claim 12, wherein, The step 12 specifically includes: The cycle control unit transmits the first calculation result t cached in the first calculation result t register to the first multiplier through a first input terminal, reads a constant q from a constant q register and transmits the constant q to the first multiplier through a second input terminal, so that the first multiplier performs a multiplication operation on the first calculation result t and the constant q, and the first multiplier transmits the multiplication operation result of the first calculation result t and the constant q as a second calculation result u of the pre-started cycle operation to a corresponding group of cycle control units.

14. The parallel operation method of the high-radix Montgomery modular multiplication circuit according to claim 13, wherein, The step 13 specifically includes: The cycle control unit caches the second calculation result u to a second calculation result u register, and simultaneously initiates a modulus N(1) read operation to the third single-port random static memory of the storage module; The cycle control unit caches the read modulus N(1) to a modulus N register; The cycle control unit transmits the multiplier A(i) cached in the multiplier A register to the first multiplier through a first input terminal and transmits the multiplier B(1) cached in the multiplier B register to the first multiplier through a second input terminal, so that the first multiplier performs a multiplication operation on the multiplier A(i) and the multiplier B(1), the cycle control unit transmits the second calculation result u cached in the second calculation result u register to the second multiplier through a third input terminal, and transmits the modulus N(1) cached in the modulus N register to the second multiplier through a fourth input terminal, so that the second multiplier performs a multiplication operation on the second calculation result u and the modulus N(1); The cyclic control unit transmits the result S(1) cached in the intermediate result S register to the adder through the fifth input end, and the first multiplier transmits the product of the multiplier A(i) and the multiplier B(1) to the adder through the seventh input end, and the second multiplier transmits the product of the modulus N(1) and the second calculation result u to the adder through the eighth input end, so that the adder performs addition operation on the result S(1), the product of the multiplier A(i) and the multiplier B(1), and the product of the modulus N(1) and the second calculation result u, and transmits the addition operation result as the third calculation result d to the corresponding set of cyclic control units; The cyclic control unit caches the third calculation result d in the third calculation result d register, and obtains the third calculation result d as the pre-starting cyclic operation result.

15. The parallel operation method of the high-radix Montgomery modular multiplication circuit according to claim 14, wherein The step 2 performs k rounds of secondary cyclic operation based on the pre-starting cyclic operation result, specifically including: The cyclic control unit initiates the multiplier B(j+1) reading operation to the second single-port random static storage of the storage module and initiates the modulus N(j+1) reading operation to the third single-port random static storage of the storage module based on the number of rounds of the secondary cyclic operation; The cyclic control unit caches the read multiplier B(j+1) in the multiplier B register and caches the read modulus N(j+1) in the modulus N register, and initiates the result S(j+1) reading operation to the dual-port random static storage; The cyclic control unit caches the read result S(j+1) in the intermediate result S register, and transmits the multiplier A(i) cached in the multiplier A register to the first multiplier through the first input end and transmits the multiplier B(j+1) cached in the multiplier B register to the first multiplier through the second input end, so that the first multiplier performs multiplication operation on the multiplier A(i) and the multiplier B(j+1); the cyclic control unit transmits the second calculation result u cached in the second calculation result u register to the second multiplier through the third input end and transmits the modulus N(j+1) cached in the modulus N register to the second multiplier through the fourth input end, so that the second multiplier performs multiplication operation on the second calculation result u and the modulus N(j+1); The cyclic control unit transmits the result S(1) cached in the intermediate result S register to the adder through the fifth input end, and the first multiplier transmits the product of the multiplier A(i) and the multiplier B(1) to the adder through the seventh input end, and the second multiplier transmits the product of the modulus N(1) and the second calculation result u to the adder through the eighth input end, so that the adder performs addition operation on the result S(1), the product of the multiplier A(i) and the multiplier B(1), and the product of the modulus N(1) and the second calculation result u, and transmits the addition operation result as the third calculation result d to the corresponding set of cyclic control units; If the number of the secondary loop operation execution rounds is equal to k, the step 2 is ended; if not, the value of the number of the secondary loop operation execution rounds is increased by 1, and the next round of the secondary loop operation is entered. Wherein, j is a positive integer less than or equal to k.

16. The parallel operation method of the high-radix Montgomery modular multiplication circuit according to claim 14, wherein The k rounds of the secondary loop operation based on the pre-starting loop operation result in step 2 further comprises: when the number of the secondary loop operation execution rounds is equal to k, the loop control unit transmits the addition operation result as the current round of the primary loop operation result to the result S register of the storage module for caching.

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