Reconfigurable matching table parameter configuration method and system based on P4 compiling

Abstract

The invention discloses a reconfigurable matching table parameter configuration method and system based on P4 compilation. The method comprises the steps that an intermediate representation generated after a P4 program is compiled through a compiler front end is obtained; obtaining matching feature information and action feature information of each node extracted by the rear end of the compiler after traversing the nodes in the intermediate representation, respectively obtaining table item information and action information, and respectively storing the table item information and the action information in the first structural body and the second structural body; judging whether a dependency relationship exists or not according to a preset dependency relationship; if yes, writing into the dependency relationship structural body; if not, analyzing the table item information and the action information, and judging whether the table item information and the action information conform to a preset hardware constraint specification or not, and if yes, obtaining table item structure information and action instruction information described by the P4 program; and further obtaining configuration information generated by the rear end of the compiler, and issuing the configuration information through the control plane. According to the invention, the universality and flexibility of the P4 compiling environment can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of programmable switches, and particularly relates to a method and system for configuring reconfigurable match table parameters based on P4 compilation. Background Art

[0002] The RMT (Reconfigurable Match Tables) architecture is a pipeline architecture based on RISC switching chips. The RMT architecture is an abstract architecture widely used in existing network switching chips. This abstract architecture abstracts the network switching chip into a reconfigurable parser and a multi-stage Match-Action pipeline. With the continuous development of switching chips, the inverse parser used to reconstruct data packets has gradually been incorporated into this abstraction. After the data frame passes through the parser to obtain the data packet (PHV), it will flow through multiple levels of the Match-Action pipeline in this abstract architecture. In each level of the pipeline, two stages, Match and Action, will be executed, as Figure 1 shown. And the form of matching and the actions to be performed by the data packet in the pipeline can be flexibly modified through configurable registers and storage in the hardware, which is a major manifestation of the switch supporting programmability.

[0003] From the above description, a conclusion can be drawn that to implement certain modification and processing functions on data packets by the switching chip, it is necessary to configure the configurable part in the hardware. For example, in the Match stage, it is necessary to configure matching rule information to perform flow classification on the data packet, and in the Action stage, it is necessary to configure action codes to clarify what kind of processing is to be performed on the packet, etc. In the early stage, the configuration of programmable network chips required network personnel to be familiar with the specific design of the switching chip and manually write configuration information according to the operations to be performed on the data packet and send it to the hardware through the control plane. This posed relatively high requirements for network personnel, and this method could not simply and clearly know the processing rules of the current switch for data packets. To solve this problem, the programming language P4 dedicated to the network switching field was born.

[0004] Among them, since the birth of the P4 language, with its gradual development, it has become the de facto programmable language standard for programmable switches and the main choice for programming programmable switches based on reconfigurable match-action tables. The P4 programming language has gone through several architectural changes. Its latest version (version 16, also known as P416) is a major redesign of the original version of the language (P414). It is designed to support packet processing on various target switches with different architectures (software switches, smartNICs, eBPF, FPGAs, RMTs, dRMTs, etc.). P4 provides language constructs to describe the architectures and runtime behaviors of these switches. Network personnel can describe the processing of data packets in programmable switches by writing P4 programs. Simply put, as a programming language dedicated to the network switching field, P4 can be more oriented towards network engineers, controlling specific hardware devices by directly describing the packet switching process. For example, describe how the parser generates the required PHV through state transitions; what types of match tables exist in the ingress pipeline (i.e., the Match-Action pipeline under the RMT architecture), the corresponding table entries, sizes of the match tables, and the types of Action operations that can be performed on the PHV; and how the inverse parser reorganizes the PHV header based on state transitions. However, these descriptions are reflected in the content of each control register and memory in the hardware in specific hardware devices.

[0005] The P4 compiler, on the other hand, needs to complete the task of mapping executable configurations highly related to the hardware. Since the P4 language is essentially independent of the target hardware and only provides high-level imperative structures to express the packet processing logic of various packet processing architectures, there is no direct mapping between the P4 program and the components of the RMT architecture. A P4 configuration compilation system is necessary to convert a given P4 program into a specific executable program (binary hardware configuration) executed by the target switch. As Figure 2 shown, the user provides a specific hardware device and a P4 program, and the P4 compiler is used to generate the target hardware configuration information (Target-specific configuration binary).

[0006] The programmable features inherent in the RMT architecture align perfectly with the concept of the SDN (Software-Defined Network); meanwhile, the separation of the control plane and the data plane has become an established trend. For these reasons, the RMT architecture has become the mainstream architecture for today's network switching plane. From the perspective of the data plane, the control-related logic is discarded, leading to an increase in data-plane throughput; from the perspective of the control plane, online programmability can be achieved through software, reducing the control threshold for switching chips. However, although there is already an open-source compiler front-end P4C developed by the P4 consortium that can obtain a hardware-independent intermediate representation (IR), it does not provide any compilation back-end. Merely having an intermediate representation that is independent of hardware obtained from the compilation front-end is far from sufficient. A compiler back-end related to the hardware is also needed to map this hardware representation to the hardware resources of the switch. However, there is no open-source compilation back-end available to check the feasibility of P416 programs on switches. At the same time, the control plane of commercial switches is closed to the outside and highly bound to specific hardware, making it impossible to be transplanted to other switching planes that adopt the RMT abstraction. The internal mapping mechanism cannot be seen. This inhibits the construction of new mapping algorithms and general compilation systems for the RMT architecture.

[0007] The emergence of the P4 language well conforms to the design concept of separating the control plane and the data plane in programmable switches in software-defined networks (SDN), enabling network personnel to no longer concern themselves with the specific hardware structure and only control different processing methods of the switch at the application layer through high-level P4 programs, simplifying the use of the RMT abstraction and providing the possibility of online programmable configuration. A complete and general P4 compilation system is a necessary condition for the programmable switching plane to truly support P4 online programmability. This raises a question, and it becomes particularly important to build a compilation back-end system for mapping the Match-Action pipeline on the basis of the open-source P4 compilation front-end system. At the same time, due to the differences in the hardware architectures, hardware resources, and hardware constraints of each programmable switch, it is very difficult to ensure the generality of the back-end compiler. Therefore, there is an urgent need for a highly general and flexible Match-Action P4 compilation back-end system to efficiently complete the configuration and control of switching chips. Summary of the Invention

[0008] To solve the above problems existing in the prior art, the present invention provides a reconfigurable match table parameter configuration method and system based on P4 compilation. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0009] In a first aspect, the present invention provides a reconfigurable match table parameter configuration method based on P4 compilation, including:

[0010] Obtain the intermediate representation generated after the P4 program is compiled by the compiler front-end; wherein, the nodes in the intermediate representation include match nodes and action nodes;

[0011] Obtain the match feature information and action feature information of each node extracted after the compiler back-end traverses the nodes in the intermediate representation, obtain the entry information and action information, and store them in the first structure and the second structure respectively;

[0012] According to the preset dependency relationship, determine whether there is a dependency relationship in the entry information in the first structure, and determine whether there is a dependency relationship in the action information in the second structure; if so, write it into the dependency relationship structure; if not, analyze the entry information and action information, and determine whether it meets the preset hardware constraint specifications. If it meets, obtain the entry structure information and action instruction information described by the P4 program;

[0013] According to the dependency relationship in the dependency relationship structure, as well as the entry structure information and action instruction information described by the P4 program, obtain the configuration information generated by the compiler back-end, and send the configuration information through the control plane.

[0014] In a second aspect, the present invention also provides a reconfigurable match table parameter configuration system based on P4 compilation, including:

[0015] A compiler front-end module for obtaining the intermediate representation generated after the P4 program is compiled by the compiler front-end; wherein, the nodes in the intermediate representation include match nodes and action nodes;

[0016] A mapping module in the compiler back-end module for obtaining the match feature information and action feature information of each node extracted after the compiler back-end traverses the nodes in the intermediate representation, obtaining the entry information and action information, and storing them in the first structure and the second structure respectively; according to the preset dependency relationship, determine whether there is a dependency relationship in the entry information in the first structure, and determine whether there is a dependency relationship in the action information in the second structure; if so, write it into the dependency relationship structure; if not, analyze the entry information and action information, and determine whether it meets the preset hardware constraint specifications. If it meets, obtain the entry structure information and action instruction information described by the P4 program;

[0017] A configuration generation module in the compiler back-end module for obtaining the configuration information generated by the compiler back-end according to the dependency relationship in the dependency relationship structure, as well as the entry structure information and action instruction information described by the P4 program, and sending the configuration information through the control plane.

[0018] Advantages of the present invention:

[0019] A method and system for configuring reconfigurable match table parameters based on P4 compilation provided by the present invention can interface with a general P4 compilation front-end. By using the idea of the recursive method for the front-end intermediate representation, the compilation system can adapt to different Match-Action hardware implementations in a general way to obtain configuration information, improving the generality and flexibility of the P4 compilation environment.

[0020] The following will further elaborate on the present invention in conjunction with the accompanying drawings and embodiments. Description of the Drawings

[0021] Figure 1 is a schematic diagram of the Match-Action architecture abstraction provided by the prior art;

[0022] Figure 2 is a schematic diagram of the interaction between a compiler and programmable network switching hardware provided by the prior art;

[0023] Figure 3 is a flowchart of a method for configuring reconfigurable match table parameters based on P4 compilation provided by an embodiment of the present invention;

[0024] Figure 4 is another flowchart of a method for configuring reconfigurable match table parameters based on P4 compilation provided by an embodiment of the present invention;

[0025] Figure 5 is a schematic diagram of the match dependency relationship provided by an embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of the action dependency relationship provided by an embodiment of the present invention;

[0027] Figure 7 is a schematic diagram of the inheritance dependency relationship provided by an embodiment of the present invention;

[0028] Figure 8 is a schematic diagram of the compilation process provided by an embodiment of the present invention;

[0029] Figure 9 is a schematic diagram of the network processor MAU structure provided by an embodiment of the present invention;

[0030] Figure 10 is a flowchart of generating configuration information by MAU P4 compilation provided by an embodiment of the present invention;

[0031] Figure 11 is a schematic diagram of a configuration information processing unit provided by an embodiment of the present invention;

[0032] Figure 12 is a schematic diagram of the MAU configuration result provided by an embodiment of the present invention;

[0033] Figure 13 It is a schematic diagram of the MPLS label modification result provided by an embodiment of the present invention;

[0034] Figure 14 It is a schematic diagram of the MPLS label pop-up result provided by an embodiment of the present invention. Detailed implementation manners

[0035] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0036] In the existing research technologies of the P4 language and its compilation system, it is difficult to achieve both in terms of a complete compilation system and generality. Representatives of high-speed programmable switches in the industry, such as Intel's Tofino series programmable switches, take supporting P4 programmability as a major advantage. However, due to interests involved, network engineers can only write P4 programs to control the processing behavior of data packets in the switch, and its entire set of P4 compilation systems is not visible to the outside.

[0037] In the academic community, Glen Gibb et al. first proposed the P4 programming language in the article "P4: Programming protocol-independent packet processors", and introduced the high-level structure of the two-stage P4 language compiler and how it is finally mapped to the target hardware through the control plane. Although the above work briefly discussed the mapping problem of the parser and the match-action stage logic to the physical layer, it lacked the discussion on how to convert the mapping relationship into specific configuration information after mapping. The realizability of compilation was lacking.

[0038] In the paper "Compiling Packet Prsograms to Reconfigurable Switches" by Lavanya Jose et al., based on the idea of the match table dependency directed graph TDG, a heuristic-based mapping algorithm was proposed, which contributed to a certain extent to generality. This work systematically studied the structure and resource limitations in programmable chips and deeply analyzed the dependency relationships that determine the relative positions of match action tables in P4 programs. Based on the above analysis, this work proposed the mapping problem of match action tables and combined existing greedy algorithms and integer linear programming algorithms to solve four types of limitations in this problem: the flow table entry allocation limitation for a single logical table, the memory capacity limitation for physical tables, the dependency limitation between logical tables, and the limitations specific to programmable chips. At the same time, the compiler efficiencies of integer linear programming ILP and greedy algorithms under different hardware resource constraints were analyzed and compared. The results showed that the greedy algorithm had higher running efficiency, but its optimization effects for different goals (such as optimizing resources, optimizing latency, etc.) were weaker than those of integer linear programming. In the paper, the TDG was abstracted from the P4 program through the ILP algorithm to infer table entry sending rules, etc. to avoid dependency problems in the Match-Action structure, and at the same time, physical constraints of the target switch were provided for the compiler. Although this work proposed an idea of a compilation algorithm, it did not borrow a highly general compilation front end such as P4C, and its essence still had high hardware-related limitations, lacking technical support for solving the online configuration problem of the data channel in the RMT architecture. All the above-mentioned work was designed to support the initial version of the P4 language (P414), and none of them provided a complete compiler backend. In addition, the latest version of the P4 language (P416) is not exactly the same as P414 in architecture. Therefore, these works cannot be directly used to compile P416 programs.

[0039] Debobroto Das Robin et al. proposed an open-source compiler backend for Match-Action in 2024. By expanding the TDG and introducing a new type of dependency relationship generated by stateful memory access, it makes decisions to generate mapping relationships, and proposed a JSON-based hardware specification language HSL to describe the hardware resource constraints of the V1Model, etc. Although this compiler backend moved closer to the P4C open-source compiler front end and proposed corresponding efficient mapping methods for the mapping stage, it lacked analysis and implementation for the most critical hardware configuration information generation stage, making it still have limitations as a truly usable general compilation system.

[0040] In addition, there are also some compilers that directly compile P4 programs into hardware description language (HDL) in an attempt to lower the hardware development threshold of programmable switches, enabling designers to obtain the corresponding hardware HDL design files simply by describing P4 programs. For example, Pavel Bena′cek et al. in the article "P4-to-VHDL: Automatic Generation of 100Gbps Packet Parsers" converted the parsing graph described by P4 into synthesizable VHDL code suitable for FPGA implementation through the design, analysis, and experimental results of an abstract packet parser generator. However, this type of work cannot generate corresponding executable configuration information for specific real hardware based on the packet processing flow described by the P4 program.

[0041] In summary, through the above analysis of existing P4 compilation systems and the analysis of other existing compilation platforms, the differences between different compilation platforms are shown in Table 1.

[0042] Table 1 Comparison of Different Compilation Systems

[0043]

[0044] Through comparative analysis, the following limitations of existing P4 compilation systems are obtained:

[0045] First, the existing P4 front-end and back-end compilation systems have weak hardware independence (poor generality). The existing compilation systems are usually strongly associated with specific hardware architectures, that is, a specific P4 compilation system can only be applicable to a specific hardware architecture. Since the Match-Action architecture has different implementation strategies in specific implementation, the same set of compilation systems cannot be simply transplanted to different programmable switches.

[0046] Second, there is a lack of a back-end compilation system developed based on the general open-source P4C compilation front-end. For example, the compilation idea proposed by Lavanya Jose et al. has well solved the mapping problem of the dependency relationship between match table entries to the hardware of P4 programmable switches, but it has not been combined with the general front-end of P4C proposed by the P4 Consortium, lacking support for reducing the threshold of P4 support in the RMT abstract switching plane.

[0047] Third, the current compilation systems have imperfect support for hardware platforms adopting the RMT architecture.

[0048] Fourth, it does not involve the generation stage of hardware configuration. For example, the open-source compiler back-end proposed by Debobroto Das Robin et al. only implements the mapping stage and does not involve the generation stage of specific hardware configuration information.

[0049] In view of this, the present invention deeply analyzes the intermediate representation (IR) obtained by the front end of the compiler (P4C), focuses on studying the manifestation form of the dependency relationship between match tables in the pipeline (Match-Action) unit in the intermediate representation, and combines the abstract match-action dependency directed graph TDG. Based on the open-source P4C general front-end compilation of the P4 consortium, a P4 language compilation system capable of adapting to the Match-Action architecture of RMT is proposed. Through the switch resource constraints specified by the user and the target-independent intermediate representation, the programmable switch configuration information of the Match-Action architecture can be quickly and accurately generated, which can improve the hardware scalability of the existing P4 compilation system, that is, only by obtaining relevant hardware constraints, the configuration information of programmable switches with different structures can be efficiently generated. In addition, the flexibility and generality of the P4 compilation process are also improved.

[0050] Please refer to Figure 3 and Figure 4 , Figure 3 FIG. is a flowchart of a method for configuring reconfigurable match table parameters based on P4 compilation provided by an embodiment of the present invention. Figure 4 FIG. is another flowchart of a method for configuring reconfigurable match table parameters based on P4 compilation provided by an embodiment of the present invention. A method for configuring reconfigurable match table parameters based on P4 compilation provided by the present invention includes:

[0051] S101. Obtain the intermediate representation generated after the P4 program is compiled by the front end of the compiler; wherein, the nodes in the intermediate representation include match nodes and action nodes.

[0052] Specifically, in this embodiment, P4C is a P4 compiler developed by the P4 consortium. As Figure 4 shown, the P4 program can be converted into a hardware-independent intermediate representation, which can be directly loaded into the software simulation switch bmv2 provided by P4C to enable it to have the forwarding and switching functions. However, due to the lack of a compiler backend that depends on specific hardware, the generated intermediate representation cannot be directly loaded into a specific real programmable switch for configuration. The present invention reads the intermediate representation IR (JSON file) generated by P4C and the hardware constraint specification information input by the user, and through the mapping and configuration information generation stages, obtains an executable configuration file for packet processing based on the target hardware, and finally sends it to the target switch through the control plane.

[0053] S102. Obtain the match feature information and action feature information of each node extracted after the compiler backend traverses the nodes in the intermediate representation, obtain the table entry information and action information, and store them in the first structure and the second structure respectively.

[0054] Specifically, in this embodiment, according to the eigenvalue of different types in the intermediate representation, using the recursive idea and regular matching function, extract the matching feature information in the matching node to obtain the entry information, and store it in the first structure, extract the action feature information in the action node to obtain the action information, and store it in the second structure for use in the subsequent configuration information generation stage.

[0055] It should be noted that the parameter extraction function using keyword matching is used to extract the matching feature information and action feature information from the intermediate representation.

[0056] It should also be noted that the regular matching function is used to obtain the entry names in different stages from the intermediate representation obtained from the compilation front end.

[0057] It should also be noted that in this embodiment, the PHV control flow in the intermediate representation is traversed in sequence to ensure that the configuration information is consistent with the description in the source P4 program.

[0058] S103. According to the preset dependency relationship, determine whether there is a dependency relationship in the entry information in the first structure, and determine whether there is a dependency relationship in the action information in the second structure; if so, write it into the dependency relationship structure; if not, analyze the entry information and the action information, and determine whether it meets the preset hardware constraint specification. If it meets, obtain the entry structure information and action instruction information described in the P4 program.

[0059] Specifically, in this embodiment, the stage where step S103 is located is the mapping stage. In the mapping stage, it is required that the user provides the preset hardware constraint specification, and at the same time, the dependency relationship needs to be obtained. Specifically:

[0060] The prerequisite for the compilation system to generate the programmable switch configuration information is that it is necessary to impose the resource constraints and other information of the specific actual hardware. These information are used to guide the compilation system to confirm whether the mapping result of the logical entry can be correctly mapped to the physical matching table, that is, the compilation system must work under the constraints of the target hardware, and at the same time, the configuration information generated by the compilation system must also meet the target hardware constraints. Through the abstraction of the Match-Action structure, the hardware constraints of the Match-Action of the present invention are summarized as the following points:

[0061] Table size: The available memory quantity and size included in the hardware switch. In the RMT architecture, it represents the available TCAM capacity and SRAM capacity.

[0062] Header field size: The bus width carrying the header PHV, and this constraint limits the size and quantity of the headers that the switch can process.

[0063] Match field constraints: Constraints such as the width, format, and quantity of fields participating in the match during the match action phase.

[0064] Action instruction code: The format, width, and maximum quantity of the action instruction code used in the action phase.

[0065] In this embodiment, according to the Match-Action architecture, the general hardware resource constraints in the standardized architecture are defined, and the configuration file boundary is controlled through the standardized resource constraints.

[0066] Before starting the compilation system, the user needs to provide the above necessary hardware constraint specifications. During the process of generating the configuration file, if it is detected that the hardware constraint specifications are exceeded, the system throws an ERROR message to remind the user to check. When the number of parsed action codes exceeds the hardware constraints, an ERROR message will be thrown.

[0067] The most important task in the mapping phase is to analyze the complete dependency relationship from the entry information and action information, and map it reasonably into different match action phases or different Match-Action units.

[0068] Since the RMT architecture supports the concurrency of data packets in different entries to obtain higher transmission rates and greater throughput, but at the same time, it inevitably brings dependency problems. In the Match-Action architecture, the dependency relationships can be summarized into the following four types:

[0069] 1. Match dependency: The match fields in the subsequent pipeline stage are modified by the previous pipeline stage in the action phase, that is, the match stage of the subsequent pipeline stage must start after the action phase of the previous pipeline stage is completed. As shown in Figure 5 shown, Figure 5 is a schematic diagram of the match dependency relationship provided by an embodiment of the present invention.

[0070] 2. Action dependency: The match fields modified in the action phase of the previous pipeline stage are modified again in the subsequent pipeline stage, that is, the action stage of the subsequent pipeline stage must start after the action phase of the previous pipeline stage is completed. As shown in Figure 6 shown, Figure 6 is a schematic diagram of the action dependency relationship provided by an embodiment of the present invention;

[0071] 3. Inheritance dependency: Whether the subsequent pipeline stage is executed depends on the match result of the previous pipeline stage, that is, the actual data flow direction of the subsequent pipeline stage is determined according to the match result of the previous pipeline stage. As shown in Figure 7 shown, Figure 7 is a schematic diagram of the inheritance dependency relationship provided by an embodiment of the present invention.

[0072] 4. Reverse matching dependency: the matching field of the previous pipeline is modified by the subsequent pipeline in the action stage, that is, the action stage of the subsequent pipeline must start after the matching stage of the previous pipeline is completed.

[0073] It should be noted that Figure 5 and Figure 6 Match Stage1 represents the matching stage of the first-level pipeline, Action Stage1 represents the action stage of the first-level pipeline, Match Stage2 represents the matching stage of the second-level pipeline, and Action Stage2 represents the action stage of the second-level pipeline.

[0074] In this embodiment, by obtaining the table entry information and action information from the intermediate representation and analyzing the control flow description of the intermediate representation, the idea of ​​the recursive method is adopted to parse layer by layer to obtain the possible table dependencies under the P4 description to guide the generation of subsequent configuration information.

[0075] In this embodiment, judging whether the entry information in the first structure has a dependency relationship, and judging whether the action information in the second structure has a dependency relationship, includes the following four situations, specifically:

[0076] The matching dependency is explained by analyzing the matching dependency in the P4 program. Any IPv4 longest prefix match (ipv4_lpm) table matches the destination IP address of the message, and executes the IPv4 forwarding (ipv4_forward) action according to the matching result. This action will modify the Layer 2 destination MAC address of the message to match the corresponding forwarding port. At the same time, the push VLAN tag (push_vlan) table matches the Layer 2 destination MAC address of the message, and pushes the corresponding VLAN tag for it before the message is output (implemented by the action vlan_distribution). According to the above description, the destination MAC address field matched by the push VLAN tag (push_vlan) table is modified by the IPv4 longest prefix match (ipv4_lpm) table, so there is a matching dependency between the two tables.

[0077] Furthermore, dependency relationships also exist in the entry information and action information, which will be further illustrated by analyzing the dependency relationships in the entry information and action information. The compiler backend will extract the entry information and action information from the intermediate representation. Specifically, their data structures are entry information table_info = [table_name, match_field, match_type, max_size, table_action], and action information action_info = [action_name, op_type, op_data]. By analyzing the descriptions of the specific operations in the action information under the intermediate representation, there is a corresponding relationship as shown in Table 2 in the P4 program.

[0078] Table 2 Corresponding Relationship between Action Information in P4 and Intermediate Representation

[0079] P4 Program JSON Intermediate Representation action Input / Output "runtime data" Value under the action Class Operation Type "op" Value under the primitives Class Operand Source "type" Value under the parameters Class Operand "value" Value under the parameters Class

[0080] Through the above description, according to the match field (match_filed) in the extracted entry information, combined with the operation type and operands in the action information, if an operation type in the action information is an assignment operation, it means that the header field represented by the operand will be modified in this action stage; and at the same time, if this field appears as a match field in a certain other entry (table), it can be inferred that there is a match dependency relationship between the two. The compiler backend will write the inferred match dependency relationship into the dependency relationship structure for storage, which is used to guide the subsequent configuration information generation stage.

[0081] For action dependencies, if the same header field is modified in different action stages, or the header field modified in the action stage of the previous pipeline stage participates in the action stage of the subsequent pipeline stage, and the action stage of the previous pipeline stage and the action stage of the subsequent pipeline stage do not belong to the same entry information, it is confirmed that there is an action dependency relationship. The compiler backend will write the inferred action dependency relationship into the dependency relationship structure for storage, which is used to guide the subsequent configuration information generation stage. The essence of the action stage is the repeated access or modification of the same header field. In some programmable switches, there may be a parallel situation in the multi-level matching action (Match-Action) stage. In this case, action dependencies need to be properly resolved, otherwise it will lead to incorrect processing of data packets. The problem of dealing with action dependencies belongs to the specific programmable hardware design problem and is not within the scope of consideration of the present invention.

[0082] For inheritance dependencies, it involves the branch processing of data packets in the Match-Action pipeline. As shown below, it is a control flow described by the P4 program. After being mapped to the Match-Action architecture, this control flow essentially represents the branch processing operation of data packets. According to the RMT architecture description, there will be a certain field in the matching domain to identify the ID information of the next table entry that the data packet will enter. At the switch hardware level, there is the ability to perform table entry branch processing. The control plane only needs to fill different matching domains in the switch to guide the branch processing of data packets within the switch. The control flow (apply) indicates that the switch will first check whether the header has the control_packet field of the header control and whether it is valid. If it is valid, the packet will enter match_control_packet for matching operations; otherwise, the packet will enter ipv4_lpm for the longest prefix match. At the same time, if the longest prefix match is hit, the packet will further execute the ipv4_nexthop table to set the next-hop address; otherwise, the packet will simply flow through this stage of the Match-Action.

[0083] Similarly, this dependency will also be reflected in the JSON intermediate representation. The description of the control flow in the intermediate representation has the corresponding relationship with the P4 program as shown in Table 3. JSON represents each branch node in the P4 program as a "node", and the specific branch condition is represented by the value under the expression class; at the same time, "ture_next" and "false_next" are used to indicate different branch paths, and the table entries to be matched under different branch paths can be obtained through the value under this class.

[0084] Table 3 Corresponding relationship of the apply control flow in P4 and JSON

[0085]

[0086]

[0087] The compiler backend will, from the jump conditions under the conditionals class in the intermediate representation, through the idea of recursion, call the same analysis process to obtain the information of each branch path. Through the above description, according to the branch condition (branch_condi) and branch path (branch_path) fields in the extracted branch information, the branch processing situation of the data packet under this P4 description can be inferred to obtain the inheritance dependency relationship. The compiler backend will write the inferred inheritance dependency relationship into the dependency relationship structure for storage, which is used to guide the subsequent configuration information generation stage.

[0088] Through the above description, the compilation system implemented by the present invention has successfully obtained the entry structure information, action instruction information in the Match-Action structure, and the possible dependencies in the Match-Action structure from the P4 description. These results will be passed backward as the mapping relationship in the mapping phase to guide the operation of the configuration information generation phase.

[0089] S103. Obtain the configuration information generated by the compiler backend according to the dependencies in the dependency structure, as well as the entry structure information and action instruction information described in the P4 program, and send the configuration information through the control plane.

[0090] Specifically, in this embodiment, after obtaining the configuration information mapping relationship formed in the mapping phase, the compilation system will enter the configuration generation phase to generate the configuration information of the specific actual hardware. This phase mainly relies on the hardware constraint information defined by the user to generate the entry configuration information of the corresponding Match-Action hardware switch and the action code information that conforms to the hardware requirement format. At the same time, it will also determine how to allocate the entries of each level of Match-Action according to the dependency relationship between the entries obtained in the mapping phase.

[0091] The present invention first abstracts the RMT architecture and obtains the general hardware constraint specification of the Match-Action structure under the RMT architecture. The specific constraint content is shown in Table 4.

[0092] Table 4 Match-Action Hardware Constraint Information

[0093]

[0094]

[0095] After obtaining the hardware constraints and the entry action information and dependencies of the P4 description obtained in the mapping phase, the generation of the configuration information can be started.

[0096] In the configuration information generation phase, if it is detected that there are dependencies in the mapping phase, the compiler backend will, according to the existing dependencies, enable the corresponding generation function to avoid dependency problems. For matching dependencies, the operation result of the current matching action Match-Action core will affect the operation of the matching Match phase of other cores. At this time, the configurations of the two cores have to be placed in two different matching action Match-Action phases respectively, and the execution order between the two phases determines the order of the configuration information to ensure that the correct value can be obtained when the subsequent core performs the matching operation. At the same time, the compiler backend obtains the configuration information based on the target hardware according to the hardware constraints defined by the user.

[0097] It should be noted that a real hardware switch only needs to have a general bus protocol interface such as AXI, and receive the bus protocol configuration information sent by a general-purpose processor CPU to complete the distribution of the configuration information. The configuration information generated by the compilation system will be used as command parameters in the configuration program of the general-purpose processor. After the configuration information is sent to the real hardware switch through the CPU, it will enter the decoding logic inside the switch for address decoding and instruction code decoding, and finally complete the configuration of various registers and memories. After that, the programmable switch can process data packets according to the rules described by P4. The process of this compilation system is as Figure 8 shown.

[0098] It should be noted that the system is divided into a mapping stage and a configuration stage. Each stage operates with different source inputs, enabling the two stages to work independently and improving the decoupling ability of the system.

[0099] It also should be noted that dependency analysis is performed in the configuration stage to generate customized configuration information to avoid dependency problems. In the configuration information generation stage, the sorted dependency relationships are read in, and the table entries with matching dependency relationships are divided into different processing units through configuration, solving the dependency problems from the front end of the process and relieving the hardware design pressure.

[0100] In summary, a method for configuring reconfigurable match table parameters based on P4 compilation provided by the present invention can interface with a general P4 compilation front end. Using the idea of the recursive method for the intermediate representation of the front end, the compilation system can adapt to different Match-Action hardware implementations in a general way to obtain configuration information as much as possible. This improves the generality and flexibility of the P4 compilation environment.

[0101] Based on the same inventive concept, the present invention also provides a system for configuring reconfigurable match table parameters based on P4 compilation, which is used to implement the method for configuring reconfigurable match table parameters based on P4 compilation provided in the above embodiments of the present invention. The embodiments of the method can be referred to above and will not be elaborated here; the system includes:

[0102] A compiler front-end module, which is used to obtain the intermediate representation generated after the P4 program is compiled by the compiler front end; wherein, the nodes in the intermediate representation include match nodes and action nodes;

[0103] The mapping module in the compiler backend module is used to obtain the matching feature information and action feature information of each node extracted after the compiler backend traverses the nodes in the intermediate representation, respectively obtain the entry information and action information, and store them in the first structure and the second structure respectively; according to the preset dependency relationship, judge whether there is a dependency relationship in the entry information in the first structure, and judge whether there is a dependency relationship in the action information in the second structure; if there is, write it into the dependency relationship structure; if not, analyze the entry information and action information, and judge whether it conforms to the preset hardware constraint specification, if it conforms, obtain the entry structure information and action instruction information described by the P4 program;

[0104] The configuration generation module in the compiler backend module is used to obtain the configuration information generated by the compiler backend according to the dependency relationship in the dependency relationship structure, as well as the entry structure information and action instruction information described by the P4 program, and send the configuration information through the control plane.

[0105] In an optional embodiment of the present invention, the effect of the reconfigurable match table parameter configuration method based on P4 compilation provided in the above embodiment is verified through a simulation experiment, specifically:

[0106] I. Simulation conditions

[0107] The simulation experiment conditions of this embodiment are as follows Figure 9 shown Figure 9 is a schematic diagram of the MAU structure of the network processor provided by the embodiment of the present invention. The MAU in the NP network processor is selected for the experiment. The main function of this MAU is to send the network data packet header vector PHV into the match-action core for matching and modifying the PHV. The main function of a series of match-action pipeline stages in the MAU is to implement the processing flow of the data packet described by the P4 language. There is a configuration plane interface in the MAU system, which can receive different configuration information to make the MAU programmable and implement different packet processing functions.

[0108] In this embodiment, the user-defined constraints for this MAU are shown in Table 5. The received PHV width is 2048 bits, the maximum number of match-action stages is 8, the exact match width is 24 bits, the TCAM ternary match width is 16 bits, the instruction code width is 50 bits, the maximum number of instructions is 64, and the number of TCAMs is 2.

[0109] Table 5 MAU target hardware constraints

[0110] Constraint Constraint Condition PHV_WIDTH 2048 MAX_STAGE 8 EXTRACT_MATCH_WIDTH 24 TCAM_MATCH_WIDTH 16 RULE_WIDTH 50 RULE_NUMBER 64 TCAM_NUMBER 2

[0111] II. Simulation Content and Result Analysis

[0112] In this embodiment, the MPLS switch scenario is selected for verification. The MPLS switch is required to be able to forward according to the MPLS label of the packet, and at the same time be able to perform related modification operations on the MPLS label of the packet. The following functions are verified in this embodiment:

[0113] 1. Replace the MPLS label: Set the Label of the non-last label with the label value Label of 20’h0_0020 to 20’h0_0040, and use the changed Label field for forwarding;

[0114] 2. Pop the last MPLS label: Delete the last label with Label of 20’h0_20_20, change the frame type field to an IPv4 packet (assuming that the network layer protocol of this label is known to be IPv4), forward using the Label field of the MPLS label before popping, and forward the remaining packets using the Lablel field of the outermost MPLS label;

[0115] First, write a P4 program for MPLS operations to describe the processing operations of data packets. Define the action of pushing and adding an MPLS label push_mpls_lable, which is used to modify or push the MPLS label in the packet. Define the action of popping and deleting the MPLS label popup_mpls_lable, which is used to pop the MPLS label of the packet and at the same time change the frame type field to an IPv4 packet (type 0x0800). Define the match table push_mpls, which stipulates that for packets with the label value Lable1 of 20’h0_0020, the mpls label value is modified to 20’b0_0040; for packets with the label value Lable1 of 20’h0_2020, the MPLS label value is popped, and at the same time the frame type field is changed to an IPv4 packet. If a successful match is made, the corresponding MPLS modification operation is executed.

[0116] As Figure 10 shown, Figure 10 is a flowchart of generating configuration information by compiling the match action unit MAU P4 provided by the embodiment of the present invention. According to the process shown in Figure 10 , the P4 description is given to the compilation system, converted into an intermediate representation and then analyzed by the compiler backend. After the mapping stage and the configuration information generation stage, the configuration information of the match action Match-Action in each stage is output.

[0117] The obtained configuration information at each stage is sent by the CPU to the config_controller unit of the specific hardware control plane through a general bus protocol such as AXI for address decoding operations, and then input into the MAU. The MAU receives the configuration information, and through the configuration information processing unit, controls the distribution of information to the internal memory and storage, and sends the corresponding PHV message to verify that the MAU can modify and pop the MPLS field according to the P4 description. The structure of the configuration information processing unit is as Figure 11 shown, Figure 11 which is a schematic diagram of the configuration information processing unit provided by an embodiment of the present invention, and uses a hierarchical decoding method to process the configuration information.

[0118] After checking the configuration result of the MAU after the configuration information generated by the compilation system enters the MAU, it should be noted that the verification platform design only prints the first 10 pieces of configuration information, as Figure 12 shown, Figure 12 which is a schematic diagram of the MAU configuration result provided by an embodiment of the present invention.

[0119] After that, the set PHV message is input into the MAU, and the operation result of its MPLS label is checked, as Figure 13 and 14 shown, Figure 13 which is a schematic diagram of the MPLS label modification result provided by an embodiment of the present invention, Figure 14 which is a schematic diagram of the MPLS label pop result provided by an embodiment of the present invention. After matching the Lable value of 20’b0_0020, the message will modify the Lable to 20’b0_0040 and then output after passing through the MAU; at the same time, after matching the Lable value of 20’b0_2020, all MPLS labels will be popped, and the frame type field will be modified to the IPv4 type (0x0800).

[0120] In addition, in this embodiment, a total of 253 configuration information distributions and writes are completed in the entire configuration plane, which takes a total of 2550 ns. Combining with the 10 ns clock cycle of the system, the present invention proposes that the configuration system can achieve the distribution of one configuration item per clock cycle. If the throughput rate of the configuration system is T_config, the throughput rate can reach:

[0121] T config = 64 bit × 100 MHz = 6400 Mbps;

[0122] After exploring the frequency upper limit in the subsequent synthesis steps of the system, the throughput rate of the configuration part will be even more remarkable. Compared with traditional serial configuration interfaces such as UART or JTAG, it has great advantages in terms of throughput rate.

[0123] In summary, a method and system for reconfigurable match table parameter configuration based on P4 compilation provided by the present invention have the following beneficial effects:

[0124] 1. The P4 compilation system proposed by the present invention has high flexibility and strong generality, and can be adapted to different Match-Action hardware implementations; by abstracting the Match-Action structure, summarizing the hardware specification constraints required by the actual hardware, and combining with the open-source P4 compilation front-end, based on the latest version of the P4 language (P416), using the idea of the recursive method, extracting the characteristic information of the intermediate representation, generating the configuration information of the Match-Action structure, and not restricting the application scenario. The P4 compilation system method proposed by the present invention is applicable to any Match-Action architecture field based on the RMT model. Compared with the existing methods, it has a certain wide applicability.

[0125] 2. Adapt to the open-source P4C compilation front-end; using the intermediate representation generated by the open-source P4 compilation front-end as the input of the compilation back-end can greatly improve the generality and portability of the compilation system. Different from other compilation systems that use proprietary compilation front-ends resulting in low portability, it also reduces the threshold for switches to support P4 programmability.

[0126] 3. Analyze the possible different dependencies between the matching action stages from the intermediate representation to guide the configuration information generation stage; avoid dependency problems through the distribution of configuration information at the configuration level to reduce the pressure on hardware processing.

[0127] 4. Use the idea of the recursive method rather than the distributed idea to generate configuration information; for different hardware configurations in different Match-Action structures, analyze the intermediate representation by reusing the same function, and there will not be too many different analysis functions resulting in low efficiency of the compilation system. Compared with the existing methods, as the hardware implementation of Match-Action becomes more and more complex, if different function methods are used in each configuration generation stage, it will lead to a large amount of resource consumption, thus affecting the execution efficiency of the compilation system.

[0128] 5. Can be extended to the front-end parser and the back-end inverse parser; for the front-end parser and the back-end inverse parser of the Match-Action pipeline, there are also hardware resources that need to be configured in advance. The method proposed by the present invention is still applicable to the parser and the inverse parser. As long as the hardware has a control plane with an interface of a general bus protocol such as AXI, the method proposed by the present invention can be transplanted to the parser or the inverse parser.

[0129] 6. High throughput configuration rate: Since the present invention distributes configurations through a general-purpose CPU and a general-purpose high-speed bus such as AXI, it has a natural advantage in terms of configuration rate. Compared with the serial configuration interface, the configuration rate can reach a throughput rate of the gigabit level, improving the configuration efficiency of the packet switching data plane.

[0130] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the article or device comprising the element. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0131] In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0132] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A reconfigurable matching table parameter configuration method based on P4 compilation, characterized in that: include: Obtaining an intermediate representation generated after the P4 program is compiled by the compiler front end; wherein the nodes in the intermediate representation include matching nodes and action nodes; Obtain matching feature information and action feature information of each node extracted by the compiler backend after traversing the nodes in the intermediate representation, obtain table entry information and action information, and store them in the first structure and the second structure respectively; According to the preset dependency relationship, determine whether the table item information in the first structure has a dependency relationship, and determine whether the action information in the second structure has a dependency relationship; if so, write it into the dependency structure; if not, analyze the table item information and the action information, and determine whether they meet the preset hardware constraint specification, if so, obtain the table item structure information and action instruction information described by the P4 program; According to the dependency relationship in the dependency relationship structure, and the table entry structure information and action instruction information described by the P4 program, the configuration information generated by the compiler backend is obtained, and the configuration information is sent down through the control plane.

2. The reconfigurable matching table parameter configuration method based on P4 compilation according to claim 1 is characterized in that: The obtaining of matching feature information and action feature information of each node extracted by the compiler backend after traversing the nodes in the intermediate representation, obtaining table entry information and action information respectively, and storing them in the first structure and the second structure respectively, includes: According to the feature values ​​of different classes in the intermediate representation, using recursive ideas and regular matching functions, the matching feature information in the matching node is extracted to obtain the table item information and store it in the first structure; the action feature information in the action node is extracted to obtain the action information and store it in the second structure.

3. The reconfigurable matching table parameter configuration method based on P4 compilation according to claim 1 is characterized in that: The preset hardware constraint specifications include table size, header field size, matching field constraints and action instruction codes.

4. The reconfigurable matching table parameter configuration method based on P4 compilation according to claim 1 is characterized in that: The preset dependency relationships include matching dependency, action dependency, inheritance dependency and reverse matching dependency; wherein, The matching dependency includes that the matching field of the subsequent pipeline is modified by the previous pipeline in the action phase; The action dependency includes that the matching field modified by the previous pipeline in the action phase is modified again in the subsequent pipeline; The inheritance dependency includes whether the execution of the subsequent pipeline depends on the matching result of the previous pipeline; The reverse matching dependency includes that the matching field of the previous pipeline is modified by the subsequent pipeline in the action stage.

5. The reconfigurable matching table parameter configuration method based on P4 compilation according to claim 1 is characterized in that: The determining whether the entry information in the first structure has a dependency relationship, and determining whether the action information in the second structure has a dependency relationship, includes: According to the matching field in the table entry information in the first structure, combined with the operation type and operand in the action information in the second structure, if an operation type in the action information is an assignment operation, it means that the header field represented by the operand will be modified in the action stage, and at the same time, the header field appears as a matching field in a certain table entry information, then it is confirmed that a matching dependency exists.

6. The reconfigurable matching table parameter configuration method based on P4 compilation according to claim 1, characterized in that: Determining whether the entry information in the first structure has a dependency relationship, and determining whether the action information in the second structure has a dependency relationship, includes: If the same header field is modified in different action stages, or the header field modified in the action stage of the previous pipeline will participate in the action stage of the next pipeline, and the action stage of the previous pipeline and the action stage of the next pipeline do not belong to the same table entry information, then it is confirmed that there is an action dependency.

7. The reconfigurable matching table parameter configuration method based on P4 compilation according to claim 1 is characterized in that: The determining whether the entry information in the first structure has a dependency relationship, and determining whether the action information in the second structure has a dependency relationship, includes: From the table entry information in the first structure and the jump condition class in the action information in the second structure, through the idea of ​​recursion, call the same analysis process to obtain the information of each branch path, and extract the branch condition and branch path fields in the branch information, infer the branch processing situation, and confirm the existence of inheritance dependency.

8. The reconfigurable matching table parameter configuration method based on P4 compilation according to claim 1 is characterized in that: The configuration information includes table entry configuration information and action code information, as well as the allocation of entries in table entries of each level of pipeline.

9. The reconfigurable matching table parameter configuration method based on P4 compilation according to claim 1, characterized in that: According to the preset dependency relationship, determining whether the entry information in the first structure has a dependency relationship, and determining whether the action information in the second structure has a dependency relationship; If it exists, after being written into the dependency structure, it also includes: The compiler backend starts the corresponding generated functions according to the dependencies stored in the dependency structure to avoid dependency problems.

10. A reconfigurable matching table parameter configuration system based on P4 compilation, characterized in that: include: A compiler front-end module, used to obtain an intermediate representation generated after the P4 program is compiled by the compiler front-end; wherein the nodes in the intermediate representation include matching nodes and action nodes; The mapping module in the compiler backend module is used to obtain the matching feature information and action feature information of each node extracted by the compiler backend after traversing the nodes in the intermediate representation, obtain the table item information and the action information, and store them in the first structure and the second structure respectively; according to the preset dependency relationship, determine whether the table item information in the first structure has a dependency relationship, and determine whether the action information in the second structure has a dependency relationship; if so, write them into the dependency relationship structure; if not, analyze the table item information and the action information, and determine whether they meet the preset hardware constraint specifications, and if so, obtain the table item structure information and action instruction information described by the P4 program; The configuration generation module in the compiler backend module is used to obtain the configuration information generated by the compiler backend according to the dependency relationship in the dependency structure, the table structure information and the action instruction information described by the P4 program, and send the configuration information through the control plane.

Images