Optimization system and method based on register file N-modular redundancy scheme
By adding voting machines and error correction circuits to each multimode redundant module, parallel read and write operations of multiple redundant modules and correcting flip errors in real time, the problem of register flip error accumulation in traditional solutions is solved, and the reliability and performance of the processor is improved.
Patent Information
- Application Number
- CN202510165272.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-14
- Publication Date
- 2025-06-20
AI Technical Summary
In complex spatial environments, traditional multi-mode redundancy schemes are difficult to effectively reduce the accumulation of register flip errors, resulting in the impact of processor reliability and performance.
By adding voting and error correction circuits to each multimode redundant module, parallel read and write operations of multiple redundant modules are realized, and flip errors in registers are corrected in real time.
It reduces the delay in table entry decision output, avoids the accumulation of flip errors, improves the reliability and stability of the system, while maintaining low resource usage and delay increase.
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Figure CN120179289A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of computer storage, and particularly to an optimized system and method based on an N-modular redundancy scheme of a register file. Background Art
[0002] In space, a space computer faces a complex space environment, including forces, heat, space radiation, etc., which may all cause failures. In addition to space radiation, the space environment also includes a vacuum environment, a thermal environment, and complex environmental impacts such as atomic oxygen and space debris. These space environments can cause permanent and instantaneous intermittent failures in electronic computers and electronic devices. Therefore, it is particularly important to use fault-tolerant technology to avoid the failures caused by the space environment to electronic computers.
[0003] As an important storage component inside a processor, the data stored in a register has the characteristic of long storage time. Therefore, the fault-tolerant ability of the register plays a crucial role in the normal and stable operation of the entire processor. When facing a complex space environment, high-energy particles in space can easily cause the register to have a flip error, which in turn causes a permanent or instantaneous intermittent failure of the electronic computer processor. If a flip error occurs in the data stored in the register bank formed by the register array, that is, a phenomenon where a certain bit in the data changes from 0 to 1 or from 1 to 0, it will directly affect the correctness of the data and the reliability of the entire processor.
[0004] To improve the reliability of the processor, designers can choose different backup schemes for deployment. However, increasing the backup will lead to an increase in path delay, which may seriously affect the performance of the processor. In addition, since the register is located at a critical position in the transmission line, the requirements for fault-tolerant design are even more stringent.
[0005] Such as Figure 4As shown in the figure, when designing a multi-mode redundancy scheme, it usually consists of N subsystems and a voter, that is, an arbiter makes decisions on the entries output by multiple subsystems. When making decisions, the voter takes the majority of the entries as the output of the system. Since a voter needs to make decisions on the outputs of multiple subsystems, the output delay is relatively high. And when there are multiple different entries to be output, they need to queue up for output. Also, traditional multi-mode redundancy schemes usually do not correct the flip errors of the voter, or correct them through the voter. For the former, if the flip errors of the voter are not corrected, the flip errors will accumulate and cause the entire system to crash. For the latter, only when the entry with flip errors is read out can the error correction check be completed. If the entries in the register have been in an unaccessed state, the entries cannot pass through the voter, then the flip errors will accumulate. For example, in a triple-module redundancy scheme, (A, B, C) is the same entry stored in the registers of different redundant modules. If the A entry has a flip error and is not corrected, after a period of time, the B entry will also have a flip error, which will cause the voter to fail.
[0006] Taking the read operation as an example, when performing a read operation, there are decoding delay, entry selection delay, entry output delay, voting delay, etc. And since the traditional multi-mode redundancy scheme runs serially, the above delays will eventually accumulate, resulting in a relatively high delay for the read operation. Summary of the Invention
[0007] The present invention provides an optimized system and method based on an N-module redundancy scheme of a register file to solve the above-mentioned deficiencies of the prior art. The aim is to reduce the delay of the critical path by performing read and write operations in parallel by multiple redundant modules and increasing the number of voters, and to ensure the fault tolerance performance of the redundant modules and the normal and stable operation of the processor.
[0008] In order to achieve the object of the present invention, the following technologies are proposed: An optimized system based on an N-module redundancy scheme of a register file, including a decoder module, a multi-mode redundancy module and a read selector module. The decoder module is respectively connected to the multi-mode redundancy module and the read selector module, the multi-mode redundancy module is connected to the read selector module. The multi-mode redundancy module has multiple multi-mode redundancy sub-modules, and each multi-mode redundancy sub-module contains a register bank composed of multiple registers; During the write operation; The decoder module is used to decode the write index signal into the corresponding register number in the multi-mode redundancy module, and each register number corresponds to a register bank one by one. The register number is used to guide the write data signal to be input into the register bank corresponding to the register number in the multi-mode redundancy module at the rising edge of the clock; During the read operation: The multi - mode redundancy module is used to output the data in each multi - mode redundancy sub - module to the read selector module. The decoder module is used to decode the read index signal into the register number corresponding to that in the multi - mode redundancy module. The read selector module is used to select the data of the register group corresponding to the decoded register number from the data output by the multi - mode redundancy module for output; The read / write operation of the data is completed within one clock cycle.
[0009] Further, the multi - mode redundancy module has 2 to 32 multi - mode redundancy sub - modules.
[0010] Further, the decoder module is used to decode a 5 - bit write / read index signal into the corresponding 32 - bit register number in the multi - mode redundancy module.
[0011] Further, the multi - mode redundancy sub - module further includes a multi - mode entry group, a voter, an error - correction circuit, and a write selector module; The multi - mode entry group contains multiple entries, and one entry is the data stored in one of the registers in the register group corresponding to the multi - mode entry group; The voter is used to make a decision on multiple entries in the multi - mode entry group within the corresponding multi - mode redundancy sub - module; In the read operation, according to the register number decoded by the decoder module, the entry in the register corresponding to the register number is read out, and the obtained entry is input to the voter for decision on whether it is used as the output; The error - correction circuit corrects and updates the flip errors that occur in the entries stored in the register in real - time in the next clock cycle; The write selector module selects the corresponding register according to the register number corresponding to the multi - mode redundancy module decoded by the decoder module, and writes the data into the register corresponding to the register number; And is used to receive the decision issued by the voter, and select the corresponding entry as the system output according to the decision of the voter, And is used to receive the flip errors corrected and updated by the error - correction circuit, and write the corrected and updated entry into the corresponding register according to the entry where the flip error is located.
[0012] Further, when N is equal to 2, a check - code module is further included. When the write data signal is input, the check - code module generates a check - code through exclusive - OR operation and attaches the generated check - code to the write data signal. When the data is output, it is used to detect whether the output data has an error.
[0013] An optimization method for an N - modular redundancy scheme based on a register file, using an optimization system for an N - modular redundancy scheme based on a register file. When N is greater than or equal to 3, it includes the steps: Step 01, obtaining the read / write index signal; When the acquired index signal is a write index signal, the write data signal matching the write index signal is acquired simultaneously; Step 02: The decoder module decodes the read / write index signal acquired in step 01, and decodes the acquired read / write index signal into the register number in the multi-mode redundancy module corresponding to the acquired read / write index signal; Step 03: If the signal acquired in step 01 is a write index signal, according to the register number obtained by decoding by the decoder module, the write selector in each multi-mode redundancy sub-module in the multi-mode redundancy module is used to select the register corresponding to the register number, and the write data signal is written into the corresponding register; If the signal acquired in step 01 is a read index signal, access the multi-mode redundancy module, and acquire multiple entries corresponding to the register number obtained by decoding in step 02 in multiple multi-mode redundancy sub-modules; Step 04: If the signal acquired in step 01 is a read index signal, make a decision on the multiple entries acquired in step 03 through a voter; Step 05: If when the voter makes a decision on multiple entries in step 04 and it is known that some of the entries have flip errors, the error correction circuit corrects and updates the entries with flip errors in the next clock cycle with the entry output by the decision of the voter in step 04 for the entries with flip errors; If when the voter makes a decision on multiple entries in step 04 and it is known that all entries do not have flip errors, execute step 06; Step 06: If the signal acquired in step 01 is a read index signal, the read selector module outputs the entry after the decision in step 04 according to the register number corresponding to the acquired read index signal.
[0014] Further, when multiple entries are decided by the voter in step 04, the voter in each multi-mode redundancy sub-module corresponding to each entry makes a decision on the corresponding entry.
[0015] Further, when the voter makes a decision on the output of the output entry in step 04, select the decision of the majority of the same entries as the output entry.
[0016] Further, when determining whether there is a flip error in the entry in step 05, the voter writes the flip error flag bits of each entry into the error correction circuit; If the values of the flip error flag bits of all entries are 1, it indicates that the entry decided by the voter has no flip error; If the flip error flag values of several table entries are 0, it indicates that there are flip errors in several table entries among the table entries decided by the voter, and the error correction circuit is triggered. The error correction circuit uses the table entries decided by the voter as the write error correction data signal and writes the write error correction data signal into the register with flip error data, so as to update and correct the table entries with flip errors.
[0017] An optimization method based on the N-modular redundancy scheme of the register file, using an optimization system based on the N-modular redundancy scheme of the register file. When N is equal to 2, it includes the following steps: Step a, obtain read / write index signals; If the obtained index signal is a write index signal, simultaneously obtain the write data signal matching the write index signal, and the checksum module attaches the checksum generated by the checksum module to the write data signal; Step b, the decoder module decodes the read / write index signals obtained in step a, and decodes the obtained read / write index signals into the register numbers in the multi-modular redundancy module corresponding to the obtained read / write index signals; Step c, if the signal obtained in step a is a write index signal, according to the register numbers decoded by the decoder module, select the registers corresponding to the register numbers through the write selectors in the two multi-modular redundancy sub-modules in the multi-modular redundancy module, and write the write data signal into the corresponding registers, and make the data stored in one register as the main table entry and the data stored in the other register as the backup table entry; If the signal obtained in step a is a read index signal, access the multi-modular redundancy module, and obtain the main table entry and the backup table entry corresponding to the register numbers decoded in step b in the two multi-modular redundancy sub-modules; Step d, if the signal obtained in step a is a read index signal, verify whether the checksums attached to the two table entries obtained in step c are consistent through the checksum matching module in the voter; If the checksums attached to the main table entry or the backup table entry are consistent, select the main table entry or the backup table entry through the table entry selection module in the voter and output it to the read selector module; If the checksums attached to the main table entry or the backup table entry are inconsistent, select the main table entry or the backup table entry with the checksum consistent with the checksum generated by the checksum module through the table entry selection module in the voter and output it to the read selector module; Step e, if the checksums attached to the main table entry or the backup table entry in step d are inconsistent, the error correction circuit corrects and updates the main table entry or the backup table entry with the attached checksum and the main table entry or the backup table entry with inconsistent checksum generated by the checksum module according to the output table entry selected by the voter as the corrected table entry.
[0018] The advantages of the above technical solution are as follows: In the present invention, by increasing the number of voters, specifically, by correspondingly setting a voter and an error correction circuit in each multi-mode redundancy module, when the table entry is output, not only the delay of the table entry decision output is reduced, but also the data stored in the register can be corrected and updated according to the decision result through the error correction circuit, so as to avoid the accumulation of flip errors resulting in the failure of the voter. In the dual-mode redundancy scheme, by attaching a check code to the table entry and verifying it through the voter as the output table entry, and the table entry with flip errors can also be corrected and updated through the error correction circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings.
[0020] Figure 1 FIG. shows the structural diagram of an optimized system based on the N-mode redundancy scheme of the register file.
[0021] Figure 2 FIG. shows the structural diagram of the multi-mode redundancy module.
[0022] Figure 3 FIG. shows the error correction flow chart of the error correction circuit.
[0023] Figure 4 FIG. shows the structural schematic diagram of the existing redundancy system (TMR scheme). DETAILED DESCRIPTION OF THE EMBODIMENTS
[0024] As Figure 1 shown, an optimized system based on the N-mode redundancy scheme of the register file includes a decoder module, a multi-mode redundancy module and a read selector module. The decoder module is respectively connected to the multi-mode redundancy module and the read selector module. The multi-mode redundancy module is connected to the read selector module. The multi-mode redundancy module has a plurality of multi-mode redundancy sub-modules. The multi-mode redundancy sub-module contains a register bank composed of a plurality of registers. Specifically, the multi-mode redundancy module has 2 to 32 multi-mode redundancy sub-modules arranged in parallel. When the multi-mode redundancy module has 2 multi-mode redundancy sub-modules, a check code module is further included. When the write data signal is input, the check code module generates a check code through exclusive OR operation and attaches the generated check code to the write data signal. When the data is output, it is used to detect whether the output data has an error.
[0025] During the write operation: The decoder module is used to decode the write index signal into the corresponding register number in the multi-mode redundancy module, and each register number corresponds to a register bank one by one. The register number is used to guide the write data signal to be input into the register bank corresponding to the register number in the multi-mode redundancy module at the rising edge of the clock.
[0026] During the read operation: The multi-mode redundancy module is used to output the data in each multi-mode redundancy sub-module to the read selector module. The decoder module is used to decode the read index signal into the corresponding register number in the multi-mode redundancy module. The read selector module is used to select the data of the register bank corresponding to the decoded register number from the data output by the multi-mode redundancy module for output.
[0027] Specifically, the decoder module is used to decode the 5-bit write / read index signal into the corresponding 32-bit register number in the multi-mode redundancy module.
[0028] And the read / write operation of the above data is completed within one clock cycle.
[0029] More specifically, the multi-mode redundancy sub-module further includes a multi-mode entry group, a voter, an error correction circuit, and a write selector module.
[0030] The multi-mode entry group contains multiple identical entries, and one entry is the data stored in one of the registers in the register bank corresponding to the multi-mode entry group. The voter is used to make decisions on multiple entries in the multi-mode entry group corresponding to the multi-mode redundancy sub-module. When the multi-mode redundancy module has 2 multi-mode redundancy sub-modules, the voter contains a check code matching module and an entry selection module. Among them, the check code matching module is used to match the consistency between the check code attached to the entry and the check code given by the check code module, and the entry selection module is used to output the selection of the entry.
[0031] During the read operation, the entry in the register corresponding to the register number decoded by the decoder module is read out, and the obtained entry is input into the voter to make a decision whether to be used as the output.
[0032] The error correction circuit corrects and updates the flip errors that occur in the entries stored in the register in the next clock cycle in real time.
[0033] The write selector module selects the corresponding register according to the register number corresponding to the multi-mode redundancy module decoded by the decoder module, and writes the data into the register corresponding to the register number. And it is used to receive the decision issued by the voter, and select the corresponding entry as the system output according to the decision of the voter. And it is used to receive the flip errors corrected and updated by the error correction circuit, and write the corrected and updated entry into the corresponding register according to the entry where the flip error is located.
[0034] Compared with the existing multi - mode redundancy scheme, this system first increases the number of voters, and each voter corresponds to a multi - mode entry group. That is, each voter only makes decisions on the entries in its multi - mode redundancy sub - module, and the voter outputs the decision result as the target entry, as described in Formula 1, where {Xi, Yi, Zi} represents a multi - mode redundancy group, Voter represents the voter, and T represents the output of this multi - mode redundancy sub - module.
[0035] T = [Voter[X0, Y0, Z0], Voter[X1, Y1, Z1]...Voter[Xi, Yi, Zi]] (Formula 1) where i ∈ (0, 1, 2...31).
[0036] Through the above description and Figure 1 and Figure 2 as shown, it can be seen that since each multi - mode redundancy sub - module contains a voter, and the decision - making executions of each voter are independent of each other, and the multiple identical entries stored in each multi - mode redundancy sub - module, namely {Xi, Yi, Zi,...}, when performing entry output, each voter in each multi - mode redundancy sub - module makes decisions on the multiple identical entries it contains, and selects the majority of the identical entries as the output entry to output to the read selector module. When performing a read operation, the selection execution of the read selector module and the decision - making of the output entries of each multi - mode redundancy sub - module are parallel, so the latency during the read operation is reduced, and each voter only responsible for the decision - making in its multi - mode redundancy sub - module, thus reducing its load. In addition, the method proposed in this embodiment can actively correct the flip errors of the entries during decision - making, so it can ensure that each entry in the multi - mode entry group will not have flip error problems, thus avoiding the problem of error accumulation, and further improving the reliability and stability of the system.
[0037] It is difficult to perform real-time error correction on each register because the same register is distributed in different backups and all registers share a voter. Adding a real-time error correction mechanism to each register would result in a large amount of area and power consumption, offsetting the advantages of the system proposed in this embodiment. Therefore, to improve the fault tolerance performance, this embodiment designs a structure of a multi-mode entry group, that is, placing the same registers in a multi-mode redundancy sub-module to form a multi-mode entry group, and through a one-to-one decision output method and also being able to cooperate with the results of the voter and the error correction circuit to correct flipped errors, so that there are no flipped errors in the entries in each multi-mode redundancy sub-module, or even if there are flipped errors during each read operation, after a read operation is completed, due to the update and correction of the entries by the error correction circuit, the flipped errors contained in each multi-mode redundancy sub-module are reduced to avoid the problem of the accumulation of flipped errors.
[0038] Take Figure 3 as an example. The write enable signal and write data signal are represented by rd_sel and rd_data_i, and the output entry is represented by rs_data_o. In the multi-mode entry group, first, the parameters of each entry are initialized. When the rd_sel signal is 1, the data of rd_data_i is written into each multi-mode redundancy sub-module. When a new entry is written, it will trigger the voter and perform a vote, and the target entry will be used as the output according to the read index.
[0039] When none of the three entries have flipped errors, that is, the values of FLAG1, FLAG2, and FLAG3 are all 1, where FLAG1, FLAG2, and FLAG3 represent the values of the flipped error flag bits. At this time, Xi is output as the target entry, and the matching signal group {FLAG1, FLAG2, FLAG3} is sent to the error correction module. Since the matching result indicates that the three entries are exactly the same, it means that no error has occurred, so no error correction is performed. When an error occurs in the Xi entry, the values of FLAG1 and FLAG2 will jump to 0. At this time, the value of the matching signal group is {001}. This indicates that there is an error in entry 1 and no errors in entries 2 and 3. At this time, the update mechanism of the error correction module will be triggered, and the target entry output by the voter will be used to rewrite entry 1. Similarly, when an error occurs in the Yi entry, the values of FLAG1 and FLAG3 will jump to 0. At this time, the value of the matching signal group is {010}. This indicates that there is an error in entry 2 and no errors in entries 1 and 3. At this time, the update mechanism of the error correction module will be triggered, and the target entry output by the voter will be used to rewrite entry 1. In this way, the flipped errors of each entry can be observed at any time and updated. Although the voter brings additional area, it can solve the problem of voting errors caused by error accumulation in the previous method and improve the reliability of fault tolerance.
[0040] To improve the parallelism of critical path code execution, in the design of this system, multiple identical table entries are stored together. The advantage of this design is that each voter is dedicated to a multi-mode table entry group, that is, it is no longer affected by the decoding result. Therefore, the delay of the voter can be excluded from the critical path, shortening the additional delay caused by error detection in the critical path. In addition, the update after the table entry has a flip error no longer depends on whether the table entry has been read.
[0041] When this system executes read data, the delay can be split into two parts. The first part of the delay consists of two parts: the table entry output delay and the decoding delay. For the table entry output delay, it includes the delay of the voter. The second part is to perform output table entry selection, and the register index is obtained according to the decoding result to determine the hit table entry. In this system, the voter and the multi-mode table entry are combined in a multi-mode table entry sub-module, so this part of the delay and the decoder delay exist in parallel. Therefore, the delay of this system consists of two parts in total. Compared with the existing multi-mode redundant system, this solution shortens the delay, improves the parallelism of code execution, and saves the delay consumption after fault tolerance by modifying the redundant structure and adding a voter.
[0042] To verify the performance of this system, the selected processor is an Intel Core i7-7700 CPU (3.6GHZ), and the memory is 16GB. The simulation experiment software platform is the hardware platform of Vivado 2019.1: First, verify the fault tolerance performance of the solution adopted by this system and the existing TMR solution, as follows: To explore the impact of external environmental radiation on the normal operation of the processor, taking single event upset (SEU) as an example, simulate a single event upset error in the register file to verify its fault tolerance performance. Conduct experiments on 10 different traces, and the experimental results are shown in Table 1. The experiment includes two solutions. One is the existing TMR solution (which executes the same task by using three identical modules or components and determines the final output result through a majority voting mechanism, so as to ensure the normal operation of the system when a single point of failure occurs). The other is the solution adopted by this system. For the single-bit flip problem, the existing TMR solution can achieve 100% fault tolerance performance, and the solution adopted by this system does not reduce its fault tolerance ability, indicating that the optimized solution can ensure its original fault tolerance performance.
[0043] Table 1 Verification table of the fault tolerance performance of the existing TMR solution and the solution adopted by this system With 10 different Traces Fault tolerance performance of existing TMR schemes Fault tolerance performance of the scheme adopted by this system 10 traces (AVG) 100% 100% Next, verify the path delay increase and resource usage increase of the solution adopted by this system, as described in detail below: The optimization strategy goal proposed by the solution adopted by this system is to reduce the delay problem caused by the critical path. As shown in Table 2, when verifying, the delay of accessing the register is set to 100% as the reference delay. For the existing TMR solution of the register, the path delay increase is 8.8%. When applying the solution adopted by this system, the path delay increase is 3.6%. Thus, it can be seen that compared with the existing TMR solution, the solution adopted by this system reduces the path delay.
[0044] In addition, based on the Vivado simulation platform, analyze the resource usage of three solutions. The resource usage unit of the register file is normalized to 1x. For the existing TMR solution, the number of FFs is 2.93x, and the number of LUTs is 3x. For the solution adopted by this system, the number of FFs is 3.08x, and the number of LUTs is 3x. That is to say, although the solution adopted by this system increases the number of arbitrators, it does not increase the resource usage significantly. Under the balance of resources and delay, the solution adopted by this system has certain advantages.
[0045] Table 2 Verification table of path delay increase and resource usage increase of the existing TMR solution and the solution adopted by this system An optimization method based on the N-modular redundancy solution of the register file, adopting an optimization system based on the N-modular redundancy solution of the register file. When N is greater than or equal to 3, it includes the following steps: Step 01, obtain read / write index signals; If the obtained index signal is a write index signal, then simultaneously obtain the write data signal matching the write index signal; Step 02, the decoder module decodes the read / write index signals obtained in Step 01, and decodes the obtained read / write index signals into the register numbers in the multi-modular redundancy module corresponding to the obtained read / write index signals; Step 03, if the signal obtained in Step 01 is a write index signal, then according to the register numbers decoded by the decoder module, select the registers corresponding to the register numbers through the write selectors in each multi-modular redundancy sub-module in the multi-modular redundancy module, and write the write data signal into the corresponding registers; If the signal obtained in Step 01 is a read index signal, then access the multi-modular redundancy module, and obtain multiple entries corresponding to the register numbers decoded in Step 02 in multiple multi-modular redundancy sub-modules; Step 04, if the signal obtained in Step 01 is a read index signal, then make a decision on the multiple entries obtained in Step 03 through a voter; In step 04, when multiple entries are decided by a voter, the voter in the multi-mode redundancy sub-module corresponding to each entry makes a decision on the corresponding entry.
[0046] In step 04, when the voter makes a decision on the output of the output entry, the entry decision with the most same ones is selected as the output entry.
[0047] Step 05: If, when the voter in step 04 makes a decision on multiple entries and it is known that several of the entries have flip errors, then the error correction circuit corrects and updates the entries with flip errors in the next clock cycle using the entry decided by the voter in step 04. If, when the voter in step 04 makes a decision on multiple entries and it is known that all the entries do not have flip errors, then step 06 is executed. Step 06: If the read index signal is obtained in step 01, then the read selector module outputs the entry after the decision in step 04 according to the register number corresponding to the obtained read index signal.
[0048] When determining whether there are flip errors in the entries in step 05, the voter writes the flip error flag bits of each entry into the error correction circuit. If the values of the flip error flag bits of all the entries are 1, it indicates that the entry decided by the voter has no flip errors. If the values of the flip error flag bits of several entries are 0, it indicates that several of the entries decided by the voter have flip errors, and the error correction circuit is triggered so that the error correction circuit uses the entry decided by the voter as the write error correction data signal and writes the write error correction data signal into the register with the flip error data, thereby updating and correcting the entries with flip errors.
[0049] When determining whether there are flip errors in the entries in step 05, the voter writes the flip error flag bits of each entry into the error correction circuit. If the values of the flip error flag bits of all the entries are 1, it indicates that the entry decided by the voter has no flip errors. If the values of the flip error flag bits of several entries are 0, it indicates that several of the entries decided by the voter have flip errors, and the error correction circuit is triggered so that the error correction circuit uses the entry decided by the voter as the write error correction data signal and writes the write error correction data signal into the register with the flip error data, thereby updating and correcting the entries with flip errors.
[0050] An optimization method based on the N-module redundancy scheme of a register file, using an optimization system based on the N-module redundancy scheme of a register file. When N is equal to 2, it includes the steps: Step a, obtain a read / write index signal; When the obtained index signal is a write index signal, obtain a write data signal matching the write index signal at the same time, and the check code module attaches a check code generated by the check code module to the write data signal; Step b, the decoder module decodes the read / write index signal obtained in step a, and decodes the obtained read / write index signal into the register number in the multi-mode redundancy module corresponding to the obtained read / write index signal; Step c, if the write index signal is obtained in step a, according to the register number decoded by the decoder module, select the register corresponding to the register number through the write selector in two multi-mode redundancy sub-modules in the multi-mode redundancy module, and write the write data signal into the corresponding register, and make the data stored in one register as the main table entry, and the data stored in the other register as the backup table entry; If the read index signal is obtained in step a, access the multi-mode redundancy module, and obtain the main table entry and the backup table entry corresponding to the register number decoded in step b in the two multi-mode redundancy sub-modules; Step d, if the read index signal is obtained in step a, verify whether the check codes attached to the two table entries obtained in step c are consistent through the check code matching module in the voter; If the check codes attached to the main table entry or the backup table entry are consistent, select the main table entry or the backup table entry through the table entry selection module in the voter and output it to the read selector module; If the check codes attached to the main table entry or the backup table entry are inconsistent, select the main table entry or the backup table entry with the check code consistent with the check code generated by the check code module through the table entry selection module in the voter and output it to the read selector module; Step e, if the check codes attached to the main table entry or the backup table entry are inconsistent in step d, the error correction circuit corrects and updates the main table entry or the backup table entry with the inconsistent check code attached to the main table entry or the backup table entry and the check code generated by the check code module according to the output table entry selected by the voter as the corrected table entry.
[0051] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and variations.
Claims
1. An optimization system based on a register file N-module redundancy scheme, characterized in that: It includes a decoder module, a multi-mode redundant module and a read selector module, the decoder module is connected to the multi-mode redundant module and the read selector module respectively, the multi-mode redundant module is connected to the read selector module, the multi-mode redundant module has a plurality of multi-mode redundant sub-modules, and the multi-mode redundant sub-module contains a register group composed of a plurality of registers; During write operation; The decoder module is used to decode the write index signal into the corresponding register number in the multi-module redundant module, and each register number corresponds to a register group one by one. The register number is used to guide the write data signal to be input into the register group corresponding to the register number in the multi-module redundant module at the rising edge of the clock; During read operation: The multi-mode redundant module is used to output the data in each multi-mode redundant sub-module to the read selector module, the decoder module is used to decode the read index signal into the corresponding register number in the multi-mode redundant module, and the read selector module is used to select the data of the register group corresponding to the register number obtained by decoding from the data output by the multi-mode redundant module for output; The data read / write operation is completed within one clock cycle.
2. The optimization system based on register file N modular redundancy scheme according to claim 1, characterized in that: The multi-mode redundant module has 2 to 32 multi-mode redundant sub-modules.
3. The optimization system based on register file N modular redundancy scheme according to claim 1, characterized in that: The decoder module is used to decode the 5-bit write / read index signal into the corresponding 32-bit register number in the multi-mode redundant module.
4. The optimization system based on register file N modular redundancy scheme according to claim 1, characterized in that: The multi-mode redundant submodule also includes a multi-mode table entry group, a voter, an error correction circuit, and a write selector module; The multi-mode table entry group contains multiple table entries, and one table entry is data stored in one of the registers in the register group corresponding to the multi-mode table entry group; The voting device is used to make a decision on a plurality of entries in a multi-mode entry group in a corresponding multi-mode redundant submodule; In the read operation, the table entry in the register corresponding to the register number is read out according to the register number decoded by the decoder module, and the obtained table entry is input into the voter to decide whether to use it as output; The error correction circuit corrects and updates the flip errors in the table entries stored in the register in real time in the next clock cycle; The write selector module selects the corresponding register according to the corresponding register number in the multi-module redundant module decoded by the decoder module, and writes the data into the register corresponding to the register number; It is used to accept the decision issued by the voting machine and select the corresponding table item as the system output according to the decision of the voting machine. It is used to receive the flip error corrected and updated by the error correction circuit, and write the corrected and updated table entry into the corresponding register according to the table entry where the flip error is located.
5. The optimization system based on the register file N modular redundancy scheme according to any one of claims 1 to 4, characterized in that: When N is equal to 2, a check code module is also included. When a write data signal is input, the check code module generates a check code through an XOR operation and appends the generated check code to the write data signal. When the data is output, it is used to detect whether an error occurs in the output data.
6. An optimization method based on register file N modular redundancy scheme, characterized in that: The optimization system based on the register file N modular redundancy scheme as claimed in any one of claims 1 to 4, when N is greater than or equal to 3, comprises the steps of: Step 01, obtain the read / write index signal; If the acquired index signal is a write index signal, a write data signal matching the write index signal is acquired simultaneously; Step 02, the decoder module decodes the read / write index signal obtained in step 01, and decodes the obtained read / write index signal into a register number in the multi-mode redundancy module corresponding to the obtained read / write index signal; Step 03, if the signal obtained in step 01 is a write index signal, then according to the register number decoded by the decoder module, the write selector in each multi-module redundant submodule in the multi-module redundant module selects the register corresponding to the register number, and writes the write data signal into the corresponding register; If the signal obtained in step 01 is a read index signal, the multi-mode redundant module is accessed to obtain multiple table entries corresponding to the register numbers obtained by decoding in step 02 in multiple multi-mode redundant sub-modules; Step 04: If the signal obtained in step 01 is a read index signal, a decision on outputting the multiple entries obtained in step 03 is made through a voter; Step 05, if the voter makes a decision on multiple entries in step 04 and finds that some of the entries have flip errors, the error correction circuit corrects and updates the entries with flip errors in the next clock cycle with the entries output by the voter in step 04; If the voter makes a decision on multiple entries in step 04 and finds that none of the entries has a rollover error, execute step 06; Step 06: If the signal obtained in step 01 is a read index signal, the read selector module outputs the entry determined in step 04 according to the register number corresponding to the obtained read index signal.
7. The optimization method based on register file N modular redundancy scheme according to claim 6, characterized in that: In step 04, when multiple entries are decided by the voter, the voter in the multi-mode redundant submodule corresponding to each entry makes a decision on the corresponding entry.
8. The optimization method based on register file N modular redundancy scheme according to claim 6, characterized in that: When determining whether there is a flip error in the table entry in step 05, the voter writes the flip error flag bit of each table entry into the error correction circuit; If the values of the flip error flag bits of all entries are 1, it means that the entry decided by the voter has no flip error; If the value of the flip error flag bit of several table entries is 0, it indicates that there are flip errors in several table entries decided by the voter, and the error correction circuit is triggered so that the error correction circuit writes the error correction data signal according to the table entry decided by the voter, and writes the write error correction data signal to the register with the flip error data, so as to update and correct the table entry with the flip error.
9. The optimization method based on register file N modular redundancy scheme according to claim 6, characterized in that: When the voter makes a decision on the output item in step 04, it selects the item with the same majority of decisions as the output item.
10. An optimization method based on register file N modular redundancy scheme, characterized in that: The optimization system based on the register file N modular redundancy scheme as claimed in claim 5, when N is equal to 2, comprises the steps of: Step a, obtaining a read / write index signal; If the acquired index signal is a write index signal, a write data signal matching the write index signal is acquired simultaneously, and the check code module adds a check code generated by the check code module to the write data signal; Step b, the decoder module decodes the read / write index signal obtained in step a, and decodes the obtained read / write index signal into a register number in the multi-mode redundant module corresponding to the obtained read / write index signal; Step c, if the signal obtained in step a is a write index signal, then according to the register number decoded by the decoder module, the register corresponding to the register number is selected by the write selectors in the two multi-module redundant sub-modules in the multi-module redundant module, and the write data signal is written into the corresponding register, and the data stored in one of the registers is used as the main table item, and the data stored in the other register is used as the backup table item; If the signal obtained in step a is a read index signal, the multi-mode redundant module is accessed, and the main table entry and the backup table entry corresponding to the register number obtained by decoding in step b are obtained in two multi-mode redundant sub-modules; Step d, if the signal obtained in step a is a read index signal, then the two entries obtained in step c are verified by the check code matching module in the voter to see whether the check codes attached to the two entries are consistent; If the check codes attached to the main table item or the backup table item are consistent, the main table item or the backup table item is selected by the table item selection module in the voter and output to the read selector module; If the check codes attached to the main table entry or the backup table entry are inconsistent, the table entry selection module in the voter selects the main table entry or the backup table entry having the check code consistent with the check code generated by the check code module and outputs it to the read selector module; In step e, if the check codes attached to the main table item or the backup table item in step d are inconsistent, the error correction circuit corrects and updates the main table item or the backup table item whose attached check codes are inconsistent with the check codes generated by the check code module according to the output table item selected by the voter as the corrected table item.