PCIe dynamic configuration method

Abstract

The invention discloses a PCIe dynamic configuration method, and relates to the technical field of PCIe configuration, and the PCIe dynamic configuration method comprises the steps that a BIOS detects whether the BMC state is normal or not; if the BIOS detects that the state of the BMC is normal, PCIe configuration information stored in an FRU in advance is obtained from the BMC side through an IPMI command, and dynamic configuration of a PCIe link configuration table is conducted through the PCIe configuration information; and if the BIOS detects that the state of the BMC is abnormal, directly obtaining PCIe configuration information pre-stored in an FRU through an I2C link, and performing dynamic configuration of a PCIe link configuration table by using the PCIe configuration information.

Description

Technical Field

[0001] The present invention relates to the technical field of PCIe (Peripheral Component Interconnect Express) configuration, and particularly to a PCIe dynamic configuration method. Background Art

[0002] The current adaptation technical solutions of BIOS (Basic Input / Output System) mostly meet the customized requirements for a single device hardware. Inevitably, this leads to a small coverage of customer needs by the whole machine manufacturers, and it is impossible to use the same hardware to meet the needs of all users. When the whole machine manufacturers are looking for a suitable BIOS manufacturer to adapt their hardware products to meet the needs of their customers, due to the diversity of customers, the whole machine manufacturers mostly adopt customized requirements and provide different firmware versions for different customers to meet the different needs of each customer. The more customized requirements for firmware versions, the higher the R & D costs generated. This involves both hardware and software aspects. If the repetitive development work can be reduced in terms of hardware and software, and a single hardware and software can be used to meet multiple customer groups, the R & D costs will be greatly reduced.

[0003] The general method adopted for OpenPOWER servers is to store PCIe configuration information in the Riser card according to the PCIe specification. The Riser card is a function expansion card or adapter card inserted on the PCIe interface: various types of PCIe configuration information are stored in the PCIe configuration document in advance; the card type information of the currently inserted Riser card is read, and the corresponding target PCIe configuration information is determined according to the card type information; the corresponding target PCIe configuration information is called from the PCIe configuration document and written into the corresponding register. This method does not clarify the method of writing the stored information on the Riser card, so to a certain extent, it still solidifies the PCIe configuration form, and it is necessary to add a storage module on the Riser card, which increases the cost of the Riser card accessories and is not conducive to users to adjust the PCIe configuration of the device according to their different needs. Summary of the Invention

[0004] The present invention provides a PCIe dynamic configuration method to solve the technical problem that customers cannot configure the PCIe of the Riser card in the existing hardware environment according to their own needs.

[0005] An embodiment of the present invention provides a PCIe dynamic configuration method, including:

[0006] The BIOS checks whether the status of the BMC (Board Manager Controller) is normal;

[0007] If the BIOS checks that the status of the BMC is normal, it obtains the PCIe configuration information pre - saved in the FRU (Field Replace Unit) from the BMC side through IPMI (Intelligent Platform Management Interface) commands, and uses the PCIe configuration information to perform dynamic configuration of the PCIe link configuration table;

[0008] If the BIOS checks that the status of the BMC is abnormal, it directly obtains the PCIe configuration information pre - saved in the FRU through the I 2 C link, and uses the PCIe configuration information to perform dynamic configuration of the PCIe link configuration table.

[0009] Preferably, it further includes: the BMC obtains PCIe configuration information according to the actual usage requirements of user peripheral devices, and writes the PCIe configuration information into the FRU on the Riser card.

[0010] Preferably, the BMC obtains PCIe configuration information according to the actual usage requirements of user peripheral devices and writes the PCIe configuration information into the FRU on the Riser card, including: the BMC performs PCIe resource allocation for each core Die of CPU0 according to the actual usage requirements of user peripheral devices, obtains the PCIe configuration data of each core Die, and performs combined processing on the PCIe configuration data of each core Die to obtain the PCIe configuration information of CPU0; the BMC performs PCIe resource allocation for each core Die of CPU1 according to the actual usage requirements of user peripheral devices, obtains the PCIe configuration data of each core Die, and performs combined processing on the PCIe configuration data of each core Die to obtain the PCIe configuration information of CPU1; the BMC uses the IPMITool tool to write the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 into the FRU on the Riser card.

[0011] Preferably, after the BIOS obtains the PCIe configuration information pre - stored in the FRU from the BMC side through IPMI commands, it further includes: the BIOS detects whether it has successfully obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 from the BMC side through IPMI commands; if the BIOS detects that it has successfully obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 from the BMC side through IPMI commands, then it parses the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1.

[0012] Preferably, after the BIOS obtains the PCIe configuration information pre - stored in the FRU from the BMC side through IPMI commands, it further includes: if the BIOS detects that it has not successfully obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 from the BMC side through IPMI commands, then it directly obtains the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 pre - stored in the FRU through the I 2 C link.

[0013] Preferably, after the BIOS directly obtains the PCIe configuration information pre - stored in the FRU through the I 2 C link, it further includes: the BIOS detects whether it has successfully directly obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 through the I 2 C link; if the BIOS detects that it has successfully directly obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 through the I 2 C link, then it parses the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1.

[0014] Preferably, after the BIOS directly obtains the PCIe configuration information pre - stored in the FRU through the I 2 C link, it further includes: if the BIOS detects that it has not successfully directly obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 through the I 2 C link, then it updates the default CPU0 PCIe link configuration table to the previous CPU0 PCIe link configuration table, and at the same time updates the default CPU1 PCIe link configuration table to the previous CPU1 PCIe link configuration table.

[0015] Preferably, the BIOS parses the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1, including: the BIOS parses the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 to obtain the PCIe link configuration table of CPU0 and the PCIe link configuration table of CPU1; the BIOS updates the PCIe link configuration table of CPU0 to the previous PCIe link configuration table of CPU0, and at the same time updates the PCIe link configuration table of CPU1 to the previous PCIe link configuration table of CPU1.

[0016] Preferably, it further includes: the BIOS performs PCIe resource configuration processing according to the updated PCIe configuration tables of CPU0 and CPU1 to achieve dynamic configuration of PCIe resources.

[0017] The beneficial effects of the present invention are as follows:

[0018] 1) For users, they can configure the device PCIe by themselves without recompiling the firmware, and can adjust the PCIe configuration at any time according to the changing actual needs. They have stronger autonomy, a more flexible preparation plan and do not need to submit requirements to the manufacturer, which greatly reduces costs; in addition, they can also be satisfied quickly, are more flexible and efficient, and improve the user experience;

[0019] 2) For BIOS developers, this solution is also more convenient, without having to modify and compile for different configuration requirements, and can further improve the reliability of the server. Description of the Drawings

[0020] Figure 1 is a flowchart of a PCIe dynamic configuration method provided by the present invention;

[0021] Figure 2 is an overall architecture block diagram provided by the present invention;

[0022] Figure 3 is a BMC-side operation flowchart provided by the present invention;

[0023] Figure 4 is a PCIe flexible configuration BIOS-side logic flowchart provided by the present invention. Detailed Embodiments

[0024] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0025] Figure 1 is a flowchart of a PCIe dynamic configuration method provided by the present invention, as Figure 1 shown, including:

[0026] Step S101: The BIOS detects whether the BMC status is normal;

[0027] Step S102: If the BIOS detects that the BMC status is normal, obtain the PCIe configuration information pre - stored in the FRU from the BMC side through IPMI commands, and use the PCIe configuration information to perform dynamic configuration of the PCIe link configuration table;

[0028] Step S103: If the BIOS detects that the BMC status is abnormal, directly obtain the PCIe configuration information pre - stored in the FRU through the I 2 C link, and use the PCIe configuration information to perform dynamic configuration of the PCIe link configuration table.

[0029] An embodiment of the present invention further includes: The BMC obtains PCIe configuration information according to the actual usage requirements of user peripheral devices, and writes the PCIe configuration information into the FRU on the Riser card.

[0030] Further, the BMC obtains PCIe configuration information according to the actual usage requirements of user peripheral devices, and writes the PCIe configuration information into the FRU on the Riser card, including: The BMC performs PCIe resource allocation for each core Die of CPU0 according to the actual usage requirements of user peripheral devices, obtains the PCIe configuration data of each core Die, and performs combination processing on the PCIe configuration data of each core Die to obtain the PCIe configuration information of CPU0; The BMC performs PCIe resource allocation for each core Die of CPU1 according to the actual usage requirements of user peripheral devices, obtains the PCIe configuration data of each core Die, and performs combination processing on the PCIe configuration data of each core Die to obtain the PCIe configuration information of CPU1; The BMC uses the IPMITool tool to write the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 into the FRU on the Riser card.

[0031] Specifically, after the BIOS obtains the PCIe configuration information pre - stored in the FRU from the BMC side through IPMI commands, it further includes: The BIOS detects whether it has successfully obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 from the BMC side through IPMI commands; If the BIOS detects that it has successfully obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 from the BMC side through IPMI commands, then parse the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1.

[0032] Further, after the BIOS obtains the PCIe configuration information pre - stored in the FRU from the BMC side through IPMI commands, it further includes: if the BIOS fails to obtain the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 from the BMC side through IPMI commands, then through I 2 C link directly obtains the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 pre - stored in the FRU.

[0033] Even further, after the BIOS directly obtains the PCIe configuration information pre - stored in the FRU through the I 2 C link, it further includes: the BIOS detects whether it has successfully directly obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 through the I 2 C link; if the BIOS detects that it has successfully directly obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 through the I 2 C link, then parses the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1.

[0034] Specifically, after the BIOS directly obtains the PCIe configuration information pre - stored in the FRU through the I 2 C link, it further includes: if the BIOS fails to directly obtain the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 through the I 2 C link, then updates the default PCIe link configuration table of CPU0 to the previous PCIe link configuration table of CPU0, and at the same time updates the default PCIe link configuration table of CPU1 to the previous PCIe link configuration table of CPU1.

[0035] Among them, the BIOS parses the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1, including: the BIOS parses the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 to obtain the PCIe link configuration table of CPU0 and the PCIe link configuration table of CPU1; the BIOS updates the PCIe link configuration table of CPU0 to the previous PCIe link configuration table of CPU0, and at the same time updates the PCIe link configuration table of CPU1 to the previous PCIe link configuration table of CPU1.

[0036] The embodiments of the present invention further include: The BIOS performs PCIe resource configuration processing according to the updated PCIe configuration tables of CPU0 and CPU1, realizing dynamic configuration of PCIe resources.

[0037] As Figure 2 shown, the user writes PCIe configuration information (hereinafter referred to as FRU information) into the FRU on the Riser card. The policy configuration module embedded in the BIOS judges whether the BMC status is normal and confirms whether the interaction can proceed smoothly. If the status is normal, the FRU information can be obtained through the IPMITool of the BMC. During the BIOS startup process, according to the pre-established protocol, the obtained FRU information is parsed to improve the PCIe link configuration table used for PCIe initialization, thus realizing dynamic configuration of PCIe. Secondly, if the BMC status is abnormal, at this time, the BIOS directly obtains the FRU information on the Riser Card through the I2C link to configure the PCIe link configuration table. If this path cannot work properly either, the policy configuration module gives a default PCIe link configuration table to enable the device to start normally, and further error checking is performed later after startup.

[0038] Figure 3 is the operation flowchart on the BMC side provided by the present invention. As Figure 3 shown, it includes:

[0039] Step 1: The user plans the required PCIe resources according to actual usage requirements and combines the configuration information according to the protocol group data. For example, if slot1 and slot2 on Riser1 need to be configured as X8 respectively, the corresponding data is combined;

[0040] Step 2: Use the IPMITool to write the configuration information into the FRU;

[0041] Step 3: During the device startup process, the BIOS first reads the PCIe configuration information in the FRU through IPMI communication;

[0042] Step 4: If the IPMI communication of the BIOS fails, the BIOS attempts to use I2C to obtain the PCIe configuration information, so as to update the PCIe link configuration table by using the PCIe configuration information for subsequent startup, and the PCIe resources will be allocated according to this PCIe configuration later.

[0043] Figure 4 is the logical flowchart on the BIOS side for flexible PCIe configuration provided by the present invention. As Figure 4 shown, it specifically includes:

[0044] Step 1: After presenting the PCIe default link configuration table that meets the device startup conditions, combine the configuration information of each byte according to the actual usage requirements;

[0045] First, allocate PCIe resources to each core Die of CPU0. "ipmitool raw 0x3a 0xA3" is a custom command for configuring PCIe resources, followed by the PCIe configuration information;

[0046] If it is necessary to configure Die0 of CPU0 as x16 and not support hot pluggability, the data assembled is: 0x71

[0047] If it is necessary to configure Die1 of CPU0 as x16 and not support hot pluggability, the data assembled is: 0x73

[0048] If it is necessary to configure Die2 of CPU0 as x16 and not support hot pluggability, the data assembled is: 0x75

[0049] If it is necessary to configure Die3 of CPU0 as x16 and not support hot pluggability, the data assembled is: 0x77

[0050] If it is necessary to configure Die1 of CPU0 as x16 and not support hot pluggability, the data assembled is: 0x73

[0051] The configuration data of CPU1 can be combined in the same way as above

[0052] After data combination, use the IPMITool tool to write the configuration information to the FRU

[0053] Use the terminal tool to access the serial port or ssh service of the BMC, and enter commands such as: ipmitool raw 0x3a 0xA3 0x71 0xf0 0x73 0xf0 0x75 0xf0 0x77 0xf0

[0054] To confirm whether the writing is correct, the user can use the command: ipmitool 0x3a 0xA2 0x01 to view the information. The data of the last byte here represents CPU1. If you want to view the data of CPU0, it should be "0x00".

[0055] Step 2: The policy configuration module detects whether the BMC is normal through IPMI communication; if abnormal, go to Step 4;

[0056] Step 3: If normal, use the IPMI protocol to send a command to obtain PCIe configuration information and determine whether the PCIe configuration information is successfully obtained;

[0057] Before the PCIe resource allocation on the BIOS side, the IPMI protocol is used to obtain the PCIe resource configuration information of CPU0 and CPU1.

[0058] Step 4: If it is determined that the PCIe configuration information is successfully obtained, then parse the obtained PCIe configuration information; if it fails, go to Step 5.

[0059] Step 5: Obtain the PCIe configuration information on the Riser card through I2C, and determine whether the acquisition through I2C is successful. If it is successful, go to Step 4; if it fails, go to Step 6.

[0060] Step 6: The policy configuration module gives the default PCIe default link configuration table to the BIOS.

[0061] Step 7: Update the PCIe link configuration table.

[0062] Execute the update of the PCIe link configuration table, that is, assign the address of the obtained PCIe link configuration table to the previous PCIe link configuration table.

[0063] Step 8: After the update is completed, continue to start.

[0064] The BIOS will continue to start according to this configuration table, and the PCIe resources will also be allocated according to this configuration.

[0065] In summary, the present invention can largely solve the problem that customers cannot configure the PCIe configuration of the Riser card of the existing hardware environment according to their own needs. For the same hardware product, users can configure the PCIe link according to the needs of their peripheral devices to achieve the purpose of normal use, which has great flexibility, reliability, and economy.

[0066] The preferred embodiments of the present invention have been described above with reference to the accompanying drawings. However, this does not limit the scope of the rights of the present invention. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the present invention shall fall within the scope of the rights of the present invention.

Claims

1. A PCIe dynamic configuration method, characterized in that, including: The BIOS detects whether the BMC status is normal; If the BIOS detects that the BMC status is normal, obtain the PCIe configuration information pre - saved in the FRU from the BMC side through IPMI commands, and use the PCIe configuration information to perform dynamic configuration of the PCIe link configuration table; If the BIOS detects that the BMC status is abnormal, it directly obtains the PCIe configuration information pre - stored in the FRU through the I 2 C link, and dynamically configures the PCIe link configuration table by using the PCIe configuration information; Wherein, the PCIe refers to the Peripheral Component Interconnect Express bus; the BIOS refers to the Basic Input / Output System; the BMC refers to the Baseboard Management Controller; the IPMI refers to the Intelligent Platform Management Interface; the FRU refers to the Field Replaceable Unit.

2. The method according to claim 1, characterized in that, It also includes: The BMC obtains PCIe configuration information according to the actual usage requirements of user peripheral devices, and writes the PCIe configuration information into the FRU on the Riser card.

3. The method according to claim 2, characterized in that, The BMC obtaining PCIe configuration information according to the actual usage requirements of user peripheral devices and writing the PCIe configuration information into the FRU on the Riser card includes: The BMC performs PCIe resource allocation for each core Die of CPU0 according to the actual usage requirements of user peripheral devices, obtains the PCIe configuration data of each core Die, and performs combination processing on the PCIe configuration data of each core Die to obtain the PCIe configuration information of CPU0; The BMC performs PCIe resource allocation for each core Die of CPU1 according to the actual usage requirements of user peripheral devices, obtains the PCIe configuration data of each core Die, and performs combination processing on the PCIe configuration data of each core Die to obtain the PCIe configuration information of CPU1; The BMC uses the IPMITool tool to write the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 into the FRU on the Riser card.

4. The method according to claim 3, characterized in that, After the BIOS obtains the PCIe configuration information pre - saved in the FRU from the BMC side through IPMI commands, it also includes: The BIOS detects whether it has successfully obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 from the BMC side through IPMI commands; If the BIOS detects that it has successfully obtained the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 from the BMC side through IPMI commands, then parse the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1.

5. The method according to claim 4, characterized in that, After the BIOS obtains the PCIe configuration information pre - saved in the FRU from the BMC side through IPMI commands, it also includes: If the BIOS fails to successfully obtain the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 from the BMC side through IPMI commands, then the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 pre-stored in the FRU are directly obtained through the I 2 C link.

6. The method according to claim 5, characterized in that, After the BIOS directly obtains the PCIe configuration information pre - stored in the FRU through the I 2 C link, it further includes: The BIOS detects whether the I 2 C link is successful and directly obtains the PCIe configuration information of the CPU0 and the PCIe configuration information of the CPU1; If the BIOS detects that it passes through I 2 C link and successfully obtains the PCIe configuration information of the CPU0 and the PCIe configuration information of the CPU1, then parse the PCIe configuration information of the CPU0 and the PCIe configuration information of the CPU1.

7. The method according to claim 6, characterized in that, After the BIOS directly obtains the PCIe configuration information pre-stored in the FRU through the I 2 C link, it further includes: If the BIOS fails to directly obtain the PCIe configuration information of the CPU0 and the PCIe configuration information of the CPU1 through the I 2 C link successfully, the default PCIe link configuration table of the CPU0 is updated to the previous PCIe link configuration table of the CPU0, and at the same time, the default PCIe link configuration table of the CPU1 is updated to the previous PCIe link configuration table of the CPU1.

8. The method according to claim 7, characterized in that, The BIOS parsing the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 includes: The BIOS parses the PCIe configuration information of CPU0 and the PCIe configuration information of CPU1 to obtain the PCIe link configuration table of CPU0 and the PCIe link configuration table of CPU1; The BIOS updates the PCIe link configuration table of the CPU0 to the PCIe link configuration table of the previous CPU0, and at the same time updates the PCIe link configuration table of the CPU1 to the PCIe link configuration table of the previous CPU1.

9. The method according to claim 8, characterized in that, It further includes: The BIOS performs PCIe resource configuration processing according to the updated PCIe configuration tables of the CPU0 and the CPU1, to achieve dynamic configuration of PCIe resources.

Images