Method and apparatus for memory initialization
By flashing the access parameters to the storage device and calibrating with an additional processor, the problems of high latency and power consumption in traditional DRAM initialization methods are solved, and the DRAM initialization time is significantly reduced and the efficient utilization of system resources is achieved.
Patent Information
- Application Number
- CN202311778773.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-06-20
AI Technical Summary
Traditional DRAM initialization methods require the transfer of large amounts of data between the CPU and the memory, resulting in high latency, time and power consumption.
The initialization time is reduced by flashing the access parameters to the storage device and only correcting the access parameters that should be corrected, calibration is performed using an additional processor in the memory device.
It significantly reduces the DRAM initialization time, can achieve one-tenth of time reduction, and frees up CPU resources, improving the overall system startup speed and power consumption efficiency.
Smart Images
Figure CN120179378A_ABST
Abstract
Description
Technical Field
[0001] This application generally relates to memories, and more particularly, to methods and apparatuses for DRAM initialization. Background Art
[0002] Dynamic random access memory (DRAM) devices are volatile memory devices. Thus, when power is no longer supplied to a DRAM device, its contents and operational configuration typically may not be retained. Each time a DRAM device is powered on, a predefined sequence of steps is required to initialize the internal state of the DRAM device and configure user-defined operational parameters.
[0003] However, traditional main memory subsystems rely on an external controller such as a central processing unit (CPU) to perform initialization operations. Thus, a large amount of data typically must be transferred back and forth between the CPU and the memory to perform initialization. Due to this arrangement, a large amount of data is transmitted over the memory bus. Thus, initialization results in high latency. This consumes a large amount of bandwidth and power.
[0004] Therefore, more efficient methods and apparatuses for DRAM initialization are needed. Summary of the Invention
[0005] Apparatuses and methods of operation thereof for DRAM initialization are provided herein. Since access parameters are flashed to a storage device and only the access parameters that should be corrected are corrected, the initialization time can be significantly reduced, up to one tenth. Additionally, when the access parameters that should be corrected are corrected, the resources of the CPU are released and calibration and correction are handed over to an additional processor in the memory device, which can also reduce the time to initialize the entire device. Further, since the processor corrects the access parameters according to the access parameters flashed to the storage device, the correction time is reduced, thereby further improving the initialization time of the memory device.
[0006] In one embodiment, an apparatus is provided that includes a memory device. The memory device includes a memory array, a storage device, and a memory controller. The storage device stores access parameters corresponding to multiple access modes. The memory controller accesses the memory array using the access parameters corresponding to one of the access modes. When the memory device is started, the memory controller flashes the access parameters corresponding to each of the access modes to the storage device.
[0007] According to an embodiment of the present invention, the device further includes a non-volatile memory device. The non-volatile memory device stores all access parameters corresponding to all access modes. When the memory device is started, the memory controller flashes the access parameters corresponding to all access modes to the storage device.
[0008] According to an embodiment of the present invention, the device further includes a preloader. The preloader starts the memory device. When the memory device is turned off, the preloader flashes the access parameters corresponding to each of the access modes from the storage device to the non-volatile memory device.
[0009] According to an embodiment of the present invention, when the preloader starts the memory device for the first time, the preloader calibrates the access parameters corresponding to each of the access modes, and then stores the access parameters corresponding to each of the access modes in the storage device.
[0010] According to an embodiment of the present invention, when the preloader starts the memory device again, the preloader flashes the access parameters corresponding to each of the access modes from the non-volatile memory device to the storage device.
[0011] According to an embodiment of the present invention, the memory device further includes a processor. When the preloader starts the memory device again, after the preloader flashes the access parameters corresponding to each of the access modes from the non-volatile memory device to the storage device, the processor corrects each of the access parameters corresponding to each of the access modes stored in the storage device according to the operating environment.
[0012] According to an embodiment of the present invention, the preloader is a central processing unit that executes a memory driver. When the processor corrects each of the access parameters corresponding to each of the access modes stored in the storage device, the central processing unit is released and can be used to initialize other devices.
[0013] According to an embodiment of the present invention, the non-volatile memory device is a flash memory.
[0014] In another embodiment, an operating method applicable to a memory device is provided. The memory device includes a memory array and a storage device. The operating method includes the following steps. Start the memory device. When the memory device is started, flash the access parameters corresponding to multiple access modes to the storage device. Access the memory array using the access parameters corresponding to one of the access modes stored in the storage device.
[0015] According to an embodiment of the present invention, the operation method may further include the following steps. When the memory device is started for the first time, a preloader is used to calibrate each corresponding access parameter in the access mode. After the step of calibrating each corresponding access parameter in the access mode, each corresponding access parameter in the access mode is stored in the storage device.
[0016] According to an embodiment of the present invention, the operation method may further include the following steps. When the memory device is restarted, all corresponding access parameters in the access mode are flashed from the non-volatile memory device to the storage device.
[0017] According to an embodiment of the present invention, the operation method may further include the following steps. When the memory device is turned off, the access parameters corresponding to each in the access mode are flashed from the storage device to the non-volatile memory device.
[0018] According to an embodiment of the present invention, the operation method may further include the following steps. When the circuit is restarted, after the step of flashing all access parameters corresponding to the access modes from the non-volatile memory device to the storage device, the processor is used to correct each corresponding access parameter in the access mode stored in the storage device according to the operating environment.
[0019] According to an embodiment of the present invention, the preloader is a central processing unit that executes the memory driver, and the non-volatile memory device is a flash memory. After the processor corrects each corresponding access parameter in the access mode, the central processor is released and can be used to initialize other devices.
[0020] A detailed description will be given below in conjunction with the embodiments of the drawings. Description of the Drawings
[0021] The present invention can be more fully understood by reading the following detailed description and examples with reference to the accompanying drawings, in which:
[0022] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;
[0023] Figure 2 is a schematic diagram of a semiconductor device according to another embodiment of the present invention;
[0024] Figure 3 is a schematic diagram of a semiconductor device according to yet another embodiment of the present invention;
[0025] Figure 4 is a schematic diagram of a semiconductor device according to another embodiment of the present invention; and
[0026] Figure 5 is a flowchart of an operation method according to an embodiment of the present invention. Detailed Implementation Modes
[0027] The following description is made to illustrate the general principles of the present invention and should not be construed in a limiting sense. The scope of the present invention is determined by reference to the appended claims.
[0028] In the following detailed description, for purposes of explanation, numerous specific details and embodiments are set forth in order to provide a thorough understanding of the present invention. The same and / or corresponding numbers are used in the drawings of different embodiments and do not imply any correlation between different embodiments.
[0029] In addition, in certain embodiments of the present invention, unless otherwise clearly described, terms related to attachment, coupling, etc. (such as "(connected)" and "(indirectly connected)") refer to the relationship in which a structure is fixedly attached to or connected to another entity directly or indirectly (e.g., electrically connected) via an intermediate structure, as well as a movable or rigid attachment or relationship.
[0030] In addition, in this specification, relative spatial expressions are used. For example, "below", "bottom", "above", or "top" are used to describe the position of one element relative to another element. It should be understood that if the device is inverted, the element that was originally "below" will become the element that is "above".
[0031] It should be understood that although terms such as "first", "second", "third", etc. are used herein to describe various elements, components, regions, layers, parts, and / or sections, these elements, components, regions, layers, parts, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, part, or section from another element, component, region, layer, or section. Therefore, without departing from the teachings of the present invention, in the claims, the first element, component, region, layer, part, or section in the specification may be referred to as the second element, component, region, layer, part, or section.
[0032] It should be understood that the description of the exemplary embodiments is intended to be read in conjunction with the drawings, which should be regarded as a part of the entire written description. The drawings are not drawn to scale. In addition, for the purpose of simplifying the drawings, the structures and devices are shown in schematic form.
[0033] The terms "about", "approximately", and "substantially" generally mean that a value is within the range of plus or minus 20% of the stated value, more commonly within the range of plus or minus 10%, plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1%, or plus or minus 0.5% of the stated value. The stated values of the present invention may be approximate values. Even if not specifically described, the stated values still include the meaning of "about", "approximately", or "substantially".
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should be understood that in each case, unless otherwise defined, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the relevant skills, background, or context of this invention, and should not be interpreted in an idealized or overly formal manner.
[0035] In the drawings, similar elements and / or features may have the same reference numerals. Identical components of the same type are distinguished, and thus similar components and / or similar features are distinguished, by adding a letter or number after the component symbol.
[0036] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. As Figure 1 shown, the semiconductor device 100 includes a memory device 110, a preloader 120, and a non-volatile memory device 130. According to an embodiment of the present invention, the memory device 110 may be a dynamic random access memory (DRAM) device.
[0037] The memory device 110 coupled to the preloader 120 and the non-volatile memory device 130 includes a memory controller 111, a memory array 112, and a storage device 113. According to an embodiment of the present invention, the storage device 113 may be a static random-access memory (SRAM). In certain embodiments, the storage device may be a 60 KB shuffle SRAM.
[0038] The memory controller 111 accesses the memory array 112 according to access parameters related to first mode data DT1, second mode data DT2, third mode data DT3,..., and Nth mode data DTN stored in the storage device 113. The first mode data DT1, second mode data DT2, third mode data DT3,..., and Nth mode data DTN stored in the storage device 113 will be described in detail below.
[0039] The preloader 120 may operate the memory device 110 in one of a first access mode MD1, a second access mode MD2, a third access mode MD3,..., and an Nth access mode MDN. According to an embodiment of the present invention, when the preloader 120 first starts the memory device 110, the preloader 120 performs an initialization operation on the memory device 110.
[0040] During the initialization operation, the pre-loader 120 calibrates the operations and communications between the memory controller 111 and the memory array 112 based on each of the first access mode MD1, the second access mode MD2, the third access mode MD3, …, and the Nth access mode MDN. In addition, the pre-loader 120 stores the access parameters related to the first access mode MD1, the second access mode MD2, the third access mode MD3, …, and the Nth access mode MDN obtained during the initialization process as the first mode data DT1, the second mode data DT2, the third mode data DT3, …, and the Nth mode data DTN in the storage device 113.
[0041] According to an embodiment of the present invention, the pre-loader 120 may be a central processing unit that executes DRAM driving. According to an embodiment of the present invention, the non-volatile memory device 130 may be a flash memory.
[0042] According to an embodiment of the present invention, when the memory device 110 is turned off after the initialization operation, the pre-loader 120 flashes all the first mode data DT1, the second mode data DT2, the third mode data DT3, …, and the Nth mode data DTN in the storage device 113 to the non-volatile memory device 130 as a backup signal BCK. Therefore, the first mode data DT1, the second mode data DT2, the third mode data DT3, …, and the Nth mode data DTN can be retained for use when the memory device 110 is started up next time. According to some embodiments of the present invention, the first startup of the memory device 110 is usually completed in the factory.
[0043] Figure 2 is a schematic diagram of a semiconductor device according to another embodiment of the present invention, where the pre-loader 120 restarts the memory device 110 again. As Figure 2 shown, when the pre-loader 120 restarts the memory device 110 again, the pre-loader 120 separately loads the first mode data DT1, the second mode data DT2, the third mode data DT3, …, and the Nth mode data DTN from the non-volatile memory device 130 to the storage device 113, and corrects the access parameters of each of the first mode data DT1, the second mode data DT2, the third mode data DT3, …, and the Nth mode data DTN according to the operating environment.
[0044] For example, when the preloader 120 loads the first mode data DT1 into the storage device 113, the preloader 120 calibrates the access parameters related to the first mode data DT1 according to the operating environment. After the access parameters related to the first mode data DT1 are calibrated, the preloader 120 then loads the second mode data DT2 into the storage device 113, and so on. According to some embodiments of the present invention, the first mode data DT1, the second mode data DT2, the third mode data DT3... and the Nth mode data DTN can be loaded into the storage device 113 through Direct Memory Access (DMA).
[0045] However, when the preloader 120 restores the first mode data DT1, the second mode data DT2, the third mode data DT3... and the Nth mode data DTN to the storage device 113, the preloader 120 also needs to recalibrate the access parameters corresponding to the first access mode MD1, the second access mode MD2, the third access mode MD3... and the Nth access mode MDN, which is time-consuming and inefficient. In addition, since the preloader 120 must recalibrate for each of the first access mode MD1, the second access mode MD2, the third access mode MD3... and the Nth access mode MDN after the memory device 110 is started, the resources of the CPU will be occupied for a long time, resulting in inefficiency, time consumption and power consumption.
[0046] Figure 3 is a schematic diagram of a semiconductor device according to another embodiment of the present invention. As Figure 3 shown, the semiconductor device 300 includes a memory device 310. Comparing the memory device 310 with the memory device 110 Figure 1 in, the memory device 310 further includes a processor 311.
[0047] According to an embodiment of the present invention, as Figure 3 shown, when the preloader 120 first starts the memory device 310, the preloader 120 performs an initialization operation on the memory device 310. During the initialization operation, the preloader 120 calibrates the operations and communications between the memory controller 111 and the memory array 112 based on each of the first access mode MD1, the second access mode MD2, the third access mode MD3... and the Nth access mode MDN.
[0048] In addition, the pre-loader 120 stores access parameters related to the first access mode MD1, the second access mode MD2, the third access mode MD3, ..., and the Nth access mode MDN, which are obtained during initialization, as the first mode data DT1, the second mode data DT2, the third mode data DT3, ..., and the Nth mode data DTN in the storage device 113.
[0049] According to an embodiment of the present invention, when the memory device 310 is turned off after the initialization operation, the pre-loader 120 flashes all the first mode data DT1, the second mode data DT2, the third mode data DT3, ..., and the Nth mode data DTN in the storage device 113 to the non-volatile memory device 130 as a backup signal BCK. Therefore, the first mode data DT1, the second mode data DT2, the third mode data DT3, ..., and the Nth mode data DTN can be retained for use when the memory device 310 is started up next time. According to some embodiments of the present invention, the first startup of the memory device 310 is typically completed in the factory.
[0050] Figure 4 is a schematic diagram of a semiconductor device according to another embodiment of the present invention, where the pre-loader 120 restarts the memory device 310 again. As Figure 4 shown, when the pre-loader 120 restarts the memory device 310 again, the pre-loader 120 flashes all the first mode data DT1, the second mode data DT2, the third mode data DT3, ..., and the Nth mode data DTN from the non-volatile memory device 130 to the storage device 113, and the processor 311 corrects the corresponding access parameters of each of the first mode data DT1, the second mode data DT2, the third mode data DT3, ..., and the Nth mode data DTN according to the operating environment.
[0051] For example, after the pre-loader 120 flashes all the first mode data DT1, the second mode data DT2, the third mode data DT3, ..., and the Nth mode data DTN from the non-volatile memory device 130 to the storage device 113, the processor 311 calibrates the access parameters of the first mode data DT1 according to the operating environment.
[0052] When the processor 311 determines that at least one access parameter of the first mode data DT1 should be corrected according to the operating environment, the processor 311 only corrects the corresponding access parameter that should be corrected and keeps the other parameters unchanged. Then, the processor 311 calibrates another one of the first mode data DT1, the second mode data DT2, the third mode data DT3, ..., and the Nth mode data DTN, and only corrects the access parameter that should be corrected.
[0053] As Figure 4As shown, since the first mode data DT1, the second mode data DT2, the third mode data DT3, ..., and the Nth mode data DTN are flash-transferred from the non-volatile memory device 130 to the storage device 113 at once, the efficiency is significantly improved, especially when the memory device 310 has more modes and a larger memory array 112. In addition, since the additional processor 311 corrects the access parameters corresponding to each of the first mode data DT1, the second mode data DT2, the third mode data DT3, ..., and the Nth mode data DTN, the resources of the CPU (i.e., the pre-loader 120) can be released at an early stage of initialization, thereby reducing the power consumption of the entire system and improving the startup speed.
[0054] Figure 5 is a flowchart of an operation method according to an embodiment of the present invention. The operation method 500 will be further explained below using Figure 3 and Figure 4 for further explanation.
[0055] As Figure 5 shown, the pre-loader 120 starts the memory device 310 (step S501), and calibrates the access parameters corresponding to each of the first access mode MD1, the second access mode MD2, the third access mode MD3, ..., and the Nth access mode MDN (step S502). After the calibration is completed, the pre-loader 120 stores the access parameters corresponding to each of the first access mode MD1, the second access mode MD2, the third access mode MD3, ..., and the Nth access mode MDN in the storage device (step S503).
[0056] As Figure 3 shown, when the pre-loader 120 starts the memory device 310, the pre-loader 120 performs an initialization operation on the memory device based on each of the first mode access mode MD1, the second mode access mode MD2, the third mode access mode MD3, ..., and the Nth mode access mode MDN to calibrate the operation and communication between the memory controller 111 and the memory array 112.
[0057] Then, the pre-loader 120 stores the calibrated access parameters as the first mode data DT1, the second mode data DT2, the third mode data DT3, ..., and the Nth mode data DTN in the storage device 113. Accordingly, the memory controller 111 operates the memory array 112 based on the first mode access mode MD1, the second mode access mode MD2, the third mode access mode MD3, ..., and the Nth mode access mode MDN.
[0058] Refer to Figure 5When the memory device 310 is turned off, all access parameters corresponding to the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN are flash-memory from the storage device 113 to the non-volatile memory device 130 (step S504).
[0059] As Figure 3 shown, when the memory device 310 is turned off after the initialization operation, the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN in the storage device 113 are flash-memory to the non-volatile memory device 130 as a backup signal BCK. In other words, during the period when the memory device 310 is turned off, the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN in the storage device 113 are retained in the non-volatile memory device 130 as a backup signal BCK.
[0060] According to certain embodiments of the present invention, the first startup and shutdown of the memory device 310 are performed in steps S501 to S504, which can be completed in the factory. In other words, steps S504 to S509 can be executed during user operation. In step S509, it is determined whether the memory device 310 / circuit is turned off.
[0061] Reference Figure 5 to, the preloader 120 further determines whether the memory device 310 is started (step S505). When the memory device 310 is started, the preloader 120 restores the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN from the non-volatile memory device 130 to the storage device 113 (step S506).
[0062] Reference Figure 4 to, when the preloader 120 starts the memory device 310 again, the preloader 120 flash-memory the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN from the non-volatile memory device 130 to the storage device 113. In other words, the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN obtained in step S502 are restored in the storage device 130.
[0063] Reference Figure 5, in step S506, after the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN are restored in the storage device 130, the processor 311 corrects each corresponding access parameter of the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN according to the operating environment (step S507). Therefore, the memory controller 111 accesses the memory array 112 using the access parameter corresponding to one of the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN stored in the storage device 113 (step S508).
[0064] Reference Figure 4 , after the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN are restored in the storage device 130, the preloader 120 is released, and the processor 311 takes over the calibration of each corresponding access parameter of the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN and corrects at least one access parameter that should be corrected.
[0065] According to an embodiment of the present invention, the preloader 120 is a CPU that executes DRAM driving. Since the preloader 120 is released after the access parameters corresponding to the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN are flashed to the storage device 113, the resources of the CPU can be used for the initialization of other devices, thereby achieving the technical effects of power consumption and time savings.
[0066] In addition, the processor 311 corrects at least one access parameter that should be corrected only based on the access parameters flashed from the non-volatile memory device 130 to the storage device 113. Compared with the Figure 2 correction in, the time required to calibrate and correct the access parameters is significantly reduced.
[0067] After the calibration and correction of the access parameters corresponding to the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN are completed, the memory controller 111 accesses the memory array 112 based on each corresponding access parameter of the first mode data DT1, second mode data DT2, third mode data DT3, ..., and Nth mode data DTN.
[0068] Since the storage array 112 is larger and the memory device 310 has more modes, the time required to initialize the memory device 310 is less. According to certain embodiments of the present invention, when the memory device 310 has 4 channels, an 8GB capacity, and 9 access modes, compared with Figure 2 the initialization in
[0069] Apparatuses and methods of operation for DRAM initialization are provided herein. Since the access parameters are flashed to the storage device and only the access parameters that should be corrected are corrected, the initialization time can be significantly reduced, up to one-tenth. In addition, when correcting the access parameters that should be corrected, the resources of the CPU are released, and the calibration and correction are switched to an additional processor in the memory device, and the initialization time of the entire apparatus should be reduced accordingly. In addition, since the processor corrects based on the access parameters flashed to the storage device, the correction time is reduced, further improving the initialization time of the memory device.
[0070] Although some embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention as defined by the appended claims. For example, those skilled in the art will readily understand that many of the features, functions, processes, and materials described in the present invention can be varied while still remaining within the scope of the present invention. In addition, the scope of the present application is not limited to the processes, machines, manufactures, compositions of matter, means, methods, and steps of the specific embodiments described in the specification. As will be readily understood by those skilled in the art from the disclosure of the present invention, currently existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same result can be utilized in accordance with the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufactures, compositions of matter, means, methods, or steps.
Claims
1. An apparatus for memory initialization, comprising: Memory device, comprising: Memory array; Storage device for storing access parameters corresponding to multiple access modes; and Memory controller for accessing the memory array using access parameters corresponding to one of the multiple access modes; Wherein when the memory device is started, the memory controller flashes the access parameters corresponding to each of the multiple access modes to the storage device.
2. The apparatus for memory initialization according to claim 1, wherein Further comprising: Non-volatile memory device for storing all access parameters corresponding to all access modes among the multiple access modes; Wherein when the memory device is started, the memory controller flashes the access parameters corresponding to all access modes among the multiple access modes to the storage device.
3. The apparatus for memory initialization according to claim 2, wherein Further comprising: Preloader for starting the memory device; Wherein when the memory device is turned off, the preloader flashes the access parameters corresponding to each of the multiple access modes from the storage device to the non-volatile memory device.
4. The apparatus for memory initialization according to claim 3, wherein When the preloader starts the memory device for the first time, the preloader calibrates the access parameters corresponding to each of the multiple access modes, and stores the access parameters corresponding to each of the multiple access modes in the storage device.
5. The apparatus for memory initialization according to claim 4, wherein When the preloader starts the memory device again, the preloader flashes the access parameters corresponding to each of the multiple access modes from the non-volatile memory device to the storage device.
6. The apparatus for memory initialization according to claim 5, wherein The memory device further comprises: Processor, when the preloader starts the memory device again, after the preloader flashes the access parameters corresponding to each of the multiple access modes from the non-volatile memory device to the storage device, the processor corrects each of the access parameters corresponding to each of the multiple access modes stored in the storage device according to the operating environment.
7. The apparatus for memory initialization according to claim 6, wherein The preloader is a central processing unit that executes a memory driver; When the processor corrects each of the access parameters corresponding to each of the multiple access modes stored in the storage device, the central processing unit is released and can be used to initialize other devices.
8. The apparatus for memory initialization according to claim 2, wherein The non-volatile memory device is a flash memory.
9. A method for memory initialization, wherein the memory device includes a memory array and a storage device, and the operation method includes the following steps: Start the memory device; When the memory device is started, flash the access parameters corresponding to multiple access modes to the storage device; And Access the memory array using access parameters corresponding to one of the multiple access modes stored in the storage device.
10. The method for memory initialization according to claim 9, wherein Further comprising the following steps: When starting the memory device for the first time, use the preloader to calibrate the access parameters corresponding to each of the multiple access modes; And After calibrating the access parameters corresponding to each of the multiple access modes, store the access parameters corresponding to each of the multiple access modes in the storage device.
11. The method for memory initialization according to claim 10, wherein, Further comprising the following steps: When the memory device is started again, flash the access parameters corresponding to each of the multiple access modes from the non-volatile memory device to the storage device.
12. The method for memory initialization according to claim 11, wherein, Further comprising the following steps: When the memory device is turned off, the access parameters corresponding to each of the access modes are flashed from the storage device to the non-volatile memory device.
13. The method for memory initialization according to claim 12, wherein, Further comprising the following steps: When the circuit is restarted, after the step of flushing each access parameter corresponding to all access modes from the non-volatile memory device to the storage device, the processor is used to correct each access parameter corresponding to each of the multiple access modes stored in the storage device according to the operating environment.
14. The method for memory initialization according to claim 13, wherein, The preloader is a central processing unit that executes the memory driver; and the non-volatile memory device is a flash memory; After each access parameter corresponding to each of the multiple access modes is corrected by the processor, the central processor is released and can be used to initialize other devices.