Display device having pixel driving circuit

Abstract

A display apparatus including a pixel driving circuit and a light emitting device in each pixel area is provided. The pixel driving circuit may be electrically connected to the light emitting device. The pixel driving circuit can generate a driving current corresponding to the data signal according to the gate signal. A driving thin film transistor of a pixel driving circuit may include a driving semiconductor pattern and a driving gate electrode. The driving gate electrode may include a first sub-gate and a second sub-gate electrically connected to the first sub-gate. The driving semiconductor pattern may include a first sub-channel overlapping the first sub-gate and a second sub-channel overlapping the second sub-gate. The first sub-channel and the second sub-channel may be disposed parallel to each other between the driving drain region and the driving source region of the driving semiconductor pattern. The second sub-gate may have a different work function than the first sub-gate. Accordingly, in the display device, an electric field applied to the second sub-channel by the second sub-gate may be different from an electric field applied to the first sub-channel by the first sub-gate.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2023 - 179936, filed on December 12, 2023, which is hereby incorporated by reference in its entirety as if fully set forth herein. Technical field

[0003] The present disclosure relates to a display device in which a pixel driving circuit electrically connected to a light - emitting device is disposed in each pixel region. Background art

[0004] Generally, a display device provides an image to a user. For example, the display device may include a plurality of light - emitting devices. Each light - emitting device may emit light of a specific color. For example, each light - emitting device may include at least one emission material layer between a first electrode and a second electrode.

[0005] Each light - emitting device may be controlled by a pixel driving circuit. For example, a pixel driving circuit electrically connected to one of the light - emitting devices may be disposed in each pixel region of the display device. The pixel driving circuit of each pixel region may provide a driving current corresponding to a data signal to the light - emitting device of the corresponding pixel region according to a gate signal of a frame. For example, the pixel driving circuit of each pixel region may include a driving thin - film transistor that generates a driving current corresponding to the data signal and at least one switching thin - film transistor that transmits the data signal and / or the driving current.

[0006] The gray level of the color realized in each pixel region may be determined by the driving current generated by the driving thin - film transistor of the corresponding pixel region. For example, the driving thin - film transistor of each pixel region may have different electrical characteristics from the switching thin - film transistor of the corresponding pixel region. Therefore, in the display device, the process of forming a pixel driving circuit in each pixel region may be complicated. Therefore, in the display device, the process efficiency may deteriorate. Also, in the display device, the quality of the image may deteriorate due to differences in the characteristics of the pixel driving circuits in each pixel region. Summary of the invention

[0007] Accordingly, the present disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0008] An object of the present disclosure is to provide a display device capable of improving the reliability of a pixel driving circuit in each pixel region.

[0009] Another object of the present disclosure is to provide a display device capable of minimizing deterioration of process efficiency and increasing the driving current generated by the driving thin - film transistor of each pixel region.

[0010] Additional advantages, objects, and features of the present disclosure will be set forth in part in the description which follows, and in part will be obvious to those of ordinary skill in the art upon examination of the following, or may be learned by practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and obtained by means of the structures particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0011] To achieve these objects and other advantages, and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, there is provided a display device including a pixel driving circuit and a light-emitting device. The light-emitting element is electrically connected to the pixel driving circuit. The pixel driving circuit includes a thin-film transistor. The gate of the thin-film transistor includes a first sub-gate and a second sub-gate. The second sub-gate is electrically connected to the first sub-gate. The semiconductor pattern of the thin-film transistor includes a first sub-channel and a second sub-channel. The first sub-channel and the second sub-channel are arranged parallel to each other between the drain region and the source region. The first sub-channel overlaps with the first sub-gate. The second sub-channel overlaps with the second sub-gate. The second sub-gate has a work function greater than that of the first sub-gate.

[0012] The work function ratio of the first sub-gate and the second sub-gate may be 1.2 or less.

[0013] The second sub-channel may be disposed between the drain region and the first sub-channel.

[0014] The resistance of the second sub-channel may be the same as that of the first sub-channel.

[0015] The gate electrode may include a third sub-gate. The third sub-gate may have a work function greater than that of the first sub-gate. The semiconductor pattern may include a third sub-channel overlapping with the third sub-gate. The first sub-channel may be disposed between the second sub-channel and the third sub-channel.

[0016] The work function of the third sub-gate may be the same as that of the second sub-gate.

[0017] The first sub-gate and the second sub-gate may include metal.

[0018] The pixel driving circuit and the light-emitting device may be supported by a device substrate. The first sub-gate and the second sub-gate may be disposed between the device substrate and the semiconductor pattern.

[0019] In another embodiment, a display device including a device substrate is provided. A first thin film transistor, a second thin film transistor, and a light emitting device are disposed on a pixel region of the device substrate. The first thin film transistor includes a first semiconductor pattern and a first gate electrode. The second thin film transistor includes a second semiconductor pattern and a second gate electrode. The light emitting device is electrically connected to the second thin film transistor. The second semiconductor pattern includes a first sub-channel and a second sub-channel. The first sub-channel and the second sub-channel are arranged side by side between a drain region and a source region. The second gate electrode includes a first sub-gate and a second sub-gate. The first sub-gate overlaps with the first sub-channel. The second sub-gate overlaps with the second sub-channel. The second sub-gate is electrically connected to the first sub-gate. An electric field applied by the first sub-gate to the first sub-channel is different from an electric field applied by the second sub-gate to the second sub-channel.

[0020] The first semiconductor pattern and the second semiconductor pattern may include an oxide semiconductor.

[0021] A distance between the second sub-channel and the second sub-gate may be the same as a distance between the first sub-channel and the first sub-gate.

[0022] The second sub-gate may be in contact with a side surface of the first sub-gate.

[0023] The second sub-gate may include a material different from that of the first sub-gate.

[0024] The first gate electrode may include the same material as the first sub-gate.

[0025] A length of the second sub-channel may be different from a length of the first sub-channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the written description, are used to explain the principles of the present disclosure. In the drawings:

[0027] Figure 1 is a view schematically showing a display device according to an embodiment of the present disclosure;

[0028] Figure 2 is a view showing a circuit of a pixel region in a display device according to an embodiment of the present disclosure;

[0029] Figure 3 is a view showing a cross-sectional view taken along I-I' and a cross-sectional view of a pixel region in a display device according to an embodiment of the present disclosure; Figure 1 is a view showing a cross-sectional view taken along I-I' and a cross-sectional view of a pixel region in a display device according to an embodiment of the present disclosure;

[0030] Figure 4 is Figure 3 an enlarged view of a K1 region in;

[0031] Figure 5 is a graph showing the rate of change of an electric field according to the work function ratio of a first sub - gate and a second sub - gate in a display device according to an embodiment of the present disclosure;

[0032] Figure 6 is a graph showing the rate of change of a driving current according to the work function ratio of a first sub - gate and a second sub - gate in a display device according to an embodiment of the present disclosure; and

[0033] Figures 7 to 10 is a view showing a display device according to another embodiment of the present disclosure. Detailed Description of the Invention

[0034] Hereinafter, through the following detailed description with reference to the drawings showing some embodiments of the present disclosure, details related to the above - mentioned objects, technical configurations, and operational effects of the embodiments of the present disclosure will be clearly understood. Here, the embodiments of the present disclosure are provided to enable the technical spirit of the present disclosure to be satisfactorily conveyed to those skilled in the art, and thus the present disclosure can be implemented in other forms and is not limited to the embodiments described below.

[0035] In addition, throughout the specification and the drawings, the same or extremely similar elements may be denoted by the same reference numerals, and for convenience, the lengths and thicknesses of layers and regions may be exaggerated. It should be understood that when a first element is referred to as being "on" a second element, although the first element may be disposed on the second element to be in contact with the second element, a third element may be inserted between the first element and the second element.

[0036] Here, terms such as "first" and "second" may be used to distinguish any one element from another element. However, without departing from the technical spirit of the present disclosure, the first element and the second element may be arbitrarily named according to the convenience of those skilled in the art.

[0037] The terms used in the specification of the present disclosure are only for describing specific embodiments and are not intended to limit the scope of the present disclosure. For example, an element described in the singular form is intended to include a plurality of elements unless the context clearly indicates otherwise. In addition, in the specification of the present disclosure, it should also be understood that the terms "comprising" and "including" specify the presence of the stated features, integers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations.

[0038] Also, unless "directly" is used, the terms "connected" and "coupled" may include that two components are "connected" or "coupled" through one or more other components located between the two components.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0040] (Embodiment)

[0041] Figure 1 is a view schematically showing a display device according to an embodiment of the present disclosure. Figure 2 is a view showing a circuit of a pixel region in a display device according to an embodiment of the present disclosure.

[0042] Referring to Figure 1 and Figure 2 , a display device according to an embodiment of the present disclosure may include a display panel DP. The display panel DP may generate an image provided to a user. For example, the display panel DP may include a plurality of pixel regions PA. Various signals may be provided in each pixel region PA through signal wirings GL, DL, and PL. For example, the signal wirings GL, DL, and PL may include a gate line GL that sequentially applies a gate signal to each pixel region PA, a data line DL that applies a data signal to each pixel region PA, and a power voltage supply line PL that supplies a power voltage to each pixel region PA. The gate line GL may be electrically connected to a gate driver GD. The data line DL may be electrically connected to a data driver DD. The gate driver GD and the data driver DD may be controlled by a timing controller TC. For example, the gate driver GD may receive a clock signal, a reset signal, and a start signal from the timing controller TC, and the data driver DD may receive digital video data and a source timing signal from the timing controller TC. The power voltage supply line PL may be electrically connected to a power supply unit PU.

[0043] The display panel DP may include an active area AA in which the pixel regions PA are provided and a border area BZ provided outside the active area AA. The border area BZ may be provided outside the pixel regions PA. For example, the active area AA may be surrounded by the border area BZ. At least one of the gate driver GD, the data driver DD, the timing controller TC, and the power supply unit PU may be provided on the border area BZ of the display panel DP. For example, a display device according to an embodiment of the present disclosure may be a GIP (gate-in-panel) type display device in which the gate driver GD is formed on the border area BZ of the display panel DP. Each of the signal wirings GL, DL, and PL may include an area provided on the border area BZ.

[0044] Each pixel region PA can implement a specific color. For example, the light-emitting device 500 and the pixel driving circuit DC electrically connected to the light-emitting device 500 can be provided in each pixel region PA. The signal wirings GL, DL, and PL can be electrically connected to the pixel driving circuit DC of each pixel region PA. For example, the pixel driving circuit DC of each pixel region PA can be electrically connected to one of the gate lines GL, one of the data lines DL, and one of the power voltage supply lines PL. The pixel driving circuit DC of each pixel region PA can supply a driving current corresponding to the data signal to the light-emitting device 500 of the corresponding pixel region PA according to the gate signal of one frame. For example, the pixel driving circuit DC of each pixel region PA can include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst.

[0045] Figure 3 is a view showing a cross-sectional view taken along Figure 1 I-I' and a cross-sectional view of a pixel region in a display device according to an embodiment of the present disclosure. Figure 4 is Figure 3 an enlarged view of the K1 region in

[0046] Referring to Figures 2 to 4 , the first thin-film transistor T1 of each pixel region PA can transfer the data signal to the second thin-film transistor T2 of the corresponding pixel region PA according to the gate signal. For example, the first thin-film transistor T1 of each pixel region PA can be a switching thin-film transistor. The first thin-film transistor T1 of each pixel region PA can include a first semiconductor pattern 211, a first gate electrode 213, a first drain electrode 215, and a first source electrode 217. For example, the first gate electrode 213 of each pixel region PA can be electrically connected to the corresponding gate line GL, and the first drain electrode 215 of each pixel region PA can be electrically connected to the corresponding data line DL.

[0047] The first semiconductor pattern 211 can include a semiconductor material. For example, the first semiconductor pattern 211 can include an oxide semiconductor such as IGZO. The first semiconductor pattern 211 can include a first drain region, a first channel region, and a first source region. The first channel region can be provided between the first drain region and the first source region. The first drain region and the first source region can have a lower resistance than the first channel region. For example, the first drain region and the first source region can include a conductive region of an oxide semiconductor. The first channel region can be an unconductivated oxide semiconductor region.

[0048] The first gate electrode 213 may be disposed on a part of the first semiconductor pattern 211. For example, the first gate electrode 213 may overlap with a first channel region of the first semiconductor pattern 211. A first drain region and a first source region of the first semiconductor pattern 211 may be disposed outside the first gate electrode 213. The first gate electrode 213 may include a conductive material. For example, the first gate electrode 213 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first gate electrode 213 may be insulated from the first semiconductor pattern 211. For example, the first drain region of the first semiconductor pattern 211 may be electrically connected to the first source region of the first semiconductor pattern 211 in accordance with a voltage applied to the first gate electrode 213.

[0049] The first drain electrode 215 may include a conductive material. For example, the first drain electrode 215 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first drain electrode 215 may include a material different from that of the first gate electrode 213. The first drain electrode 215 may be disposed on a layer different from that of the first gate electrode 213. For example, the first drain electrode 215 may be insulated from the first gate electrode 213. The first drain electrode 215 may be electrically connected to the first drain region of the first semiconductor pattern 211.

[0050] The first source electrode 217 may include a conductive material. For example, the first source electrode 217 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first source electrode 217 may include a material different from that of the first gate electrode 213. The first source electrode 217 may be disposed on a layer different from that of the first gate electrode 213. For example, the first source electrode 217 may be insulated from the first gate electrode 213. The first source electrode 217 may be disposed on the same layer as the first drain electrode 215. For example, the first source electrode 217 may include the same material as the first drain electrode 215. The first source electrode 217 may be formed by the same process as the first drain electrode 215. For example, the first source electrode 217 may be formed simultaneously with the first drain electrode 215. The first source electrode 217 may be spaced apart from the first drain electrode 215. The first source electrode 217 may be electrically connected to the first source region of the first semiconductor pattern 211.

[0051] The second thin-film transistor T2 of each pixel region PA can generate a driving current corresponding to the data signal. For example, the second thin-film transistor T2 of each pixel region PA can be a driving thin-film transistor. The second thin-film transistor T2 of each pixel region PA can include a second semiconductor pattern 221, a second gate electrode 223, a second drain electrode 225, and a second source electrode 227. For example, the second gate electrode 223 of each pixel region PA can be electrically connected to the first source electrode 217 of the corresponding pixel region PA, and the second drain electrode 225 of each pixel region PA can be electrically connected to the corresponding power supply voltage line PL.

[0052] The second semiconductor pattern 221 can include a semiconductor material. For example, the second semiconductor pattern 221 can include an oxide semiconductor such as IGZO. The second semiconductor pattern 221 can include the same material as the first semiconductor pattern 211. The second semiconductor pattern 221 can be disposed on the same layer as the first semiconductor pattern 211. The second semiconductor pattern 221 can be formed by the same process as the first semiconductor pattern 211. For example, the second semiconductor pattern 221 can be formed simultaneously with the first semiconductor pattern 211.

[0053] The second semiconductor pattern 221 can include a second drain region 221d, a second channel region 221c, and a second source region 221s. The second channel region 221c can be disposed between the second drain region 221d and the second source region 221s. The second drain region 221d and the second source region 221s can have a smaller resistance than the second channel region 221c. For example, the second drain region 221d and the second source region 221s can include conductive regions of an oxide semiconductor. The second channel region 221c can be an unconductivated oxide semiconductor region.

[0054] The second channel region 221c may include a first sub-channel 221c1, a second sub-channel 221c2, and a third sub-channel 221c3 that are parallel to each other between the second drain region 221d and the second source region 221s. The first sub-channel 221c1 may be disposed between the second sub-channel 221c2 and the third sub-channel 221c3. For example, the second sub-channel 221c2 may be disposed between the second drain region 221d and the first sub-channel 221c1, and the third sub-channel 221c3 may be disposed between the first sub-channel 221c1 and the second source region 221s. The resistance of the third sub-channel 221c3 may be the same as the resistance of the second sub-channel 221c2. The second sub-channel 221c2 and the third sub-channel 221c3 may have the same resistance as the first sub-channel 221c1. For example, the amount of oxygen contained in the first sub-channel 221c1 may be the same as the amount of oxygen contained in the second sub-channel 221c2 and the amount of oxygen contained in the third sub-channel 221c3. The amount of oxygen contained in the second drain region 221d and the amount of oxygen contained in the second source region 221s may be less than the amount of oxygen contained in the first sub-channel 221c1, the amount of oxygen contained in the second sub-channel 221c1, and the amount of oxygen contained in the third sub-channel 221c3.

[0055] The second gate electrode 223 may be disposed on a part of the second semiconductor pattern 221. For example, the second gate electrode 223 may be disposed on the second channel region 221c of the second semiconductor pattern 221. The second drain region 221d and the second source region 221s of the second semiconductor pattern 221 may be disposed outside the second gate electrode 223. The second gate electrode 223 may include a conductive material. For example, the second gate electrode 223 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second gate electrode 223 may be insulated from the second semiconductor pattern 221. For example, the second drain region 221d of the second semiconductor pattern 221 may be electrically connected to the second source region 221s of the second semiconductor pattern 221 according to the voltage applied to the second gate electrode 223.

[0056] The second gate electrode 223 may include a first sub-gate G1 and a second sub-gate G2. The first sub-gate G1 may overlap with the first sub-channel 221c1. The second sub-gate G2 may overlap with the first sub-channel 221c1, the second sub-channel 221c2, and the third sub-channel 221c3. For example, the first sub-gate G1 may be disposed between the first sub-channel 221c1 and the second sub-gate G2. The second sub-channel 221c2 and the third sub-channel 221c3 may be disposed outside the first sub-gate G1. For example, a channel generated by the first sub-gate G1 may be formed in the first sub-channel 221c1, and channels generated by the second sub-gate G2 may be formed in the second sub-channel 221c2 and the third sub-channel 221c3. The second sub-gate G2 may be electrically connected to the first sub-gate G1. The distance between the second sub-channel 221c2 and the second sub-gate G2 and the distance between the third sub-channel 221c3 and the second sub-gate G2 may be the same as the distance between the first sub-channel 221c1 and the first sub-gate G1. For example, the lower surface of the first sub-gate G1 facing the second semiconductor pattern 221 may have the same level as the lower surface of the second sub-gate G2 located on the second sub-channel 221c2 and the third sub-channel 221c3 and facing the second semiconductor pattern 221. The first sub-gate G1 may be covered by the second sub-gate G2. The side surface and the upper surface of the first sub-gate G1 facing the second sub-gate G2 may be in direct contact with the second sub-gate G2.

[0057] The first sub-gate G1 and the second sub-gate G2 may be metals. The second sub-gate G2 may include a material different from that of the first sub-gate G1. For example, the work function of the second sub-gate G2 may be different from the work function of the first sub-gate G1. In a general thin film transistor, the electric field applied to the channel of the semiconductor pattern through the gate electrode may be inversely proportional to the work function of the corresponding gate electrode. For example, the electric field applied to the second sub-channel 221c2 through the second sub-gate G2 and the electric field applied to the third sub-channel 221c3 through the second sub-gate G2 may be different from the electric field applied to the first sub-channel 221c1 through the first sub-gate G1.

[0058] Figure 5 is a graph showing the rate of change of the electric field according to the work function ratio of the first sub-gate G1 and the second sub-gate G2 in a display device according to an embodiment of the present disclosure. Figure 6 is a graph showing the rate of change of the driving current according to the work function ratio of the first sub-gate G1 and the second sub-gate G2 in a display device according to an embodiment of the present disclosure.

[0059] Reference Figure 5 and Figure 6, in a display device according to an embodiment of the present disclosure, the work function ratio G1 / G2 of the first sub-gate G1 and the second sub-gate G2 can be inversely proportional to the electric field applied to the second channel region 221c of the second semiconductor pattern 221, and the driving current generated by the second thin film transistor T2 can be proportional to the work function ratio G1 / G2 of the first sub-gate G1 and the second sub-gate G2. For example, when the second sub-gate G2 has a larger work function than the first sub-gate G1, the electric field applied by the second sub-gate G2 to the second sub-channel 221c2 and the third sub-channel 221c3 can be smaller than the electric field applied by the first sub-gate G1 to the first sub-channel 221c1. When the electric field applied to the second sub-channel 221c2 and the third sub-channel 221c3 decreases, the driving current generated by the second thin film transistor T2 can increase. That is, in a display device according to an embodiment of the present disclosure, the driving current generated by the second thin film transistor T2 in each pixel region PA can be increased without reducing the length of the second channel region 221c in each pixel region PA. Therefore, in a display device according to an embodiment of the present disclosure, it is possible to prevent a situation where leakage current occurring in the second semiconductor pattern 221 in each pixel region PA may cause a failure of the second thin film transistor T2 in each pixel region PA, and the electrical characteristics of the second thin film transistor T2 in each pixel region PA can be improved. Therefore, in a display device according to an embodiment of the present disclosure, the efficiency and reliability of the pixel driving circuit DC in each pixel region PA can be improved.

[0060] Reference Figures 2 to 4 , the first sub-channel 221c1 can be disposed between the second sub-channel 221c2 and the third sub-channel 221c3. For example, the second sub-channel 221c2 can be disposed between the second drain region 221d and the first sub-channel 221c1, and the third sub-channel 221c3 can be disposed between the first sub-channel 221c1 and the second source region 221s. Generally, the speed and energy of electrons moving through a channel formed in a semiconductor pattern are proportional to the electric field applied to the corresponding channel. Therefore, in a display device according to an embodiment of the present disclosure, the speed and energy of electrons moving through the channel formed in the second channel region 221c can be reduced due to the second sub-channel 221c2 and the third sub-channel 221c3. That is, in a display device according to an embodiment of the present disclosure, the second sub-channel 221c2 and the third sub-channel 221c3 can be used as a lightly doped drain (LDD). Therefore, in a display device according to an embodiment of the present disclosure, it is possible to prevent a failure of the second thin film transistor T2 in each pixel region PA without a doping process. And, in a display device according to an embodiment of the present disclosure, the reliability of the pixel driving circuit DC in each pixel region PA can be improved.

[0061] The first sub-gate G1 can be disposed on the same layer as the first gate electrode 213. The first sub-gate G1 can include the same material as the first gate electrode 213. The first sub-gate G1 can be formed by the same process as the first gate electrode 213. For example, the first sub-gate G1 can be formed simultaneously with the first gate electrode 213. The second sub-gate G2 can include a material different from that of the first gate electrode 213. For example, the work function of the second sub-gate G2 can be greater than that of the first gate electrode 213. The process of forming the second sub-gate G2 can be performed after forming the first gate electrode 213 and the first sub-gate G1.

[0062] The second drain electrode 225 can include a conductive material. For example, the second drain electrode 225 can include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second drain electrode 225 can include a material different from that of the first sub-gate G1 and the second sub-gate G2. The second drain electrode 225 can be disposed on a layer different from that of the first sub-gate G1 and the second sub-gate G2. For example, the second drain electrode 225 can be insulated from the second gate electrode 223. The second drain electrode 225 can be disposed on the same layer as the first drain electrode 215. The second drain electrode 225 can include the same material as the first drain electrode 215. The second drain electrode 225 can be formed by the same process as the first drain electrode 215. For example, the second drain electrode 225 can be formed simultaneously with the first drain electrode 215. The second drain electrode 225 can be electrically connected to the second drain region 221d of the second semiconductor pattern 221.

[0063] The second source electrode 227 can include a conductive material. For example, the second source electrode 227 can include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second source electrode 227 can include a material different from that of the first sub-gate G1 and the second sub-gate G2. The second source electrode 227 can be disposed on a layer different from that of the first sub-gate G1 and the second sub-gate G2. For example, the second source electrode 227 can be insulated from the second gate electrode 223. The second source electrode 227 can be disposed on the same layer as the second drain electrode 225. The second source electrode 227 can include the same material as the second drain electrode 225. The second source electrode 227 can be formed by the same process as the second drain electrode 225. For example, the second source electrode 227 can be formed simultaneously with the second drain electrode 225. The second source electrode 227 can be spaced apart from the second drain electrode 225. The second source electrode 227 can be electrically connected to the second source region 221s of the second semiconductor pattern 221.

[0064] The storage capacitor Cst of each pixel region PA can maintain the voltage applied to the second gate electrode 223 of the corresponding pixel region PA within one frame. For example, the storage capacitor Cst of each pixel region PA can be electrically connected between the second gate electrode 223 and the second source electrode 227 of the corresponding pixel region PA. The storage capacitor Cst of each pixel region PA can have a stacked structure of capacitor electrodes 251 and 252. The storage capacitor Cst of each pixel region PA can be formed by using the processes for forming the first thin film transistor T1 and the second thin film transistor T2 of the corresponding pixel region PA. For example, the storage capacitor Cst of each pixel region PA can include a first capacitor electrode 251 disposed on the same layer as the first sub-gate G1, and a second capacitor electrode 252 disposed on the same layer as the second source electrode 227. Therefore, in the display device according to an embodiment of the present disclosure, the process of forming the pixel driving circuit DC in each pixel region PA can be simplified. Therefore, in the display device according to an embodiment of the present disclosure, the process efficiency can be improved.

[0065] The gate driver GD formed on the border region BZ may include at least one circuit thin film transistor 290. The circuit thin film transistor 290 may be a switching thin film transistor. For example, the circuit thin film transistor 290 may include a circuit semiconductor pattern 291, a circuit gate electrode 293, a circuit drain electrode 295, and a circuit source electrode 297.

[0066] The circuit semiconductor pattern 291 may include a semiconductor material. The circuit semiconductor pattern 291 may be disposed on a layer different from the first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA. The circuit semiconductor pattern 291 may include a material different from the first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA. For example, the circuit semiconductor pattern 291 may include low temperature polycrystalline silicon (LTPS). The circuit semiconductor pattern 291 may include a circuit drain region, a circuit channel region, and a circuit source region. The circuit channel region may be disposed between the circuit drain region and the circuit source region. The circuit drain region and the circuit source region may have a smaller resistance than the circuit channel region. For example, the circuit drain region and the circuit source region may include conductive impurities. The circuit channel region may be a region not doped with conductive impurities.

[0067] The circuit gate electrode 293 may be disposed on a part of the circuit semiconductor pattern 291. For example, the circuit gate electrode 293 may overlap with the circuit channel region of the circuit semiconductor pattern 291. The circuit drain region and the circuit source region of the circuit semiconductor pattern 291 may be disposed outside the circuit gate electrode 293. The circuit gate electrode 293 may include a conductive material. For example, the circuit gate electrode 293 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The circuit gate electrode 293 may be insulated from the circuit semiconductor pattern 291. For example, the circuit drain region of the circuit semiconductor pattern 291 may be electrically connected to the circuit source region of the circuit semiconductor pattern 291 according to the voltage applied to the circuit gate electrode 293.

[0068] The circuit gate electrode 293 may be disposed on a layer different from the first gate electrode 213, the first sub-gate G1, and the second sub-gate G2 of each pixel region PA. For example, the circuit gate electrode 293 may include a material different from the first gate electrode 213, the first sub-gate G1, and the second sub-gate G2 of each pixel region PA.

[0069] The circuit drain electrode 295 may include a conductive material. For example, the circuit drain electrode 295 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The circuit drain electrode 295 may include a material different from the circuit gate electrode 293. The circuit drain electrode 295 may be disposed on a layer different from the circuit gate electrode 293. For example, the circuit drain electrode 295 may be insulated from the circuit gate electrode 293. The circuit drain electrode 295 may be disposed on the same layer as the first drain electrode 215 of each pixel region PA. The circuit drain electrode 295 may include the same material as the first drain electrode 215 of each pixel region PA. The circuit drain electrode 295 may be formed by the same process as the first drain electrode 215 of each pixel region PA. For example, the circuit drain electrode 295 may be formed simultaneously with the first drain electrode 215 of each pixel region PA. The circuit drain electrode 295 may be electrically connected to the circuit drain region of the circuit semiconductor pattern 291.

[0070] The circuit source electrode 297 may include a conductive material. For example, the circuit source electrode 297 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The circuit source electrode 297 may include a material different from that of the circuit gate electrode 293. The circuit source electrode 297 may be disposed on a layer different from that of the circuit gate electrode 293. For example, the circuit source electrode 297 may be insulated from the circuit gate electrode 293. The circuit source electrode 297 may be disposed on the same layer as the circuit drain electrode 295. The circuit source electrode 297 may include the same material as the circuit drain electrode 295. The circuit source electrode 297 may be formed by the same process as the circuit drain electrode 295. For example, the circuit source electrode 297 may be formed simultaneously with the circuit drain electrode 295. The circuit source electrode 297 may be spaced apart from the circuit drain electrode 295. The circuit source electrode 297 may be electrically connected to the circuit source region of the circuit semiconductor pattern 291.

[0071] The pixel driving circuit DC and the circuit thin film transistor 290 of each pixel region PA may be disposed on the device substrate 100. For example, the light emitting device 500, the pixel driving circuit DC, and the circuit thin film transistor 290 of each pixel region PA may be supported by the device substrate 100. The device substrate 100 may include an insulating material. For example, the device substrate 100 may include glass or plastic. A plurality of insulating layers 110, 121, 122, 130, 140, 150, 160, 170, 180, and 190 for preventing unnecessary electrical connection in each pixel region PA and the gate driver GD may be disposed on the device substrate 100. For example, the lower buffer layer 110, the first gate insulating layer 121, the second gate insulating layer 122, the lower interlayer insulating layer 130, the partition insulating layer 140, the upper buffer layer 150, the upper interlayer insulating layer 160, the lower planarization layer 170, the upper planarization layer 180, and the bank insulating layer 190 may be disposed on the device substrate 100.

[0072] The lower buffer layer 110 may be disposed close to the device substrate 100. The lower buffer layer 110 may prevent contamination caused by the device substrate 100 in the process of forming the pixel driving circuit DC and the circuit thin film transistor 290 of each pixel region PA. For example, the upper surface of the device substrate 100 facing the pixel driving circuit DC and the circuit thin film transistor 290 of each pixel region PA may be completely covered by the lower buffer layer 110. The lower buffer layer 110 may be in direct contact with the upper surface of the device substrate 100. The pixel driving circuit DC and the circuit thin film transistor 290 of each pixel region PA may be disposed on the lower buffer layer 110. The lower buffer layer 110 may include an insulating material. For example, the lower buffer layer 110 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0073] The first gate insulating layer 121 may be disposed on the lower buffer layer 110. The circuit gate electrode 293 may be insulated from the circuit semiconductor pattern 291 through the first gate insulating layer 121. For example, the circuit semiconductor pattern 291 may be covered by the first gate insulating layer 121. The circuit gate electrode 293 may be disposed on the first gate insulating layer 121. The first gate insulating layer 121 may include an insulating material. For example, the first gate insulating layer 121 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0074] The interlayer insulating layer 130 may be disposed on the first gate insulating layer 121. The circuit drain electrode 295 and the circuit source electrode 297 may be insulated from the circuit gate electrode 293 through the interlayer insulating layer 130. For example, the circuit gate electrode 293 may be covered by the interlayer insulating layer 130. The circuit drain electrode 295 and the circuit source electrode 297 may be disposed on the interlayer insulating layer 130. The interlayer insulating layer 130 may include an insulating material. For example, the interlayer insulating layer 130 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0075] The first light blocking pattern 310 may be disposed between the first gate insulating layer 121 and the interlayer insulating layer 130 in each pixel region PA. The first light blocking pattern 310 in each pixel region PA may include a material that absorbs or reflects light. For example, the first light blocking pattern 310 in each pixel region PA may include a metal. The first light blocking pattern 310 in each pixel region PA may be disposed on the same layer as the circuit gate electrode 293. The first light blocking pattern 310 in each pixel region PA may include the same material as the circuit gate electrode 293. The first light blocking pattern 310 in each pixel region PA may be formed through the same process as the circuit gate electrode 293. For example, the first light blocking pattern 310 in each pixel region PA may be formed simultaneously with the circuit gate electrode 293. The first light blocking pattern 310 in each pixel region PA may overlap with the first semiconductor pattern 211 in the corresponding pixel region PA. For example, light traveling through the device substrate 100 toward the first semiconductor pattern 211 in each pixel region PA may be blocked by the first light blocking pattern 310 in the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, characteristics of the first thin film transistor T1 in each pixel region PA may be prevented from being different due to external light without reducing process efficiency.

[0076] A specific voltage may be applied to the first light-blocking pattern 310 of each pixel region PA. For example, the first light-blocking pattern 310 of each pixel region PA may be electrically connected to the first gate electrode 213 of the corresponding pixel region PA. Thus, in a display device according to an embodiment of the present disclosure, the first light-blocking pattern 310 of each pixel region PA may serve as the gate electrode of the first thin-film transistor T1 in the corresponding pixel region PA. Thus, in a display device according to an embodiment of the present disclosure, the response speed of the first thin-film transistor T1 in each pixel region PA may be increased.

[0077] The separation insulating layer 140 may be disposed on the interlayer insulating layer 130. The separation insulating layer 140 may prevent the circuit semiconductor pattern 291 from being deteriorated and damaged due to the process of forming the pixel driving circuit DC in each pixel region PA. For example, the first thin-film transistor T1, the second thin-film transistor T2, and the storage capacitor Cst of each pixel region PA may be disposed on the separation insulating layer 140. The separation insulating layer 140 may include an insulating material. For example, the separation insulating layer 140 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The separation insulating layer 140 may be thicker than the interlayer insulating layer 130. The separation insulating layer 140 may have a multi-layer structure. For example, the separation insulating layer 140 may have a stacked structure of an inorganic insulating layer made of silicon oxide (SiOx) and an inorganic insulating layer made of silicon nitride (SiNx).

[0078] The upper buffer layer 150 may be disposed on the separation insulating layer 140. The upper buffer layer 150 may prevent contamination caused by the first light-blocking pattern 310, the circuit semiconductor pattern 291, and the circuit gate electrode 293 of each pixel region PA during the process of forming the first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA. For example, the first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA may be disposed on the upper buffer layer 150. The upper buffer layer 150 may include an insulating material. For example, the upper buffer layer 150 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0079] The second light-blocking pattern 320 may be disposed between the partition insulating layer 140 and the upper buffer layer 150 of each pixel region PA. The second light-blocking pattern 320 of each pixel region PA may include a material that absorbs or reflects light. For example, the second light-blocking pattern 320 of each pixel region PA may include a metal. The second light-blocking pattern 320 of each pixel region PA may overlap with the second semiconductor pattern 221 of the corresponding pixel region PA. For example, light traveling through the device substrate 100 toward the second semiconductor pattern 221 of each pixel region PA may be blocked by the second light-blocking pattern 320 of the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, characteristics of the second thin-film transistor T2 in each pixel region PA may be prevented from being different due to external light.

[0080] A specific voltage may be applied to the second light-blocking pattern 320 of each pixel region PA. For example, the second light-blocking pattern 320 of each pixel region PA may be electrically connected to the second drain electrode 225 of the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, characteristics of the second thin-film transistor T2 in each pixel region PA may be effectively prevented from being different due to external light.

[0081] The distance between the second light-blocking pattern 320 and the second semiconductor pattern 221 in each pixel region PA may be less than the distance between the first light-blocking pattern 310 and the first semiconductor pattern 211 in the corresponding pixel region PA. Generally, a change amount of an effective gate voltage of a thin-film transistor disposed on a conductive pattern may be determined by the following equation. Here, ΔV eff represents the change amount of the effective gate voltage, ΔV GAT represents the change amount of the voltage applied to the gate electrode, C1 represents the capacitance of a parasitic capacitor formed between the conductive pattern and the semiconductor pattern of the corresponding thin-film transistor, C2 represents the capacitance of a parasitic capacitor formed between the semiconductor pattern of the corresponding thin-film transistor and the gate electrode, and C ACT represents the capacitance of a parasitic capacitor formed by the voltage applied to the drain region and the source region of the corresponding thin-film transistor.

[0082] [Equation]

[0083]

[0084] The capacitance of a capacitor is inversely proportional to the distance between the conductors constituting the corresponding capacitor. In a display device according to an embodiment of the present disclosure, the capacitance of the parasitic capacitor formed between the second light-blocking pattern 320 and the second semiconductor pattern 221 in each pixel region PA may be greater than the capacitance of the parasitic capacitor formed between the first light-blocking pattern 310 and the first semiconductor pattern 211 in the corresponding pixel region PA. Accordingly, in a display device according to an embodiment of the present disclosure, the amount of change in the effective gate voltage of the second thin-film transistor T2 in each pixel region PA may be less than the amount of change in the effective gate voltage of the first thin-film transistor T1 in the corresponding pixel region PA. In a general thin-film transistor, when the amount of change in the effective gate voltage decreases, the amount of change in the current according to the change in the voltage applied to the gate electrode of the corresponding thin-film transistor may decrease, and the S-factor of the corresponding thin-film transistor may increase. Here, the S-factor of a thin-film transistor refers to the inverse ratio of the amount of change in the current generated by the corresponding thin-film transistor to the amount of change in the voltage applied to the gate electrode of the corresponding thin-film transistor. That is, in a display device according to an embodiment of the present disclosure, the S-factor of the second thin-film transistor T2 in each pixel region PA may have a greater value than the S-factor of the first thin-film transistor T1 in the corresponding pixel region PA, and the amount of change in the driving current generated by the corresponding pixel region PA according to the change in the voltage applied to the second gate electrode 223 of the corresponding pixel region PA may be reduced. Accordingly, in a display device according to an embodiment of the present disclosure, when a low gray-level image is implemented, the appearance of stains may be prevented.

[0085] The second gate insulating layer 122 may be disposed on the upper buffer layer 150. The first gate electrode 213 and the second gate electrode 223 of each pixel region PA may be insulated from the first semiconductor pattern 211 and the second semiconductor pattern 221 of the corresponding pixel region PA through the second gate insulating layer 122. For example, the first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA may be covered by the second gate insulating layer 122. The first sub-gate G1 of each pixel region PA may be disposed between the second gate insulating layer 122 and the second sub-gate G2 of the corresponding pixel region PA. The second gate insulating layer 122 may include an insulating material. For example, the second gate insulating layer 122 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0086] The upper interlayer insulating layer 160 may be disposed on the second gate insulating layer 122. The first drain electrode 215, the first source electrode 217, the second drain electrode 225, and the second source electrode 227 of each pixel region PA may be insulated from the first gate electrode 213 and the second gate electrode 223 of the corresponding pixel region PA through the upper interlayer insulating layer 160. For example, the first gate electrode 213 and the second gate electrode 223 of each pixel region PA may be covered by the upper interlayer insulating layer 160. The second sub-gate G2 of each pixel region PA may be disposed between the first sub-gate G1 of the corresponding pixel region PA and the upper interlayer insulating layer 160. The first drain electrode 215, the first source electrode 217, the second drain electrode 225, and the second source electrode 227 of each pixel region PA may be disposed on the upper interlayer insulating layer 160. The upper interlayer insulating layer 160 may include an insulating material. For example, the upper interlayer insulating layer 160 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0087] The first drain electrode 215 of each pixel region PA may be electrically connected to the first drain region of the first semiconductor pattern 211 in the corresponding pixel region PA through the second gate insulating layer 122 and the upper interlayer insulating layer 160 of the corresponding pixel region PA, and the first source electrode 217 of each pixel region PA may be electrically connected to the first source region of the first semiconductor pattern 211 in the corresponding pixel region PA through the second gate insulating layer 122 and the upper interlayer insulating layer 160 of the corresponding pixel region PA. The second drain electrode 225 of each pixel region PA may be electrically connected to the second drain region 221d of the second semiconductor pattern 221 in the corresponding pixel region PA through the second gate insulating layer 122 and the upper interlayer insulating layer 160 of the corresponding pixel region PA, and the second source electrode 227 of each pixel region PA may be electrically connected to the second source region 221s of the second semiconductor pattern 221 in the corresponding pixel region PA through the second gate insulating layer 122 and the upper interlayer insulating layer 160 of the corresponding pixel region PA. In each pixel region PA, the contact holes for connecting the first drain electrode 215 and the first drain region and the contact holes for connecting the first source electrode 217 and the first source region may be formed simultaneously with the contact holes for connecting the second drain electrode 225 and the second drain region 221d and the contact holes for connecting the second source electrode 227 and the second source region 221s. Therefore, in the display device according to an embodiment of the present disclosure, the process efficiency may be improved.

[0088] The second drain electrode 255 of each pixel region PA may be connected to the second light blocking pattern 320 of the corresponding pixel region PA by penetrating the upper buffer layer 150, the second gate insulating layer 122, and the upper interlayer insulating layer 160. The circuit drain electrode 295 may be connected to the circuit drain region of the circuit semiconductor pattern 291 by penetrating the first gate insulating layer 121, the lower interlayer insulating layer 130, the partition insulating layer 140, the upper buffer layer 150, the second gate insulating layer 122, and the upper interlayer insulating layer 160, and the circuit source electrode 297 may be connected to the circuit source region of the circuit semiconductor pattern 291 by penetrating the first gate insulating layer 121, the lower interlayer insulating layer 130, the partition insulating layer 140, the upper buffer layer 150, the second gate insulating layer 122, and the upper interlayer insulating layer 160. The contact holes for the connection between the circuit drain electrode 295 and the circuit drain region and the contact holes for the connection between the circuit source electrode 297 and the circuit source region may be formed by using the process of forming the contact holes for the connection between the second drain electrode 225 and the second light blocking pattern 320 of each pixel region PA. For example, the circuit drain electrode 295 and the circuit source electrode 297 may penetrate the upper buffer layer 150, the second gate insulating layer 122, and the upper interlayer insulating layer 160 through holes formed simultaneously with the contact holes for the connection between the second drain electrode 255 and the second light blocking pattern 320 of each pixel region PA.

[0089] The lower planarization layer 170 may be disposed on the upper interlayer insulating layer 160. The upper planarization layer 180 may be disposed on the lower planarization layer 170. The lower planarization layer 170 and the upper planarization layer 180 may remove the thickness difference caused by the pixel driving circuit DC of each pixel region PA. For example, the first drain electrode 215, the first source electrode 217, the second drain electrode 225, the second source electrode 227, and the second capacitor electrode 252 of each pixel region PA may be covered by the lower planarization layer 170. The lower planarization layer 170 and the upper planarization layer 180 may extend onto the border region BZ of the device substrate 100. For example, the lower planarization layer 170 and the upper planarization layer 180 may be stacked on the circuit drain electrode 295 and the circuit source electrode 297. The thickness difference caused by the circuit thin film transistor 290 may be removed by the lower planarization layer 170 and the upper planarization layer 180. The upper surface of the upper planarization layer 180 opposite to the device substrate 100 may be a flat surface.

[0090] The lower planarization layer 170 and the upper planarization layer 180 may include an insulating material. The lower planarization layer 170 and the upper planarization layer 180 may include a material different from that of the upper interlayer insulating layer 160. The lower planarization layer 170 and the upper planarization layer 180 may include a material having relatively high fluidity. For example, the lower planarization layer 170 and the upper planarization layer 180 may include an organic insulating material. The upper planarization layer 180 may include the same material as the lower planarization layer 170. For example, the interface between the lower planarization layer 170 and the upper planarization layer 180 may not be recognizable.

[0091] The light-emitting device 500 of each pixel region PA may be disposed on the upper planarization layer 180 corresponding to the pixel region PA. The light-emitting device 500 of each pixel region PA may emit light of a specific color for display. For example, the light-emitting device 500 of each pixel region PA may include a first electrode 510, a light-emitting unit 520, and a second electrode 530 sequentially stacked on the upper planarization layer 180 corresponding to the pixel region PA.

[0092] The first electrode 510 may include a conductive material. The first electrode 510 may include a material having a high reflectivity. For example, the first electrode 510 may include a metal such as aluminum (Al) or silver (Ag). The first electrode 510 may have a multilayer structure. For example, the first electrode 510 may have a structure in which a reflective electrode made of a metal is disposed between transparent electrodes made of a transparent conductive material such as ITO and IZO.

[0093] The light-emitting unit 520 may generate light having a brightness corresponding to the voltage difference between the first electrode 510 and the second electrode 530. For example, the light-emitting unit 520 may include at least one emission material layer (EML). The emission material layer may include an emission material. The emission material may include an organic material, an inorganic material, or a hybrid material. For example, the display device according to an embodiment of the present disclosure may be an organic light-emitting display device including an organic emission material.

[0094] The light-emitting unit 520 may include at least one functional layer to smoothly supply holes or electrons. For example, the light-emitting unit 520 may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Therefore, in the display device according to an embodiment of the present disclosure, the efficiency of the light-emitting unit 520 may be improved.

[0095] The second electrode 530 may include a conductive material. The second electrode 530 may include a material different from that of the first electrode 510. The transmittance of the second electrode 530 may be greater than that of the first electrode 510. For example, the second electrode 530 may be a transparent electrode made of a transparent conductive material such as ITO and IZO, or a semi-transparent electrode in which a metal such as Ag and Mg is thinly formed. Therefore, in the display device according to an embodiment of the present disclosure, the light generated by the light emitting unit 520 may be emitted to the outside through the second electrode 530.

[0096] The light emitting device 500 of each pixel region PA may be electrically connected to the second thin film transistor T2 of the corresponding pixel region PA. For example, the first electrode 510 of each pixel region PA may be electrically connected to the second source electrode 227 of the corresponding pixel region PA. The first electrode 510 of each pixel region PA may include a region in direct contact with the upper surface of the upper planarization layer 180 on the corresponding pixel region PA. The light emitting unit 520 and the second electrode 530 of each pixel region PA may be stacked on the region of the corresponding first electrode 510 that is in direct contact with the upper surface of the upper planarization layer 180. Therefore, in the display device according to an embodiment of the present disclosure, luminance deviation according to the generation position of the light emitted from the light emitting device 500 of each pixel region PA may be prevented.

[0097] The intermediate electrode 400 that electrically connects the first electrode 510 of each pixel region PA to the second source electrode 227 of the corresponding pixel region PA may be disposed between the lower planarization layer 170 and the upper planarization layer 180 of the corresponding pixel region PA. The intermediate electrode 400 of each pixel region PA may include a conductive material. The intermediate electrode 400 of each pixel region PA may include a material having a relatively small resistance. For example, the intermediate electrode 400 may include a metal. The intermediate electrode 400 of each pixel region PA may be in direct contact with the second source electrode 227 and the first electrode 510 of the corresponding pixel region PA. For example, the intermediate electrode 400 of each pixel region PA may be connected to the second source electrode 227 of the corresponding pixel region PA by penetrating the lower planarization layer 170, and the first electrode 510 of each pixel region PA may be connected to the intermediate electrode 400 of the corresponding pixel region PA by penetrating the upper planarization layer 180. Therefore, in the display device according to an embodiment of the present disclosure, the first electrode 510 of each pixel region PA may be stably connected to the second source electrode 227 of the corresponding pixel region PA. Therefore, in the display device according to an embodiment of the present disclosure, the reliability of the electrical connection between the pixel driving circuit DC and the light emitting device 500 in each pixel region PA may be improved.

[0098] The bank insulation layer 190 may be disposed on the upper planarization layer 180. The bank insulation layer 190 may define an emission region in each pixel region PA. For example, the bank insulation layer 190 may partially expose the first electrode 510 in each pixel region PA. The portion of each first electrode 510 exposed by the bank insulation layer 190 may be a region directly contacting the upper surface of the upper planarization layer 180. For example, the light-emitting unit 520 and the second electrode 530 in each pixel region PA may be stacked on the portion of the corresponding first electrode 510 exposed by the bank insulation layer 190. The edge of the first electrode 510 in each pixel region PA may be covered by the bank insulation layer 190. For example, the first electrode 510 in each pixel region PA may be insulated from the first electrode 510 in an adjacent pixel region PA through the bank insulation layer 190. The bank insulation layer 190 may include an insulating material. For example, the bank insulation layer 190 may include an organic insulating material. The bank insulation layer 190 may include a material different from that of the upper planarization layer 180.

[0099] The light emitted from the light-emitting device 500 in each pixel region PA may display a color different from the light emitted from the light-emitting device 500 in an adjacent pixel region PA. For example, the light-emitting unit 520 in each pixel region PA may be spaced apart from the light-emitting unit 520 in an adjacent pixel region PA. The light-emitting layer 520 in each pixel region PA may include an end portion located on the bank insulation layer 190.

[0100] The voltage applied to the second electrode 530 in each pixel region PA may be the same as the voltage applied to the second electrode 530 in an adjacent pixel region PA. For example, the second electrode 530 in each pixel region PA may be electrically connected to the second electrode 530 in an adjacent pixel region PA. The second electrode 530 in each pixel region PA may include the same material as the second electrode 530 in an adjacent pixel region PA. The second electrode 530 in each pixel region PA may be formed through the same process as the second electrode 530 in an adjacent pixel region PA. For example, the second electrode 530 in each pixel region PA may be formed simultaneously with the second electrode 530 in an adjacent pixel region PA. The second electrode 530 in each pixel region PA may be in direct contact with the second electrode 530 in an adjacent pixel region PA. For example, the second electrode 530 in each pixel region PA may extend on the bank insulation layer 160. Accordingly, in the display device according to an embodiment of the present disclosure, the process of forming the second electrode 530 in each pixel region PA may be simplified. Also, in the display device according to an embodiment of the present disclosure, the brightness of the light generated by the light-emitting device 500 in each pixel region PA may be adjusted through a data signal applied to a pixel driving circuit DC in the corresponding pixel region PA.

[0101] The encapsulation unit 600 may be disposed on the light-emitting device 500 in each pixel region PA. The encapsulation unit 600 may prevent the light-emitting device 500 from being damaged due to external moisture and impact. The encapsulation unit 600 may have a multilayer structure. For example, the encapsulation unit 600 may include a first encapsulation layer 610, a second encapsulation layer 620, and a third encapsulation layer 630 stacked in sequence. The first encapsulation layer 610, the second encapsulation layer 620, and the third encapsulation layer 630 may include an insulating material. The second encapsulation layer 620 may include a material different from that of the first encapsulation layer 610 and the third encapsulation layer 630. For example, the first encapsulation layer 610 and the third encapsulation layer 630 may include inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx), and the second encapsulation layer 620 may include an organic insulating material. The thickness difference caused by the light-emitting device 500 in each pixel region PA may be removed by the second encapsulation layer 620. For example, the upper surface of the encapsulation unit 600 facing the device substrate 100 may be a flat surface. Therefore, in the display device according to an embodiment of the present disclosure, the light-emitting device 500 in each pixel region PA can be effectively prevented from being damaged due to external moisture and impact.

[0102] Accordingly, the display device according to an embodiment of the present disclosure may include a pixel driving circuit DC and a light-emitting device 500 in each pixel region PA, wherein the pixel driving circuit DC electrically connected to the light-emitting device 500 may include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst, wherein a second gate electrode 223 of the second thin-film transistor T2 serving as a driving thin-film transistor may include a first sub-gate G1 and a second sub-gate G2 disposed side by side between a second drain electrode 225 and a second source electrode 227 of the second thin-film transistor T2, and wherein the second sub-gate G2 electrically connected to the first sub-gate G1 may have a work function different from that of the first sub-gate G1. Accordingly, in the display device according to an embodiment of the present disclosure, the electric field applied to the second channel region 221c of the second thin-film transistor T2 by the second sub-gate G2 may be different from the electric field applied to the second channel region 221 by the first sub-gate G1. That is, in the display device according to an embodiment of the present disclosure, the driving current generated by the second thin-film transistor T2 can be increased by the second sub-gate G2 having a relatively large work function without reducing the length of the second channel region 221. Accordingly, in the display device according to an embodiment of the present disclosure, the deterioration of process efficiency can be minimized, and the electrical characteristics of the second thin-film transistor T2 in each pixel region PA can be improved. Also, in the display device according to an embodiment of the present disclosure, the efficiency and reliability of the pixel driving circuit DC in each pixel region PA can be improved.

[0103] Reference Figure 5 and Figure 6, in a display device according to an embodiment of the present disclosure, the electric field applied to the second channel region 221c of the second semiconductor pattern 221 may not change significantly. However, when the work function ratio G1 / G2 of the first sub-gate G1 and the second sub-gate G2 is 1.2 or greater, the driving current generated by the second thin film transistor T2 may continuously increase. That is, in a display device according to an embodiment of the present disclosure, Figure 5 and Figure 6 The graph of may be interpreted as that when the work function ratio G1 / G2 of the first sub-gate G1 and the second sub-gate G2 is 1.2 or greater, charges accumulate in the second gate insulating layer 122. In a general thin film transistor, when charges accumulate excessively in the gate insulating layer, the threshold voltage may decrease and the possibility of leakage current may increase. Therefore, in a display device according to an embodiment of the present disclosure, the work function ratio G1 / G2 of the first sub-gate G1 and the second sub-gate G2 in each pixel region PA may be 1.2 or less. Therefore, in a display device according to an embodiment of the present disclosure, the characteristic differences of the second thin film transistor T2 serving as a driving thin film transistor can be prevented, and the reliability of the pixel driving circuit DC in each pixel region PA can be effectively improved.

[0104] In a display device according to an embodiment of the present disclosure, the sum of the lengths of the second sub-channel 221c2 and the third sub-channel 221c3 may be the same as the length of the first sub-channel 221c1. The length of the third sub-channel 221c3 may be the same as the length of the second sub-channel 221c2. For example, in a display device according to an embodiment of the present disclosure, the lengths of the second sub-channel 221c2 and the third sub-channel 221c3 may be half of the length of the first sub-channel 221c1. Therefore, in a display device according to an embodiment of the present disclosure, the electric field applied to the second channel region 221c of the second semiconductor pattern 221 can be effectively reduced by the second sub-gate G2 having a relatively large work function.

[0105] A display device according to an embodiment of the present disclosure is described as follows: The driving circuit DC of each pixel region PA may be composed of a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. However, in a display device according to another embodiment of the present disclosure, the pixel driving circuit DC of each pixel region PA may include a driving thin-film transistor and at least one switching thin-film transistor. For example, in a display device according to another embodiment of the present disclosure, the pixel driving circuit DC of each pixel region PA may include a first thin-film transistor T1, a second thin-film transistor T2, a storage capacitor Cst, and a third thin-film transistor. The third thin-film transistor of each pixel region PA may be a switching thin-film transistor to initialize the storage capacitor Cst of the corresponding pixel region PA according to a gate signal. For example, the third thin-film transistor of each pixel region PA may include a third gate electrode electrically connected to the corresponding gate line GL, a third drain electrode electrically connected to an initial line to which an initial signal is applied, and a third source electrode electrically connected to the corresponding storage capacitor Cst. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of each pixel driving circuit DC can be increased.

[0106] In a display device according to an embodiment of the present disclosure, the positions and electrical connections of the first drain electrode 215, the first source electrode 217, the second drain electrode 225, and the second source electrode 227 in each pixel driving circuit DC may vary according to the configuration of the corresponding pixel driving circuit DC and / or the types of the corresponding thin-film transistors T1 and T2. For example, in a display device according to another embodiment of the present disclosure, the second gate electrode 223 of each pixel driving circuit DC may be electrically connected to the first drain electrode 215 of the corresponding pixel driving circuit DC. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of each pixel driving circuit DC and the types of each thin-film transistor T1 and T2 can be increased.

[0107] A display device according to an embodiment of the present disclosure is described as follows: The first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA may be made of an oxide semiconductor. However, in a display device according to another embodiment of the present disclosure, the second semiconductor pattern 221 of each pixel region PA may include a material different from the first semiconductor pattern 211 of the corresponding pixel region PA. For example, in a display device according to another embodiment of the present disclosure, the first semiconductor pattern 211 of each pixel region PA may include low-temperature polycrystalline silicon (LTPS). The first thin-film transistor T1 of each pixel region PA may be formed to have the same structure as the circuit thin-film transistor 290. For example, the first semiconductor pattern 211 of each pixel region PA may be disposed between the lower buffer layer 110 and the first gate insulating layer 121, and the first gate electrode 213 of each pixel region PA may be disposed between the first gate insulating layer 121 and the lower interlayer insulating layer 130. In a display device according to another embodiment of the present disclosure, the first light-blocking pattern 310 of each pixel region PA may not be formed. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in configuring each pixel driving circuit DC and the types of each of the thin-film transistors T1 and T2 can be increased.

[0108] A display device according to an embodiment of the present disclosure is described as follows: The upper planarization layer 180 may include the same material as the lower planarization layer 170. However, in a display device according to another embodiment of the present disclosure, the upper planarization layer 180 may include a material different from the lower planarization layer 170. Therefore, in a display device according to another embodiment of the present disclosure, the thickness difference caused by the pixel driving circuit DC and the circuit thin-film transistor 290 of each pixel region PA can be effectively removed.

[0109] A display device according to an embodiment of the present disclosure is described as follows: The first sub-gate G1 and the second sub-gate G2 may include a metal. However, in a display device according to another embodiment of the present disclosure, at least one of the first sub-gate G1 and the second sub-gate G2 may include a conductive oxide such as ITO and IZO. For example, in a display device according to another embodiment of the present disclosure, the first sub-gate G1 may have a single-layer structure made of a metal, and the second sub-gate G2 may have a multi-layer structure in which a layer made of a metal and a layer made of a conductive oxide are stacked. Therefore, in a display device according to another embodiment of the present disclosure, the work function ratio G1 / G2 of the first sub-gate G1 and the second sub-gate G2 can be effectively adjusted. Therefore, in a display device according to another embodiment of the present disclosure, the efficiency and reliability of the pixel driving circuit DC in each pixel region PA can be improved.

[0110] A display device according to an embodiment of the present disclosure is described as: the amount of oxygen contained in the second sub-channel 221c2 and the amount of oxygen contained in the third sub-channel 221c3 may be the same as the amount of oxygen contained in the first sub-channel 221c1. However, in a display device according to another embodiment of the present disclosure, the resistance of the second sub-channel 221c2 and the resistance of the third sub-channel 221c3 may be different from the resistance of the first sub-channel 221c1. For example, in a display device according to another embodiment of the present disclosure, the second sub-channel 221c2 may have a resistance between the second drain region 221d and the first sub-channel 221c1, and the third sub-channel 221c3 may have a resistance between the first sub-channel 221c1 and the second source region 221s. The second drain region 221d, the second sub-channel 221c2, the third sub-channel 221c3, and the second source region 221s may include conductive impurities. For example, in a display device according to another embodiment of the present disclosure, the second sub-channel 221c2 and the third sub-channel 221c3 may be doped with conductive impurities at a low concentration, and the second drain region 221d and the second source region 221d may be doped with conductive impurities at a low concentration. Therefore, in a display device according to another embodiment of the present disclosure, deterioration of the characteristics of the second thin film transistor T2 due to hot carrier effects between the second drain region 221d and the first sub-channel 221c1 and between the first sub-channel 221c1 and the second source region 221s can be effectively prevented.

[0111] A display device according to an embodiment of the present disclosure is described as: the second channel region 221c of the second semiconductor pattern 221 may include a first sub-channel 221c1, a second sub-channel 221c2, and a third sub-channel 221c3. However, in a display device according to another embodiment of the present disclosure, the second channel region 221c of the second semiconductor pattern 221 may include at least two sub-channels. For example, in a display device according to another embodiment of the present disclosure, the second semiconductor pattern 221 may include a first sub-channel 221c1 between the second drain region 221d and the second source region 221s and a second sub-channel 221c2 between the first sub-channel 221c1 and the second source region 221s, as Figure 7As shown. The second sub-gate G2 may include an end portion on the upper surface of the first sub-gate G1. For example, the first sub-gate G1 may include a region in direct contact with the upper interlayer insulating layer 160. Thus, in a display device according to another embodiment of the present disclosure, the electric field between the first sub-channel 221c1 and the second sub-channel 221c1 in each pixel region PA may be changed by the difference in work function between the first sub-gate G1 and the second sub-gate G2 of the corresponding pixel region PA. For example, in a display device according to another embodiment of the present disclosure, the speed of electrons accelerated in the channel formed by the second sub-gate G2 having a relatively large work function in the second sub-channel 221c2 may be reduced by the channel formed by the first sub-gate G1 having a relatively small work function in the first sub-channel 221c1. Thus, in a display device according to another embodiment of the present disclosure, deterioration of the characteristics of the second thin film transistor due to the hot carrier effect between the second drain region 221d and the second source region 221s may be prevented.

[0112] In a display device according to another embodiment of the present disclosure, the length of the second sub-channel 221c2 may be different from the length of the first sub-channel 221c1. For example, the second sub-channel 221c2 may have a longer length than the first sub-channel 221c1. The speed and energy of electrons moving from the second source region 221s to the second drain region 221d may be proportional to the length of the second sub-channel 221c2. That is, in a display device according to another embodiment of the present disclosure, the drive current generated by the second thin film transistor may be maximized without deteriorating the characteristics of the second thin film transistor by adjusting the relative lengths of the first sub-channel 221c1 and the second sub-channel 221c2. Thus, in a display device according to another embodiment of the present disclosure, the efficiency of the pixel driving circuit in each pixel region may be maximized.

[0113] A display device according to an embodiment of the present disclosure is described as: the channel of the second sub-channel 221c2 and the channel of the third sub-channel 221c3 may be formed by the second sub-gate G2. However, in a display device according to another embodiment of the present disclosure, the second gate electrode may include a first sub-gate G1 overlapping with the first sub-channel 221c1, a second sub-gate G2 overlapping with the second sub-channel 221c2, and a third sub-gate G3 overlapping with the third sub-channel 221c3, as Figure 8 shown. The third sub-gate G3 may be spaced apart from the second sub-gate G2. The third sub-gate G3 may be electrically connected to the first sub-gate G1 and the second sub-gate G2. For example, the first side of the first sub-gate G1 may be in direct contact with the second sub-gate G2, and the second side of the first sub-gate G1 may be in direct contact with the third sub-gate G3.

[0114] The third sub-gate G3 may have a larger work function than the first sub-gate G1. For example, the work function of the third sub-gate G3 may be the same as the work function of the second sub-gate G2. The third sub-gate G3 may include the same material as the second sub-gate G2. The third sub-gate G3 may be formed by the same process as the second sub-gate G2. For example, the third sub-gate G3 may be formed simultaneously with the second sub-gate G2. Accordingly, in a display device according to another embodiment of the present disclosure, the degree of freedom of the second gate electrode in each pixel region may be increased.

[0115] A display device according to an embodiment of the present disclosure has been described as: a second semiconductor pattern 221 of each pixel region PA may be disposed between the device substrate 100 and the second gate electrode 223 of the corresponding pixel region PA. However, in a display device according to another embodiment of the present disclosure, the structure of the second thin film transistor T2 in each pixel region PA may be different from the structure of the first thin film transistor T1 in the corresponding pixel region PA. For example, in a display device according to another embodiment of the present disclosure, a first semiconductor pattern 211 of each pixel region PA may be disposed between the device substrate 100 and the first gate electrode 213 of the corresponding pixel region PA, and the first sub-gate G1 and the second sub-gate G2 of each pixel region PA may be disposed between the device substrate 100 and the second semiconductor pattern 221 of the corresponding pixel region PA, as Figure 9 and Figure 10As shown. The second gate insulating layer 122 may be disposed between the first sub-gate G1 and the second semiconductor pattern 221 in each pixel region PA and between the second sub-gate G2 and the second semiconductor pattern 221 in each pixel region PA. For example, the first sub-gate G1 may be disposed between a part of the second sub-gate G2 and the second gate insulating layer 122. The first gate electrode 213 of each pixel region PA may be insulated from the first semiconductor pattern 211 of the corresponding pixel region PA through the third gate insulating layer 123. For example, the first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA may be covered by the third gate insulating layer 123. The first gate electrode 213 of each pixel region PA may be disposed on the third gate insulating layer 123. The third gate insulating layer 123 may include an insulating material. For example, the third gate insulating layer 123 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The third gate insulating layer 123 may be in direct contact with the second gate insulating layer 122 outside the first semiconductor pattern 211 and the second semiconductor pattern 221 in each pixel region PA. The third gate insulating layer 123 may include the same material as the second gate insulating layer 122. For example, the interface between the second gate insulating layer 122 and the third gate insulating layer 123 may not be recognized. The upper interlayer insulating layer 160 may be disposed between the third gate insulating layer 123 and the lower planarization layer 170. Accordingly, in a display device according to another embodiment of the present disclosure, regardless of the structure of the second thin film transistor T2 in each pixel region PA, a failure of the second thin film transistor T2 in each pixel region PA can be prevented, and a driving current generated by the second thin film transistor T2 of each pixel region PA can be increased. Accordingly, in a display device according to another embodiment of the present disclosure, the efficiency and reliability of the pixel driving circuit in each pixel region PA can be improved. Also, in a display device according to another embodiment of the present disclosure, lower power driving can be performed, and power consumption can be reduced.

[0116] The second light-blocking pattern 320 of each pixel region PA may be disposed between the third gate insulating layer 123 and the upper interlayer insulating layer 160. For example, the second light-blocking pattern 320 of each pixel region PA may be disposed on the same layer as the first gate electrode 213 of the corresponding pixel region PA. The second light-blocking pattern 320 of each pixel region PA may include the same material as the first gate electrode 213 of the corresponding pixel region PA. The second light-blocking pattern 320 of each pixel region PA may be formed by the same process as the first gate electrode 213 of the corresponding pixel region PA. For example, the second light-blocking pattern 320 of each pixel region PA may be formed simultaneously with the first gate electrode 213 of the corresponding pixel region PA. Accordingly, in a display device according to another embodiment of the present disclosure, characteristic deviation of the second thin film transistor T2 in each pixel region PA due to external light and light emitted from the light-emitting device 500 of the corresponding pixel region PA may be prevented. Accordingly, in a display device according to another embodiment of the present disclosure, the efficiency and reliability of the pixel driving circuit in each pixel region PA may be effectively improved.

[0117] The storage capacitor Cst of each pixel region PA may include a first capacitor electrode 251 disposed on the same layer as the second sub-gate G2, a second capacitor electrode 252 disposed on the same layer as the second light-blocking pattern 320, and a third capacitor electrode 253 disposed on the same layer as the second source electrode 227. Accordingly, in a display device according to another embodiment of the present disclosure, the area occupied by the storage capacitor Cst of each pixel region PA may be minimized without degrading process efficiency.

[0118] As a result, a display device according to an embodiment of the present disclosure may include a pixel driving circuit electrically connected to a light-emitting device, wherein the pixel driving circuit may include a driving thin film transistor and at least one switching thin film transistor, and wherein a driving gate electrode of the driving thin film transistor may have at least two work functions. Accordingly, in a display device according to an embodiment of the present disclosure, a failure of the driving thin film transistor may be prevented, and a driving current generated by the driving thin film transistor may be increased. That is, in a display device according to an embodiment of the present disclosure, the electrical characteristics of the driving thin film transistor may be improved. Accordingly, in a display device according to an embodiment of the present disclosure, the efficiency and reliability of the pixel driving circuit may be improved. Also, in a display device according to an embodiment of the present disclosure, power consumption may be reduced by driving with lower power.

Claims

1. A display device, comprising: A pixel driving circuit, wherein the pixel driving circuit comprises a thin film transistor; as well as a light emitting device, the light emitting device being electrically connected to the pixel driving circuit, The gate of the thin film transistor includes a first sub-gate and a second sub-gate electrically connected to the first sub-gate. The semiconductor pattern of the thin film transistor includes a first sub-channel and a second sub-channel arranged in parallel with each other between the drain region and the source region, and The second sub-gate overlapping the second sub-channel has a larger work function than the first sub-gate overlapping the first sub-channel.

2. The display device according to claim 1, wherein: A work function ratio of the first sub-gate to the second sub-gate is 1.2 or less. 3 . The display device according to claim 1 , wherein the second sub-channel is provided between the drain region and the first sub-channel.

4. The display device according to claim 3, wherein: The resistance of the second sub-channel is the same as the resistance of the first sub-channel.

5. The display device according to claim 3, wherein: The gate electrode includes a third sub-gate having a larger work function than the first sub-gate, The semiconductor pattern includes a third sub-channel overlapping the third sub-gate, and Wherein, the first sub-channel is arranged between the second sub-channel and the third sub-channel.

6. The display device according to claim 5, wherein: A work function of the third sub-gate is the same as a work function of the second sub-gate.

7. The display device according to claim 1, wherein: The first sub-gate and the second sub-gate include metal.

8. The display device according to claim 1, further comprising a device substrate supporting the pixel driving circuit and the light emitting device, in, The first sub-gate and the second sub-gate are disposed between the device substrate and the semiconductor pattern.

9. A display device, comprising: A first thin film transistor, located on a pixel region of the device substrate, wherein the first thin film transistor comprises a first semiconductor pattern and a first gate electrode; A second thin film transistor, located on the pixel region of the device substrate, the second thin film transistor comprising a second semiconductor pattern and a second gate electrode; as well as a light emitting device located on the pixel region of the device substrate, the light emitting device being electrically connected to the second thin film transistor, The second semiconductor pattern includes a first sub-channel and a second sub-channel arranged side by side between the drain region and the source region. The second gate electrode includes a first sub-gate overlapping the first sub-channel and a second sub-gate overlapping the second sub-channel, and The electric field applied to the first sub-channel by the first sub-gate is different from the electric field applied to the second sub-channel by the second sub-gate electrically connected to the first sub-gate.

10. The display device according to claim 9, wherein: The first semiconductor pattern and the second semiconductor pattern include an oxide semiconductor.

11. The display device according to claim 9, wherein: A distance between the second sub-channel and the second sub-gate is the same as a distance between the first sub-channel and the first sub-gate.

12. The display device according to claim 11, wherein: The second sub-gate contacts a side surface of the first sub-gate.

13. The display device according to claim 9, wherein: The second sub-gate includes a material different from that of the first sub-gate.

14. The display device according to claim 13, wherein: The first gate electrode includes the same material as the first sub-gate.

15. The display device according to claim 9, wherein: The length of the second sub-channel is different from the length of the first sub-channel.

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