Display device and controller

Abstract

Embodiments of the present disclosure relate to a display device and a controller, and more particularly, may provide a display device including: a display panel including a plurality of sub-pixels; a memory that stores image control data for controlling an image displayed on the display panel; a mode control signal generation circuit that generates a mode control signal based on a first mode signal supplied from the first controller; and a second controller configured to share the memory with the first controller and determine the control authority of the first controller to the memory through the mode control signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10 - 2023 - 0184076, filed on December 18, 2023, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] Embodiments of the present disclosure relate to a display device and a controller, and more particularly, to a display device and a controller capable of achieving smooth mode switching for using a memory between multiple controllers when the multiple controllers share one memory. Background art

[0004] The development of the intelligent society has led to an increased demand for image display devices, and various types of display devices are used, such as liquid crystal displays, organic light - emitting displays, etc.

[0005] Among these display devices, organic light - emitting display devices use self - emitting organic light - emitting diodes, and thus have advantages such as a fast response speed, better contrast, luminous efficiency, brightness, and viewing angle.

[0006] A display device may include light - emitting elements respectively disposed in a plurality of sub - pixels provided on a display panel, and control the light - emitting elements to emit light by controlling the voltage applied to the light - emitting elements, thereby displaying an image while controlling the brightness of each sub - pixel.

[0007] In recent years, the application fields of display devices have gradually expanded, including not only portable computers but also desktop computer monitors, displays for in - vehicle systems, and wall - mounted TVs.

[0008] A display device may provide various functions according to the use of an electronic device equipped with a display panel. For example, in the case of a display device for a vehicle system, a first controller provided in the vehicle system and a second controller provided in the display device may share one memory.

[0009] Therefore, when multiple controllers share one memory, a failure in the smooth mode - switching process for using the memory between multiple controllers may cause the display screen to be temporarily turned off or require resetting the power of the display. Summary of the invention

[0010] Accordingly, the inventors of the present disclosure have invented a display device and a controller capable of achieving smooth mode switching for using a memory between multiple controllers when the multiple controllers share one memory.

[0011] Embodiments of the present disclosure may provide a display device and a controller. The display device and the controller can achieve smooth mode switching for using the memory among multiple controllers by detecting a first mode period during which a first controller uses the memory and controlling a second controller to be in a high impedance state during the first mode period.

[0012] Embodiments of the present disclosure may provide a display device and a controller, which can effectively detect a first mode period during which a first controller uses the memory by using a chip select signal and a memory enable signal generated for the first controller to use the memory.

[0013] Embodiments of the present disclosure provide a display device, including: a display panel including a plurality of sub-pixels; a memory storing image control data for controlling an image displayed on the display panel; a mode control signal generation circuit generating a mode control signal based on a first mode signal provided from a first controller; and a second controller configured to share the memory with the first controller and determine a control authority of the first controller over the memory through the mode control signal.

[0014] Embodiments of the present disclosure may provide a timing controller, including: a first edge detection circuit generating a mode enable edge signal by detecting an edge at which a mode enable signal provided from a host controller is turned on; a second edge detection circuit generating a chip select edge signal by detecting an edge at which a chip select signal provided from the host controller is turned off; a first logic gate generating a mode control signal for determining a control authority of the host controller over the memory by using the mode enable edge signal and the chip select edge signal; and a second logic gate generating a reset signal for a reset operation of the first edge detection circuit and the second edge detection circuit by using the mode enable edge signal and the chip select edge signal, wherein the timing controller shares the memory with the host controller.

[0015] Effects of the present disclosure

[0016] According to embodiments of the present disclosure, when multiple controllers share a memory, smooth mode switching for using the memory among multiple controllers can be achieved.

[0017] According to embodiments of the present disclosure, by detecting a first mode period during which a first controller uses the memory and controlling a second controller to be in a high impedance state during the first mode period, unnecessary driving loss can be reduced, and low-power driving capable of saving power can be achieved.

[0018] According to an embodiment of the present disclosure, a chip select signal and a memory enable signal generated for a first controller to use a memory can be used to effectively detect a first mode period during which the first controller uses the memory. Description of the Drawings

[0019] The above and other objects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a partial view showing an example inside a vehicle system according to an embodiment of the present disclosure;

[0021] Figure 2 is a view schematically showing a display device according to an embodiment of the present disclosure;

[0022] Figure 3 is a view showing an example of a system formed by a display device according to an embodiment of the present disclosure;

[0023] Figure 4 is a view showing an example of the structure of a memory in a display device according to an embodiment of the present disclosure;

[0024] Figure 5 is a block diagram showing a display system according to an embodiment of the present disclosure;

[0025] Figure 6 is a block diagram showing a mode control signal generation circuit in a display device according to an embodiment of the present disclosure;

[0026] Figure 7 is a view showing the waveform of each node signal of a mode control signal generation circuit in a display device according to an embodiment of the present disclosure; and

[0027] Figure 8 is a view showing the structure of controlling a main buffer and a slave buffer according to a mode control signal in a display device according to an embodiment of the present disclosure. Detailed Description of the Embodiment

[0028] In the following, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In the following description of the examples or embodiments of the present disclosure, reference will be made to the drawings, in which specific examples or embodiments that can be implemented are shown in an illustrative manner, and the same reference numerals and symbols may be used to represent the same or similar components, even if they are shown in different drawings from each other. In addition, in the following description of the examples or embodiments of the present disclosure, when it is determined that the description may make the subject matter in some embodiments of the present disclosure less clear, the detailed description of well-known functions and components incorporated herein will be omitted. Terms such as "including", "having", "containing", "constituting", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0029] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the essence, order, sequence, quantity, etc. of the element, but only to distinguish the corresponding element from other elements.

[0030] When it is mentioned that a first element is "connected or coupled to", "in contact with or overlapping" (etc.) a second element, it should be understood that: the first element can not only be "directly connected or coupled to" or "directly in contact with or overlapping" the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or coupled to" each other, "in contact with or overlapping" each other (etc.) through a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled to" each other, "in contact with or overlapping" each other (etc.).

[0031] When using time relative terms, such as "after", "subsequently", "next", "before", etc. to describe the process or operation of an element or configuration, or the flow or steps in an operation, process, manufacturing method, these terms can be used to describe a non - continuous or non - sequential process or operation, unless used together with the terms "directly" or "immediately".

[0032] In addition, when referring to any size, relative size, etc., it should be considered that even if the relevant description is not specified, the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature also includes the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can".

[0033] Various embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0034] Figure 1 It is a partial view showing an example inside a vehicle system according to an embodiment of the present disclosure.

[0035] Referring Figure 1 , the vehicle system 1000 according to an embodiment of the present disclosure may include a driver's seat and a passenger seat, a dashboard positioned in front of the driver's seat and the passenger seat and on which various instruments required for driving are arranged, and a center fascia having a control panel with electronic devices.

[0036] The dashboard may include a first display panel 111 that displays information required for driving, including a speedometer. The first display panel 111 may be referred to as the dashboard display panel.

[0037] The first display panel 111 is a display panel capable of safely driving the vehicle system 1000 by transmitting information about the driving state of the vehicle system 1000 and the operation of various electronic devices set in the vehicle system 1000 to the driver. A speedometer indicating the driving speed, an odometer indicating the driving distance, a tachometer indicating the revolutions per minute (RPM) of the engine, a fuel gauge, a water temperature gauge, an engine thermometer, and various warning lights can be displayed through the first display panel 111. The first display panel 111 may be positioned behind the steering wheel relative to the driver's seat.

[0038] The center fascia is positioned between the driver's seat and the passenger seat and may correspond to the area where the dashboard and the gear shifter intersect vertically. In this area, an audio, an air conditioner, a heater controller, a navigator, a blower, a cigar lighter socket, an ashtray, a cup holder, etc. may be provided. In addition, the center fascia may include a second display panel 112.

[0039] The second display panel 112 may guide the route to the destination or display a map image corresponding to the current location, and display a user interface related to controlling various electronic devices installed in the vehicle system 1000. In addition, when the vehicle system 1000 is connected to a mobile terminal, the screen provided by the mobile terminal may be displayed.

[0040] The second display panel 112 positioned between the driver's seat and the passenger seat of the vehicle system 1000 may be referred to as the center fascia display panel.

[0041] In addition, for the convenience of the passenger on the passenger seat, a third display panel 113 may be additionally installed in front of the passenger seat. The third display panel 113 positioned in front of the passenger seat may be referred to as the passenger seat display panel.

[0042] Furthermore, in addition to the instrument panel display panel 111, the central instrument panel display panel 112, and the passenger seat display panel 113, the display panel 110 included in the vehicle system 1000 may further include at least one of a front window display panel, a side mirror display panel, a rearview mirror display panel, and a side window display panel. In addition, various types of display panels can be installed.

[0043] The front window display panel may be a display panel that projects a virtual image onto a partial area of the front window through which the front of the vehicle system 1000 can be observed. By displaying the speed of the vehicle system, the remaining fuel amount, route direction information, etc. on the front window display panel, unnecessary gaze changes of the driver in different directions can be minimized.

[0044] The side mirror display panel may be a display panel that can display a side image captured by a side camera in a partial area or the entire area of the side mirror formed to observe the side of the vehicle system 1000. Therefore, the driver can identify not only the side image reflected by the side mirror but also the side image captured by the side camera through the side mirror display panel.

[0045] The rearview mirror display panel may be a display panel that can display a rear image captured by a rear camera in a partial area or the entire area of the rearview mirror formed to observe the rear of the vehicle system 1000. Therefore, the driver can identify not only the rear image reflected by the rearview mirror but also the rear image captured by the rear camera through the rearview mirror display panel.

[0046] The side window display panel may be a display panel that projects a virtual image onto a partial area of the side window through which the side of the vehicle system 1000 can be observed. Various information about the vehicle system 1000 can be displayed through the side window display panel.

[0047] Figure 2 is a view schematically showing a display device according to an embodiment of the present disclosure.

[0048] Referring to Figure 2 , the display device 100 according to an embodiment of the present disclosure may include a display panel 110, a gate driving circuit 120, a data driving circuit 130, a timing controller 140, and a level shifter 190.

[0049] In the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may cross each other, and sub-pixels SP may be arranged in a matrix form in each crossing area, thereby forming a sub-pixel array.

[0050] In the case of a liquid crystal display device, the display panel 110 may include a liquid crystal layer formed between two substrates and may operate in any known mode, such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, or an edge field switching (FFS) mode. In the case of an organic light-emitting display device, the display panel 110 may be implemented using a top emission scheme, a bottom emission scheme, or a dual emission scheme.

[0051] A sub-pixel SP may include, for example, a thin film transistor (TFT) disposed in an area formed by a data line DL and a gate line GL, a light-emitting element that emits light according to a data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the data voltage. The thin film transistor may include a driving transistor and one or more switching transistors and may be implemented as a P-type transistor or an N-type transistor. Alternatively, it may be implemented in a hybrid form of a P-type transistor and an N-type transistor.

[0052] For example, when the display device 100 with a resolution of 2,160X 3,840 includes four sub-pixels SP of white (W), red (R), green (G), and blue (B), the data line DL may be connected to 2,160 gate lines GL and the four sub-pixels WRGB, and thus, 3,840X 4 = 15,360 data lines DL may be provided. Each sub-pixel SP is disposed in an area formed by the gate line GL and the data line DL.

[0053] The timing controller 140 may receive an interface signal IF from the host controller 200 through a specified interface scheme and convert it into image data DATA for internal use.

[0054] In the case of the display device 100 for the vehicle system 1000, the host controller 200 and the display device 100 may use a low-voltage differential signal (LVDS) interface or a serial peripheral interface (SPI).

[0055] In the low-voltage differential signal (LVDS) interface, the interface signal IF transmitted from the host controller 200 to the display device 100 may be a low-voltage differential data signal.

[0056] The low-voltage differential signal (LVDS) interface is a standard interface defined in ANSI / TIA / EIA-644 and can be used as an interface in fields that require high-speed data transmission, low power consumption, and noise immunity. When using the low-voltage differential signal (LVDS) interface, since the interface signal IF is transmitted as a differential input signal with a swing width of approximately 350 mV, high noise immunity and high-speed data transmission can be achieved.

[0057] The Serial Peripheral Interface (SPI) is a synchronous communication solution that supports one-to-many (1:N) interface communication, has a high speed, and can be used for communication between chips such as memories. For example, in the case of the vehicle system 1000, the host controller 200 provided in the vehicle system 1000 can be used as a master device to operate, while the timing controller 140 provided in the display device 100 can be used as a slave device to operate.

[0058] The Serial Peripheral Interface SPI may include a synchronous clock signal transmitted from the host controller 200 or the timing controller 140, a Master Out Slave In (MOSI) signal output from the host and input to the slave, a Master In Slave Out (MISO) signal output from the slave and input to the host, and a chip select signal. The MOSI signal may include a memory enable signal for starting the use of the memory.

[0059] The timing controller 140 may correct the image data DATA based on the sensing result of the characteristic value of the sub-pixel (e.g., the threshold voltage or mobility of the driving transistor) to compensate for the driving deviation of the sub-pixel SP, and then transmit it to the data driving circuit 130.

[0060] The timing controller 140 may receive a timing signal (e.g., a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal) and an interface signal IF from the host controller 200. The timing controller 140 generates a source control signal SCS for controlling the operation timing of the data driving circuit 130 and a timing control signal TCS for controlling the operation timing of the gate driving circuit 120 based on the timing signal input from the host controller 200.

[0061] The source control signal SCS includes a source sampling clock signal, a source output enable signal, etc. The source sampling clock signal is a clock signal that controls the sampling timing of the image data DATA in the data driving circuit 130 based on the rising edge or falling edge of the source sampling clock signal. The source output enable signal is a signal for controlling the output timing of the analog data voltage applied to the display panel 110.

[0062] The data driving circuit 130 may include a plurality of source driver integrated chips SDIC. The data driving circuit 130 receives the image data DATA from the timing controller 140. In response to the source control signal SCS transmitted from the timing controller 140, the data driving circuit 130 converts the image data DATA into a gamma voltage, thereby generating a data voltage, synchronizes the data voltage with the scan signal of the gate driving circuit 120, and provides it to the data line DL of the display panel 110.

[0063] The data driving circuit 130 may be connected to the data lines DL of the display panel 110 through a chip - on - glass (COG) process or a tape - automated bonding (TAB) process.

[0064] The display device 100 may include a level shifter 190 that generates a gate control signal GCS using a timing control signal TCS output from the timing controller 140 and provides the generated gate control signal GCS to the gate driving circuit 120. The level shifter 190 may be positioned inside the gate driving circuit 120 or may be positioned on the source printed circuit board where the data driving circuit 130 is provided.

[0065] The level shifter 190 may convert the transistor - transistor - logic (TTL) level voltage of the timing control signal (TCS) input from the timing controller 140 into a conduction level voltage and a cutoff level voltage capable of switching the transistors formed on the display panel 110. Then, the level shifter 190 provides the gate control signal GCS to the gate driving circuit 120.

[0066] The timing control signal TCS may include a conduction clock signal, a cutoff clock signal, an AC control pulse signal, etc.

[0067] The gate control signal GCS may include a gate start signal, a gate clock signal, an even AC voltage, an odd AC voltage, a line selection signal, a reset signal, and a panel on signal. The gate clock signal may be composed of N (where N is a natural number) phase clock signals having different phases. When the gate driving circuit 120 includes a scan driving circuit and an emission driving circuit, the gate start signal may include a scan start signal and a light emission start signal, and the gate clock signal may include a scan clock signal and a light emission clock signal.

[0068] For example, in the display device 100 with a resolution of 2,160X3,840, for 2,160 gate lines GL, when the gate signals are sequentially output from the first gate line to the 2,160th gate line, it may not be called 2,160 - phase driving. Or, when the gate signals are sequentially output based on every four gate lines GL, for example, when the gate signals are sequentially output from the first gate line to the fourth gate line and then the gate signals are sequentially output from the fifth gate line to the eighth gate line, it is called four - phase driving. In other words, when the gate signals are sequentially output at intervals of N gate lines GL, it may be called N - phase driving.

[0069] When the gate driving circuit 120 includes a scan driving circuit and an emission driving circuit, the gate signals may include scan signals and light emission signals.

[0070] In addition, the gate driving circuit 120 may include one or more gate driving integrated circuits GDIC.

[0071] Based on the gate control signal GCS input from the level shifter 190 and one or more power supply voltages GVDD and GVSS input from a display power management circuit (not shown), the gate driver circuit 120 can output a display gate signal during a display driving period and output a sensing gate signal for sensing characteristic values of the sub-pixels SP during a blank period.

[0072] The gate driver circuit 120 can be directly formed on the substrate of the display panel 110 in a gate-in-panel (GIP) manner.

[0073] The gate driver circuit 120 can be formed in a border area of the display panel 110 where no image is displayed, but is not limited thereto. The gate driver circuit 120 can be formed in a double dam structure, where a first gate driver circuit 120a is disposed within a first border area of the display panel 110 and a second gate driver circuit 120b is disposed within a second border area of the display panel 110 so as to minimize distortion of the gate signal due to signal delay.

[0074] The timing controller 140 can control the display driving operation and the sensing driving operation of the sub-pixel lines of the display panel 110 based on a source control signal SCS and a timing control signal TCS, so as to sense the characteristic values of the sub-pixels SP in real time even during a period of displaying an image.

[0075] Here, the sub-pixel line refers to a set of a row number of sub-pixels SP adjacent to each other in a horizontal direction.

[0076] The sensing driving operation refers to an operation of sensing the characteristic values of corresponding sub-pixels SP by applying sensing data to the sub-pixels SP disposed in a specific sub-pixel line and updating a compensation value based on the sensing result so as to compensate for changes in the characteristic values of the corresponding sub-pixels SP.

[0077] The display device 100 can include a display power management circuit that provides various voltages or currents to the display panel 110, the gate driver circuit 120, the data driver circuit 130, etc., or controls various voltages or currents to be provided.

[0078] The display power management circuit generates power required to drive the display panel 110, the gate driver circuit 120, and the data driver circuit 130 by adjusting a direct current (DC) voltage provided from an external host system.

[0079] The display device 100 can be one of various types of devices, such as a liquid crystal display, an organic light emitting diode display, or a plasma display panel.

[0080] Figure 3It is a view showing an example of a system formed by a display device according to an embodiment of the present disclosure.

[0081] Referring Figure 3 , in a display device 100 according to an embodiment of the present disclosure, a source driver integrated circuit SDIC included in a data driver circuit 130 is implemented in a chip - on - film (COF) type among various types (e.g., TAB, COG, or COF), and a gate driver circuit 120 is implemented in an in - panel gate (GIP) type among various types (e.g., TAB, COG, COF, or GIP).

[0082] When the gate driver circuit 120 is implemented in the GIP type, a plurality of gate driver integrated circuits GDIC included in the gate driver circuit 120 can be directly formed in a non - display area of the display panel 110. In this case, the gate driver integrated circuit GDIC can receive various signals (e.g., a clock signal, a gate high signal, a gate low signal, etc.) required to generate a scan signal through gate - driving related signal lines provided in the non - display area.

[0083] Similarly, one or more source driver integrated circuits SDIC included in the data driver circuit 130 can be respectively mounted on a source film SF, and one side of the source film SF can be electrically connected to the display panel 110. Lines for electrically connecting the source driver integrated circuit SDIC and the display panel 110 can be provided on the source film SF.

[0084] The display device 100 may include at least one source printed circuit board SPCB for circuit connection between a plurality of source driver integrated circuits SDIC and other devices, and a control printed circuit board CPCB for mounting control components and various electrical devices.

[0085] The other side of the source film SF on which the source driver integrated circuit SDIC is mounted can be connected to at least one source printed circuit board SPCB. In other ways, one side of the source film SF on which the source driver integrated circuit SDIC is mounted can be electrically connected to the display panel 110, and the other side of the source film SF can be electrically connected to the source printed circuit board SPCB.

[0086] A timing controller 140 and a display power management circuit 180 can be mounted on the control printed circuit board CPCB. The timing controller 140 can control the operations of the data driver circuit 130 and the gate driver circuit 120. The display power management circuit 180 can supply a driving voltage or current to the display panel 110, the data driver circuit 130, and the gate driver circuit 120, and control the supplied voltage or current.

[0087] At least one source printed circuit board SPCB and a control printed circuit board CPCB may be circuit-connected through at least one connection member. The connection member may include, for example, a flexible printed circuit FPC or a flexible flat cable FFC. At least one source printed circuit board SPCB and a control printed circuit board CPCB may be integrated into a single printed circuit board.

[0088] The display device 100 may further include a setting board 170 electrically connected to the control printed circuit board CPCB. In this case, the setting board 170 may also be referred to as a power board. A main power management circuit 160 for managing the total power of the display device 100 may be present on the setting board 170. The main power management circuit 160 may interact with the display power management circuit 180.

[0089] In the display device 100 configured as such, a driving voltage is generated in the setting board 170 and is transmitted to the display power management circuit 180 in the control printed circuit board CPCB. The display power management circuit 180 transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board SPCB through a flexible printed circuit FPC or a flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is provided to specific sub-pixels SP in the display panel 110 through a source driver integrated circuit SDIC so as to emit light or sense specific sub-pixels SP in the display panel 100.

[0090] Each sub-pixel SP arranged in the display panel 110 disposed in the display device 100 may include a light-emitting element and circuit elements, such as a driving transistor, for allowing the light-emitting element to emit light.

[0091] The type and number of circuit elements constituting each sub-pixel SP may vary according to the functions to be provided and the design scheme.

[0092] Furthermore, the display device 100 according to the present disclosure may include a memory 150 for storing image data transmitted from a host controller 200 or data calculated by a timing controller 140.

[0093] The memory 150 may include a non-volatile memory, such as a flash memory, a resistive random access memory (RRAM), etc.

[0094] When the memory 150 includes a non-volatile memory (such as a flash memory), a basic unit capable of accessing data stored in the memory 150 may be defined as a sector, and the sector may be determined according to the configuration of the memory 150.

[0095] In this case, the size of a sector corresponding to the basic unit of the flash memory may be 1KB, 2KB, or 4KB, and two or more consecutive sectors may be configured as a block.

[0096] Figure 4 It is a view showing an example of the structure of a memory in a display device according to an embodiment of the present disclosure.

[0097] Referring to Figure 4 , in the memory 150 of the display device 100 according to an embodiment of the present disclosure, there is a core region where a plurality of memory cells are aggregated and an auxiliary region corresponding to the remaining region of the memory 150 other than the core region and supporting the operation of the memory cells arranged in an array.

[0098] The core region may include a page (PG) and a string (STR). In the core region, a plurality of wordlines (WL1 to WL9) and a plurality of bitlines (BL) are arranged to cross each other.

[0099] The plurality of wordlines WL1 to WL9 may be connected to the row decoder 151, and the plurality of bitlines BL may be connected to the column decoder 152. A data register 153 corresponding to the read / write circuit may exist between the plurality of bitlines BL and the column decoder 152.

[0100] The plurality of wordlines WL1 to WL9 correspond to a plurality of pages PG. For example, each of the plurality of wordlines WL1 to WL9 may correspond to one page PG. Alternatively, when each of the plurality of wordlines WL1 to WL9 has a large size, each of the plurality of wordlines WL1 to WL9 may correspond to two or more (e.g., two or four) pages PG. The page PG may be the smallest unit for performing a write operation and a read operation, and during the write operation and the read operation, all the memory cells in the same page PG may perform operations simultaneously.

[0101] The plurality of bitlines BL may be connected to the column decoder 152 while being divided into odd bitlines ODD and even bitlines EVEN.

[0102] To access a memory cell, an address may enter the core region through the row decoder 151 and the column decoder 152 to specify a target memory cell. The specification of the target memory cell means accessing the memory cell located at the intersection of the wordlines WL1 to WL9 connected to the row decoder 151 and the bitlines BL connected to the column decoder 152 to record data, or reading the recorded data.

[0103] Since the data processing of the memory 150 is recorded and read through the data register 153, the data register 153 plays a key role. If the data processing of the data register 153 is delayed, all other areas must wait for the data register 153 to complete the data processing. In addition, if the performance of the data register 153 deteriorates, the overall performance of the memory 150 will decline.

[0104] A plurality of transistors TR1 to TR9 connected to a plurality of word lines WL1 to WL9 may exist in a single string STR. A plurality of regions in which the plurality of transistors TR1 to TR9 are present correspond to a plurality of memory cells.

[0105] The plurality of word lines WL1 to WL9 include two outermost word lines WL1 and WL9. Among the two outermost word lines WL1 and WL9, a first select line DSL may be further provided outside the first outermost word line WL1 that is closer to the data register 153 on the signal path, and a second select line SSL may be further provided outside the other second outermost word line WL9.

[0106] A first select transistor D-TR controlled to be turned on and off by the first select line DSL is a transistor that only has a gate electrode connected to the first select line DSL but does not include a floating gate. A second select transistor S-TR controlled to be turned on and off by the second select line SSL is a transistor that only has a gate electrode connected to the second select line SSL but does not include a floating gate.

[0107] The first select transistor D-TR serves as a switch for turning on or off the connection between the corresponding string STR and the data register 153. The second select transistor S-TR serves as a switch for turning on or off the connection between the corresponding string STR and the source line SL. In other words, the first select transistor D-TR and the second select transistor S-TR are positioned at two opposite ends of the corresponding string STR and serve as gatekeepers for connecting and disconnecting signals.

[0108] Since the memory 150 needs to fill the target memory cell to be recorded on the bit line BL with electrons during the data recording operation, the first select transistor D-TR is turned on by applying a predetermined on voltage to the gate electrode of the first select transistor D-TR, and the second select transistor S-TR is turned off by applying a predetermined off voltage (e.g., 0V) to the gate electrode of the second select transistor S-TR.

[0109] During a read operation or a verify operation, the memory 150 turns on the first select transistor D-TR and the second select transistor S-TR simultaneously. As a result, current can pass through the corresponding string STR and fall into the source line SL corresponding to the ground, so that the voltage level of the bit line BL can be measured. However, during a read operation, there may be a time difference between the on and off timings of the first select transistor D-TR and the second select transistor S-TR.

[0110] In an erase operation, the memory 150 can supply a predetermined voltage (e.g., +20V) to the substrate through the source line SL. During the erase operation, the memory 150 floats both the first select transistor D-TR and the second select transistor S-TR to generate an infinite resistance. Therefore, it is configured such that the first select transistor D-TR and the second select transistor S-TR are inoperative, and electrons can be operated only due to the potential difference between the floating gate and the substrate.

[0111] Meanwhile, an electrically erasable PROM (EEPROM) has the advantage of being able to read or record data in bytes when installed on a printed circuit board. However, when data is recorded in the EEPROM, each byte requires a time delay of several milliseconds or longer, so it is not suitable for high-speed storage of a large amount of data.

[0112] In particular, as the resolution of the display device 100 increases, when high-speed processing of a large amount of data is required, the demand for flash memory increases.

[0113] Meanwhile, in the case of the vehicle system 1000, the host controller 200 provided in the vehicle system and the timing controller 140 provided in the display device 100 can share a memory 150.

[0114] As described above, when multiple controllers 200 and 140 share a memory 150, if the mode switching of using the memory 150 cannot be smoothly performed between the multiple controllers 200 and 140, the display screen will be temporarily interrupted or the display power needs to be reset.

[0115] The display device 100 according to the present disclosure allows for smooth execution of mode switching of using the memory 150 between multiple controllers 200 and 140 when the multiple controllers 200 and 140 share a memory 150. Therefore, even when mode switching is performed without interrupting the display screen or resetting the display power, a stable display operation can be executed.

[0116] Figure 5 It is a block diagram showing a display system according to an embodiment of the present disclosure.

[0117] Refer to Figure 5, a display system according to an embodiment of the present disclosure may include a display device 100 connected to a host controller 200.

[0118] The display device 100 may include a timing controller 140, and the timing controller 140 includes a slave buffer 146, a memory 150, a display panel 110 (not shown in Figure 5 etc.).

[0119] The host controller 200 may include a main buffer 206. The host controller 200 may use an external control signal ECS transmitted through the main buffer 206 to control the memory 150 of the display device 100.

[0120] The timing controller 140 may access the memory 150 using an internal control signal ICS transmitted through the slave buffer 146.

[0121] The memory 150 may store image control data, such as gamma data in the form of a look-up table for controlling the brightness of an image displayed on the display panel 110.

[0122] The display device 100 may operate in a first mode under the control of the host controller 200 to display an image, and operate in a second mode under the control of the timing controller 140 to display an image.

[0123] When the display device 100 operates in the first mode, the memory 150 may be controlled by an external control signal ECS provided from the main buffer 206 under the control of the host controller 200. When the display device 100 operates in the second mode, the memory 150 may be controlled by an internal control signal ICS provided from the slave buffer 146 under the control of the timing controller 140.

[0124] The main buffer 206 and the slave buffer 146 may be switched to an on state or a high-impedance state according to a mode control signal MCS generated in the display device 100 (e.g., in the timing controller 140).

[0125] The main buffer 206 and the slave buffer 146 may be tri-state buffers, which transmit or block the external control signal ECS or the internal control signal ICS through the mode control signal MCS.

[0126] The main buffer 206 may be located inside the host controller 200, and the slave buffer 146 may be located inside the timing controller 140. Alternatively, the slave buffer 146 may be a separate component and be located on a control printed circuit board (CPCB) outside the timing controller 140.

[0127] The host controller 200 can use the mode enable signal ME and the chip select signal CS to transmit whether the first mode is operating to the timing controller 140. The mode enable signal ME and the chip select signal CS can be referred to as the first mode signals. The mode enable signal ME is the first mode entry signal for the host controller 200 to control the memory 150, and the chip select signal CS corresponds to the selection signal for the host controller 200 to select a chip in the memory 150 in the first mode to access specific data stored in the chip.

[0128] When the host controller 200 enters the first mode to control the display operation, the host controller 200 can transmit the operation of entering the first mode by applying the mode enable signal ME at the on level, and use the chip select signal CS to select the chip to be controlled inside the memory 150.

[0129] When entering the first mode, the mode enable signal ME can be first changed to the on level, and then the chip select signal CS can be changed to the on level. On the other hand, when entering the second mode, the chip select signal CS can be first changed to the off level, and then the mode enable signal ME can be changed to the off level.

[0130] When both the mode enable signal ME and the chip select signal CS are at the on level, the timing controller 140 determines that the first mode has been entered, and maintains the buffer 146 in the high impedance state and the main buffer 206 in the on state through the mode control signal MCS.

[0131] Therefore, when the timing controller 140 switches from the second mode of displaying an image to the first mode where the host controller 200 controls the display operation, the display device 100 according to the present disclosure can allow the control authority of the memory 150 to be smoothly changed. As a result, power consumption can be reduced by reducing unnecessary driving losses for mode switching, and continuous display operations can be performed without interrupting the display screen or resetting the display power during the mode switching process.

[0132] Figure 6 is a block diagram showing a mode control signal generation circuit in a display device according to an embodiment of the present disclosure. Figure 7 is a view showing the waveform of each node signal of the mode control signal generation circuit in a display device according to an embodiment of the present disclosure.

[0133] Referring to Figure 6 and Figure 7 , in the display device 100 according to an embodiment of the present disclosure, the mode control signal generation circuit can be located inside the timing controller 140 or can be provided on the control printed circuit board CPCB. An example where the mode control signal generation circuit is located inside the timing controller 140 is shown here.

[0134] The timing controller 140 may include a first edge detection circuit 141, a second edge detection circuit 142, a first logic gate 143, a second logic gate 144, a reset buffer 145, and a slave buffer 146, as Figure 6 shown. The first edge detection circuit 141, the second edge detection circuit 142, the first logic gate 143, and the second logic gate 144 (optionally, the reset buffer 145) constitute a mode control signal generation circuit.

[0135] The first edge detection circuit 141 may detect the edge at which the mode enable signal ME transmitted from the host controller 200 is turned on. The first edge detection circuit 141 may be a flip-flop that operates according to the input signal VIN and receives the mode enable signal ME through a clock terminal.

[0136] When the turn-on level of the mode enable signal ME is high, the first edge detection circuit 141 may detect the edge at which the mode enable signal ME is switched from a low level to a high level, so as to generate a high-level mode enable edge signal ME_R. In other words, the high-level mode enable edge signal ME_R may indicate that the mode enable signal ME is at the turn-on level.

[0137] In this case, due to the clock timing of the first edge detection circuit 141, a time delay may occur between the mode enable signal ME and the mode enable edge signal ME_R.

[0138] The second edge detection circuit 142 may detect the edge at which the chip select signal CS transmitted from the host controller 200 is turned off. The second edge detection circuit 142 may be a flip-flop that operates according to the input signal VIN and receives the chip select signal CS through a clock terminal.

[0139] When the turn-on level of the chip select signal CS is low, the second edge detection circuit 142 may generate a chip select edge signal CS_R by detecting the edge at which the chip select signal CS is switched from a low level to a high level. In other words, the high-level chip select edge signal CS_R may indicate that the chip select signal CS is at the turn-off level.

[0140] In this case, due to the clock timing of the second edge detection circuit 142, a time delay may occur between the chip select signal CS and the chip select edge signal CS_R.

[0141] The first logic gate 143 generates a mode control signal MCS using the mode enable edge signal ME_R and the chip select edge signal CS_R.

[0142] For example, the mode control signal MCS may be output at a high level during a first mode period MODE1 controlled by the host controller 200, and may be output at a low level during a second mode period MODE2 controlled by the timing controller 140. In other words, the mode control signal MCS may represent the first mode period MODE1 from the time point when the mode enable signal ME is turned on to the time point when the chip select signal CS is turned off as a high level.

[0143] To this end, the first logic gate 143 may include an exclusive OR (XOR) gate that can detect a situation where the mode enable edge signal ME_R is at a high level while the chip select edge signal CS_R is at a low level. When the chip select edge signal CS_R is at a high level (the chip select signal CS is at an off level), the first edge detection circuit 141 and the second edge detection circuit 142 are reset by the reset signal RESET generated by the second logic gate 144. Therefore, a situation where the mode enable edge signal ME_R is at a low level while the chip select edge signal CS_R is at a high level does not occur.

[0144] The first mode period MODE1 may terminate when the chip select signal CS is switched from an on level (low level) to an off level (high level).

[0145] To this end, the second logic gate 144 may generate a reset signal RESET capable of resetting the first edge detection circuit 141 and the second edge detection circuit 142 by detecting the time when the chip select signal CS becomes an off level (high level) while the mode enable signal ME is at an on level (high level).

[0146] In other words, the second logic gate 144 outputs the reset signal RESET at the time when the chip select edge signal CS_R becomes a high level while the mode enable edge signal ME_R is at a high level. The reset signal RESET may be applied to the reset terminals of the first edge detection circuit 141 and the second edge detection circuit 142 through a reset buffer 145. The reset buffer 145 delays the reset signal by a predetermined time.

[0147] To this end, the second logic gate 144 may include an AND gate that detects a situation where the mode enable edge signal ME_R is at a high level and the chip select edge signal CS_R is at a high level.

[0148] In this case, the reset buffer 145 may be omitted.

[0149] The period during which the mode control signal MCS is output at a low level may correspond to the second mode period MODE2 in which the display operation is controlled by the timing controller 140.

[0150] Therefore, the slave buffer 146 provided in the timing controller 140 can be enabled by a low-level mode control signal MCS to transmit an internal control signal ICS, and can be put into a high-impedance state by a high-level mode control signal MCS to interrupt the internal control signal ICS.

[0151] On the other hand, the master buffer 206 provided in the host controller 200 can be enabled by a high-level mode control signal MCS to transmit an external control signal ECS, and can be put into a high-impedance state by a low-level mode control signal MCS to interrupt the external control signal ECS.

[0152] Figure 8 FIG. is a view showing a structure for controlling a master buffer and a slave buffer according to a mode control signal in a display device according to an embodiment of the present disclosure.

[0153] Refer to Figure 8 , in a display device 100 according to an embodiment of the present disclosure, the host controller 200 and the timing controller 140 can share a memory 150.

[0154] The host controller 200 can access the memory 150 by transmitting an external control signal ECS through the master buffer 206. The external control signal ECS can include an external clock signal ECLK and n external control signals ECS1 to ECSn.

[0155] The timing controller 140 can access the memory 150 by transmitting an internal control signal ICS through the slave buffer 146. The internal control signal ICS can include an internal clock signal ICLK and n internal control signals ICS1 to ICSn.

[0156] In this case, the host controller 200 can transmit whether to enter the first mode to the timing controller 140 using a mode enable signal ME and a chip select signal CS.

[0157] During a first mode period MODE1 when both the mode enable signal ME and the chip select signal CS are at an active level, the timing controller 140 maintains the slave buffer 146 in a high-impedance state and the master buffer 206 in an enabled state through a mode control signal MCS, thereby allowing the host controller 200 to control the memory 150.

[0158] On the other hand, the timing controller 140 can control the memory 150 by maintaining the slave buffer 146 in an enabled state and the master buffer 206 in a high-impedance state through a mode control signal MCS during a second mode period MODE2 when both the mode enable signal ME and the chip select signal CS are at an inactive level.

[0159] Thus, when the display device 100 according to the present disclosure switches from the second mode in which the timing controller 140 controls the display operation to the first mode in which the host controller 200 controls the display operation, the control authority over the memory 150 can be smoothly changed, thereby preventing defects in the display screen of the display and enabling a stable display operation.

[0160] The embodiments of the present disclosure described above will be briefly described below.

[0161] A display device according to the present disclosure may include: a display panel including a plurality of sub-pixels; a memory storing image control data for controlling an image displayed on the display panel; a mode control signal generation circuit generating a mode control signal based on a first mode signal provided from a first controller; and a second controller configured to share the memory with the first controller and determine the control authority of the first controller over the memory through the mode control signal.

[0162] The image control data may be gamma data for controlling the brightness of an image displayed on the display panel.

[0163] The first controller may be a host controller, and the second controller may be a timing controller.

[0164] The first controller may include a main buffer for transmitting an external control signal to the memory, and the display device may further include a slave buffer for transmitting an internal control signal to the memory and located inside the second controller or on a control printed circuit board located outside the second controller. The main buffer and the slave buffer may be controlled by the mode control signal.

[0165] During the first mode period in which the first controller controls the memory, the mode control signal may keep the main buffer in an on state and keep the slave buffer in a high impedance state.

[0166] During the second mode period in which the second controller controls the memory, the mode control signal may keep the main buffer in a high impedance state and keep the slave buffer in an on state.

[0167] The first mode signal may include a mode enable signal indicating entry into the first mode in which the first controller controls the memory, and a chip select signal for selecting a chip in the memory for the first controller in the first mode.

[0168] The mode control signal generation circuit may include: a first edge detection circuit that generates a mode enable edge signal by detecting the edge at which the mode enable signal is turned on; a second edge detection circuit that generates a chip select edge signal by detecting the edge at which the chip select signal is turned off; a first logic gate that uses the mode enable edge signal and the chip select edge signal to generate a mode control signal; and a second logic gate that uses the mode enable edge signal and the chip select edge signal to generate a reset signal for the reset operation of the first edge detection circuit and the second edge detection circuit.

[0169] The first edge detection circuit may be a flip-flop that receives the mode enable signal through a clock terminal.

[0170] The second edge detection circuit may be a flip-flop that receives the chip select signal through a clock terminal.

[0171] The first logic gate may be an exclusive OR gate.

[0172] The second logic gate may be an AND gate.

[0173] The mode control signal generation circuit may further include a reset buffer that delays the reset signal by a predetermined time.

[0174] The mode control signal generation circuit may be located in the second controller.

[0175] The mode control signal generation circuit may be located on a control printed circuit board.

[0176] When entering the first mode, the mode enable signal may first be changed to the on level, and then the chip select signal may be changed to the on level.

[0177] When entering the second mode in which the second controller controls the memory, the chip select signal may first be changed to the off level, and then the mode enable signal may be changed to the off level.

[0178] A timing controller according to the present disclosure may include: a first edge detection circuit that generates a mode enable edge signal by detecting the edge at which a mode enable signal provided from a host controller is turned on; a second edge detection circuit that generates a chip select edge signal by detecting the edge at which a chip select signal provided from the host controller is turned off; a first logic gate that uses the mode enable edge signal and the chip select edge signal to generate a mode control signal for determining the control authority of the host controller over the memory; and a second logic gate that uses the mode enable edge signal and the chip select edge signal to generate a reset signal for the reset operation of the first edge detection circuit and the second edge detection circuit, wherein the timing controller shares the memory with the host controller.

[0179] The timing controller may further include a slave buffer for transmitting an internal control signal to the memory. The host controller may include a master buffer for transmitting an external control signal to the memory, and the master buffer and the slave buffer may be controlled by a mode control signal.

[0180] The mode control signal may keep the master buffer in an on state and the slave buffer in a high-impedance state during a first mode period when the host controller controls the memory.

[0181] The mode control signal may keep the master buffer in a high-impedance state and the slave buffer in an on state during a second mode period when the timing controller controls the memory.

[0182] A display system according to the present disclosure may include the display device as described above and a first controller connected to the display device.

[0183] The foregoing description has been presented to enable a person skilled in the art to make and use the inventive concept of the present disclosure and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The foregoing description and the accompanying drawings have provided examples of the inventive concept of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the inventive concept of the present disclosure.

Claims

1. A display device, comprising: A display panel comprising a plurality of sub-pixels; a memory configured to store image control data for controlling an image displayed on the display panel; a mode control signal generating circuit configured to generate a mode control signal based on a first mode signal provided from the first controller; as well as The second controller is configured to share the memory with the first controller and determine the control authority of the first controller over the memory through the mode control signal.

2. The display device according to claim 1, wherein: The image control data is gamma data for controlling the brightness of the image displayed on the display panel.

3. The display device according to claim 1, wherein: The first controller is a host controller, and the second controller is a timing controller.

4. The display device according to claim 1, wherein: The first controller includes a master buffer that transmits an external control signal to the memory, and the display device also includes a slave buffer that transmits an internal control signal to the memory and is located inside the second controller or on a control printed circuit board that is located outside the second controller, and The master buffer and the slave buffer are controlled by the mode control signal.

5. The display device according to claim 4, wherein: In a first mode period in which the first controller controls the memory, the mode control signal maintains the master buffer in an on state and maintains the slave buffer in a high impedance state.

6. The display device according to claim 4, wherein: In a second mode period in which the second controller controls the memory, the mode control signal maintains the master buffer in a high impedance state and maintains the slave buffer in an on state.

7. The display device according to claim 1, wherein: The first mode signal includes: a mode enable signal indicating entering a first mode in which the first controller controls the memory; and A chip select signal selects a chip in the memory for the first controller in the first mode.

8. The display device according to claim 7, wherein: The mode control signal generating circuit comprises: a first edge detection circuit configured to generate a mode enable edge signal by detecting an edge at which the mode enable signal is turned on; a second edge detection circuit configured to generate a chip select edge signal by detecting an edge at which the chip select signal is turned off; a first logic gate configured to generate the mode control signal using the mode enable edge signal and the chip select edge signal; and A second logic gate is configured to generate a reset signal for a reset operation of the first edge detection circuit and the second edge detection circuit using the mode enable edge signal and the chip select edge signal.

9. The display device according to claim 8, wherein: The first edge detection circuit is a trigger that receives the mode enable signal through a clock terminal.

10. The display device according to claim 8, wherein: The second edge detection circuit is a trigger that receives the chip selection signal through a clock terminal.

11. The display device according to claim 8, wherein: The first logic gate is an XOR gate.

12. The display device according to claim 8, wherein: The second logic gate is an AND gate.

13. The display device according to claim 8, wherein: The mode control signal generating circuit further includes a reset buffer that delays the reset signal for a predetermined time.

14. The display device according to claim 1, wherein: The mode control signal generating circuit is located in the second controller.

15. The display device according to claim 1, wherein: The mode control signal generating circuit is located on the control printed circuit board.

16. The display device according to claim 8, wherein: When entering the first mode, the mode enable signal is first turned into an on level, and then the chip select signal is turned into an on level.

17. The display device according to claim 8, wherein: When entering the second mode in which the second controller controls the memory, the chip selection signal is first changed to a OFF level, and then the mode enable signal is changed to a OFF level.

18. A timing controller, comprising: a first edge detection circuit configured to generate a mode enable edge signal by detecting an edge at which a mode enable signal provided from a host controller is turned on; a second edge detection circuit configured to generate a chip select edge signal by detecting an edge at which a chip select signal provided from the host controller is turned off; a first logic gate configured to generate a mode control signal for determining a control authority of the host controller over the memory using the mode enable edge signal and the chip select edge signal; as well as a second logic gate configured to generate a reset signal for a reset operation of the first edge detection circuit and the second edge detection circuit using the mode enable edge signal and the chip select edge signal, Wherein, the timing controller and the host controller share the memory.

19. The timing controller according to claim 18, wherein: The timing controller further includes a slave buffer for transmitting an internal control signal to the memory, The host controller includes a master buffer for transmitting an external control signal to the memory, and the master buffer and the slave buffer are controlled by the mode control signal.

20. The timing controller according to claim 19, wherein: In a first mode period in which the host controller controls the memory, the mode control signal maintains the master buffer in an on state and maintains the slave buffer in a high impedance state.

21. The timing controller according to claim 19, wherein: In a second mode period in which the timing controller controls the memory, the mode control signal maintains the master buffer in a high impedance state and maintains the slave buffer in an on state.

22. A display system comprising: The display device according to any one of claims 1 to 17; as well as A first controller is connected to the display device.

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