Display driving chip and display device

Abstract

The invention provides a display driving chip and a display device. The display driving chip comprises a digital signal processing circuit used for processing digital signals, and the digital signal processing circuit comprises a three-dimensional data processing module used for converting input three-dimensional display data into general display data in a three-dimensional display mode; the general data processing module is used for processing general display data from the data input interface in a two-dimensional display state and processing general display data from the three-dimensional data processing module in a three-dimensional display state; the data caching and mapping module is used for caching the display data processed by the general data processing module and outputting the display data; the first power supply module is used for supplying power to the three-dimensional data processing module in a three-dimensional display mode; and the second power supply module is used for supplying power to the general data processing module and the data cache mapping module. According to the embodiment of the invention, the energy consumption of two-dimensional display can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display driving chip and a display device. Background Art

[0002] With the development of display technologies, three-dimensional (3D) display technologies have increasingly become functions that users are concerned about. A display device capable of implementing 3D display usually also supports 2D display. In the 3D display state, due to the large amount of display data, the power consumption of the display driving chip is relatively high in order to process this display data. However, when switching to the 2D mode, although the amount of display data for 2D display is small, due to the data structure limitation of the display device, a large amount of dummy data still needs to be inserted for filling. This results in the power consumption of a terminal product equipped with a 3D display chip being much higher than that of a conventional 2D display terminal during 2D display, affecting the battery life of the terminal device. Summary of the Invention

[0003] Embodiments of this application provide a display driving chip and a display device to reduce the power consumption of the display device and improve the battery life of the display device.

[0004] In a first aspect, embodiments of this application provide a display driving chip. The display driving chip includes a digital signal processing circuit for processing digital signals. The digital signal processing circuit includes:

[0005] A 3D data processing module, connected to the data input interface of the display driving chip, for converting input 3D display data into general display data in the 3D display mode, where the general display data is display data common to both the 3D display mode and the 2D display mode;

[0006] A general data processing module, connected to both the 3D data processing module and the data input interface, for processing the general display data from the data input interface in the 2D display state, and processing the general display data from the 3D data processing module in the 3D display state;

[0007] A data cache mapping module, connected to the general data processing module, for caching and outputting the display data processed by the general data processing module;

[0008] A first power supply module, connected to the 3D data processing module, for supplying power to the 3D data processing module in the 3D display mode;

[0009] A second power supply module, connected to the general data processing module and the data cache mapping module, for supplying power to the general data processing module and the data cache mapping module.

[0010] In some of these embodiments, the three-dimensional data processing module includes:

[0011] A data decompression sub-module, connected to the data input interface of the display driver chip, for decompressing the input three-dimensional display data;

[0012] A three-dimensional data processing sub-module, connected to the output end of the data decompression sub-module, for processing the three-dimensional display data decompressed by the data decompression sub-module into general display data.

[0013] In some of these embodiments, the display driver chip satisfies m / n = N1 / N2, where m is the number of three-dimensional data paths between the three-dimensional data processing module and the general data processing module, n is the number of two-dimensional data paths between the data input interface of the display driver chip and the general data processing module, N1 is the data volume of the display data in the three-dimensional display state, and N2 is the data volume of the display data in the two-dimensional display state.

[0014] In some of these embodiments, the display driver chip includes an analog signal processing circuit for processing analog signals, and the analog signal processing circuit includes:

[0015] A latch, connected to the output end of the data cache mapping module, for latching the display data output by the data cache mapping module;

[0016] Multiple first amplifiers, with their input ends connected to the output end of the latch, for amplifying the display data output by the latch in the three-dimensional display state;

[0017] Multiple second amplifiers, with their input ends connected to the output end of the latch, for amplifying the display data output by the latch.

[0018] In some of these embodiments, the number of latches is equal to the sum of the number of first amplifiers and the number of second amplifiers, and the number of latches is equal to the number of communication channels of the display panel.

[0019] In some of these embodiments, the analog signal processing circuit further includes:

[0020] A multiplexer, with its input end connected to the input end of the operational amplifier and its output end for connecting to the communication channel of the display panel;

[0021] The multiplexer is configured to be in a closed state in the three-dimensional display mode, so that each latch and operational amplifier are connected in one-to-one correspondence, and the operational amplifier is the first amplifier or the second amplifier.

[0022] In some of these embodiments, the display driving chip further includes:

[0023] A first bias current source, connected to the first amplifier, for providing a bias current to the first amplifier in a three-dimensional display state.

[0024] A second bias current source, connected to the second amplifier, for providing a bias current to the second amplifier.

[0025] In some of these embodiments, the first amplifier is arranged along a first direction on the display driving chip, the second amplifier is arranged along the first direction on the display driving chip, and the first amplifier and the second amplifier are arranged along a second direction on the display driving chip;

[0026] Both the first bias current source and the second bias current source extend along the first direction and are spaced apart along the second direction;

[0027] The first direction and the second direction are intersecting directions.

[0028] In some of these embodiments, the first amplifier and the second amplifier are arranged along a first direction to form an operational amplifier column, both the first bias current source and the second bias current source extend along the first direction, and are respectively arranged on both sides of the operational amplifier column.

[0029] In a second aspect, an embodiment of the present application provides a display device, including the display driving chip according to any one of the first aspect.

[0030] By separately powering the three-dimensional data processing module in the embodiments of the present application, in a two-dimensional display state, the three-dimensional data processing module does not need to work, thereby being able to reduce the power consumption of two-dimensional display while being compatible with two-dimensional and three-dimensional displays. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments of the present application. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0032] Figure 1 is an architecture diagram of a display driving chip in an embodiment of the present application;

[0033] Figure 2 is a layout schematic diagram of a display driving chip in an embodiment of the present application;

[0034] Figure 3It is another layout schematic diagram of the display driving chip in an embodiment of the present application;

[0035] Figure 4 It is a connection schematic diagram of the multiplexer in an embodiment of the present application;

[0036] Figure 5 It is another connection schematic diagram of the multiplexer in an embodiment of the present application. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0038] The terms "first", "second", etc. in the embodiments of the present application are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices. In addition, the use of "and / or" in the present application represents at least one of the connected objects. For example, A and / or B and / or C represents seven situations including A alone, B alone, C alone, A and B existing together, B and C existing together, A and C existing together, and A, B, and C existing together.

[0039] The embodiments of the present application provide a display driving chip.

[0040] As Figure 1 shown, in the technical solution of this embodiment, the display driving chip includes a digital signal processing circuit (digital part) 101 for processing digital signals and an analog signal processing circuit (analog part) 102 for processing analog signals.

[0042] In one of the embodiments, the above digital part includes a three-dimensional data processing module 1011, a general data processing module 1012, a data cache mapping module 1013, a first power supply module 1014, and a second power supply module 1015.

[0043] The three-dimensional data processing module 1011 is connected to the data input interface 1016 of the display driving chip, and is used to convert the input three-dimensional display data into general display data in the three-dimensional display mode.

[0044] The general data processing module 1012 is respectively connected to the three-dimensional data processing module 1011 and the data input interface 1016, and is used for processing the general display data from the data input interface 1016 in the two-dimensional display state.

[0045] The display driver chip of this embodiment can compatibly process three-dimensional display data (3D) and two-dimensional display data (2D). In other words, the display driver chip can be compatible with two display modes, namely the three-dimensional display mode and the two-dimensional display mode.

[0046] In the display stage, the display data is transmitted from the front end to the display driver chip. The display driver chip can select various general ports as the data input interface 1016. For example, it can select general transmission interfaces such as MIPI (Mobile Industry Processor Interface) and eDP (Embedded Display Port).

[0047] In some of these embodiments, the three-dimensional data processing module 1011 specifically includes a data decompression sub-module 10111 and a three-dimensional data processing sub-module 10112.

[0048] The data decompression sub-module 10111 is connected to the data input interface 1016 of the display driver chip and is used for decompressing the input three-dimensional display data; the three-dimensional data processing sub-module 10112 is connected to the output end of the data decompression sub-module 10111 and is used for processing the three-dimensional display data decompressed by the data decompression sub-module 10111 into general display data.

[0049] In the technical solution of this embodiment, the general display data is the display data common to the three-dimensional display mode and the two-dimensional display mode.

[0050] It should be understood that when conditions such as resolution and refresh rate are the same, the amount of display data required in the three-dimensional display mode is usually several times that of the display data in the two-dimensional display mode. Therefore, in the three-dimensional display mode, the display data is usually highly compressed by the front-end system chip and then transmitted to the display driver chip through the data input interface 1016. In the two-dimensional display mode, the amount of display data is relatively small, so it can be directly provided to the display driver chip through the data input interface 1016.

[0051] It can also be understood that in the two-dimensional display mode, the format of the input display data is general display data, while in the three-dimensional display mode, it needs to be processed into this general display data.

[0052] The general data processing module 1012 is respectively connected to the three-dimensional data processing module 1011 and the data input interface 1016. In the two-dimensional display state, the general data processing module 1012 directly obtains and processes the general display data from the data input interface 1016. In the three-dimensional display state, the general data processing module 1012 receives and processes the general display data from the three-dimensional data processing module 1011.

[0053] That is to say, after the three-dimensional data processing module 1011 processes the three-dimensional display data into general display data, it sends it to the general data processing module 1012 for further processing.

[0054] The data cache mapping module 1013 is connected to the general data processing module 1012, and is used to cache the display data processed by the general data processing module 1012 and output it. In the cache mapping stage, after the data cache mapping module 1013 receives the display data from the general data processing module 1012, each row of cached data is divided into multiple data blocks, and then the position arrangement is carried out, and then it is further provided to the analog part of the display driver chip through the data cache and distribution process.

[0055] According to the above analysis, in the two-dimensional display mode, the three-dimensional data processing module 1011 does not need to work, and the display data processing of the digital part can be realized by the cooperation of the general data processing module 1012 and the data cache mapping module 1013; while in the three-dimensional display mode, the three-dimensional data processing module 1011, the general data processing module 1012 and the data cache mapping module 1013 need to work together to realize the display data processing of the digital part.

[0056] In this embodiment, the first power supply module 1014 is connected to the three-dimensional data processing module 1011 and is used to supply power to the three-dimensional data processing module 1011 in the three-dimensional display mode; the second power supply module 1015 is connected to the general data processing module 1012 and the data cache mapping module 1013 and is used to supply power to the general data processing module 1012 and the data cache mapping module 1013.

[0057] It should be understood that the decompression and three-dimensional display related digital processing modules usually require more complex algorithm logic calculations and data interactions to be realized. The number of gate circuits required accounts for a large proportion in the chip, and the corresponding power consumption is large. Even when these modules are not working, the static power consumption also accounts for a certain proportion. In the two-dimensional display mode of this embodiment, the first power supply module 1014 can suspend power supply to the three-dimensional data processing module 1011, which can save the digital static power consumption of the three-dimensional data processing module 1011 during non-working hours, that is, reduce the power consumption of the display driver chip in the two-dimensional display mode.

[0058] In some of these embodiments, the number of data paths (ports) of the display driving chip satisfies m / n = N1 / N2, where m is the number of three-dimensional data paths between the three-dimensional data processing module 1011 and the general data processing module 1012, n is the number of two-dimensional data paths between the data input interface 1016 of the display driving chip and the general data processing module 1012, N1 is the data volume of the display data in the three-dimensional display state, and N2 is the data volume of the display data in the two-dimensional display state.

[0059] It should be understood that, under the condition of the same resolution, refresh frequency, etc., the data volume of three-dimensional display data is much higher than that of two-dimensional display data, that is, N1 is greater than N2. Correspondingly, m is greater than n, and the data path between the digital part and the analog part of the display driving chip needs to satisfy at least the data volume of three-dimensional display data in order to meet the data transmission requirements between the digital part and the analog part.

[0060] Due to the number of three-dimensional data paths between the three-dimensional data processing module 1011 and the general data processing module 1012 in this embodiment, therefore, setting m paths between the digital part and the analog part can meet the data transmission requirements. Taking the bandwidth as 24 bytes (24 bit) or 30 bytes (bit), the total data volume D satisfies:

[0061] D = m * 24 / 30 bit * M;

[0062] Where M represents a specific time length of M clk.

[0063] However, for the two-dimensional display mode, the data volume of its display data is small. If m data paths are still used for data transmission, the number of clk of the required transmission time will be very short. If the same refresh frequency as that of 3D is to be maintained, the digital part needs to insert dummy clk (dummy time frames) or invalid data inside the display data so that the total number of clocks remains unchanged. But this way increases the digital logic in disguise and generates additional power consumption.

[0064] In the technical solution of this embodiment, in the two-dimensional display mode, only part of the data paths are used for transmission. This can ensure that the number of clocks remains the same or is an integer multiple in the two-dimensional display mode and the three-dimensional display mode, which can simplify the digital implementation logic and further reduce the digital power consumption.

[0065] In the cache mapping stage, the data cache mapping module 1013 first caches the display data processed by the data processing module row by row, and then divides each row of display data into z data blocks (z is a positive integer) according to the communication channel positions of the analog part, and further sends them to the analog part of the display driving chip.

[0066] The analog part of the display driver chip includes a latch 1021 (SR LATCH), a first amplifier 10221, a second amplifier 10222, an operational amplifier 1022, and a multiplexer 1023. Among them, the operational amplifier 1022 specifically includes the first amplifier 10221 and the second amplifier 10222.

[0067] The latch 1021 is connected to the output end of the data cache mapping module 1013. The data cache mapping module 1013 sends the divided data blocks to the corresponding latches 1021, and the latches 1021 latch the corresponding display data.

[0068] The input ends of multiple first amplifiers 10221 are connected to the output end of the latch 1021, and are used to amplify the display data output by the latch 1021 in the three-dimensional display state; the input ends of multiple second amplifiers 10222 are connected to the output end of the latch 1021, and are used to amplify the display data output by the latch 1021.

[0069] In the technical solution of this embodiment, the first amplifier 10221 only works in the three-dimensional display state. In other words, in the two-dimensional display state, the display data is amplified by the second amplifier 10222. At this time, the first amplifier 10221 is controlled to be in the off or low-power state; in the three-dimensional display state, the first amplifier 10221 and the second amplifier 10222 work simultaneously to amplify the display data. In this way, by controlling the working state of the first amplifier 10221 in different display states, the energy consumption generated by the operation of the first amplifier 10221 can be reduced in the two-dimensional display state.

[0070] The number of latches 1021 is equal to the sum of the numbers of the first amplifier 10221 and the second amplifier 10222, and the number of latches 1021 is equal to the number of communication channels 103 of the display panel.

[0071] In the technical solution of this embodiment, in the three-dimensional display state, the above-mentioned data blocks, operational amplifier 1022, and communication channels 103 are in one-to-one correspondence. The operational amplifier 1022 mentioned here includes the above-mentioned first amplifier 10221 and second amplifier 10222. That is to say, the sum of the numbers of the first amplifier 10221 and the second amplifier 10222 is equal to the number z of data blocks, and the number of communication channels 103 is z.

[0072] In some of these embodiments, the analog signal processing circuit 102 further includes a multiplexer 1023.

[0073] The input end of the multiplexer 1023 is connected to the input end of the operational amplifier 1022, and the output end is used to connect to the communication channel 103 of the display panel. The multiplexer 1023 is configured to be in the off state in the three-dimensional display mode, so that each latch 1021 and the operational amplifier 1022 are connected one by one, and the operational amplifier 1022 is the first amplifier 10221 or the second amplifier 10222.

[0074] In the technical solution of this embodiment, in the two-dimensional display state, since the number of communication channels 103 is greater than the number of working second amplifiers 10222, it is necessary to switch the connection state between the second amplifier 10222 and each communication channel 103 through the multiplexer 1023, so that each path communication channel 103 of the display panel has display data input, thereby realizing display control.

[0075] In some embodiments, the display driving chip further includes a first bias current source 1024 and a second bias current source 1025.

[0076] The first bias current source 1024 is connected to the first amplifier 10221 and is used to provide a bias current for the first amplifier 10221 in the three-dimensional display state; the second bias current source 1025 is connected to the second amplifier 10222 and is used to provide a bias current for the second amplifier 10222.

[0077] In this embodiment, when in the three-dimensional display state, both the first bias current source 1024 and the second bias current source 1025 are in the power supply state, so as to be able to supply power to the first amplifier 10221 and the second amplifier 10222. In the two-dimensional display state, the first bias current source 1024 stops providing the bias current, and the second bias current source 1025 provides the bias current for the second amplifier 10222, thereby realizing two-dimensional display when only some of the operational amplifiers 1022 are working.

[0078] As Figure 2 shown, in some embodiments, the first amplifiers 10221 are arranged along a first direction on the display driving chip, the second amplifiers 10222 are arranged along the first direction on the display driving chip, and the first amplifiers 10221 and the second amplifiers 10222 are arranged along a second direction on the display driving chip; both the first bias current source 1024 and the second bias current source 1025 extend along the first direction and are spaced apart along the second direction; the first direction and the second direction are intersecting directions.

[0079] In one embodiment, the first direction is Figure 2 the horizontal direction shown, and the second direction is Figure 2The longitudinal direction shown. On the layout of the display driving chip, the first row from top to bottom is the first amplifier 10221, and the second row is the second amplifier 10222. Correspondingly, both the first bias current source 1024 and the second bias current source 1025 are arranged horizontally, and the first bias current source 1024 is connected to the first amplifier 10221, and the second bias current source 1025 is connected to the second amplifier 10222. In this way, during the working process, by controlling the bias currents provided by the first bias current source 1024 and the second bias current source 1025, the working states of the first amplifier 10221 and the second amplifier 10222 can be controlled.

[0080] In this embodiment, each block conducts data transmission through a separate data path. When in the display state, all blocks #1 to #z are output. At the same time, both the first bias current source 1024 and the second bias current source 1025 are turned on and provide bias currents.

[0081] In the two-dimensional display state, only some blocks are transmitted. For example, in this embodiment, only the data paths corresponding to blocks #2, #4... are transmitted, and the first bias current source 1024 is turned off, or the first bias current source 1024 can be set to a low-power state and kept on to prevent the restart time from being too long.

[0082] In this way, in the technical solution of this embodiment, in the two-dimensional display state, the power supplies of some idle blocks can be completely turned off to meet the low-power requirement.

[0083] As Figure 3 shown, in another embodiment, the first amplifier 10221 and the second amplifier 10222 are arranged in a row in the first direction to form an operational amplifier column. The first bias current source 1024 and the second bias current source 1025 both extend in the first direction and are respectively arranged on both sides of the operational amplifier column.

[0084] In this embodiment, the first amplifier 10221 and the second amplifier 10222 are arranged in a row. During implementation, the first amplifier 10221 and the second amplifier 10222 can be alternately arranged, or they can be arranged according to a certain rule according to their quantity ratio.

[0085] The first bias current source 1024 is arranged above the operational amplifier column and is connected to the first amplifier 10221 to provide a bias current. The second bias current source 1025 is arranged below the operational amplifier column and is connected to the second amplifier 10222 to provide a bias current. In this way, it is also possible to respectively provide bias currents to the first amplifier 10221 and the second amplifier 10222 to control their working states.

[0086] As Figure 3As shown, in this embodiment, each block has an independent data path for transmission. When in the three-dimensional display state, all blocks #1 to #z output, and both the first bias current source 1024 and the second bias current source 1025 are turned on to provide bias current.

[0087] In the two-dimensional display state, if the data path is connected to the latch 1021 in an interleaved manner, it will occupy a huge area. Therefore, when reasonably controlling the area of the circuit board, it is difficult for the data path to be connected to the latch 1021 in an interleaved manner. However, the data paths corresponding to each block need to be transmitted. Therefore, in the data mapping and distribution stage, black data is inserted at the positions that do not need to be displayed.

[0088] Taking the different filling effects in the figure representing valid data and invalid data as an example, the data needs to be arranged in the manner of [data|data|black|black|data|data...]. When transmitted to the operational amplifier 1022, the bias current of the first amplifier 10221 that does not need to be displayed is set to off or low power consumption mode. In the technical solution of this embodiment, the operational amplifier 1022 only occupies one row of area and occupies a small chip area.

[0089] As Figure 4 shown, in one embodiment, in the three-dimensional display mode, all blocks #1 to #z are turned on, the multiplexer 1023 is turned off, and each operational amplifier 1022 outputs one-to-one with the communication channel 103. In the two-dimensional display mode, only some of the operational amplifiers 1022 are turned on, and the data is mapped to different communication channels 103 through the multiplexer 1023 in a time-sharing manner, thereby reducing the static power consumption of the operational amplifier 1022.

[0090] As Figure 5 shown, in another embodiment, in the two-dimensional display state, the horizontal three-dimensional data needs to be filled with the same display data. By the way of turning on multiple multiplexers 1023 simultaneously, one operational amplifier 1022 is used to push the data of multiple communication channels 103 at the same time. Combining the above-mentioned method of power supply for each block group, the effect of turning off the useless blocks in the two-dimensional display mode to achieve low power consumption can also be achieved.

[0091] This embodiment also provides a display device, including any one of the above display driver chips. Since the display device of this embodiment includes all the technical solutions of the above display driver chip embodiment, it can at least achieve all the above technical effects, which will not be elaborated here.

[0092] It should be noted that in this text, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising that element. In addition, it should be pointed out that the scope of the methods and apparatuses in the embodiments of the present application is not limited to performing functions in the order shown or discussed, but may also include performing functions in a substantially simultaneous manner or in the reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, the features described with reference to certain examples may be combined in other examples.

[0093] Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions for causing a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present application.

[0094] The embodiments of the present application have been described above with reference to the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them fall within the protection scope of the present application.

Claims

1. A display driver chip, characterized in that: The display driver chip includes a digital signal processing circuit for processing digital signals, and the digital signal processing circuit includes: a three-dimensional data processing module connected to the data input interface of the display driver chip, and used to convert the input three-dimensional display data into common display data in the three-dimensional display mode, wherein the common display data is display data common to the three-dimensional display mode and the two-dimensional display mode; a general data processing module, connected to the three-dimensional data processing module and the data input interface, respectively, for processing the general display data from the data input interface in a two-dimensional display state, and for processing the general display data from the three-dimensional data processing module in a three-dimensional display state; A data cache mapping module, connected to the general data processing module, for caching and outputting the display data processed by the general data processing module; A first power supply module, connected to the three-dimensional data processing module, and configured to supply power to the three-dimensional data processing module in a three-dimensional display mode; The second power supply module is connected to the general data processing module and the data cache mapping module, and is used to supply power to the general data processing module and the data cache mapping module.

2. The display driver chip according to claim 1, characterized in that: The three-dimensional data processing module includes: A data decompression submodule, connected to the data input interface of the display driver chip, and used for decompressing input three-dimensional display data; The three-dimensional data processing submodule is connected to the output end of the data decompression submodule and is used to process the three-dimensional display data decompressed by the data decompression submodule into general display data.

3. The display driver chip according to claim 1, characterized in that: The display driver chip satisfies m / n=N1 / N2, wherein m is the number of three-dimensional data paths between the three-dimensional data processing module and the general data processing module, n is the number of two-dimensional data paths between the data input interface of the display driver chip and the general data processing module, N1 is the amount of display data in a three-dimensional display state, and N2 is the amount of display data in a two-dimensional display state.

4. The display driver chip according to claim 1, characterized in that: The display driver chip includes an analog signal processing circuit for processing an analog signal, and the analog signal processing circuit includes: A latch connected to the output terminal of the data cache mapping module and used for latching the display data output by the data cache mapping module; A plurality of first amplifiers, whose input ends are connected to the output ends of the latches, and are used to amplify the display data output by the latches in a three-dimensional display state; A plurality of second amplifiers have input ends connected to the output ends of the latches and are used to amplify the display data output by the latches.

5. The display driver chip according to claim 4, characterized in that: The number of the latches is equal to the sum of the number of the first amplifiers and the number of the second amplifiers, and the number of the latches is equal to the number of communication channels of the display panel.

6. The display driver chip according to claim 4 or 5, characterized in that: The analog signal processing circuit also includes: a multi-way switch, the input end of which is connected to the input end of the operational amplifier, and the output end of which is used to be connected to the communication channel of the display panel; The multi-way switch is configured to be in a closed state in a three-dimensional display mode so that each latch is connected to an operational amplifier in a one-to-one correspondence, and the operational amplifier is the first amplifier or the second amplifier.

7. The display driver chip according to claim 4 or 5, characterized in that: The display driver chip also includes: a first bias current source connected to the first amplifier and configured to provide a bias current to the first amplifier in a three-dimensional display state; The second bias current source is connected to the second amplifier and is used to provide a bias current for the second amplifier.

8. The display driver chip according to claim 7, characterized in that: The first amplifiers are arranged along a first direction on the display driver chip, the second amplifiers are arranged along the first direction on the display driver chip, and the first amplifiers and the second amplifiers are arranged along a second direction on the display driver chip; The first bias current source and the second bias current source both extend along the first direction and are spaced apart along the second direction; The first direction and the second direction are intersecting directions.

9. The display driver chip according to claim 7, characterized in that: The first amplifier and the second amplifier are arranged along a first direction to form an operational amplifier column. The first bias current source and the second bias current source both extend along the first direction and are respectively disposed on two sides of the operational amplifier column.

10. A display device, characterized in that: A display driver chip comprising any one of claims 1 to 9.

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