Display device

Abstract

A display device according to an embodiment includes: a substrate; a plurality of pixels disposed in the display region on the substrate; and a data signal line that supplies a data signal to each of the plurality of pixels. Each of the plurality of pixels includes a pixel circuit having a first transistor and a holding capacitor, and a light emitting element driven by the pixel circuit. The holding capacitor is configured so as to be written with a voltage that controls a current supplied to the light-emitting element. The first transistor is configured so as to supply a current to the light-emitting element on the basis of a voltage written to the holding capacitor. A one-frame period in which one frame is displayed in the display area includes a second period in which the first transistor is turned on, the second period being disposed prior to a first period in which a voltage corresponding to the data signal is written to the holding capacitor.

Description

[0001] This application is based on Japanese Patent Application 2023-214905 (filing date: December 20, 2023) and claims priority therefrom. This application incorporates the entire contents of the same application by reference thereto. Technical Field

[0002] Embodiments of the present invention relate to a display device. Background Art

[0003] In recent years, a display device using an organic light-emitting diode (OLED), which functions as a display element, has been put into practical use.

[0004] In such a display device, the light-emitting element is driven by a pixel circuit. However, depending on the driving method of the light-emitting element, the display quality of the display device may deteriorate. Summary of the Invention

[0005] An object of the present invention is to provide a display device capable of suppressing deterioration of display quality.

[0006] The display device according to the embodiment includes: a substrate; a plurality of pixels disposed in a display area on the substrate; and a data signal line that supplies a data signal to each of the plurality of pixels. Each of the plurality of pixels includes a pixel circuit having a first transistor and a holding capacitor, and a light-emitting element driven by the pixel circuit. The holding capacitor is configured to be written with a voltage for controlling a current supplied to the light-emitting element. The first transistor is configured to supply a current to the light-emitting element based on the voltage written to the holding capacitor. A first period during which a voltage corresponding to the data signal is written to the holding capacitor is preceded by a second period in which the first transistor is set to an on state during one frame period for displaying one frame in the display area. Description of the Drawings

[0007] Figure 1 The figure shows a configuration example of the display device according to the first embodiment.

[0008] Figure 2 The figure shows an example of the layout of a plurality of sub-pixels included in a pixel.

[0009] Figure 3 The figure shows another example of the layout of a plurality of sub-pixels included in a pixel.

[0010] Figure 4 is along Figure 2 a schematic cross-sectional view of the display device taken along line A-A in

[0011] Figure 5 a schematic enlarged cross-sectional view of the partition wall.

[0012] Figure 6 It is a schematic cross-sectional view for explaining a light-emitting element formed using a partition wall.

[0013] Figure 7 It is a schematic cross-sectional view for explaining a light-emitting element formed using a partition wall.

[0014] Figure 8 It is a schematic cross-sectional view for explaining a light-emitting element formed using a partition wall.

[0015] Figure 9 It is a diagram showing an example of the circuit configuration of a pixel circuit.

[0016] Figure 10 It is a diagram showing an example of the operation of a pixel circuit in a comparative example of the present embodiment.

[0017] Figure 11 It is a diagram for explaining the case where the frame displayed within each one-frame period is a black image.

[0018] Figure 12 It is a diagram for explaining the case where the frame displayed within each one-frame period is a white image.

[0019] Figure 13 It is a diagram for explaining the case of switching from displaying black to displaying white.

[0020] Figure 14 It is a diagram showing a configuration example during the pre-activation period in the present embodiment.

[0021] Figure 15 It is a diagram for explaining an example of the operation of a pixel circuit in the present embodiment.

[0022] Figure 16 It is a diagram for explaining a scan circuit and an EM circuit for implementing a gate signal and a control signal in a comparative example of the present embodiment.

[0023] Figure 17 It is a diagram showing an example of the configuration of a gate driver composed of a scan circuit and an EM circuit.

[0024] Figure 18 It is a diagram for explaining a scan circuit and an EM circuit for implementing a gate signal and a control signal in the present embodiment.

[0025] Figure 19 It is a diagram showing an example of the circuit configuration of a pixel circuit in the second embodiment.

[0026] Figure 20 It is a diagram for explaining an example of the operation of a pixel circuit in the present embodiment.

[0027] Figure 21 This is a diagram for explaining a scanning circuit and an EM circuit for implementing the gate signal and control signal in the present embodiment.

[0028] Figure 22 This is a diagram showing an example of the configuration of a gate driver composed of a scanning circuit and an EM circuit.

[0029] Among them, the reference numerals are explained as follows:

[0030] DSP display device, DA display area, NDA non-display area, PX pixel,

[0031] SP, SP1, SP2, SP3 sub-pixels, AP, AP1, AP2, AP3 openings, LE, LE1,

[0032] LE2, LE3 lower electrodes, UE, UE1, UE2, UE3 upper electrodes, OR, OR1, OR2,

[0033] OR3 organic layer, SE, SE1, SE2, SE3 encapsulation layer, Tr1 to Tr7 transistors, Cst holding capacitor, SR1 to SR4 registers, ER1 to ER3 registers, 5 ribs, 6 partitions, 10 substrates, 11 insulating layers, 12 circuit layers, 13 insulating layers, 14 resin layers, 15 encapsulation layers, 16 resin layers, 20 light-emitting elements, 61 lower part, 62 upper part, 100 pixel circuits, 301 shift register for scanning circuit, 302 shift register for EM circuit, 302a NOT circuit, 302b NOR circuit. Specific Embodiments

[0034] An embodiment will be described with reference to the accompanying drawings.

[0035] The present disclosure is merely an example, and appropriate modifications that those skilled in the art can easily think of while maintaining the gist of the invention are of course included in the scope of the present invention. In addition, for the sake of clarity of explanation, the width, thickness, shape, etc. of each part of the drawings are sometimes schematically shown compared with the actual mode, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each drawing, components that perform the same or similar functions as those described in the accompanying drawings that have appeared previously are sometimes labeled with the same reference numerals, and repeated detailed descriptions are appropriately omitted.

[0036] It should be noted that in the drawings, the X-axis, Y-axis, and Z-axis orthogonal to each other are recorded as needed for easy understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Observing various elements parallel to the third direction Z is called a top view.

[0037] The display device of this embodiment is an organic electroluminescence display device that includes an organic light-emitting diode (OLED) as a display element (light-emitting element), and is mounted on a television, a laptop computer, a portable terminal, a mobile phone, etc.

[0038] (First Embodiment)

[0039] First, the first embodiment will be described. Figure 1 It is a diagram showing a configuration example of the display device DSP of this embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA around the display area DA on an insulating substrate 10. The substrate 10 can be glass or a flexible resin film.

[0040] In this embodiment, the shape of the substrate 10 in a top view is rectangular. However, the shape of the substrate 10 in a top view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0041] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y that intersect each other. The pixel PX includes a plurality of sub-pixels SP. In one example, the plurality of sub-pixels SP include a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. It should be noted that the plurality of sub-pixels SP may include sub-pixels of other colors such as white in addition to the sub-pixels SP1, SP2, and SP3. In addition, the plurality of sub-pixels SP may include sub-pixels of other colors instead of one of the sub-pixels SP1, SP2, and SP3.

[0042] It should be noted that, as will be described in detail later, each of the plurality of sub-pixels SP includes a pixel circuit and a light-emitting element driven by the pixel circuit. The pixel circuit is composed of, for example, a plurality of transistors (switching elements composed of thin film transistors). The light-emitting element is the above-mentioned organic light-emitting diode. For example, the sub-pixel SP1 has a light-emitting element that emits light in a wavelength range of red, the sub-pixel SP2 has a light-emitting element that emits light in a wavelength range of green, and the sub-pixel SP3 has a light-emitting element that emits light in a wavelength range of blue.

[0043] Figure 2 An example of the layout of the plurality of sub-pixels SP (SP1, SP2, and SP3) included in the pixel PX is shown. Here, four pixels PX will be described.

[0044] The sub-pixels SP1, SP2, and SP3 that make up one pixel PX are each formed in a substantially rectangular shape extending in the second direction Y and are arranged in the first direction X. If we focus on two pixels PX arranged in the first direction X, the colors displayed in the sub-pixels SP adjacent in the first direction X are different from each other. Additionally, if we focus on two pixels PX arranged in the second direction Y, the colors displayed in the sub-pixels SP adjacent in the second direction Y are the same. It should be noted that the area of each of the sub-pixels SP1, SP2, and SP3 may be the same or different from each other.

[0045] Figure 3 Fig. shows another example of the layout of the multiple sub-pixels SP (SP1, SP2, and SP3) included in the pixel PX.

[0046] The sub-pixels SP1 and SP2 that make up one pixel PX are arranged in the second direction Y, the sub-pixels SP1 and SP3 are arranged in the first direction X, and the sub-pixels SP2 and SP3 are arranged in the first direction X. The sub-pixel SP1 is formed in a substantially rectangular shape extending in the first direction X, and the sub-pixels SP2 and SP3 are formed in a substantially rectangular shape extending in the second direction Y. The area of the sub-pixel SP2 is larger than the area of the sub-pixel SP1, and the area of the sub-pixel SP3 is larger than the area of the sub-pixel SP2. It should be noted that the shape and area of the sub-pixel SP1 may also be the same as those of the sub-pixel SP2.

[0047] If we focus on two pixels PX arranged in the first direction X, in the regions where the sub-pixels SP1 and SP3 are alternately arranged and the regions where the sub-pixels SP2 and SP3 are alternately arranged, the colors displayed in the sub-pixels SP adjacent in the first direction X are different from each other. On the other hand, if we focus on two pixels PX arranged in the second direction Y, in the region where the sub-pixels SP1 and SP2 are alternately arranged, the colors displayed in the sub-pixels SP adjacent in the second direction Y are different from each other. Additionally, in the region where multiple sub-pixels SP3 are arranged, the colors displayed in the sub-pixels SP adjacent in the second direction are the same.

[0048] It should be noted that Figure 2 and Figure 3 The outer shapes of the sub-pixels SP1, SP2, and SP3 shown are equivalent to the outer shapes of the regions (i.e., the light-emitting regions) where colors are displayed in the sub-pixels SP, but these outer shapes are shown in a simplified manner and do not necessarily reflect the actual shapes.

[0049] Here, in the display area DA of the present embodiment, ribs and partition walls are provided, and the details will be described later. The ribs have openings in the sub-pixels SP1, SP2, and SP3 respectively. The partition walls are arranged at the boundaries of adjacent sub-pixels SP and coincide with the ribs in a top view. Specifically, the partition walls are arranged between the openings (sub-pixels SP) adjacent in the first direction X and between the openings (sub-pixels SP) adjacent in the second direction Y. Thus, the partition walls as a whole have a lattice shape formed in a manner of dividing the sub-pixels SP1, SP2, and SP3. In other words, similar to the ribs, it can also be said that the partition walls have openings in the sub-pixels SP1, SP2, and SP3.

[0050] Figure 4 is a schematic cross-sectional view of the display device DSP along the A-A line in Figure 2 . In the display device DSP, an insulating layer 11 called a bottom coating layer is provided on the light-transmissive substrate 10 such as the above-mentioned glass (on the surface on the side where the light-emitting elements and the like are arranged).

[0051] The insulating layer 11 has, for example, a three-layer stacked structure of a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). It should be noted that the insulating layer 11 is not limited to the three-layer stacked structure. The insulating layer 11 may have a stacked structure with more than three layers, or may have a single-layer structure or a two-layer stacked structure.

[0052] A circuit layer 12 is provided on the insulating layer 11. The circuit layer 12 has pixel circuits (various circuits and wirings) for driving the light-emitting elements included in each of the sub-pixels SP1, SP2, and SP3 as described above. The circuit layer 12 is covered by an insulating layer 13.

[0053] The insulating layer 13 functions as a planarization film for planarizing the unevenness generated by the circuit layer 12. Although not shown in Figure 4 , contact holes for connecting the lower electrodes LE to the pixel circuits are provided in the insulating layer 13.

[0054] The lower electrodes LE (LE1, LE2, and LE3) are provided on the insulating layer 13. The ribs 5 are provided on the insulating layer 13 and the lower electrodes LE. The ends (a part) of the lower electrodes LE are covered by the ribs 5.

[0055] The partition wall 6 has a lower part 61 provided on the rib 5 and an upper part 62 covering the upper surface of the lower part 61. The upper part 62 has a larger width than the lower part 61 in the first direction X and the second direction Y. Thus, the partition wall 6 has a shape in which both ends of the upper part 62 protrude from the side surfaces of the lower part 61. This shape of the partition wall 6 can be called a hanging shape.

[0056] The organic layer OR (OR1, OR2, and OR3) and the upper electrode UE (UE1, UE2, and UE3) together with the lower electrode LE (LE1, LE2, and LE3) constitute the light-emitting element included in the sub-pixel SP.

[0057] As Figure 4 shown, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b that are separated from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b that are separated from each other. The first organic layer OR1a passes through the opening AP1 (the opening provided in the rib 5 in the sub-pixel SP1) and contacts the lower electrode LE1, and covers a part of the rib 5. The second organic layer OR1b is located above the upper portion 62. The first upper electrode UE1a is opposed to the lower electrode LE1 and covers the first organic layer OR1a. Moreover, the first upper electrode UE1a contacts the side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0058] In addition, as Figure 4 shown, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b that are separated from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b that are separated from each other. The first organic layer OR2a passes through the opening AP2 (the opening provided in the rib 5 in the sub-pixel SP2) and contacts the lower electrode LE2, and covers a part of the rib 5. The second organic layer OR2b is located above the upper portion 62. The first upper electrode UE2a is opposed to the lower electrode LE2 and covers the first organic layer OR2a. Moreover, the first upper electrode UE2a contacts the side surface of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0059] In addition, as Figure 4 shown, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b that are separated from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b that are separated from each other. The first organic layer OR3a passes through the opening AP3 (the opening provided in the rib 5 in the sub-pixel SP3) and contacts the lower electrode LE3, and covers a part of the rib 5. The second organic layer OR3b is located above the upper portion 62. The first upper electrode UE3a is opposed to the lower electrode LE3 and covers the first organic layer OR3a. Moreover, the first upper electrode UE3a contacts the side surface of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0060] In Figure 4In the example shown, the sub-pixels SP1, SP2, and SP3 include cover layers CP1, CP2, and CP3 (optical path adjustment layers) for adjusting the optical characteristics of the light emitted from the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0061] The cover layer CP1 includes a first cover layer CP1a and a second cover layer CP1b that are separated from each other. The first cover layer CP1a is located in the opening AP1 and is disposed above the first upper electrode UE1a. The second cover layer CP1b is located above the partition wall 6 and is disposed above the second upper electrode UE1b.

[0062] The cover layer CP2 includes a first cover layer CP2a and a second cover layer CP2b that are separated from each other. The first cover layer CP2a is located in the opening AP2 and is disposed above the first upper electrode UE2a. The second cover layer CP2b is located above the partition wall 6 and is disposed above the second upper electrode UE2b.

[0063] The cover layer CP3 includes a first cover layer CP3a and a second cover layer CP3b that are separated from each other. The first cover layer CP3a is located in the opening AP3 and is disposed above the first upper electrode UE3a. The second cover layer CP3b is located above the partition wall 6 and is disposed above the second upper electrode UE3b.

[0064] Sealing layers SE1, SE2, and SE3 are respectively disposed in the sub-pixels SP1, SP2, and SP3. The sealing layer SE1 continuously covers the components of the sub-pixel SP1 including the first cover layer CP1a, the partition wall 6, and the second cover layer CP1b. The sealing layer SE2 continuously covers the components of the sub-pixel SP2 including the first cover layer CP2a, the partition wall 6, and the second cover layer CP2b. The sealing layer SE3 continuously covers the components of the sub-pixel SP3 including the first cover layer CP3a, the partition wall 6, and the second cover layer CP3b.

[0065] In Figure 4 In the example shown, the second organic layer OR1b, the second upper electrode UE1b, the second cover layer CP1b, and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the second organic layer OR2b, the second upper electrode UE2b, the second cover layer CP2b, and the sealing layer SE2 on the same partition wall 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, the second cover layer CP2b, and the sealing layer SE2 on the partition wall 6 between the sub-pixels SP2 and SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, the second cover layer CP3b, and the sealing layer SE3 on the same partition wall 6.

[0066] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 14 (planarization film). The resin layer 14 is covered by a sealing layer 15. Moreover, the sealing layer 15 is covered by a resin layer 16.

[0067] The insulating layer 13 and the resin layers 14 and 16 are formed of an organic material. The rib portion 5, the sealing layer 15, and the SEs (SE1, SE2, and SE3) are formed of an inorganic material such as silicon nitride (SiNx), for example.

[0068] The lower portion 61 of the partition wall 6 has conductivity. The upper portion 62 of the partition wall 6 may also have conductivity similarly. The lower electrode LE may also be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), or may have a laminated structure of a metal material such as silver (Ag) and a conductive oxide. The upper electrode UE may also be formed of a conductive oxide such as ITO.

[0069] When the potential of the lower electrode LE is relatively higher than the potential of the upper electrode UE, the lower electrode LE serves as an anode and the upper electrode UE serves as a cathode. Further, when the potential of the upper electrode UE is relatively higher than the potential of the lower electrode LE, the upper electrode UE serves as an anode and the lower electrode LE serves as a cathode.

[0070] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between these functional layers. As an example, the organic layer OR has a structure in which a hole injection layer, a hole input layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in sequence.

[0071] The cover layer CP (CP1, CP2, and CP3) is formed of a multilayer body of a plurality of transparent thin films, for example. The multilayer body may also include a thin film formed of an inorganic material and a thin film formed of an organic material as the plurality of thin films. Further, these plurality of thin films have different refractive indexes from each other. The material of the thin film constituting the multilayer body is different from the material of the upper electrode UE and is also different from the material of the sealing layer SE. It should be noted that the cover layer CP may be omitted.

[0072] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE (the first upper electrodes UE1a, UE2a, and UE3a) in contact with the side surface of the lower portion 61, respectively. A pixel voltage is supplied to the lower electrodes LE (LE1, LE2, and LE3) through the pixel circuits 1 each included in the sub-pixels SP (SP1, SP2, and SP3).

[0073] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength range.

[0074] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may also emit light of the same color (e.g., white). In this case, the display device DSP may also include a color filter that converts the light emitted from the light-emitting layer into light of colors corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that generate light of colors corresponding to the sub-pixels SP1, SP2, and SP3 when excited by the light emitted from the light-emitting layer.

[0075] Figure 5 is a schematic enlarged cross-sectional view of the partition wall 6. In Figure 5 , elements other than the rib 5, the partition wall 6, the insulating layer 13, and the pair of lower electrodes LE are omitted. The pair of lower electrodes LE corresponds to one of the lower electrodes LE1, LE2, and LE3 described above.

[0076] In Figure 5 In the example shown, the lower portion 61 of the partition wall 6 includes a blocking layer (bottom) 611 disposed on the rib 5 and a metal layer (shaft portion) 612 disposed on the blocking layer 611. The blocking layer 611 is formed of a material different from that of the metal layer 612 and is formed of a metal material such as molybdenum (Mo), titanium (Ti), and titanium nitride (TiN), for example. The metal layer 612 is formed thicker than the blocking layer 611. The metal layer 612 may have a single-layer structure or may be only a stacked structure of metal materials. As an example, the metal layer 612 is formed of aluminum (Al) or an aluminum alloy, for example.

[0077] The upper portion (top) 62 is thinner than the lower portion 61. In Figure 5 In the example shown, the upper portion 62 includes a first layer 621 disposed on the metal layer 612 and a second layer 622 disposed on the first layer 621. As an example, the first layer 621 is formed of titanium (Ti), for example, and the second layer 622 is formed of ITO, for example.

[0078] In Figure 5 In the example shown, the width of the lower portion 61 becomes smaller as it approaches the upper portion 62. That is, the side surfaces 61a and 61b of the lower portion 61 are inclined with respect to the direction Z. It should be noted that the upper portion 62 includes an end portion 62a protruding from the side surface 61a and an end portion 62b protruding from the side surface 61b.

[0079] The protruding amounts D of the end portions 62a and 62b from the side surfaces 61a and 61b (hereinafter, referred to as the protruding amount D of the partition wall 6) are, for example, 2.0 μm or less. The protruding amount D of the partition wall 6 in the present embodiment corresponds to the distance in the width direction (the first direction X or the second direction Y) orthogonal to the third direction Z of the partition wall 6 between the lower ends (the blocking layer 611) of the side surfaces 61a and 61b and the end portions 62a and 62b.

[0080] It should be noted that, in the Figure 5 example shown, the side surface of the blocking layer 611 is aligned with the side surface of the metal layer 612, forming a flat surface without steps. However, for example, the side surface of the blocking layer 611 may also be slightly recessed relative to the side surface of the metal layer 612, or may protrude relative to the side surface of the metal layer 612. Additionally, in Figure 5 , the side surfaces of the blocking layer 611 and the metal layer 612 (that is, the side surfaces 61a and 61b of the lower part 61) are inclined with respect to the third direction Z, but these side surfaces may also be parallel to the third direction Z.

[0081] The structure of the partition wall 6 and the materials of the respective parts of the partition wall 6 can be appropriately selected in consideration of, for example, the method of forming the partition wall 6.

[0082] Here, in the present embodiment, the partition wall 6 is formed to divide the sub-pixels SP in a plan view. The above-mentioned organic layer OR is formed, for example, by an anisotropic or directional vacuum evaporation method. However, when the organic material for forming the organic layer OR is evaporated on the entire substrate 10 in a state where the partition wall 6 is disposed, the partition wall 6 has Figure 4 and Figure 5 such a shape as shown. Therefore, almost no organic layer OR is formed on the side surface of the partition wall 6. Thus, it is possible to form such an organic layer OR (light-emitting element) that is partitioned for each sub-pixel SP by the partition wall 6.

[0083] Figures 6 - 8 is a schematic cross-sectional view for explaining the light-emitting element formed by the partition wall 6. It should be noted that, in Figures 6 - 8 , the substrate 10, the insulating layer 11, and the circuit layer 12 are omitted. Additionally, Figures 6 - 8 the sub-pixels SPα, SPβ, and SPγ shown correspond to one of the sub-pixels SP1, SP2, and SP3.

[0084] First, as described above, in a state where the partition wall 6 is disposed, as Figure 6As shown, an organic layer OR, an upper electrode UE, a cover layer CP, and a sealing layer SE are sequentially formed by vapor deposition over the entire substrate 10. The organic layer OR includes a light-emitting layer that emits light corresponding to the sub-pixel SPα. The organic layer OR is partitioned by a hanging partition wall 6 into a first organic layer Ora that passes through the opening AP and contacts the lower electrode LE, and a second organic layer Orb on the partition wall 6. The upper electrode UE is partitioned into a first upper electrode UEa that covers the first organic layer Ora and a second upper electrode UEb that covers the second organic layer Orb. The cover layer CP is partitioned into a first cover layer CPa that covers the first upper electrode UEa and a second cover layer CPb that covers the second upper electrode UEb. The first upper electrode UEa contacts the lower portion 61 of the partition wall 6. The sealing layer SE continuously covers the first cover layer CPa, the partition wall 6, and the second cover layer CPb.

[0085] Next, as Figure 7 shown, a resist R is formed over the sealing layer SE. The resist R covers the sub-pixel SPα. That is, the resist R is disposed directly above the first organic layer Ora, the first upper electrode UEa, and the first cover layer CPa of the sub-pixel SPα. The resist R is also located directly above the portion of the second organic layer Orb, the second upper electrode UEb, and the second cover layer CPb on the partition wall 6 between the sub-pixel SPα and the sub-pixel SPβ that is closer to the sub-pixel SPα. That is, at least a part of the partition wall 6 is exposed from the resist R.

[0086] Moreover, by etching using the resist R as a mask, as Figure 8 shown, the portions of the organic layer OR, the upper electrode UE, the cover layer CP, and the sealing layer SE that are exposed from the resist R are removed. Thereby, a light-emitting element including the lower electrode LE, the first organic layer Ora, the first upper electrode UEa, and the first cover layer CPa is formed in the sub-pixel SPα. On the other hand, in the sub-pixels SPβ and SPγ, the lower electrode LE is exposed. It should be noted that the above etching includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cover layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0087] As described above, if the light-emitting element of the sub-pixel SPα is formed, the resist R is removed, and in the same manner as the sub-pixel SPα, the light-emitting elements of the sub-pixels SPβ and SPγ are sequentially formed.

[0088] The light-emitting elements of the sub-pixels SP1, SP2, and SP3 are formed as exemplified for the above sub-pixels SPα, SPβ, and SPγ, and further, a resin layer 14, a sealing layer 15, and a resin layer 16 are formed, thereby realizing Figure 4 the structure of the display device DSP shown.

[0089] Here, as described above, each of the plurality of sub-pixels SP includes a pixel circuit that drives a light-emitting element. Hereinafter, with reference to Figure 9 an example of the circuit configuration of the pixel circuit will be described. It should be noted that Figure 9 the pixel circuit 100 shown is a 7Tr1C pixel circuit having seven transistors Tr1 to Tr7 and one holding capacitor Cst.

[0090] In the following description, Figure 9 one of the source and drain terminals of each of the transistors Tr1 to Tr7 shown is set as the first terminal, and the other is set as the second terminal. In addition, Figure 9 one terminal of the holding capacitor Cst (the capacitor element that realizes the holding capacitor Cst) shown is set as the first terminal, and the other terminal is set as the second terminal.

[0091] The first terminal of the transistor Tr1 is connected to the first terminal of the transistor Tr2 and the second terminal of the transistor Tr5 via the node n3. The second terminal of the transistor Tr1 is connected to the data signal line that supplies the data signal Data. The data signal Data corresponds to the signal (pixel signal) written to the pixel. It should be noted that the transistor Tr1 is, for example, an n-channel transistor.

[0092] The transistor Tr2 corresponds to a driving transistor (DRT) that supplies current to the light-emitting element 20 included in the sub-pixel SP (that is, the light-emitting element 20 driven by the pixel circuit 100). The first terminal of the transistor Tr2 is connected to the first terminal of the transistor Tr1 and the second terminal of the transistor Tr5 via the node n3. The second terminal of the transistor Tr2 is connected to the second terminal of the transistor Tr3, the first terminal of the transistor Tr4, and the first terminal of the transistor Tr7 via the node n1. It should be noted that the transistor Tr2 is, for example, an n-channel transistor.

[0093] The first terminal of the transistor Tr3 is connected to the gate terminal of the transistor Tr2 and the second terminal of the holding capacitor Cst via the node n2. The second terminal of the transistor Tr3 is connected to the second terminal of the transistor Tr2, the first terminal of the transistor Tr4, and the first terminal of the transistor Tr7 via the node n1. It should be noted that the transistor Tr3 is, for example, an n-channel transistor.

[0094] The first terminal of the transistor Tr4 is connected to the second terminal of the transistor Tr2, the second terminal of the transistor Tr3, and the first terminal of the transistor Tr7 via the node n1. The second terminal of the transistor Tr4 is connected to the power supply line that supplies the power supply voltage VDDEL. It should be noted that the transistor Tr4 is, for example, a p-channel transistor.

[0095] The first terminal of transistor Tr5 is connected to the first terminal of transistor Tr6, the first terminal of holding capacitor Cst, and the anode terminal of light-emitting element 20 via node n4. The second terminal of transistor Tr5 is connected to the first terminal of transistor Tr1 and the first terminal of transistor Tr2 via node n3. It should be noted that transistor Tr5 is, for example, a p-channel transistor.

[0096] The first terminal of transistor Tr6 is connected to the first terminal of transistor Tr5, the first terminal of holding capacitor Cst, and the anode terminal of light-emitting element 20 via node n4. The second terminal of transistor Tr6 is connected to the power supply line for supplying the initialization voltage Vini. It should be noted that transistor Tr6 is, for example, an n-channel transistor.

[0097] The first terminal of transistor Tr7 is connected to the second terminal of transistor Tr2, the second terminal of transistor Tr3, and the first terminal of transistor Tr4 via node n1. The second terminal of transistor Tr7 is connected to the power supply line for supplying the power supply voltage VSH. It should be noted that transistor Tr7 is, for example, an n-channel transistor.

[0098] In addition, as Figure 9 shown, the gate terminal of transistor Tr1 is connected to the gate signal line for supplying the gate signal Scan2. The gate terminal of transistor Tr3 is connected to the gate signal line for supplying the gate signal Scan1. The gate terminals of transistors Tr4 to Tr6 are connected to the control signal line for supplying the control signal EM. The gate terminal of transistor Tr7 is connected to the gate signal line for supplying the gate signal Scan3.

[0099] The first terminal of holding capacitor Cst is connected to the first terminal of transistor Tr5, the first terminal of transistor Tr6, and the anode terminal of light-emitting element 20 via node n4. The second terminal of holding capacitor Cst is connected to the gate terminal of transistor Tr2 and the first terminal of transistor Tr3 via node n2.

[0100] The anode terminal of light-emitting element 20 is connected to the first terminal of transistor Tr5, the first terminal of transistor Tr6, and the first terminal of holding capacitor Cst via node n4. The cathode terminal of light-emitting element 20 is connected to the power supply line for supplying the power supply voltage VSSEL. The above-mentioned power supply voltage VDDEL corresponds to the anode voltage supplied to light-emitting element 20, and the power supply voltage VSSEL corresponds to the cathode voltage supplied to light-emitting element 20.

[0101] Hereinafter, with reference to Figure 10 , an example of the operation of the pixel circuit 100 (7Tr1C pixel circuit) in the comparative example of the present embodiment will be described. Figure 10It is a timing chart showing output examples of gate signals Scan1 to Scan3 and control signal EM with respect to pixel circuit 100 (including sub-pixel SP of this pixel circuit 100).

[0102] It should be noted that the multiple transistors constituting pixel circuit 100 include n-channel transistors and p-channel transistors. The n-channel transistor is a switching element that becomes an off state (non-conducting state) when a low (level) signal is supplied to the gate terminal, and becomes an on state (conducting state) when a high (level) signal is supplied to the gate terminal. On the other hand, the p-channel transistor is a switching element that becomes an off state (non-conducting state) when a high (level) signal is supplied to the gate terminal, and becomes an on state (conducting state) when a low (level) signal is supplied to the gate terminal.

[0103] During Figure 10 In the shown period t0, the control signal EM is at a low level. Therefore, transistors Tr4 and Tr5 among the seven transistors included in pixel circuit 100 are in an on state, and transistor Tr6 is in an off state.

[0104] In addition, during period t0, the gate signals Scan1 to Scan3 are at a low level. Therefore, transistors Tr1, Tr3, and Tr7 are in an off state.

[0105] Thus, the current controlled by the gate voltage of transistor Tr2 (the voltage supplied to the gate terminal of transistor Tr2 based on the data signal Data of the previous frame) flows to light-emitting element 20 (OLED), maintaining the state where light-emitting element 20 emits light.

[0106] It should be noted that at the timing when period t0 ends, the control signal EM is switched from a low level to a high level.

[0107] Next, Figure 10 The shown period t1 corresponds to a reset period for resetting the voltage written to holding capacitor Cst based on power supply voltage VSH and initialization voltage Vini. During period t1, the control signal EM is at a high level. Therefore, transistors Tr4 and Tr5 are in an off state, and transistor Tr6 is in an on state. In this case, the initialization voltage Vini is supplied to node n4 via transistor Tr6. However, the initialization voltage Vini is set to a value where no current flows through light-emitting element 20. Therefore, no current flows through this light-emitting element 20 during period t1.

[0108] In addition, at the timing when period t1 starts, the gate signal Scan1 is switched from low level to high level. Therefore, within period t1, the transistor Tr3 becomes conductive. Moreover, after period t0 ends and before period t1 starts, the gate signal Scan3 is switched from low level to high level. Therefore, within period t1, the transistor Tr7 is in a conductive state. As a result, a state is formed in which the power supply voltage VSH is supplied to the gate terminal of the transistor Tr2 via the transistor Tr7 and the transistor Tr3. In this case, a voltage of VSH - Vini is applied across the holding capacitor Cst (between the first and second terminals), and the information of the previous frame is reset.

[0109] It should be noted that at the timing when period t1 ends, the gate signal Scan3 is switched from high level to low level.

[0110] Next, Figure 10 The shown period t2 corresponds to a sampling period in which a voltage corresponding to the data signal Data is written to the holding capacitor Cst. At the timing when period t2 starts, the gate signal Scan2 is switched from low level to high level. Therefore, within period t2, the transistor Tr1 becomes conductive. In addition, within period t2, the gate signal Scan3 is at low level, so the transistor Tr7 is in an off state.

[0111] In this case, the data signal Data (the voltage Vdata corresponding to this signal) and the threshold voltage Vth of the second transistor Tr2 (that is, a voltage equivalent to Vdata + Vth) are supplied to the gate terminal of the transistor Tr2 (node n2) via the transistors Tr1 to Tr3. As a result, a voltage of Vdata + Vth - Vini is applied across the holding capacitor Cst, and the information related to Vdata and Vth is written to the holding capacitor Cst (that is, the voltage that controls the current supplied by the control transistor Tr2 to the light-emitting element 20 is written to the holding capacitor Cst).

[0112] It should be noted that at the timing when period t2 ends, the gate signal Scan1 is switched from high level to low level.

[0113] Next, Figure 10 The shown period t3 corresponds to a light-emitting period in which current is supplied to the light-emitting element 20 (that is, the light-emitting element 20 emits light). During period t3, the gate signal Scan1 is at low level, so the transistor Tr3 is in an off state. In addition, before period t3 starts, the gate signal Scan2 is switched from high level to low level, so the transistor Tr1 is in an off state. Moreover, at the timing when period t3 starts, the control signal EM is switched from high level to low level. Therefore, the transistors Tr4 and Tr5 become conductive, and the transistor Tr6 becomes non-conductive.

[0114] Here, if the first terminal of the transistor Tr2 is set as the source terminal, the voltage Vgs between the gate terminal and the source terminal (nodes n2 to n3) of the transistor Tr2 becomes the voltage of the holding capacitor Cst (Vdata + Vth - Vini). In this case, the transistor Tr2 becomes in an on state, and current flows from the power supply line (the power supply line supplying the power supply voltage VDDEL) connected to the second terminal of the transistor Tr4 to the node n4. Accordingly, the potential of the node n4 starts to rise, and when this potential exceeds the threshold value of the light-emitting element 20 (OLED), current starts to flow through this light-emitting element 20, and this light-emitting element 20 starts to emit light. Finally, when the current Ioled flowing through the light-emitting element 20 reaches the output current (the output current in the saturation region of the transistor Tr2) Idrt given by the transistor Tr2, the potential of the node n4 stops rising, and the light-emitting element 20 becomes in a stable light-emitting state.

[0115] It should be noted that when substituting the voltage Vgs = Vdata + Vth - Vini between the gate terminal and the source terminal of the transistor Tr2 into the TFT saturation formula, i.e., Idrt = 1 / 2Cox * μ * W / L * (Vgs - Vth) 2 it becomes Idrt (= Ioled) = 1 / 2Cox * μ * W / L * (Vdata - Vini) 2 . Cox is the gate electrostatic capacitance per unit area, μ is the carrier mobility, W is the channel width of the transistor Tr2, and L is the channel length of the transistor Tr2.

[0116] From this, it can be known that Idrt is a value independent of the threshold voltage Vth of the transistor Tr2 (that is, current independent of the threshold voltage Vth of the transistor Tr2 flows through the light-emitting element 20), and the influence of the deviation of the threshold voltage Vth on Idrt can be eliminated.

[0117] That is, the above pixel circuit 100 (7Tr1C pixel circuit) has a function of correcting the deviation of the threshold voltage Vth of the transistor Tr2 (Vth correction function).

[0118] It should be noted that the display device DSP operates in such a way that frames (images) are sequentially displayed in the display area DA. However, in the comparative example of the present embodiment, during the period of displaying one frame in this display area DA (hereinafter, referred to as one frame period), it includes the above reset period ( Figure 10 the period t1 shown), the sampling period ( Figure 10 the period t2 shown), and the light-emitting period ( Figure 10 the period t3 shown).

[0119] Here, refer to Figure 11, it describes the case where the frame displayed within each one-frame period is an image of black (hereinafter, marked as displaying black). As described above, during the light-emitting period included in one-frame period, current is supplied from the transistor Tr2 to the light-emitting element 20 based on the voltage of the write-hold capacitor Cst. However, during the light-emitting period when displaying black, in order to achieve Figure 11 the shown brightness 201, the voltage Vgs applied to the transistor Tr2 is decreased (that is, the transistor Tr2 is turned off so as not to supply current to the light-emitting element 20). In this case, at the timing when the light-emitting period when displaying black ends, the transistor Tr2 is in a state where carriers are not trapped by defects in the channel region of the semiconductor layer constituting the transistor Tr2 (hereinafter, marked as non-trapping state).

[0120] Next, with reference to Figure 12 , it describes the case where the frame displayed within each one-frame period is an image of white (hereinafter, marked as displaying white). During the light-emitting period when displaying white, in order to achieve Figure 12 the shown brightness 202, the voltage Vgs applied to the transistor Tr2 is increased (that is, the transistor Tr2 is turned on so as to supply current to the light-emitting element 20). In this case, at the timing when the light-emitting period when displaying white ends, the transistor Tr2 is in a state where carriers are trapped by defects in the channel region of the semiconductor layer constituting the transistor Tr2 (hereinafter, marked as trapping state). In this way, the current flowing through the transistor Tr2 in the trapping state is smaller than in the non-trapping state.

[0121] It should be noted that in the above Figure 11 and Figure 12 , the configurations of the reset period, sampling period, and light-emitting period included in one-frame period are schematically shown. "Reset" represents the reset period, and "Samp" represents the sampling period. In addition, Figure 11 the shown "Black" represents the light-emitting period when displaying black, Figure 12 the shown "White" represents the light-emitting period when displaying white. The same applies to the following Figure 13 and Figure 14 .

[0122] Here, with reference to Figure 13 , it describes the case of switching from displaying black to displaying white. In Figure 13 , it is assumed that the frame displayed in the (n - 1)-th one-frame period is an image of black, and the frames displayed in the n-th to (n + 2)-th one-frame periods are images of white.

[0123] First, during the light emission period included in the (n - 1)-th 1-frame period, the transistor Tr2 is in the off state. Therefore, at the timing when the light emission period ends, the transistor Tr2 is in the non-captured state.

[0124] Next, during the reset period and the sampling period included in the n-th 1-frame period, the pixel circuit 100 operates. As a result, a voltage of Vdata + Vth - Vini is written (applied) to the holding capacitor Cst. Thus, during the light emission period included in the n-th 1-frame period, based on the voltage (Vdata + Vth - Vini) written to the holding capacitor Cst, the light emitting element 20 emits light according to the current Idrt (=1 / 2Cox*μ*W / L*(Vdata - Vini)2) supplied from the transistor Tr2.

[0125] It should be noted that during the light emission period included in the n-th 1-frame period, the transistor Tr2 is in the on state. Therefore, at the timing when the light emission period ends, the transistor Tr2 is in the captured state.

[0126] Next, during the reset period and the sampling period included in the (n + 1)-th 1-frame period, when the pixel circuit 100 operates, the transistor Tr2 is in the captured state. Therefore, during this sampling period, the current flowing into the transistor Tr2 becomes smaller than the current flowing into the transistor Tr2 during the sampling period included in the above-mentioned n-th 1-frame period.

[0127] In this case, a voltage equivalent to Vdata + Vth is supplied to the node n2 during the sampling period included in the n-th 1-frame period. In contrast, during the sampling period included in the (n + 1)-th 1-frame period, the potential of the node n2 does not reach Vdata + Vth (that is, Vdata + Vth is not written, and a voltage equivalent to Vdata + Vth + α is supplied to the node n2). As a result, a voltage of Vdata + Vth - Vini + α is written to the holding capacitor Cst, and the voltage written to the holding capacitor Cst during the (n + 1)-th 1-frame period is higher than the voltage written to Cst during the n-th 1-frame period.

[0128] During the light emission period included in the (n + 1)-th 1-frame period, like this, based on the voltage (Vdata + Vth - Vini + α) written to the holding capacitor Cst, the light emitting element 20 emits light according to the current Idrt (=1 / 2Cox*μ*W / L*(Vdata - Vini + α)2) supplied from the transistor Tr2.

[0129] Here, the (n + 1)-th 1-frame period has been described, but the same applies to the (n + 2)-th 1-frame period. Therefore, the detailed description of the (n + 2)-th 1-frame period is omitted.

[0130] In the case of switching from displaying black to displaying white as described above, as Figure 13 shown by the luminance 203, during the nth one-frame period, a luminance display frame (the first frame for displaying white) is achieved by causing the light-emitting element 20 to emit light according to the current Idrt (= 1 / 2Cox * μ * W / L * (Vdata - Vini) 2 ). In contrast, the frames during the one-frame periods after the (n + 1)th one (the second and subsequent frames for displaying white) are displayed with a luminance achieved by causing the light-emitting element 20 to emit light according to the current Idrt (= 1 / 2Cox * μ * W / L * (Vdata - Vini + α) 2 ).

[0131] That is, in the comparative example of the present embodiment described above, the progress of sampling during the sampling period included in the one-frame period for displaying the first frame of white is very fast (that is, a large amount of current flows through the transistor Tr2 during this sampling period). Therefore, the luminance of the first frame for displaying white becomes lower than the luminance of the second and subsequent frames for displaying white, and due to this luminance difference, the display quality of the display device DSP deteriorates.

[0132] Then, in the present embodiment, as Figure 14 shown, a pre-activate period is arranged between the reset period and the sampling period included in each one-frame period. It should be noted that the pre-activate period is a period during which a voltage Vgs is applied to the transistor Tr2 to set it in an on state.

[0133] In the present embodiment, by previously setting the transistor Tr2 in an on state during the above-described pre-activate period, for example, even for the first frame for displaying white, the transistor Tr2 is in a capture state. Therefore, during the sampling period, the current flowing through the transistor Tr2 is at the same level as that for the second and subsequent frames for displaying white. Thus, in the present embodiment, as Figure 14 shown by the luminance 204, the luminance difference between the first frame for displaying white and the second and subsequent frames is reduced, and a decrease in the display quality of the display device DSP can be suppressed.

[0134] Hereinafter, with reference to Figure 15 , an example of the operation of the pixel circuit 100 in the present embodiment will be described. It should be noted that mainly the parts different from the above Figure 10 will be described here.

[0135] As Figure 15 shown, in the present embodiment, a period t4 (pre-activate period) is arranged between the period t1 (reset period) and the period t2 (sampling period).

[0136] At the timing starting at time t4, the gate signal Scan1 switches from a high potential to a low potential. Therefore, within time t4, the transistor Tr3 becomes an off state.

[0137] According to this time t4, by using the gate signal line (transistor Tr3) supplying the gate signal Scan1 and the coupling of the node n1, the voltages of the source terminal and the drain terminal of the transistor Tr2 (node n1 and node n3) can be reduced below the gate voltage.

[0138] Specifically, within time t4, no current flows through the transistor Tr3, but the voltage of the node n1 decreases due to the influence of the coupling of the gate signal line supplying the gate signal Scan1. Thereby, the transistor Tr2 becomes an on state by the voltage Vgd between the gate terminal and the drain terminal of the transistor Tr2, and the voltage of the node n3 decreases. Therefore, compared with the period between time t1 and t2 in the comparative example of the present embodiment, a higher voltage Vgs can be applied to the transistor Tr2.

[0139] In the present embodiment, within time t4 arranged before time t1, the pixel circuit 100 operates as described above, whereby a pre-activation period in which the transistor Tr2 is set to an on state can be realized. According to this pre-activation period, even when the previous frame is a black image, the state (non-capture state) of the transistor Tr2 based on that frame is eliminated, and current equivalent to that after the second frame can flow through the transistor Tr2 at the time point of the first frame displaying white (that is, the brightness drop in the first frame displaying white is suppressed).

[0140] Here, with reference to Figure 16 , a scan circuit and an EM circuit for the gate signals Scan1 to Scan3 and the control signal EM for realizing the comparative example of the present embodiment will be briefly described.

[0141] The scan circuit is a circuit for outputting the gate signals Scan1 to Scan3, and includes a shift register (hereinafter, referred to as a scan circuit shift register) composed of a plurality of registers (circuits). The scan circuit operates in such a manner that the start signal G1VST and the clock signals G1CLK1 to G1CLK3 supplied according to the horizontal period (H) shown in Figure 16 are input to the scan circuit shift register, and thereby the gate signals Scan1 to Scan3 are output from the registers arranged at each stage of the scan circuit shift register. It should be noted that the gate signals Scan1 to Scan3 can be output at the timing when the start signal G1VST and the clock signals G1CLK1 to G1CLK3 input to the scan circuit shift register switch from a low potential to a high potential.

[0142] In addition, the EM circuit is a circuit for outputting a control signal EM, and includes a shift register (hereinafter referred to as the shift register for the EM circuit) composed of a plurality of registers (circuits). The EM circuit operates in such a manner that the start signal E1VST and the clock signal E1CLK supplied in accordance with the Figure 16 shown horizontal period (H) are input to the shift register for the EM circuit, whereby the control signal EM is output from the registers arranged at each stage of the shift register for the EM. It should be noted that the control signal EM can be output at the timing when the start signal E1VST and the clock signal E1CLK1 input to the shift register for the EM circuit are switched from a low potential to a high potential.

[0143] In addition, Figure 17 An example of the configuration of the gate driver including the above-described scan circuit and EM circuit is shown.

[0144] In Figure 17 the example shown, the shift register 301 for the scan circuit is composed of a plurality of registers including registers SR1 to SR4. The registers SR1 to SR4 are respectively connected to the gate signal lines connected to the plurality of sub-pixels SP (pixel circuits 100 included) of each row constituting the display area DA, and the shift register 301 for the scan circuit operates to sequentially output the gate signal Scan3D from the registers SR1 to SR4.

[0145] Specifically, for example, when the gate signal Scan3 is output to the plurality of sub-pixels SP of the m + 1 row constituting the display area DA by the register SR1, after the gate signal Scan3 is output from the register SR1, the register SR2 outputs the gate signal Scan3 to the plurality of sub-pixels SP of the m + 2 row constituting the display area DA. It should be noted that the gate signal Scan3 output from the register SR2 is used as the gate signal Scan1 output to the plurality of sub-pixels SP of the m + 1 row constituting the display area DA.

[0146] Moreover, for example, when the register SR2 outputs the gate signal Scan3 to the plurality of sub-pixels SP of the m + 2 row constituting the display area DA, after the gate signal Scan3 is output from the register SR2, the register SR3 outputs the gate signal Scan3 to the plurality of sub-pixels SP of the m + 3 row constituting the display area DA. It should be noted that the gate signal Scan3 output from the register SR3 is used as the gate signal Scan2 output to the plurality of sub-pixels SP of the m + 1 of the display area DA and the gate signal Scan1 output to the plurality of sub-pixels SP of the m + 2 of the display area DA.

[0147] In addition, inFigure 17 In the example shown, the displacement register 302 for the EM circuit is composed of a plurality of registers including registers ER1 to ER3. The registers ER1 to ER3 are respectively connected to NOT circuits (inverters) 302a, and the NOT circuits 302a are respectively connected to control signal lines, and the control signal lines are connected to a plurality of sub-pixels SP (pixel circuits 100 included) in each row constituting the display area DA. The displacement register 302 for the EM circuit operates in such a manner that control signals EM are sequentially output from the NOT circuits 302a respectively connected to the registers ER1 to ER4.

[0148] According to Figure 17 the configuration of the gate driver shown, gate signals Scan1 to Scan3 and control signal EM can be sequentially output for each row of the display area DA (a plurality of sub-pixels SP constituting the row).

[0149] In addition, in the comparative example of the present embodiment, it was described that based on the Figure 16 start signal VST and clock signals G1CLK1 to G1CLK3, and start signal E1VST and clock signal E1CLK1 shown, gate signals Scan1 to Scan3 and control signal EM are output from the scanning circuit and the EM circuit. In the present embodiment, based on the Figure 18 start signal VST and clock signals G1CLK1 to G1CLK3, and start signal E1VST and clock signal E1CLK1 shown, gate signals Scan1 to Scan3 and control signal EM are output from the scanning circuit and the EM circuit.

[0150] It should be noted that the gate signals Scan1 and Scan2 in the comparative example of the present embodiment are signals formed by timing with the phase of the gate signal Scan3 shifted, and as Figure 15 shown, the gate signals Scan1 and Scan2 in the present embodiment are also set to signals formed by timing with the phase of Scan3 shifted. In addition, the control signal EM in the present embodiment is the same as the control signal EM in the comparative example of the present embodiment.

[0151] Thus, the gate signals Scan1 to Scan3 and the control signal EM in the present embodiment can be realized by the displacement register 301 for the scanning circuit and the displacement register 302 for the EM circuit (that is, a displacement register of one system) in the comparative example of the present embodiment. Therefore, compared with the comparative example of the present embodiment, the width of the peripheral circuit does not increase.

[0152] As described above, the display device DSP of the present embodiment includes: a substrate 10; a plurality of sub-pixels SP in a display area DA disposed on the substrate 10; and data signal lines that supply data signals Data to the plurality of sub-pixels SP respectively. Each of the plurality of sub-pixels SP includes a pixel circuit 100 having a transistor Tr2 (first transistor) and a holding capacitor Cst, and a light-emitting element 20 driven by the pixel circuit 100. The holding capacitor Cst is configured to be written with a voltage for controlling the current supplied to the light-emitting element 20. The transistor Tr2 is configured to supply current to the light-emitting element 20 based on the voltage written to the holding capacitor Cst. A pre-activation period (second period) in which the transistor Tr2 is turned on is provided before a sampling period (first period) in which a voltage corresponding to the data signal Data is written to the holding capacitor Cst during one frame period of displaying one frame (image) in the display area DA.

[0153] In the present embodiment, the above-described configuration can be used to suppress a decrease in the display quality of the display device DSP. Specifically, in the comparative example of the present embodiment, when switching from displaying black to displaying white, the sampling in the first frame of displaying white progresses faster than the sampling after the second frame (that is, the sampling at the time of the first white writing is faster than the other white writings), and thus, the brightness of the first frame decreases. In contrast, in the present embodiment, during the pre-activation period before the sampling period included in one frame period of displaying the first frame of displaying white, the transistor Tr2 is turned on (that is, current is made to flow through the transistor Tr2 in advance to set the transistor Tr2 in a captured state), and thus, during the sampling period, the magnitude of the current flowing through the transistor Tr2 can be made equal to that in the second frame, and therefore, the difference in brightness can be reduced between the first frame of displaying white and the frames after the second frame (that is, the black-and-white response is improved and the decrease in display quality is suppressed).

[0154] In other words, in the comparative example of the present embodiment, in the first frame when switching from displaying black to displaying white, the current flowing through the transistor Tr2 increases, and as a result, the brightness of the first frame decreases. In contrast, in the present embodiment, a pre-activation period is provided before the sampling period within each one frame period, and thus, regardless of whether the previous frame is an image of black or an image of white, the magnitude of the current flowing through the transistor Tr2 (that is, the progress of sampling) can be made equal within the sampling period included in each one frame period.

[0155] Note that, in the present embodiment, the description of one frame period includes a reset period (the fourth period) for resetting the voltage written to the holding capacitor Cst based on the power supply voltage VSH (the first voltage) and the initialization voltage Vini (the second voltage). The pre-activation period is arranged between this reset period and the sampling period. However, for example, the pre-activation period may be arranged between the light emission period (the third period) included in the one frame period before this one frame period and the sampling period included in the one frame period including this pre-activation period (that is, after this light emission period and before this sampling period).

[0156] In addition, the pixel circuit 100 in the present embodiment further includes a transistor Tr3 (the second transistor). The second terminal (one of the source terminal and the drain terminal) of the transistor Tr3 is connected to the second terminal (one of the source terminal and the drain terminal) of the transistor Tr2. The first terminal (the other of the source terminal and the drain terminal) of the transistor Tr3 is connected to the gate terminal of the transistor Tr2 and the second terminal (one terminal) of the holding capacitor Cst. In addition, the power supply voltage VSH is supplied to the second terminal of the holding capacitor Cst, and the initialization voltage Vini is supplied to the first terminal (the other terminal) of the holding capacitor Cst. The transistor Tr3 is in an on state during the reset period and the sampling period, and is in an off state during the pre-activation period. In the present embodiment, according to this configuration, a pre-activation period can be inserted into one frame period.

[0157] (Second Embodiment)

[0158] Next, the second embodiment will be described. In the above first embodiment, it is described that by turning off the transistor Tr3 during the pre-activation period, the voltages of the source terminal and the drain terminal of the transistor Tr2 are reduced to be lower than the gate voltage. However, when the magnitude of Vgs applied during this pre-activation period is insufficient, the degree of improvement in the black and white response may be small.

[0159] Therefore, in the present embodiment, a configuration for further increasing the voltage Vgs applied to the transistor Tr2 during the pre-activation period described in the above first embodiment will be described.

[0160] Figure 19 An example of the circuit configuration of the pixel circuit in the present embodiment is shown. In Figure 19 the same parts as Figure 9 are labeled with the same reference numerals, and the detailed description thereof is omitted. The parts different from Figure 9 will be mainly described.

[0161] In the above-described first embodiment, it was described that the gate terminals of the transistors Tr4 to Tr6 are connected to one control signal line (the control signal line for supplying the control signal EM). However, in the present embodiment, this control signal line is separated. Specifically, as Figure 19 shown, the gate terminal of the transistor Tr4 is connected to the control signal line for supplying the control signal EM1. In addition, the gate terminals of the transistors Tr5 and Tr6 are connected to the control signal line for supplying the control signal EM2.

[0162] Next, with reference to Figure 20 , an example of the operation of the pixel circuit 100 in the present embodiment will be described. It should be noted that mainly the differences from the above Figure 15 will be described here.

[0163] As Figure 20 shown, the control signal EM2 is switched from a low potential to a high potential before the start of the period t1. Therefore, within the period t1, the transistor Tr5 is in the off state and the transistor Tr6 is in the on state. As a result, as described above, a voltage of VSH - Vini is applied to the holding capacitor Cst.

[0164] In addition, the control signal EM2 is switched from a high potential to a low potential after the end of the period t1. Therefore, within the period t4, the transistor Tr5 is in the on state and the transistor Tr6 is in the off state.

[0165] Here, according to the above control signal EM2, from the period t1 to the period t4, the transistors Tr6 and Tr5 are sequentially turned on. Therefore, in the present embodiment, the initialization voltage Vini is supplied to the node n3 during the period t4 via the transistors Tr6 and Tr5. As a result, the voltages of the source terminal and the drain terminal of the transistor Tr2 can be reduced to be lower than the gate voltage by using the initialization voltage Vini supplied to the node n3.

[0166] In the above-described first embodiment, it was described that a voltage Vgs is applied to the transistor Tr2 by the coupling of the gate signal line for supplying the gate signal Scan1 and the node n1. However, in the present embodiment, as described above, the voltage Vgs is applied to the transistor Tr2 by using the initialization voltage Vini. In this way, in the present embodiment, the voltage Vgs applied to the transistor Tr2 becomes larger than the voltage Vgs applied to the transistor Tr2 in the above-described first embodiment.

[0167] It should be noted that the control signal EM1 in the present embodiment is the same as the control signal EM in the present embodiment except that it is only supplied to the transistor Tr4.

[0168] It should be noted that detailed description is omitted, but the scanning circuit in the present embodiment is the same as the scanning circuit in the above-described first embodiment in that it is based onFigure 21 It operates in such a manner that the start signal G1VST and the clock signals G1CLK1 to G1CLK3 shown output the gate signals Scan1 to Scan3.

[0169] On the other hand, the EM circuit in the present embodiment is different from the EM circuit in the first embodiment described above, and operates in such a manner that Figure 21 the start signal E1VST, the clock signals E1CLK1 and E1CLK2 shown output the control signals EM1 and EM2.

[0170] In addition, as Figure 22 shown, the EM circuit in the present embodiment is configured with a shift register 302 to output the control signal EM1 from the NOT circuits 302a respectively connected to the registers ER1 to ER3, and output the control signal EM2 from the NOR circuits 302b connected to each of the registers ER1 to ER3 and connected to the signal line supplying the clock signal E1CLK2.

[0171] That is, in the present embodiment, with respect to the EM circuit (EM circuit with shift register 302) in the first embodiment described above, the control signals EM1 and EM2 can be realized by adding a simple circuit element such as a signal line for supplying a clock signal and a NOR circuit (terminal).

[0172] It should be noted that, as Figure 22 shown, the scan circuit shift register 301 in the present embodiment is the same as the Figure 17 scan circuit shift register 301 shown and does not need to be changed.

[0173] As described above, in the present embodiment, during the pre-activation period, the initialization voltage Vini is supplied to the first terminal of the transistor Tr2.

[0174] It should be noted that, in order to supply the initialization voltage Vini to the first terminal of the transistor Tr2 during the pre-activation period in the present embodiment, the on-state and off-state of the transistor Tr4 (third transistor) disposed between the power supply line supplying the power supply voltage VDDEL (third voltage) and the node n1 are controlled based on the control signal EM1 (first control signal), and the transistor Tr5 (fourth transistor) disposed between the node n3 and the node n4 and the transistor Tr6 (fifth transistor) disposed between the power supply line supplying the initialization voltage Vini and the node n4 are controlled based on the control signal EM2 (second control signal).

[0175] In this case, the transistor Tr4 is controlled to be in the off state during the reset period, the pre-activation period, and the sampling period, and in the on state during the light emission period. The transistor Tr5 is controlled to be in the off state during the reset period and the sampling period, and in the on state during the pre-activation period and the light emission period. The transistor Tr6 is controlled to be in the off state during the pre-activation period and the light emission period and in the on state during the reset period and the sampling period.

[0176] In the present embodiment, according to the above configuration, compared with the configuration of the first embodiment, the voltage Vgs applied to the transistor Tr2 can be increased, and thus, the black-and-white response can be further improved.

[0177] All display devices implemented by those skilled in the art by making appropriate design changes based on the display device described above as an embodiment of the present invention belong to the scope of the present invention as long as they include the gist of the present invention.

[0178] In the scope of the idea of the present invention, various modifications can be conceived by those skilled in the art, and it should be understood that these modifications also belong to the scope of the present invention. For example, modifications obtained by those skilled in the art by appropriately adding, deleting, or changing the design of the constituent elements, or adding, omitting, or changing the conditions of the process with respect to the above embodiments are included in the scope of the present invention as long as they have the gist of the present invention.

[0179] In addition, other effects brought about by the forms described in the above embodiments, which are clearly obtained from the description of this specification or appropriately conceived by those skilled in the art, should of course be understood to be brought about by the present invention.

Claims

1. A display device, characterized in that: have: Base material; A plurality of pixels of a display area arranged on the substrate; and a data signal line for supplying a data signal to each of the plurality of pixels, Each of the plurality of pixels includes a pixel circuit having a first transistor and a holding capacitor, and a light emitting element driven by the pixel circuit. The holding capacitor is configured to have a voltage written therein for controlling a current supplied to the light emitting element. The first transistor is configured to supply a current to the light emitting element based on a voltage written to the holding capacitor. One frame period in which the display region displays one frame includes a second period arranged before a first period in which the first transistor is turned on, and a voltage corresponding to the data signal is written to the holding capacitor during the first period.

2. The display device according to claim 1, characterized in that The one frame period includes a third period arranged after the first period for supplying current to the light emitting element, The second period is arranged between a third period included in a frame period preceding the one frame period including the second period and a first period included in the one frame period including the second period.

3. The display device according to claim 2, characterized in that: Also available: a first power supply line for supplying a first voltage to each of the plurality of pixels; and a second power supply line for supplying a second voltage to each of the plurality of pixels, The one frame period includes a fourth period, and in the fourth period, the voltage written to the holding capacitor is reset based on the first voltage and the second voltage supplied from the first power line and the second power line, The second period is arranged between the fourth period and the first period.

4. The display device according to claim 3, characterized in that The pixel circuit further comprises a second transistor. One of a source terminal and a drain terminal of the second transistor is connected to one of a source terminal and a drain terminal of the first transistor, The other of the source terminal and the drain terminal of the second transistor is connected to the gate terminal of the first transistor and one terminal of the holding capacitor. supplying a first voltage from the first power line to one terminal of the holding capacitor, supplying a second voltage from the second power line to the other terminal of the holding capacitor, The second transistor is in an on state during the fourth period and the first period, and is in an off state during the second period.

5. The display device according to claim 3, characterized in that: During the second period, the second voltage is supplied to one of the source terminal and the drain terminal of the first transistor.

6. The display device according to claim 5, characterized in that: further comprising a third power supply line for supplying a third voltage to each of the plurality of pixels, The pixel circuit includes a third transistor, a fourth transistor and a fifth transistor. One of the source terminal and the drain terminal of the third transistor is connected to the third power line. The other of the source terminal and the drain terminal of the third transistor is connected to one of the source terminal and the drain terminal of the first transistor. One of the source terminal and the drain terminal of the fourth transistor is connected to the other of the source terminal and the drain terminal of the first transistor, The other of the source terminal and the drain terminal of the fourth transistor is connected to the light emitting element and one of the source terminal and the drain terminal of the fifth transistor. One of the source terminal and the drain terminal of the fifth transistor is further connected to the other terminal of the holding capacitor. The other of the source terminal and the drain terminal of the fifth transistor is connected to the second power supply line. The third transistor is in an off state during the fourth period, the second period, and the first period, and is in an on state during the third period. The fourth transistor is in an off state during the fourth period and the first period, and is in an on state during the second period and the third period. The fifth transistor is in an off state during the second period and the third period, and is in an on state during the fourth period and the first period.

7. The display device according to claim 6, characterized in that: Also available: a first control signal line for supplying a first control signal to each of the plurality of pixels; and a second control signal line for supplying a second control signal to each of the plurality of pixels, The off state and the on state of the third transistor are controlled based on the first control signal, The off state and the on state of the fourth transistor and the fifth transistor are controlled based on the second control signal.

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