Memory reading method, memory and electronic equipment

Abstract

The invention provides a memory reading method, a memory and electronic equipment, and the method comprises the steps: determining whether a target storage block is in a writable data state or not after a reading instruction for the target storage block in the memory is detected; if the target storage block is in the writable data state, determining a first reading voltage, and reading the target storage block based on the first reading voltage; if the target storage block is not in the writable data state, a second reading voltage is determined, the target storage block is read based on the second reading voltage, and the first reading voltage is larger than the second reading voltage. According to the method, the situation that the memory block fails to read due to the threshold voltage change of the memory caused by data editing can be avoided, and the reading success rate of the memory is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular, to a memory reading method, a memory, and an electronic device. Background Art

[0002] With the development of technology, the semiconductor industry has been continuously seeking new ways to enable each memory die in a memory device to have a larger number of memory cells. In non-volatile memories, such as NAND memories, one way to increase the memory density is to use a vertical memory array, i.e., a three-dimensional memory, which improves the integration density by arranging the memory cells three-dimensionally on a substrate.

[0003] As the integration level gets higher and higher, three-dimensional memories have evolved from 32 layers to 64 layers, and even higher layer counts. With the increasing number of stacked layers in three-dimensional storage devices, more and more problems regarding their structures and electrical characteristics have emerged. Among them, the Background Pattern Dependency (BPD) effect, hereinafter referred to as the BPD effect, is one of the problems faced after the number of layers increases. The BPD effect means that when pre-programmed memory cells are in the programming verification stage and the read stage, the change in the drain resistance will cause the threshold voltage (Threshold Voltage, Vt) of the three-dimensional memory to change, resulting in a threshold voltage drift phenomenon, such as the Vt Shift phenomenon. The Vt Shift phenomenon will increase the difficulty of reading data, thus affecting the overall storage performance of the three-dimensional memory. Summary of the Invention

[0004] Embodiments of this application disclose a memory reading method, a memory, and an electronic device to reduce the influence of the BPD effect on three-dimensional memories.

[0005] This application provides a memory reading method, the method including: after detecting a read instruction for a target storage block in a memory, determining whether the target storage block is in a data-writable state; if the target storage block is in the data-writable state, determining a first read voltage and reading the target storage block based on the first read voltage; if the target storage block is not in the data-writable state, reading the target storage block based on a preset second read voltage, where the first read voltage is greater than the second read voltage.

[0006] In some alternative embodiments, determining whether the target storage block is in a data-writable state includes: determining the read position corresponding to the read instruction; querying in a first file based on the read position; if there is a corresponding record at the read position in the first file, determining that the target storage block is in a data-writable state; if there is no corresponding record at the read position in the first file, determining that the target storage block is not in a data-writable state.

[0007] In some alternative embodiments, if the target storage block is in the data-writable state, determining a first read voltage includes: if the target storage block is in the data-writable state, determining the programming level of the target storage block, where the programming level is used to represent the degree to which data is written to the target storage block; based on the programming level, determining the first read voltage.

[0008] In some alternative embodiments, based on the programming level, determining the first read voltage includes: querying in a second file to determine a degree value that matches the programming level, and calculating the first read voltage according to the offset read voltage corresponding to the degree value.

[0009] In some alternative embodiments, based on the programming level, determining the first read voltage includes: querying in a third file to determine a target degree range that matches the programming level; calculating the first read voltage according to the offset read voltage corresponding to the target degree range.

[0010] In some alternative embodiments, based on the programming level, determining the first read voltage includes: determining a preset read voltage corresponding to the target storage block; using a first formula, based on the programming level and the preset read voltage, obtaining the first read voltage; the first formula is expressed as: X = A + int(B ÷ C × A); where X represents the first read voltage, A represents the preset read voltage, B represents the programming level, and C represents the target programming level corresponding to the target storage block.

[0011] In some alternative embodiments, before determining whether the target storage block is in a writable data state after detecting a read instruction for the target storage block in the memory, the method further includes: after detecting an edit instruction for the target storage block in the memory, setting the read voltage corresponding to the target storage block in the fifth file to an initial voltage value; updating the read voltage corresponding to the target storage block in the fifth file based on a programming operation on the target storage block; and the step of determining a first read voltage if the target storage block is in the writable data state includes: if the target storage block is in the writable data state, determining the read voltage corresponding to the target storage block in the fifth file as the first read voltage.

[0012] The present application also provides a memory reading method, the method including: after detecting an edit instruction for a target storage block in the memory, setting the read voltage corresponding to the target storage block in a target file to an initial voltage value; determining a first read voltage based on a programming operation on the target storage block, and updating the read voltage corresponding to the target storage block in the target file according to the determined first read voltage; if it is checked that the target storage block is not in a writable data state, updating the read voltage corresponding to the target storage block in the target file based on a second read voltage, where the first read voltage is greater than the second read voltage; and after detecting a read instruction for the target storage block in the memory, reading the target storage block based on the read voltage corresponding to the target storage block in the target file.

[0013] The present application also provides a memory, in which at least one instruction is stored, and when the at least one instruction is executed by a processor, the memory reading method as described above is implemented.

[0014] The present application also provides an electronic device, the electronic device including a processor and the memory as described above.

[0015] In the memory reading method provided by the present application, when receiving a read instruction for a target storage block, the state of the target storage block is verified, and when the target storage block is in a writable data state and not in a writable data state, two different read voltages are respectively used to read the target storage block, avoiding the situation that the storage block reading fails due to the change of the threshold voltage of the memory during editing, and improving the success rate of memory reading. Description of the Drawings

[0016] Figure 1 It is a schematic structural diagram of a three-dimensional memory provided by an embodiment of the present application.

[0017] Figure 2A schematic diagram of the word line P-E state provided by an embodiment of the present application.

[0018] Figure 3 A schematic structural diagram of an electronic device with a 3D memory provided by an embodiment of the present disclosure.

[0019] Figure 4 A flowchart of a memory reading method provided by an embodiment of the present application.

[0020] Figure 5 A schematic diagram of a threshold voltage provided by an embodiment of the present application.

[0021] Figure 6 A schematic diagram of a voltage offset provided by an embodiment of the present application.

[0022] Figure 7 A flowchart of a memory reading method provided by an embodiment of the present application. Detailed implementation manners

[0023] For ease of understanding, some explanations of concepts related to the embodiments of the present application are exemplarily given for reference.

[0024] It should be noted that "at least one" in the present application means one or more, and "a plurality" means two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims, and drawings of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0025] When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0026] Figure 1 A schematic structural diagram of a 3D memory provided by an embodiment of the present application. As Figure 1As shown, the 3D memory 10 includes a memory array 11 and a control circuit 12. The control circuit 12 is configured to perform read, write, erase, and verify operations on the memory array 11, and the control circuit 12 may include a word line driver, a bit line driver, a column decoder, a sensing circuit, a data buffer, program verification logic, and erase verification circuitry. The memory array 11 is divided into a plurality of memory blocks, and the plurality of memory blocks (Block) are denoted as BLOCK1 to BLOCKI, where I is a positive integer. Each memory block contains a set of NAND strings (i.e., memory cell strings) 13 accessed via bit lines BL1 to BLM and a common set of word lines WL1 to WLN, where M and N are integers greater than 1. One terminal of the NAND string 13 is connected to the corresponding bit line via a top select transistor (connected to the top select gate line SGTL), and the other terminal is connected to the common source line (CSL) via a bottom select transistor (connected to the bottom select gate line SGBL). The memory block is the unit of a conventional erase operation, and the page is the unit of a conventional programming operation. However, other erase / programming units may also be used. It should be understood that the above examples are provided for illustrative purposes, and the NAND flash memory device to which the technical solution of the present invention is applicable is not limited to the above examples. Similarly, the NAND may additionally or alternatively include other features or include fewer features without departing from the scope of the present application.

[0027] Once a memory block (Block) in the 3D memory starts programming, it will be in an open state until it is fully programmed, and the programmed memory block is in a closed state (Close Block). For a memory block (OpenBlock) in a writable data state, when a programming operation is performed on the selected word line WLn, the word line WLn is in a writable data state P, and the word lines WLn+1 and above are in an erased state E; so the data combination in the programmed word line WLn and the corresponding upper word line WLn+1 will be presented as Figure 2 the P-E state shown in, at this time there is a very large threshold voltage difference between adjacent cells located on these two word lines, which will cause very serious charge lateral migration, resulting in a significant increase in the series resistance of the memory cells corresponding to the word lines WLn+1 and above in the Open Block during reading, thereby causing a change in the threshold voltage Vt of the Open Block during reading, resulting in a Vt Shift phenomenon, and further possibly causing a failure to read the Open Block, thereby causing an increase in the failure bit count (FBC, Fail bit count).

[0028] In view of the above problems, the following embodiments of the present invention propose a memory reading method. When receiving a read instruction for a target storage block, this control method verifies the state of the target storage block, and when the target storage block is in a writable data state and not in a writable data state, two different read voltages are respectively used to read the target storage block, avoiding the situation of failed Open Block reading caused by the change of the threshold voltage of the memory during editing, and improving the success rate of memory reading.

[0029] To better understand the memory reading method, electronic device, and storage medium provided in the embodiments of the present application, the memory reading method of the present application will be described below with reference to the accompanying drawings.

[0030] Figure 3 FIG. is a schematic structural diagram of an electronic device having a three-dimensional memory provided by an embodiment of the present disclosure. The electronic device 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a three-dimensional memory. As Figure 3 shown in FIG., the electronic device 10 may include a processor 101 and a memory system 102.

[0031] The processor 101 may be a central processing unit (CPU), and may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The processor 101 is the operation core and control center of the electronic device 10, connecting various parts of the entire electronic device 10 through various interfaces and lines, and executing the operating system of the electronic device 10 and various installed application programs, program codes, etc.

[0032] The memory system 102 has one or more memories 1021 and a memory controller 1022. The memory controller 1022 is used to control the operations of the memory 1021, such as read, erase, and program operations. The memory controller 1022 can also be used to manage various functions regarding the data stored in or to be stored in the memory 1021, including but not limited to functions such as bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. The processor 101 can send data to the memory 1021 or receive data from the memory 1021.

[0033] The memory 1021 can be any three-dimensional memory in the present disclosure. For example, it can be a non-volatile memory device. The non-volatile memory device can be a NAND flash memory, such as a three-dimensional NAND flash memory, etc. The memory 1021 can be used to store computer-readable instructions and / or modules. The processor 101 runs or executes the computer-readable instructions and / or modules stored in the memory 1021 to call the data stored in the memory 1021 or store data into the memory 1021, thereby implementing various functions of the electronic device 10. The memory 1021 mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system, application programs required for at least one function (such as a sound playback function, an image playback function, etc.); the data storage area can store data created according to the use of the electronic device 10. The memory 1021 can include non-volatile and volatile memories, such as: hard disk, memory, plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, at least one magnetic disk storage device, flash memory device, or other storage devices. In an embodiment of the present application, the memory 1021 can be an external memory and / or an internal memory of the electronic device 10. Further, the memory 1021 can be a memory in physical form, such as a memory stick, a TF card (Trans-flash Card), etc.

[0034] In some embodiments of the present application, the memory controller 1022 may be coupled to the memory 1021 or the processor 101 to control the memory 1021. The memory controller 1022 may manage the data stored in the memory 1021 and communicate with the processor 101. In some embodiments, the memory controller 1022 is configured to execute the programming method provided in the embodiments of the present disclosure to directly control the memory 1021 to implement the memory reading method proposed in the embodiments of the present application. In other embodiments, the processor 101 is configured to execute the programming method provided in the embodiments of the present disclosure. The processor 101 may indirectly control the memory 1021 through the memory controller 1022 to implement the memory reading method proposed in the embodiments of the present application.

[0035] In some embodiments, the memory controller 1022 is used to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. Alternatively, the memory controller 1022 is used to operate in a high duty cycle environment such as a Solid State Drive (SSD) or an Embedded Multimedia Card (eMMC), where the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0036] In some embodiments, the memory controller 1022 is further configured to process an Error Correction Code (ECC) for data read from or written to the memory 1021. The memory controller 1022 may also perform any other suitable functions, such as formatting the memory 1021. The memory controller 1022 may communicate with external devices (e.g., the processor 101) according to a specific communication protocol. For example, the memory controller 1022 may communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0037] In an embodiment of the present application, the memory controller 1022 and one or more memories 1021 may be integrated into various types of storage devices, for example, included in the same package, such as Universal Flash Storage, UF package, eMMC package, etc. That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0038] Exemplarily, the computer-readable instructions may be divided into one or more modules / sub-modules / units. One or more modules / sub-modules / units are stored in the memory 1021 and executed by the processor 101 to complete this application. One or more modules / sub-modules / units may be a series of computer-readable instruction segments capable of performing specific functions, and the computer-readable instruction segments are used to describe the execution process of the computer-readable instructions in the electronic device 10.

[0039] If the modules / units integrated in the electronic device 10 are implemented in the form of software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium. Based on such an understanding, to implement all or part of the processes in the above-described embodiment methods of this application, it may also be completed by computer-readable instructions to instruct relevant hardware. The computer-readable instructions may be stored in a computer-readable storage medium. When the computer-readable instructions are executed by the processor, the steps of the above various method embodiments may be implemented.

[0040] Among them, the computer-readable instructions include computer-readable instruction codes, and the computer-readable instruction codes may be in the form of source code, object code, executable files, or some intermediate forms, etc. The computer-readable medium may include: any entity or device capable of carrying the computer-readable instruction code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory). The I / O interface 1004 is used to provide a channel for user input or output. For example, the I / O interface 1004 may be used to connect various input / output devices, such as a mouse, keyboard, touch device, display screen, etc., so that the user can input information or visualize the information. The memory controller 1022 may also be configured to manage various functions regarding the data stored in or to be stored in the memory 1021, including but not limited to bad block management, garbage collection, logical-to-physical address conversion, wear leveling, etc.

[0041] Those skilled in the art can understand that the schematic diagram is only an example of the electronic device 10, and does not constitute a limitation on the electronic device 10. It may include more or fewer components than shown, or combine some components, or different components. For example, the electronic device 10 may further include, but is not limited to, a communication module, an input / output (I / O) interface. The communication module may include a wired communication module and / or a wireless communication module. The wired communication module may provide one or more of the solutions for wired communication such as Universal Serial Bus (USB), Controller Area Network (CAN), etc. The wireless communication module may provide one or more of the solutions for wireless communication such as Wireless Fidelity (Wi-Fi), Bluetooth (BT), mobile communication network, Frequency Modulation (FM), near field communication (NFC), Infrared (IR) technology, etc.

[0042] Figure 4 is a flowchart of a memory reading method provided by an embodiment of the present application. This memory reading method is applied to an electronic device or a memory. For example, as Figure 3 shown in the electronic device 10 or the memory 1021. According to different requirements, the order of the steps in this flowchart can be changed, and some steps can be omitted.

[0043] Step S401, after detecting a read instruction for a target storage block in the memory, determine whether the target storage block is in a writable data state.

[0044] The target storage block can be any storage block in the memory. The read instruction is used to read the data in the target storage block. The writable data state means that the storage block can continue to write data. When the target storage block is in the writable data state, the target storage block is an Open Block; when the target storage block is not in the writable data state, that is, the non-writable data state, the target storage block is a close Block. When the word line editing in the target storage block is completed, the target storage block will change from the writable data state to the non-writable data state. In an embodiment of the present application, when a target storage block is in the writable data state, if no new data is written to the target storage block within a preset time duration, the target storage block is set to the non-writable data state, and the target storage block cannot continue to write new data.

[0045] In an embodiment of the present application, determining whether the target storage block is in a data-writable state includes: determining the read position corresponding to the read instruction; querying in the fourth file and the first file based on the read position; if there is a corresponding record in the first file at the read position, determining that the target storage block is in a data-writable state; if there is no corresponding record in the first file at the read position, determining that the target storage block is not in a data-writable state.

[0046] The read instruction includes the read position corresponding to the target storage block. The first file is used to record storage blocks in a data-writable state. In an embodiment of the present application, when an electronic device or a memory controller detects that a storage block is in a data-writable state, it adds a module record corresponding to the storage block to the first file. In an embodiment of the present application, the first file can be presented in the form of a table. For example, the first file can be as shown in Table 1, and the module record corresponding to each storage block may include the read position corresponding to the storage block, such as WL8Str4.

[0047] Table 1

[0048] Index Block Open Location 0 218 WL8Str4 1 100 WL10Str0 2 3 WL0Str3 … … …

[0049] Step S402, if the target storage block is in the data-writable state, determine a first read voltage and read the target storage block based on the first read voltage.

[0050] In an embodiment of the present application, the step of, if the target storage block is in the data-writable state, determining a first read voltage includes: if the target storage block is in the data-writable state, determining the programming degree of the target storage block; and determining the first read voltage based on the programming degree.

[0051] The programming degree is used to represent the degree to which data is written into the storage block. The higher the programming degree of the storage block, the more data is written into the storage block. A storage block is composed of multiple word lines WL. When programming the storage block, programming starts from the first layer of word lines and goes up. For example, after programming the first layer of word lines, the second layer of word lines is programmed, and so on. A programming degree of 10% means that 10% of the word lines in the programmed storage block; a programming degree of 50% means that 50% of the word lines in the programmed storage block. Different programming degrees correspond to different read voltages. The smaller the programming degree of a storage block in a data-writable state, the greater the degree to which the threshold voltage corresponding to the storage block is shifted to the left relative to the threshold voltage when the storage block is in the off state. Figure 5Schematic diagram of a threshold voltage provided by an embodiment of the present application. In the figure, the threshold voltages of a storage block in three states are shown. Among them, Open@10% means that the storage block is in a data-writable state and the programming degree is 10% of the word line WL; Open@50% means that the storage block is in a data-writable state and the programming degree is 50% of the word line WL; close Block means that the storage block is in a closed state. For example, a storage block includes 200 layers of WL. Open@10% means that the first 20 layers in the storage block are programmed, and Open@50% means that the first 100 layers in the storage block are programmed. As Figure 5 shown, the threshold voltage of the storage block in the Open@50% state is shifted to the left compared to the storage block in the close Block state; the threshold voltage of the storage block in the Open@10% state is shifted to the left compared to the storage block in the Open@50% state. In an embodiment of the present application, when the target storage block is in a data-writable state, the higher its programming degree, the smaller its corresponding read voltage. For example, the read voltage of the storage block in the Open@50% state is less than the read voltage of the storage block in the Open@10% state.

[0052] In an embodiment of the present application, the offset read voltages corresponding to different programming degrees of the storage block can be preset, and a degree voltage mapping table can be generated based on the mapping relationship between the programming degree and the read voltage. The offset read voltage is used to calculate the error voltage value of the threshold voltage corresponding to the current programming degree, so that the first read voltage corresponding to the programming degree can be calculated based on the calculated error voltage value and the preset read voltage. In an embodiment of the present application, the degree voltage mapping table with different finenesses can be set according to the user's needs. For example, the calculated error voltage value and the preset read voltage of the memory can be added to obtain the first read voltage corresponding to the current programming degree. In an embodiment of the present application, based on the preset offset (offset) and offset read voltage of the memory, the error voltage value of the threshold voltage corresponding to the current programming degree can be calculated. For example, assuming that the offset of the memory is 0.01V, the offset read voltage corresponding to the current programming degree is -9V, and the preset read voltage of the memory is -1.2V, multiplying 0.01V by -9V gives the error voltage value of the threshold voltage corresponding to the current programming degree as -0.09V. Adding the preset read voltage of the memory to the error voltage value, the first read voltage corresponding to the current programming degree is -1.29V.

[0053] For example, a second file can be generated according to the offset read voltage corresponding to each word line. The second file can include the offset read voltage corresponding to each word line in the storage block. In some embodiments of the present application, the second file can be presented in the form of a table, as shown in Table 2.

[0054] Table 2

[0055] WL Vrd1 Vrd2 Vrd3 Vrd4 Vrd5 Vrd6 Vrd7 0 -12 -12 -12 -12 -12 -12 -12 1 -12 -12 -12 -12 -12 -12 -12 … … … … … … … … 32 -9 -9 -9 -9 -9 -9 -9 … … … … … … … …

[0056] For another example, a third file can be generated by reading voltages corresponding to the offset of each word line group. Each word line group can include multiple word lines, and the number of word lines corresponding to the word line group can be set according to the user's needs, such as 10, 20, 30, etc. Different word line groups can correspond to different numbers of word lines, and the third file can include the offset read voltages corresponding to each word line group in the storage block. In some embodiments of the present application, the third file can be presented in the form of a table, as shown in Table 3.

[0057] Table 3

[0058] WL Vrd1 Vrd2 Vrd3 Vrd4 Vrd5 Vrd6 Vrd7 0-31 -12 -12 -12 -12 -12 -12 -12 32-63 -9 -9 -9 -9 -9 -9 -9 64-95 -6 -6 -6 -6 -6 -6 -6 96-127 -3 -3 -3 -3 -3 -3 -3 128 0 0 0 0 0 0 0

[0059] In an embodiment of the present application, determining the first read voltage based on the programming level includes: querying in the first file to determine a level value matching the programming level, and calculating the first read voltage corresponding to the programming level based on the offset read voltage corresponding to the level value. The error voltage value corresponding to the programming level can be calculated based on the offset of the memory and the offset read voltage corresponding to the programming level. Based on the preset read voltage of the memory and the error voltage value corresponding to the programming level, the first read voltage corresponding to the programming level is obtained. For some specific embodiments of calculating the first read voltage, reference can be made to the relevant descriptions above and will not be elaborated here. As shown in Table 2, if the target storage block is in a data-writable state and the programming level of the target storage block is an unprogrammed word line, the offset read voltage of the target storage block is determined to be -12V; for another example, if the target storage block is in a data-writable state and the programming level of the target storage block is programmed to the 32nd word line, the offset read voltage of the target storage block is determined to be -9V.

[0060] In another embodiment of the present application, determining the first read voltage based on the programming level includes: querying in a second file to determine a target level range that matches the programming level; calculating the first read voltage according to the offset read voltage corresponding to the target level range. As shown in Table 2, if the target storage block is in a data-writable state and the programming level of the target storage block is an unprogrammed word line, the determined target level range that matches the programming level is: 0 - 31, and according to this range of 0 - 31, the offset read voltage of this target storage block is determined to be -12V; for another example, if the target storage block is in a data-writable state and the programming level of the target storage block is programmed to the 70th word line, the determined target level range that matches the programming level is: 64 - 95, and according to this range of 64 - 95, the offset read voltage of this target storage block is determined to be -6V; for another example, if the target storage block is in a data-writable state and the programming level of the target storage block is programmed to the 150th word line, the determined target level range that matches the programming level is: 128, and according to this range of 128, the offset read voltage of this target storage block is determined to be 0V.

[0061] In still another embodiment of the present application, determining the first read voltage based on the programming level includes: determining a preset read voltage corresponding to the target storage block; substituting the programming level and the preset read voltage into a first formula for calculation to obtain the first read voltage;

[0062] The first formula is expressed as:

[0063] X = A + int(B ÷ C × A)

[0064] Wherein, X represents the first read voltage, A represents the preset read voltage, B represents the programming level, and C represents the target programming level corresponding to the target storage block. int represents taking the integer of the calculated value.

[0065] The preset read voltage is the read voltage when the storage block is in the close Block state and is set in advance. The preset read voltage can be set according to user requirements. In one embodiment of the present application, the preset read voltage can be a value set by the manufacturer of the memory, or a value determined according to the gear changes provided by the manufacturer of the memory according to PE changes, or a value optimized online based on Firmware, and no further limitation is made here. In one embodiment of the present application, the preset read voltage can be the second read voltage mentioned in the present application and is used to read the storage block in the closed state.

[0066] The target programming level corresponding to the target storage block refers to the programming level when the target storage block is completely programmed. The target programming level corresponding to the target storage block can be determined according to the number of word lines of the target storage block. For example, if the number of word lines of the target storage block is 200, the determined target programming level corresponding to the target storage block is 200. It can be understood that the programming level and the target programming level are in the same unit. For example, when the programming level is in terms of word lines, the target programming level is also in terms of word lines. For example, when the programming level is 20 word lines, the target programming level is 200 word lines; when the programming level is a ratio, the target programming level is also a ratio. For example, when the programming level is 10%, the target programming level is 1.

[0067] Figure 6 This is a schematic diagram of voltage offset provided by an embodiment of the present application. As Figure 6 shown, there is an approximately linear relationship between the programming level and the degree of voltage offset. Therefore, based on the first formula and the preset read voltage, the read voltage corresponding to the current programming level of the target storage block can be determined. In an embodiment, based on integer arithmetic, for every 10 WL increase in the programming level, the read voltage increases by 1V.

[0068] Step S403, if the target storage block is not in the writable data state, determine a second read voltage, and read the target storage block based on the second read voltage.

[0069] Among them, the first read voltage is greater than the second read voltage. In an embodiment of the present application, the situation where the target storage block is not in the writable data state includes: the target storage block is in the close Block state or the ClosePartial Block state. Among them, the Close Partial Block state means that not all the word lines in the storage block are programmed, but before the storage block is erased, no more valid data will be written into it.

[0070] The second read voltage is the preset read voltage of the storage block, which can include the read voltage when the storage block is in the closeBlock state set in advance. In an embodiment of the present application, the same second read voltage can be set for all storage blocks in the memory. In some embodiments of the present application, for some storage products with high performance requirements, such as enterprise-level SSDs, a corresponding second read voltage can be set for each storage block in the memory to generate a fourth file. Different storage blocks can correspond to different storage voltages. The fourth file includes the module identifier corresponding to each storage block, such as the module number. The fourth file includes the second voltage corresponding to each storage block in the memory. In some embodiments of the present application, the fourth file can be presented in the form of a table. For example, as shown in Table 4.

[0071] Table 4

[0072] LUN Block Vrd1 Vrd2 Vrd3 Vrd4 Vrd5 Vrd6 Vrd7 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 … … … … … … … … …

[0073] In some embodiments of the present application, when it is determined that the target storage block is not in the writable data state, determining a second read voltage includes: if the target storage block is not in the writable data state, determining the module identifier corresponding to the target storage block; querying in a fourth file based on the module identifier, determining the target read voltage corresponding to the module identifier, and determining the target read voltage corresponding to the module identifier as the second read voltage.

[0074] In some embodiments of the present application, when the target storage block triggers an IVS (Initial Vt Shift, its early Vt Shift) Retry, the corresponding retry gear can be determined according to the programming degree of the target storage block.

[0075] In order to determine the speed of the first read voltage when the target storage block is in the writable data state, in an embodiment of the present application, before determining whether the target storage block is in the writable data state after detecting a read instruction for the target storage block in the memory, the method further includes: after detecting an edit instruction for the target storage block in the memory, setting the read voltage corresponding to the target storage block in a fifth file to an initial voltage value; and updating the read voltage corresponding to the target storage block in the fifth file based on the programming operation on the target storage block.

[0076] The fifth file is used to store the read voltage corresponding to the target storage block. The fifth file can be a pre-set table. For example, as shown in Table 5, the fifth file may include multiple word line groups corresponding to the target storage block and the read voltage corresponding to each word line group. A word line group can correspond to one or more word lines, which can be set according to the actual situation.

[0077] Table 5

[0078]

[0079]

[0080] In an embodiment of the present application, after detecting an opening instruction for a target storage block in the memory, when it is determined that the target storage block is in the close Block state, the read voltage corresponding to the target storage block in the fifth file is set to the initial voltage value. The edit instruction is used to edit the target storage block. After receiving the edit instruction, the target storage block will enter the edit state, that is, change from the close Block state to the OpenBlock state. The initial voltage value can be the value obtained by adding the read voltage of the target storage block at WL0 to the read voltage of the target storage block when it is in the close Block state. The read voltage of the target storage block at WL0 can be confirmed according to the second file or the third file. The initial voltage value can also be the value obtained by adding the preset read voltage corresponding to the target storage block in the first formula to the read voltage of the target storage block when it is in the close Block state.

[0081] In an embodiment of the present application, based on the programming operation on the target storage block, the read voltage corresponding to the target storage block in the fifth file is updated. For example, after programming a word line in the target storage block is completed, the read voltage corresponding to the target storage block in the fifth file can be updated. Based on the programming operation on the target storage block, the programming degree of the target storage block can be determined; based on the programming degree, the target read voltage of the target storage block can be determined; and the read voltage corresponding to the target storage block in the fifth file is set to the target read voltage. In an embodiment of the present application, the read voltage corresponding to the target storage block in the fifth file can be updated based on the second file, the third file, or the first formula.

[0082] In an embodiment of the present application, a time limit for allowing the target storage block to be opened can be set. If the time limit is reached, the read voltage corresponding to the target storage block in the fifth file is updated according to the current programming degree of the target storage block.

[0083] In an embodiment of the present application, determining the first read voltage when the target storage block is in the writable data state includes: when the target storage block is in the writable data state, determining the read voltage corresponding to the target storage block in the fifth file as the first read voltage. The read voltage corresponding to the target storage block can be determined in the fifth file according to the programming degree of the target storage block. In this embodiment, during the programming process of the target storage block, the update of the read voltage of the target storage block in the fifth file is completed, so that when a read instruction for the target storage block is received, the read voltage corresponding to the target storage block can be directly retrieved from the fifth file, reducing the read delay of the target storage block and improving the read efficiency.

[0084] The method provided in the above embodiments verifies the state of the target storage block when receiving a read instruction for the target storage block, and when the target storage block is in a writable data state and not in a writable data state, two different read voltages are respectively used to read the target storage block, avoiding the situation of failed Open Block reading caused by the change of the threshold voltage of the memory during editing, and improving the success rate of memory reading.

[0085] Figure 7 It is a flowchart of a memory reading method provided by an embodiment of the present application. This memory reading method is applied to an electronic device or a memory controller. For example, as Figure 3 shown in the electronic device 10 or the memory controller 1022. According to different requirements, the order of the steps in this flowchart can be changed, and some steps can be omitted.

[0086] Step S701, after detecting an edit instruction for the target storage block in the memory, set the read voltage corresponding to the target storage block in the target file to the initial voltage value.

[0087] The target file is used to store the read voltage corresponding to the target storage block. The read voltage in the target file can be updated according to the programming situation of the target storage block. The initial voltage value can be the value obtained by adding the read voltage of the target storage block at WL0 and the read voltage when the target storage block is in the close Block state. The target file is equivalent to the fifth file in the above text. For some specific descriptions of the target file, reference can be made to the relevant descriptions in the above text. The relevant descriptions of the initial voltage value can also be referred to the relevant descriptions in the above text.

[0088] Step S702, based on the programming operation on the target storage block, determine the first read voltage, and update the read voltage corresponding to the target storage block in the target file according to the determined first read voltage.

[0089] The first read voltage is the read voltage corresponding to the current programming degree of the target storage block. The current programming degree of the target storage block can be determined based on the programming operation on the target storage block. Some specific implementation manners for determining the first read voltage can be referred to the relevant descriptions in the above text, such as the relevant descriptions of the method for determining the first read voltage based on the second file, the third file, and the first formula in the above text.

[0090] Step S703, if it is detected that the target storage block is not in a writable data state, update the read voltage corresponding to the target storage block in the target file based on the second read voltage.

[0091] Among them, the first read voltage is greater than the second read voltage. The second read voltage is the read voltage when the storage block is in the close Block state, which is set in advance. The second read voltage can be set according to the user's needs. In an embodiment of the present application, the second read voltage can be a value set by the manufacturer of the memory, or a value determined according to the gear changing based on the PE provided by the manufacturer of the memory, or a value optimized online based on the Firmware. There is no further limitation here.

[0092] Step S704: After detecting a read instruction for the target storage block in the memory, read the target storage block based on the read voltage corresponding to the target storage block in the target file.

[0093] In an embodiment of the present application, query the read voltage corresponding to the current editing degree of the target storage block in the target file, and read the target storage block based on the determined read voltage. For example, when the target storage block is in a state where data can be written, the first read voltage can be used to read the target storage block; when the target storage block is not in a state where data can be written, the second read voltage can be used to read the target storage block.

[0094] The method provided in the above embodiment can read the target storage block with two different read voltages when the target storage block is in a state where data can be written and not in a state where data can be written, avoiding the situation that the Open Block read fails due to the change of the threshold voltage of the memory during editing, and improving the success rate of memory reading. At the same time, the read voltage of the target storage block in the target file is updated during the programming process of the target storage block, so that when a read instruction for the target storage block is received, the read voltage corresponding to the target storage block can be directly retrieved from the target file, reducing the read latency of the target storage block and improving the read efficiency.

[0095] In several embodiments provided by the present application, it should be understood that the disclosed system, device, and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules is only a logical function division, and there can be other division methods in actual implementation.

[0096] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they can be located in one place, or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0097] In addition, in each embodiment of the present application, each functional module can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware, or in the form of a combination of hardware and software functional modules.

[0098] Therefore, from any perspective, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present application is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed within the present application. Any reference signs in the claims should not be construed as limiting the claims involved.

[0099] In addition, it is obvious that the term "including" does not exclude other units or steps, and the singular does not exclude the plural. A plurality of units or devices can also be implemented by one unit or device through software or hardware. The terms "first", "second", etc. are used to denote names and do not denote any particular order.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and not to limit them. Although the present application has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present application can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A memory reading method, characterized in that, The method includes: After detecting a read instruction for a target storage block in the memory, determining whether the target storage block is in a data-writable state; If the target storage block is in the data-writable state, determining a first read voltage and reading the target storage block based on the first read voltage; If the target storage block is not in the data-writable state, reading the target storage block based on a preset second read voltage, where the first read voltage is greater than the second read voltage.

2. The memory reading method according to claim 1, characterized in that, The determining whether the target storage block is in the data-writable state includes: Determining a read position corresponding to the read instruction; Querying in a first file based on the read position; If there is a corresponding record for the read position in the first file, determining that the target storage block is in the data-writable state; if there is no corresponding record for the read position in the first file, determining that the target storage block is not in the data-writable state.

3. The memory reading method according to claim 1, characterized in that, The if the target storage block is in the data-writable state, determining the first read voltage includes: If the target storage block is in the data-writable state, determining a programming degree of the target storage block, where the programming degree is used to represent the degree of data writing of the target storage block; Based on the programming degree, determining the first read voltage.

4. The memory reading method according to claim 3, characterized in that, The based on the programming degree, determining the first read voltage includes: Querying in a second file, determining a degree value matching the programming degree, and calculating the first read voltage according to an offset read voltage corresponding to the degree value.

5. The memory reading method according to claim 3, characterized in that, The based on the programming degree, determining the first read voltage includes: Querying in a third file, determining a target degree interval matching the programming degree; calculating the first read voltage according to an offset read voltage corresponding to the target degree interval.

6. The memory reading method according to claim 3, characterized in that, The based on the programming degree, determining the first read voltage includes: Determining a preset read voltage corresponding to the target storage block; Using a first formula, obtaining the first read voltage based on the programming degree and the preset read voltage; The first formula is expressed as: X = A + int(B ÷ C × A) Where X represents the first read voltage, A represents the preset read voltage, B represents the programming degree, and C represents a target programming degree corresponding to the target storage block.

7. The memory reading method according to claim 1, characterized in that, Before determining whether the target storage block is in the data-writable state after detecting a read instruction for the target storage block in the memory, the method further includes: After detecting an edit instruction for the target storage block in the memory, setting the read voltage corresponding to the target storage block in a fifth file to an initial voltage value; Based on a programming operation on the target storage block, updating the read voltage corresponding to the target storage block in the fifth file; The if the target storage block is in the data-writable state, determining the first read voltage includes: If the target storage block is in the data-writable state, determining the read voltage corresponding to the target storage block in the fifth file as the first read voltage.

8. A memory reading method, characterized in that, The method includes: After detecting an edit instruction for a target storage block in the memory, setting the read voltage corresponding to the target storage block in the target file to an initial voltage value; Based on a programming operation on the target storage block, determining a first read voltage, and updating the read voltage corresponding to the target storage block in the target file according to the determined first read voltage; If it is checked that the target storage block is not in a state where data can be written, based on a second read voltage, updating the read voltage corresponding to the target storage block in the target file, where the first read voltage is greater than the second read voltage; After detecting a read instruction for the target storage block in the memory, reading the target storage block based on the read voltage corresponding to the target storage block in the target file.

9. A memory, characterized in that, At least one instruction is stored in the memory, and when the at least one instruction is executed by a processor, the memory reading method described in any one of claims 1 to 8 is implemented.

10. An electronic device, characterized in that, The electronic device includes a processor and the memory described in claim 9.

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