Magnetic random access memory and operation method thereof

Abstract

The invention relates to the field of memories, and discloses a magnetic random access memory and an operation method thereof.The operation method comprises the steps that when a peripheral control logic circuit obtains an erasing instruction and an erasing address, the peripheral control logic circuit generates a mark signal and sets the mark signal as a first target value; the read-write circuit writes data corresponding to the erasure address in the flag bit array into a first target value according to the erasure instruction; when the peripheral control logic circuit obtains the programming instruction, the programming page address and the programming data, the peripheral control logic circuit generates a mark signal and sets the mark signal as a second target value according to the programming instruction; the read-write circuit writes data corresponding to the programming page address in the flag bit array into a second target value; the read-write circuit writes the programming data into a region corresponding to the programming page address in the storage array according to the programming instruction; write clocks of the storage array and the zone bit array are clock signals output by the oscillator so as to be compatible with a Nor Flash erasing instruction and a programming instruction.

Description

Technical Field

[0001] This application relates to the field of memories, and particularly to a magnetic random access memory and an operation method thereof. Background Art

[0002] When a Nor Flash (NOR-type flash memory) performs a programming operation, the host will pull up the chip select signal CS#, and no longer provide a clock. Once CS# is set high, the Nor Flash will start a self-timed internal programming cycle; when the Nor Flash performs an erase operation, the host will pull up the chip select signal CS#, and no longer provide a clock. Once CS# is set high, the Nor Flash will start a self-timed internal erase cycle. When an MRAM (Magnetic Random Access Memory) performs a write operation and a programming operation, the chip select signal CS# of the chip is always pulled low to enable, and an external clock is continuously provided. When the host no longer needs to write, the host will pull up the chip select signal CS# and no longer provide a clock, and the MRAM is in a standby state.

[0003] Since the timings of the MRAM and the Nor Flash during programming and erase operations are different, when the MRAM is used to replace the Nor Flash, it is impossible to achieve compatibility with erase instructions and programming instructions.

[0004] Therefore, how to solve the above technical problems should be the focus of attention of those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a magnetic random access memory and an operation method thereof, so that the magnetic random access memory can be used to replace the Nor Flash and be compatible with erase instructions and programming instructions.

[0006] To solve the above technical problems, this application provides a magnetic random access memory operation method, including:

[0007] When the peripheral control logic circuit obtains an erase instruction and an erase address, the peripheral control logic circuit generates a flag signal and sets the flag signal to a first target value;

[0008] The read / write circuit writes the data corresponding to the erase address in the flag bit array as the first target value according to the erase instruction;

[0009] When the peripheral control logic circuit obtains a programming instruction, a programming page address, and programming data, the peripheral control logic circuit generates a flag signal and sets the flag signal to a second target value according to the programming instruction;

[0010] The read / write circuit writes the data corresponding to the programming page address in the flag bit array as the second target value;

[0011] The read / write circuit writes the programming data into the area corresponding to the programming page address in the storage array according to the programming instruction;

[0012] Wherein, the write clocks of the storage array and the flag bit array are the clock signals output by the oscillator in the magnetic random access memory.

[0013] Optionally, before the read / write circuit writes the programming data into the area corresponding to the programming page address in the storage array according to the programming instruction, it further includes:

[0014] The peripheral control logic circuit determines whether the size of the programming data is equal to a preset target byte;

[0015] If the size of the programming data is less than the preset target byte, the peripheral control logic circuit supplements the size of the programming data to the preset target byte to obtain new programming data;

[0016] Correspondingly, the read / write circuit writes the programming data into the area corresponding to the programming page address in the storage array according to the programming instruction, including:

[0017] The read / write circuit writes the new programming data into the area corresponding to the programming page address in the storage array according to the programming instruction.

[0018] Optionally, the peripheral control logic circuit supplements the size of the programming data to the preset target byte, including:

[0019] The peripheral control logic circuit supplements the size of the programming data to the preset target byte by using the first target value.

[0020] Optionally, before the storage array writes the programming data into the area corresponding to the programming page address, it further includes:

[0021] The peripheral control logic circuit caches the programming data into a register.

[0022] Optionally, before the peripheral control logic circuit generates a flag signal and sets the flag signal to a first target value, it further includes:

[0023] The peripheral control logic circuit identifies the received erase operation instruction to obtain an erase instruction and an erase address set;

[0024] The peripheral control logic circuit extracts the erase address from the erase address set.

[0025] Optionally, before the peripheral control logic circuit generates a flag signal and sets the flag signal to a second target value according to the programming instruction,

[0026] The peripheral control logic circuit identifies the received programming operation instruction to obtain a programming instruction, a programming page address, and programming data.

[0027] Optionally, it further includes:

[0028] The peripheral control logic circuit receives a read operation instruction; the read operation instruction includes a read instruction and a read address;

[0029] The read-write circuit reads the value of the flag signal of the flag bit array corresponding to the target page address according to the read instruction and the read address; the target page address corresponds to the read address;

[0030] The read-write circuit outputs corresponding data information according to the value of the flag signal.

[0031] Optionally, the read-write circuit outputs corresponding data information according to the value of the flag signal, including:

[0032] The read-write circuit determines whether the value of the flag signal is the second target value;

[0033] If the value of the flag signal is not the second target value, the first target value is output;

[0034] If the value of the flag signal is the second target value, the data corresponding to the read address in the storage array is read and the data is output.

[0035] Optionally, when the flag bit array includes a voting circuit and at least three differential arrays, and the number of differential arrays is odd, before reading the value of the flag signal of the flag bit array corresponding to the target page address, it further includes:

[0036] Each of the differential arrays outputs the value of the flag signal to the voting circuit;

[0037] The voting circuit outputs the value of the flag signal with the largest number.

[0038] This application also provides a magnetic random access memory, including: an oscillator, a peripheral control logic circuit, a storage array, a flag bit array, and a read-write circuit;

[0039] Wherein, the oscillator is used to generate a clock signal as the write clock of the storage array and the flag bit array;

[0040] The peripheral control logic circuit is used to generate a flag signal and set the flag signal to a first target value when an erase instruction and an erase address are obtained; and to generate a flag signal and set the flag signal to a second target value according to the programming instruction when a programming instruction, a programming page address, and programming data are obtained;

[0041] The read / write circuit is used to write the data corresponding to the erase address in the flag bit array as the first target value; to write the data corresponding to the programming page address in the flag bit array as the second target value; and to write the programming data into the area corresponding to the programming page address in the storage array.

[0042] A method for operating a magnetic random access memory provided by the present application includes: when the peripheral control logic circuit obtains an erase instruction and an erase address, the peripheral control logic circuit generates a flag signal and sets the flag signal to a first target value; the read / write circuit writes the data corresponding to the erase address in the flag bit array as the first target value according to the erase instruction; when the peripheral control logic circuit obtains a programming instruction, a programming page address, and programming data, the peripheral control logic circuit generates a flag signal and sets the flag signal to a second target value according to the programming instruction; the read / write circuit writes the data corresponding to the programming page address in the flag bit array as the second target value; the read / write circuit writes the programming data into the area corresponding to the programming page address in the storage array according to the programming instruction; wherein, the write clock of the storage array and the flag bit array is the clock signal output by the oscillator in the magnetic random access memory.

[0043] It can be seen that in the operation method of the present application, the clock signal output by the internal oscillator of the magnetic random access memory is used as the write clock of the storage array and the flag bit array. During the erase operation, the read / write circuit writes the first target value into the flag bit array corresponding to the erase address and does not operate on the storage array; during the programming operation, the read / write circuit writes the second target value into the flag bit array corresponding to the programming page address and writes the programming data into the storage array, thereby solving the problem that the magnetic random access memory cannot be compatible with Nor Flash erase instructions and programming instructions. In addition, when executing the erase instruction, only the flag bit array is operated on, and the storage array does not need to be operated on, so that the time required for erasure is shorter than that of Nor Flash, and the power consumption during erasure is smaller than that of Nor Flash.

[0044] In addition, the present application also provides a magnetic random access memory having the above advantages. Description of the Drawings

[0045] To more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0046] Figure 1 Flowchart of a method for operating a magnetic random access memory provided by an embodiment of the present application Figure 1 ;

[0047] Figure 2 Flowchart of a method for operating a magnetic random access memory provided by an embodiment of the present application Figure 2 ;

[0048] Figure 3 Flowchart of a read operation of a magnetic random access memory provided by an embodiment of the present application;

[0049] Figure 4 Schematic structural diagram of a flag bit array provided by an embodiment of the present application;

[0050] Figure 5 Flowchart of a method for operating a magnetic random access memory provided by an embodiment of the present application Figure 3 ;

[0051] Figure 6 Schematic diagram of a magnetic random access memory provided by an embodiment of the present application;

[0052] Figure 7 Schematic diagram of the operation process of an erase operation of a magnetic random access memory provided by an embodiment of the present application;

[0053] Figure 8 Schematic diagram of the operation process of a programming operation of a magnetic random access memory provided by an embodiment of the present application;

[0054] Figure 9 Schematic diagram of the operation process of a read operation of a magnetic random access memory provided by an embodiment of the present application. Detailed implementation manners

[0055] To enable those skilled in the art to better understand the solution of the present application, the following will further elaborate on the present application in conjunction with the accompanying drawings and specific implementation manners. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0056] In the following description, many specific details are set forth to provide a thorough understanding of the present invention. However, the present invention may be practiced in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the spirit of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0057] The writing of data to Nor Flash is completed by the cooperation of an erase instruction and a programming instruction. The erase instruction can change all the data in the specified address area to "1", and the programming instruction can change the data in the specified address area from "1" to "0".

[0058] As described in the background art section, since the timing of the programming and erasing operations of MRAM and Nor Flash is different, when MRAM is used to replace Nor Flash, it is impossible to achieve compatibility with the erase instruction and the programming instruction.

[0059] In view of this, the present application provides a method for operating a magnetic random access memory. Please refer to Figure 1 , which includes:

[0060] Step S101: When the peripheral control logic circuit receives an erase instruction and an erase address, the peripheral control logic circuit generates a flag signal and sets the flag signal to a first target value.

[0061] The first target value of the flag signal (flag signal) can be "1".

[0062] As an implementable manner, before the peripheral control logic circuit generates a flag signal and sets the flag signal to a first target value, it may further include:

[0063] The peripheral control logic circuit identifies the received erase operation instruction to obtain an erase instruction and an erase address set;

[0064] The peripheral control logic circuit extracts the erase address from the erase address set.

[0065] The erase operation instruction includes an erase instruction, an erase address set, and erase data. After identification, the erase instruction, the erase address set, and the erase data can be obtained respectively, and the erase instruction and the erase address set are given to the peripheral control logic circuit.

[0066] The erase address set includes multiple erase addresses. The erase address is a part of the erase address set. Erasing is generally performed by block or sector. The data size of each sector can be 4KB.

[0067] The address of each 1 bit of the flag bit array is 1 page address. The page address is the address of one page of data, and each page of data can be 256 Byte (bytes).

[0068] Step S102: The read / write circuit writes the data corresponding to the erasure address in the flag bit array as the first target value according to the erasure instruction.

[0069] Step S103: When the peripheral control logic circuit receives a programming instruction, a programming page address, and programming data, the peripheral control logic circuit generates a flag signal and sets the flag signal to a second target value according to the programming instruction.

[0070] The second target value of the flag signal (flag signal) can be "0".

[0071] As an implementable manner, before the peripheral control logic circuit generates a flag signal and sets the flag signal to a second target value according to the programming instruction, it further includes:

[0072] The peripheral control logic circuit identifies the received programming operation instruction to obtain a programming instruction, a programming page address, and programming data.

[0073] The programming operation instruction includes a programming instruction, a programming page address, and programming data. After identification, the programming instruction, the programming page address, and the programming data can be obtained.

[0074] Step S104: The read / write circuit writes the data corresponding to the programming page address in the flag bit array as the second target value.

[0075] Step S105: The read / write circuit writes the programming data into the area corresponding to the programming page address in the storage array according to the programming instruction;

[0076] Wherein, the write clocks of the storage array and the flag bit array are the clock signals output by the oscillator in the magnetic random access memory.

[0077] The clock signal output by the oscillator is first transmitted to the peripheral control logic circuit, and then the peripheral control logic circuit outputs the received clock signal to the read / write circuit, the storage array, and the flag bit array.

[0078] In the traditional technology, the oscillator generates a clock signal, which is generally used to read the clock signal of the EFUSE during the power-on process. In this application, the clock signal generated by the oscillator is not only used to read the clock signal of the EFUSE, but also used as the clock signal for the write operations of the storage array and the flag bit array.

[0079] Wherein, the data bit width of each address of the flag bit array is 1 bit (bit), and the capacity of the flag bit array is the number of pages of the storage array.

[0080] As an implementable manner, before the storage array writes the programming data into the area corresponding to the programming page address, it may further include:

[0081] The peripheral control logic circuit caches the programming data into a register, that is, temporarily stores the programming data in the register.

[0082] In the operation method of this embodiment, the clock signal output by the internal oscillator of the magnetic random access memory is used as the write clock for the storage array and the flag bit array. During the erase operation, the read / write circuit writes the first target value into the flag bit array corresponding to the erase address and does not operate on the storage array; during the programming operation, the read / write circuit writes the second target value into the flag bit array corresponding to the programming page address and writes the programming data into the storage array, thereby solving the problem that the magnetic random access memory cannot be compatible with the erase instruction and the programming instruction of Nor Flash. In addition, when executing the erase instruction, only the flag bit array is operated on, and the storage array does not need to be operated on, so that the time required for erasure is shorter than that of Nor Flash, and the power consumption during erasure is smaller than that of Nor Flash.

[0083] The reason why it is not necessary to erase the data to be erased in this application is that the writing mechanism of MRAM itself can write from "1" to "0" and from "0" to "1", and there is no need to first erase (write "1") and then program (write "0"). Therefore, it is possible to judge whether it is an erase instruction by judging the flag bit, and there is no need to erase the storage area. However, Nor Flash must be erased before the programming operation, which is determined by the physical structure and writing mechanism of the Nor Flash storage unit. The storage unit of NorFlash can only change from "1" to "0" and cannot change from "0" to "1", so it is necessary to first erase (set all to "1") and then program (write "0").

[0084] Please refer to Figure 2 , on the basis of the above embodiment, in an embodiment of the present application, the operation method of the magnetic random access memory includes:

[0085] Step S201: When the peripheral control logic circuit receives an erase instruction and an erase address, the peripheral control logic circuit generates a flag signal and sets the flag signal to a first target value.

[0086] Step S202: The read / write circuit writes the data corresponding to the erase address in the flag bit array as the first target value according to the erase instruction.

[0087] Step S203: When the peripheral control logic circuit receives a programming instruction, a programming page address, and programming data, the peripheral control logic circuit generates a flag signal and sets the flag signal to a second target value according to the programming instruction.

[0088] Step S204: The read / write circuit writes the data corresponding to the programming page address in the flag bit array as the second target value.

[0089] Step S205: The peripheral control logic circuit determines whether the size of the programming data is equal to a preset target byte.

[0090] In this embodiment, the size of the preset target byte is not specifically limited and depends on the situation. For example, the size of the preset target byte can be 256 Bytes.

[0091] Step S206: If the size of the programming data is less than the preset target byte, the peripheral control logic circuit supplements the size of the programming data to the preset target byte to obtain new programming data.

[0092] When the programming data data in is less than the preset target byte, the programming data data in is supplemented to the preset target byte to fill the page of the programming page address.

[0093] As an implementable manner, the peripheral control logic circuit supplementing the size of the programming data to the preset target byte includes:

[0094] The peripheral control logic circuit supplements the size of the programming data to the preset target byte by using the first target value.

[0095] When the first target value is "1", the programming data is supplemented by using the first target value, that is, the programming data is supplemented with 'hff.

[0096] Step S207: The read / write circuit writes the new programming data into the area corresponding to the programming page address in the storage array according to the programming instruction.

[0097] Step S208: If the size of the programming data is equal to the preset target byte, the read / write circuit writes the programming data into the area corresponding to the programming page address in the storage array according to the programming instruction;

[0098] Wherein, the write clocks of the storage array and the flag bit array are the clock signals output by the oscillator in the magnetic random access memory.

[0099] It can be understood that when the size of the programming data data in is already the preset target byte, there is no need to supplement it, and the read / write circuit can directly write the programming data into the storage array.

[0100] During the erasure operation of the present application, the storage array is not actually erased (writing "1"). During programming, if the data of one page is less than the preset target bytes, then the bits that are not written may be data "0"; while in fact, the erased areas are all "1". During programming, when the data of one page is less than the preset target bytes, the bits that are not written are all "1". Therefore, filling the insufficient byte data with all "1" can avoid the risk of data reading errors.

[0101] Please refer to Figure 3 Based on any of the above embodiments, in an embodiment of the present application, the magnetic random access memory operation method further includes:

[0102] Step S301: The peripheral control logic circuit receives a read operation instruction; the read operation instruction includes a read instruction and a read address.

[0103] Step S302: The read-write circuit reads the value of the flag signal of the flag bit array corresponding to the target page address according to the read instruction and the read address; the target page address corresponds to the read address.

[0104] The value of the flag signal is output by the flag bit array and read by the read-write circuit.

[0105] In order to ensure the accuracy of the value of the flag signal output by the flag bit array, as an implementable manner, the flag bit array can be in the form of a differential array and a voting circuit. For example, the flag bit array includes a voting circuit and at least three differential arrays, and the number of differential arrays is odd. Correspondingly, before reading the value of the flag signal of the flag bit array corresponding to the target page address, it further includes:

[0106] Each of the differential arrays outputs the value of the flag signal to the voting circuit;

[0107] The voting circuit outputs the value of the flag signal with the largest number.

[0108] Each differential array will output the value of a flag bit signal (the first target value or the second target value) to the voting circuit. Since the number of differential arrays is odd, the number of the first target values and the second target values received by the voting circuit must be unequal, and finally the value with a larger proportion is output.

[0109] Taking the number of differential arrays as three as an example, the value of the flag signal finally output by the flag bit array is shown in Table 1. In the table, Flag out0, Flag out1, and Flag out2 respectively represent the values of the flag bit signals output by the three differential arrays, and Flag out is the value of the flag signal finally output by the voting circuit.

[0110] Table 1 Output truth table of the output data of the flag bit array

[0111]

[0112]

[0113] When the number of differential arrays is three, that is, the flag bit array adopts a triple modular redundancy design, a schematic diagram of the value of the flag signal output by the flag bit array is as Figure 4 shown.

[0114] Step S303: The read / write circuit outputs corresponding data information according to the value of the flag signal.

[0115] The value of the flag signal Flag out is the first target value or the second target value.

[0116] As an implementable manner, the read / write circuit outputs corresponding data information according to the value of the flag signal, including:

[0117] Step S3031: The read / write circuit determines whether the value of the flag signal is the second target value.

[0118] Step S3032: If the value of the flag signal is not the second target value, output the first target value.

[0119] Step S3033: If the value of the flag signal is the second target value, read the data corresponding to the read address in the storage array and output the data.

[0120] When the value of the flag signal is not the second target value, that is, the value of the flag signal is the first target value, it indicates that the target page address is the area that has only been erased, and all "first target values" ("1") are output; when the value of the flag signal is the second target value, it indicates that the target page address is the area that has been programmed, and the data read out from the storage array Data out is output.

[0121] Next, in combination with Figure 5 a specific situation is used to introduce the operation method of the magnetic random access memory.

[0122] After power-on, the chip is initialized and enters the standby mode. After receiving an operation instruction, it determines whether the operation instruction is an erase operation instruction. If it is an erase operation instruction, it identifies the erase instruction and the erase address from the erase operation instruction, sets the flag signal to "1", and writes "1" to the area to be erased (the area corresponding to the erase address) in the flag bit array; if it is not an erase operation instruction, it determines whether it is a programming operation instruction. If it is a programming operation instruction, it identifies the programming instruction, the programming page address, and the programming data from the programming operation instruction, performs a write operation on the storage array area corresponding to the page to be programmed. If the written data is less than 256 bytes, it fills up to 256 bytes with 'hff, then sets the flag signal to "0", and then writes "0" to the flag bit array corresponding to the page to be programmed; if it is not a programming operation instruction, it determines whether it is a read instruction. If it is a read instruction, it reads out the data data out corresponding to the read address in the storage array, and at the same time reads out the data Flag out of the flag bit array corresponding to the page of the read address, and determines whether Flag out is equal to "0". If it is equal to "0", it outputs the data Data out. If it is not equal to "0", it outputs all "1"; if it is not a read instruction, it continues to enter the standby mode.

[0123] The present application also provides a magnetic random access memory. Please refer to Figures 6 to 9 , including: an oscillator 2, a peripheral control logic circuit 1, a storage array 3, a flag bit array 4, and a read / write circuit 5;

[0124] Among them, the oscillator 2 is used to generate a clock signal as the write clock for the storage array 3 and the flag bit array 4;

[0125] The peripheral control logic circuit 1 is used to generate a flag signal and set the flag signal to a first target value when an erase instruction and an erase address are obtained; and generate a flag signal and set the flag signal to a second target value according to the programming instruction when a programming instruction, a programming page address, and programming data are obtained;

[0126] The read / write circuit 5 is used to write the data corresponding to the erase address in the flag bit array 4 as the first target value; write the data corresponding to the programming page address in the flag bit array 4 as the second target value; and write the programming data into the area corresponding to the programming page address in the storage array 3.

[0127] It should be noted that the magnetic random access memory also includes input / output electrodes (I / OPADs) 7 and a selector 6 (mux), and various operation instructions are transmitted to the peripheral control logic circuit 1 through the input / output electrodes.

[0128] The oscillator 2 (abbreviated as OSC) generates a clock signal CLK for the peripheral control logic circuit 1, and the peripheral control logic circuit 1 then supplies the clock signal generated by the oscillator 2 to the read / write circuit 5, the memory array 3, and the flag bit array 4.

[0129] The peripheral control logic circuit 1 transmits a flag signal set to a first target value to the selector 6 (mux), and then the selector 6 outputs a signal flag_int = "first target value" to the read / write circuit 5. The read / write circuit 5 then determines that an erase operation needs to be performed and writes the data corresponding to the erase address in the flag bit array 4 as the first target value.

[0130] The peripheral control logic circuit 1 transmits a flag signal set to a second target value to the selector 6 (mux), and then the selector 6 outputs a signal flag_int = "second target value" to the read / write circuit 5. The read / write circuit 5 then determines that a programming operation needs to be performed and writes the data corresponding to the programming page address in the flag bit array 4 as the second target value.

[0131] When an erase operation is performed, the operation process in the magnetic random access memory is as Figure 7 shown by the dashed line therein, where the erase address is denoted as A0; when a programming operation is performed, the operation process in the magnetic random access memory is as Figure 8 shown by the dashed line therein, where the programming page address is denoted as A1; when a read operation is performed, the operation process in the magnetic random access memory is as Figure 9 shown by the dashed line therein, where the read page address is denoted as A2.

[0132] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts between the various embodiments, reference can be made to each other.

[0133] The above has introduced in detail the magnetic random access memory and its operation method provided in this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for operating a magnetic random access memory, characterized in that, Including: When the peripheral control logic circuit receives an erase instruction and an erase address, the peripheral control logic circuit generates a flag signal and sets the flag signal to a first target value; The read / write circuit writes the data in the flag bit array corresponding to the erase address as the first target value according to the erase instruction; When the peripheral control logic circuit receives a programming instruction, a programming page address, and programming data, the peripheral control logic circuit generates a flag signal and sets the flag signal to a second target value according to the programming instruction; The read / write circuit writes the data in the flag bit array corresponding to the programming page address as the second target value; The read / write circuit writes the programming data into the area corresponding to the programming page address in the storage array according to the programming instruction; Wherein, the write clocks of the storage array and the flag bit array are the clock signals output by the oscillator in the magnetic random access memory.

2. The method for operating a magnetic random access memory according to claim 1, characterized in that, Before the read / write circuit writes the programming data into the area corresponding to the programming page address in the storage array according to the programming instruction, it further includes: The peripheral control logic circuit determines whether the size of the programming data is equal to a preset target byte; If the size of the programming data is less than the preset target byte, the peripheral control logic circuit supplements the size of the programming data to the preset target byte to obtain new programming data; Correspondingly, the read / write circuit writing the programming data into the area corresponding to the programming page address in the storage array according to the programming instruction includes: The read / write circuit writes the new programming data into the area corresponding to the programming page address in the storage array according to the programming instruction.

3. The method for operating a magnetic random access memory according to claim 2, characterized in that, The peripheral control logic circuit supplementing the size of the programming data to the preset target byte includes: The peripheral control logic circuit supplements the size of the programming data to the preset target byte by using the first target value.

4. The method for operating a magnetic random access memory according to claim 1, characterized in that, Before the storage array writes the programming data into the area corresponding to the programming page address, it further includes: The peripheral control logic circuit caches the programming data into a register.

5. The method for operating a magnetic random access memory according to claim 1, characterized in that, Before the peripheral control logic circuit generates a flag signal and sets the flag signal to a first target value, it further includes: The peripheral control logic circuit identifies the received erase operation instruction to obtain an erase instruction and an erase address set; The peripheral control logic circuit extracts the erase address from the erase address set.

6. The method for operating a magnetic random access memory according to claim 1, characterized in that, Before the peripheral control logic circuit generates a flag signal and sets the flag signal to a second target value according to the programming instruction, it further includes: The peripheral control logic circuit identifies the received programming operation instruction to obtain a programming instruction, a programming page address, and programming data.

7. The method for operating a magnetic random access memory according to any one of claims 1 to 6, characterized in that, It further includes: The peripheral control logic circuit receives a read operation instruction; the read operation instruction includes a read instruction and a read address; The read / write circuit reads the value of the flag signal of the flag bit array corresponding to the target page address according to the read instruction and the read address; the target page address corresponds to the read address; The read / write circuit outputs corresponding data information according to the value of the flag signal.

8. The method for operating a magnetic random access memory according to claim 7, characterized in that, The read / write circuit outputting corresponding data information according to the value of the flag signal includes: The read-write circuit determines whether the value of the flag signal is the second target value; If the value of the flag signal is not the second target value, the first target value is output; If the value of the flag signal is the second target value, the data corresponding to the read address in the storage array is read and the data is output.

9. The method for operating a magnetic random access memory according to claim 7, wherein, When the flag bit array includes a voting circuit and at least three differential arrays, and the number of differential arrays is odd, before reading the value of the flag signal of the flag bit array corresponding to the target page address, it further includes: Each of the differential arrays outputs the value of the flag signal to the voting circuit; The voting circuit outputs the value of the flag signal with the largest number.

10. A magnetic random access memory, wherein, It includes: An oscillator, a peripheral control logic circuit, a storage array, a flag bit array, and a read-write circuit; Wherein, the oscillator is used to generate a clock signal as the write clock of the storage array and the flag bit array; The peripheral control logic circuit is used to generate a flag signal and set the flag signal to the first target value when an erase instruction and an erase address are obtained; and generate a flag signal and set the flag signal to the second target value according to the programming instruction when a programming instruction, a programming page address, and programming data are obtained; The read-write circuit is used to write the data corresponding to the erase address in the flag bit array as the first target value; write the data corresponding to the programming page address in the flag bit array as the second target value; and write the programming data into the area corresponding to the programming page address in the storage array.

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