Package architecture with die comprising a vertical stack of high capacity memory for

Abstract

An embodiment of an integrated circuit (IC) package includes: at least two first IC dies having a first surface, an opposing second surface, and including memory circuitry, where the first IC dies are stacked and coupled at respective first and second surfaces, a redistribution layer (RDL) between respective ones of the first IC dies, the RDL including a conductive path; a second IC die having a first surface, an opposing second surface, a third surface orthogonal to the first and second surfaces, and a conductive trace parallel to the first and second surfaces, the first surface of the second IC die being electrically coupled to the conductive path in the RDL; and a third IC die, wherein the second surface of the bottom die of the stack of first IC dies and the third surface of the second IC die are electrically coupled to the third IC die.

Description

Background Art

[0001] Electronic circuits are typically fabricated on wafers of semiconductor material (e.g., silicon) and are referred to as integrated circuits (ICs). Wafers with such ICs are typically diced into many individual die. The die can be packaged into an IC package that contains one or more die and other electronic components (e.g., resistors, capacitors, and inductors). The IC package can be integrated into an electronic system (e.g., a consumer electronics system) or a server (e.g., a mainframe). Brief Description of the Drawings

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For the sake of description, like reference numerals denote like structural elements. In the figures of the drawings, the embodiments are shown by way of example and not by way of limitation

[0003] Figure 1A-1C is a schematic cross-sectional view of an example IC die in accordance with some embodiments of the present disclosure.

[0004] Figure 2A is in accordance with some embodiments of the present disclosure Figure 1A schematic perspective view of an example IC die.

[0005] Figure 2B is in accordance with some embodiments of the present disclosure Figure 1B schematic perspective view of an example IC die.

[0006] Figure 2C is in accordance with some embodiments of the present disclosure Figure 1C schematic perspective view of an example IC die.

[0007] Figure 3A is a schematic cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0008] Figure 3B is Figure 3A schematic cross-sectional view of a portion of an example microelectronic component.

[0009] Figure 3C is in accordance with some embodiments of the present disclosure Figure 3A schematic cross-sectional view of a portion of an example microelectronic component.

[0010] Figure 3D is in accordance with some embodiments of the present disclosure Figure 3A schematic cross-sectional view of a portion of an example microelectronic component.

[0011] Figure 3E is a schematic cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0012] Figure 4 is a schematic perspective view of an example microelectronic component including an example IC die in accordance with some embodiments of the present disclosure. Figure 2A

[0013] Figure 5A is a schematic perspective view of an example IC package in accordance with some embodiments of the present disclosure.

[0014] Figure 5B is a schematic cross - sectional view of an example IC package in accordance with some embodiments of the present disclosure.

[0015] Figure 6A is a schematic perspective view of an example IC package in accordance with some embodiments of the present disclosure.

[0016] Figure 6B is a schematic cross - sectional view of an example IC package in accordance with some embodiments of the present disclosure.

[0017] Figure 6C is a schematic perspective view of an example IC package in accordance with some embodiments of the present disclosure.

[0018] Figure 6D is a schematic cross - sectional view of an example IC package in accordance with some embodiments of the present disclosure.

[0019] Figure 6E is a schematic perspective view of another example IC package in accordance with some embodiments of the present disclosure.

[0020] Figure 7A is a schematic perspective view of an example IC package in accordance with some embodiments of the present disclosure.

[0021] Figure 7B is a schematic cross - sectional view of an example IC package in accordance with some embodiments of the present disclosure.

[0022] Figure 8A is a schematic perspective view of an example IC package in accordance with some embodiments of the present disclosure.

[0023] Figure 8B is a schematic cross - sectional view of an example IC package in accordance with some embodiments of the present disclosure.

[0024] Figure 9 is a cross - sectional view of a device package including one or more microelectronic components in accordance with any of the embodiments disclosed herein.

[0025] Figure 10 is a cross - sectional side view of a device component including one or more microelectronic components in accordance with any of the embodiments disclosed herein.

[0026] Figure 11 ​is a block diagram of an example computing device that includes one or more microelectronic components according to any of the embodiments disclosed herein. Detailed Description

[0027] Overview

[0028] To illustrate the IC packages described herein, it is important to understand the phenomena that may occur during the assembly and packaging of an IC. The following basic information can be considered as a basis on which the present disclosure can be correctly interpreted. Such information is provided for illustrative purposes only and should not be construed in any way as limiting the broad scope of the present disclosure and its potential applications.

[0029] A trend in the computer industry is to use multiple processors in large servers, where multiple processors are coupled together in a single package, such as a multi-chip module (MCM). The multiple processors, along with other IC dies that include memory circuits (e.g., cache memory circuits, high-bandwidth memory circuits, etc.), are interconnected via high-speed data buses in the package substrate of the MCM, e.g., to enable all processors to operate together. However, the current technology in such MCMs has inherent limitations in its ability to scale to the bandwidth / distance requirements of next-generation servers, which may have signal speeds greater than 10 GHz and / or data speeds of 3 - 10 terabytes per second. These limitations are mainly related to bandwidth reduction, signal latency, signal loss, and signal distortion due to various reasons, one of which is the configuration in which multiple processors are coupled together within the package, as well as a complex and inefficient power delivery network.

[0030] Current packaging architectures, whether 2D, 2.5D, or 3D, utilize multiple IC dies that are oriented parallel to each other and interconnected via various interconnections (e.g., copper micro-bumps, solder balls, etc.). Generally, any typical IC die consists of a substrate, active regions in the substrate (including transistors and other active circuitry), and a metallization stack above the substrate (sharing contact regions with the active regions). The metallization stack is the region of the IC die in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected via conductive traces and conductive vias. Common metals for conductive traces and conductive vias are copper and aluminum. The metallization stack typically includes contact pads, insulating layers (e.g., interlayer dielectric (ILD) materials such as silicon oxide), conductive layers that include conductive traces, and bonding sites for chip-to-chip or chip-to-package connections. Modern IC dies can include more than ten (10) conductive layers in the metallization stack.

[0031] Conventionally, various such IC die can be stacked in a package in various ways: (1) back-to-back, where the substrate of one IC die is in direct contact with the substrate of another IC die; (2) back-to-front, where the substrate of one IC die is in direct contact with the metallization stack of another IC die; and (3) front-to-front, where the metallization stacks of two IC die are in direct contact. In all these configurations, the IC die are parallel to each other, and the active circuitry is disposed in a plane parallel to the contact regions of adjacent IC die. This architecture is subject to certain inherent limitations. For example, a compute IC die, including high-performance compute circuitry that generates a large amount of heat, must be placed on top of any such stack in order to be able to dissipate heat properly. This placement limits the number of high-power compute IC die that can be placed in a package with a limited (or restricted) footprint.

[0032] The microelectronic components disclosed herein can include IC die that are vertically stacked at their lateral edges and electrically coupled (e.g., back-to-back, back-to-front, or front-to-front stacked and rotated 90 degrees) to the surface of a base IC die. Such vertically stacked IC packages can include memory IC die, compute IC die, or both memory IC die and compute IC die. The various microelectronic components disclosed herein can include high-capacity memory while reducing complexity and improving the efficiency of power delivery to the package relative to conventional methods.

[0033] IC die are disclosed herein that have a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces. The IC die can further include a substrate attached to a metallization stack along an interface parallel to the first and second surfaces. The substrate can include memory circuitry. The metallization stack of the IC die can include multiple conductive traces in a dielectric material, the conductive traces being parallel to the first and second surfaces and exposed at the third surface. The third surface of the IC die can be coupled to a base die through an interconnect, where the interconnect is coupled to the conductive traces exposed on the third surface. In some embodiments, the interconnect can include oxide-oxide bonding and metal-metal bonding, the metal-metal bonding including a first bonding pad in the first IC die and a second bonding pad in the base die, where the first bonding pad includes a portion of the conductive trace exposed on the third surface.

[0034] Accordingly, the present disclosure provides IC packages, related devices, and methods. In some embodiments, an integrated circuit (IC) package may include: a microelectronic component including a plurality of first IC die, the plurality of first IC die including memory circuitry, the plurality of first IC die having a first surface and a second surface opposite the first surface, wherein the plurality of first IC die are stacked and electrically coupled at respective first and second surfaces; and a redistribution layer (RDL) between each of the plurality of first IC die, wherein the RDL includes conductive vias; a second IC die having a first surface, a second surface opposite the first surface, a third surface orthogonal to the first and second surfaces, and conductive traces exposed at the third surface and parallel to the first and second surfaces, wherein the first surface of the second IC die is electrically coupled to some of the conductive vias in the RDL; and a third IC die having a surface, wherein the second surface of an individual one of the plurality of first IC die is electrically coupled to the surface of the third IC die, and wherein the conductive traces exposed at the third surface of the second IC die are electrically coupled to the surface of the third IC die.

[0035] Each of the structures, components, packages, methods, devices, and systems of the present disclosure may have several innovative aspects, none of which alone is responsible for all of the desired features disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the following description and the drawings.

[0036] In the following detailed description, aspects of illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

[0037] The terms "circuit" and "circuitry" mean one or more passive and / or active electrical and / or electronic components arranged to cooperate with each other to provide a desired function. These terms also refer to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical hardware electrical and / or electronic components.

[0038] The term "integrated circuit" means a circuit integrated into a single semiconductor or similar material.

[0039] In some embodiments, the IC die disclosed herein may include a substantially single-crystalline semiconductor (e.g., silicon or germanium) as a base material (e.g., substrate, body) on which integrated circuits are fabricated using conventional semiconductor processing methods. The semiconductor base material may include, for example, N-type or P-type material. The die may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the base material of one or more IC dies may include alternative materials, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of Group III-N, III-V, II-VI, or IV group materials. In still some other embodiments, the base material may include a compound semiconductor, for example, having a first sublattice of at least one element of Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element of Group V of the periodic table (e.g., P, As, Sb). In still some other embodiments, the base material may include an intrinsic Group IV or III-V semiconductor material or alloy without intentionally doping any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In yet some other embodiments, the die may include an amorphous material, such as a polymer; for example, the base material may include silica-filled epoxy resin. In other embodiments, the base material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, the base material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, cupric peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although several examples of die materials are described herein, any material or structure that can be used as a base (e.g., base material) on which the IC circuits and structures described herein can be built falls within the spirit and scope of the present disclosure.

[0040] Unless otherwise specified, the IC die described herein includes one or more IC structures (or simply referred to as "IC") that implement (i.e., are configured to perform) certain functions. In one such example, the term "memory die" can be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., an IC that implements one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In another such example, the term "compute die" can be used to describe a die that includes one or more ICs that implement logic / compute circuitry (e.g., an IC that implements one or more of I / O functions, arithmetic operations, pipelining of data, etc.).

[0041] In another example, the terms "package" and "IC package" are synonyms, and the terms "die" and "IC die" are also synonyms. Note that the terms "chip", "die", and "IC die" can be used interchangeably herein.

[0042] The term "optical structure" includes an arrangement in an IC fabricated for receiving, converting, and / or transmitting optical signals, as described herein. It can include optical conductors such as waveguides, sources of electromagnetic radiation such as lasers and light-emitting diodes (LEDs), and electro-optic devices such as photodetectors.

[0043] In various embodiments, any photonic IC (PIC) described herein can include semiconductor materials, such as N-type or P-type materials. The PIC can include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a SOI structure (or generally a semiconductor-on-insulator structure). In some embodiments, the PIC can be formed using alternative materials that can be combined with or without silicon, the alternative materials including but not limited to lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, gallium phosphide, aluminum gallium arsenide, aluminum arsenide, aluminum indium arsenide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of Group III-N or Group IV materials. In some embodiments, the PIC can include amorphous materials, such as polymers. In some embodiments, the PIC can be formed on a printed circuit board (PCB). In some embodiments, the PIC can be heterogeneous, including a carrier material (e.g., glass or silicon carbide) as the base material, which has a thin semiconductor layer, above which is an active side that includes transistors and similar components. Although several examples of materials for PICs are described herein, any material or structure that can serve as a base on which a PIC can be built falls within the spirit and scope of this disclosure.

[0044] Unless otherwise specified, the term "insulated" means "electrically insulated" and the term "conductive" means "electrically conductive". With respect to optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conductive" may also mean "optically conductive".

[0045] The terms "oxide", "carbide", "nitride", etc. refer to compounds containing oxygen, carbon, nitrogen, etc., respectively.

[0046] The term "high-k dielectric" refers to a material having a dielectric constant higher than that of silicon oxide, while the term "low-k dielectric" refers to a material having a dielectric constant lower than that of silicon oxide.

[0047] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to a solid material (and / or a liquid material cured after the processes described herein) that is substantially non-conductive. By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, ceramics, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide or combinations thereof. They may include dielectric materials, high polarizability materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Other examples of insulating materials are underfills and molding or shaping materials used in packaging applications, including, for example, materials used in organic interposers, package supports, and other such components.

[0048] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include elements monolithically integrated within the IC, mounted on the IC, or connected to the IC. The ICs described herein may be analog or digital and may be used in a variety of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The ICs described herein may be used in a single IC die or as part of a chipset for performing one or more related functions in a computer.

[0049] In various embodiments of the present disclosure, the transistors described herein can be field effect transistors (FETs), such as MOSFETs. In many embodiments, the FET is a four-terminal device. In silicon-on-insulator, or nanoribbon, or gate-all-around (GAA) FETs, the FET is a three-terminal device that includes a source terminal, a drain terminal, and a gate terminal, and uses an electric field to control the current flowing through the device. The FET generally includes a channel material, source and drain regions provided in and / or on the channel material, and a gate stack that includes gate electrode material (or what is referred to as "work function" material) provided on a portion of the channel material ("channel portion") between the source and drain regions, and optionally, also includes a gate dielectric material between the gate electrode material and the channel material.

[0050] In a general sense, an "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, facilitating the communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components, facilitating the communication of optical signals between them. As used herein, both electrical and optical interconnects are included in the term "interconnect". The nature of the described interconnects should be understood herein with reference to the signal medium associated with them. Thus, when used in reference to an electronic device (e.g., an IC that operates using electrical signals), the term "interconnect" describes any element formed of a conductive material that is used to provide an electrical connection to one or more elements associated with the IC or / and an electrical connection between various such elements. In such cases, the term "interconnect" can refer to conductive traces (sometimes also referred to as "lines", "wires", "metal lines", or trenches) and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, the conductive traces and vias can be referred to as "conductive traces" and "conductive vias", respectively, to highlight the fact that these elements include a conductive material such as metal. Similarly, when used in reference to a device that also operates on optical signals (e.g., a PIC), "interconnect" can also describe any element formed of an optically conductive material that is used to provide an optical connection to one or more elements associated with the PIC. In such cases, the term "interconnect" can refer to optical waveguides, including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0051] The term "waveguide" refers to any structure used to guide light from one location to another through a substrate material such as silicon or glass. In various examples, the waveguide can be formed of silicon, doped silicon, silicon nitride, glass such as silica (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70 - 80 wt% SiO2, 7 - 13 wt% B2O3, 4 - 8 wt% Na2O or K2O, and 2 - 8 wt% Al2O3), etc. The waveguide can be formed using various techniques, including but not limited to in-situ formation of the waveguide. For example, in some embodiments, the waveguide can be formed in-situ in the glass using low-temperature glass-to-glass bonding or by direct laser writing. The in-situ formed waveguide can have lower loss characteristics.

[0052] The term "conductive trace" can be used to describe a conductive element isolated by an insulating material. Within an IC die, such insulating material includes the interlayer low-k dielectric provided within the IC die. Within a package substrate and a PCB, such insulating material includes organic materials such as Ajinomoto Build-up Film (ABF), polyimide, or epoxy resin. Such conductive traces are typically arranged in several levels or layers of a metallization stack.

[0053] The term "conductive via" can be used to describe a conductive element that interconnects two or more conductive traces of different levels of a metallization stack. For this purpose, the via can be provided substantially perpendicular to the plane of the IC die / chip or the support structure, on which the IC structure is provided, and the via can interconnect two conductive traces in adjacent levels or two conductive traces in non-adjacent levels.

[0054] The term "package substrate" can be used to describe any substrate material that facilitates the encapsulation of any collection of semiconductor dies and / or other electrical components (e.g., passive electrical components) together. As used herein, the package substrate can be formed of any material, including but not limited to insulating materials such as resin-impregnated fiberglass (e.g., PCB or Printed Wiring Board (PWB)), glass, ceramic, silicon, silicon carbide, etc. Additionally, as used herein, the package substrate can refer to a substrate that includes build-up layers (e.g., ABF layers).

[0055] The term "metallization stack" can be used to refer to a stack of one or more interconnects used to provide connections to different circuit components of an IC die / chip and / or a package substrate.

[0056] As used herein, the "pitch" of an interconnect refers to the center-to-center distance between adjacent interconnects.

[0057] It should be recognized that one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy resin) can be provided in the IC packages described herein and may not be labeled to avoid cluttering the figures. In various embodiments, the underfill for each level can include the same or different insulating materials. In some embodiments, the underfill for each level can include a thermosetting epoxy resin with silica particles; in some embodiments, the underfill for each level can include any suitable material that can perform the underfill function (e.g., support the die and reduce thermal stress on the interconnects). In some embodiments, the selection of the underfill material can be based on design considerations such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of the underfill material can be based on material properties and processing conditions such as cure temperature, glass transition temperature, viscosity, and chemical resistance, etc.; in some embodiments, the selection of the underfill material can be based on both design and processing considerations.

[0058] In some embodiments, one or more levels of solder mask (e.g., epoxy resin liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic resin, solvent) can be provided in the IC packages described herein and may not be labeled or shown to avoid cluttering the figures. The solder mask can be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder mask can be non - photoimageable.

[0059] The terms "substantially", "near", "about", "close to", and "approximately" generally mean within + / - 20% of the target value (e.g., within + / - 5% or 10% of the target value) based on the context of a particular value as described herein or known in the art.

[0060] The terms indicating the orientation of various elements (e.g., "coplanar", "perpendicular", "orthogonal", "parallel", or any other angle between elements) generally mean within + / - 5% - 20% of the target value based on the context of a particular value as described herein or known in the art.

[0061] The term "connected" means a direct connection between the things being connected (which may be one or more of mechanical, electrical, and / or thermal connections) without any intermediate device, while the term "coupled" means a direct connection between the things being connected or an indirect connection through one or more passive or active intermediate devices.

[0062] The specification uses the phrases "in an embodiment" or "in embodiments", each of which can refer to one or more identical or different embodiments.

[0063] Furthermore, the terms "comprising", "including", "having", etc. used with respect to the embodiments of the present disclosure are synonyms.

[0064] The present disclosure may use perspective-based descriptions such as "above", "below", "top", "bottom", and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0065] As used herein, the terms "above", "below", "between", and "on" refer to the relative position of one layer or component of a material with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intermediate layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intermediate layers. In contrast, a first layer described as "on" a second layer refers to a layer in direct contact with the second layer. Similarly, unless otherwise explicitly stated, a feature disposed between two features may be in direct contact with the adjacent features or may have one or more intermediate layers.

[0066] As used herein, the term "disposed" refers to position, location, placement, and / or arrangement and does not refer to any particular method of formation.

[0067] When used in reference to a measurement range, the term "between" includes the endpoints of the measurement range.

[0068] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the symbol "A / B / C" means (A), (B), and / or (C).

[0069] Although certain elements may be referred to in the singular herein, these elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0070] Unless otherwise specified, the use of ordinal adjectives "first", "second", and "third", etc. to describe common objects merely indicates different instances of the same object and is not intended to imply that the objects so described must be in a given order in terms of time, space, ranking, or in any other way.

[0071] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description should not be considered limiting.

[0072] The drawings are not necessarily to scale.

[0073] In the drawings, like reference numerals refer to like or similar elements / materials shown, and thus, unless otherwise specified, the explanation of an element / material provided with a given reference numeral in the context of one of the drawings applies to other drawings in which an element / material with the same reference numeral may be shown. Additionally, the singular and plural forms of the identifiers may be used with the reference numerals to denote single and multiple elements of the same or similar type, kind, or category, respectively.

[0074] Furthermore, in the drawings, some schematic diagrams of the exemplary structures of the various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that such schematic diagrams may not reflect real-life process limitations, which may result in the features looking less "ideal" when inspecting any structure described herein using images from suitable characterization tools such as, for example, scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometers. In images of such real structures, possible processing and / or surface defects may also be visible, e.g., surface roughness, curvature or profile deviations, pits or scratches, edges of the material not being perfectly straight, tapered vias or other openings, unintentional rounding, or variations in the thickness of different material layers, occasional helices, edge or combination dislocations within (one or more) crystal regions, and / or occasional dislocation defects of individual atoms or atomic clusters. There may be other defects not listed herein, but these are common in the field of device fabrication and / or packaging.

[0075] Note that in the figures, for ease of illustration, various components (e.g., interconnects) are shown as aligned (e.g., at respective interfaces); in reality, some or all of them may not be aligned. Additionally, there may be other components in the assembly, such as bond pads, landing pads, metallization, etc., which are not shown in the figures to prevent clutter. Furthermore, these figures are intended to show the relative arrangement of the components within them, and generally, these assemblies may include other components not shown (e.g., various interface layers or various other components related to optical functions, electrical connections, or thermal mitigation). For example, in some further embodiments, the assemblies shown in the figures may include more die and other electrical components. Additionally, although some components of the assemblies are shown in the figures as planar rectangles or formed by cuboids, this is for ease of illustration only, and embodiments of these assemblies may be curved, circular, or of other irregular shapes, which is determined by the manufacturing processes used to fabricate the various components and is sometimes inevitable.

[0076] In the drawings, for purposes of illustration, a specific number and arrangement of structures and components are presented, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0077] In addition, unless otherwise specified, the structures shown in the figures may take any suitable form or shape depending on material properties, manufacturing processes, and operating conditions.

[0078] For convenience, if there are sets of figures designated by different letters (e.g., Figure 1A-1C ), such sets may be referred to herein without the letter (e.g., referred to as "Figure 1"). Similarly, if there are sets of figure numbers designated by different letters (e.g., 110A, 110B), such sets may be referred to herein without the letter (e.g., referred to as "110").

[0079] The various operations may be described sequentially as a number of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations are necessarily order-dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0080] Example Embodiment

[0081] Figure 1A is a schematic cross-sectional view of an example IC die 100 according to some embodiments of the present disclosure. In the illustrated embodiment, the IC die 100 includes a metallization stack 102 having a surface 104 that is orthogonal to another surface 106A, 106B. In various embodiments, the surfaces 104 and 106A, 106B may be planarized. Generally, an IC die different from the IC die 100 does not have a planarized edge along the thickness. For example, when the IC die is separated from the wafer, after a dicing operation, the vertical surface corresponding to the surface 104 will be rough. In contrast, the surface 104 of the IC die 100 may be flat and planar, with a surface roughness less than 10 angstroms and a total thickness variation (TTV) on the surface 104 of less than 3 micrometers.

[0082] The metallization stack 102 can be located on the substrate 110 (e.g., at the interface 108). The interface 108 can be orthogonal to the surface 104 and parallel to the surface 106 (e.g., in the xy plane). It should be understood that although the interface 108 is in the xy plane, the interface 108 may not be completely planar. The substrate 110 can also include an active region 112. In some embodiments, the active region 112 can include transistors, diodes, and other active circuitry, and can be close to the interface 108. In some other embodiments, the active region 112 may not exist, or alternatively, transistors, diodes, and other active circuitry may not be present in the active region 112. In some embodiments, the active circuitry can include memory circuitry and / or computing circuitry. The substrate 110 can have a surface 114 that can be coplanar with the surface 104. In some embodiments, the substrate 110 can include a semiconductor material as listed in the previous subsection above. In other embodiments, the substrate 110 can include glass, ceramic, or other materials that can be suitable for creating functional elements of an IC.

[0083] In various embodiments, the metallization stack 102 can include a dielectric material or a multi-layer dielectric material, and conductive traces 120 passing through the dielectric material. The conductive traces 120 can be parallel to the surface 106 such that the conductive traces 120 are orthogonal to the surface 104. In some embodiments, the dielectric material of the metallization stack 102 can include silicon oxide; in other embodiments, the dielectric material of the metallization stack 102 can include any suitable dielectric substance used as an interlayer dielectric (ILD) in a typical semiconductor IC die, as described in the previous subsection above. In many embodiments, the conductive traces 120 can include a conductive metal, such as copper. In some embodiments, there can be 2 to 6 layers of conductive traces 120 in the multi-layer dielectric material. Conductive vias 122 passing through the dielectric material can conductively connect the conductive traces 120 to the active circuitry in the active region 112. The conductive vias 122 are orthogonal to the conductive traces 120. The conductive traces 120 can extend to the surface 104 such that a portion of the conductive traces 120 is exposed on the surface 104; such an exposed portion can form a bonding portion 124. In various embodiments, there can be several conductive traces 120 between the interface 108 and the surface 106A. One or more conductive traces 120 can be exposed on the surface 104 as the bonding portion 124. In some embodiments, the linear dimension (e.g., length, width, or diagonal) of the largest bonding portion 124 can be less than 5 micrometers. In some embodiments, the bonding portions 124 can be spaced apart at a pitch of less than 9 micrometers. In some embodiments, bonding pads (e.g., similar to the conductive bonding pads 308 shown in FIG. 3) can be formed on the bonding portions 124 at the surface 104.

[0084] Figure 1B is a schematic cross-sectional view of another example IC die 100 in accordance with some other embodiments of the present disclosure. In some embodiments, the IC die 100 may include metallization stacks 102A and 102B on either side of a substrate 110. The metallization stack 102A may share an interface 108A with the substrate 110, and the metallization stack 102B may share an interface 108B with the substrate 100. In some embodiments, as Figure 1B shown, the active region 112 may be close to the interface 108A; in other embodiments, the active region 112 may be close to the interface 108B. Conductive traces 120A and conductive vias 122A may be in the metallization stack 102A. Conductive traces 120B and conductive vias 122B may be in the metallization stack 102B. In some embodiments, the conductive trace 120A may be configured to route signals, while the conductive trace 120B may be configured to route power and ground to the active region 112. In such embodiments, the conductive trace 120B may be thicker than the conductive trace 120A (i.e., the conductive trace 120A may be thinner than the conductive trace 120B). In other embodiments, the conductive traces 120A and 120B may be configured to route signals, power, and ground without any difference between them. In such embodiments, the conductive traces 120A and 120B may have similar thicknesses. Through-silicon vias (TSVs) 202 passing through the substrate 110 may implement conductive paths between the conductive traces 120A and 120B and / or between the active region 112 and the conductive trace 120B. In some embodiments, the TSV 202 may pass through the active region 112 (not shown).

[0085] Figure 1CFIG. 0 is a schematic cross-sectional view of another example IC die 100 in accordance with some embodiments of the present disclosure. In some embodiments, IC die 100 may include substrates 110A and 110B on either side of metallization stack 102. Substrate 110A may include surface 106A, and substrate 110B may include surface 106B. Substrate 110A may share interface 108A with metallization stack 102, and substrate 110B may share interface 108B with metallization stack 102. Substrate 110A may include active region 112A, and substrate 110B may include active region 112B. Active regions 112A and 112B may be adjacent to metallization stack 102 at respective interfaces 108A and 108B. Substrates 110A and 110B may have respective surfaces 114A and 114B that may be coplanar with surface 104. Metallization stack 102 may include dielectric material and conductive traces 120 and conductive vias 122 that pass through the dielectric material. Conductive vias 122 are orthogonal to conductive traces 120. Conductive traces 120 may be parallel to interfaces 108A and 108B such that conductive traces 120 are orthogonal to surface 104. Conductive vias 122 that pass through the dielectric material may conductively connect conductive traces 120 to active circuitry in active regions 112A and 112B. One or more conductive vias 122 may further extend through active regions 112A and / or 112B (not shown). In some embodiments, conductive traces 120 and conductive vias 122 may be configured to route signals between active regions 112A and 112B. In some embodiments, conductive traces 120 and conductive vias 122 may be configured to route power and ground between active regions 112A and 112B. In such embodiments, conductive traces 120 may be thicker (i.e., similar to Figure 1B conductive trace 120B therein). In some embodiments, conductive traces 120 may have a linear dimension (e.g., x-dimension and z-dimension) between 1 micron and 10 microns. Conductive traces 120 may extend to surface 104 such that portions of conductive traces 120 are exposed on surface 104; such exposed portions may form bond pads 124.

[0086] Figure 2A FIG. 6 is a simplified perspective view of IC die 100. Figure 2A FIG. 8 shows Figure 1A IC die 100 of

[0087] Figure 2B FIG. 14 is a simplified perspective view of IC die 100.Figure 2B shows Figure 1B IC die 100, which has been rotated 90 degrees such that surfaces 114, 104A, and 104B are on the bottom and surfaces 106A, 106B are on the sides. IC die 100 may include substrate 110, active region 112, and metallization stacks 102A, 102B. IC die 100 may have any suitable dimensions, including those described above with reference to Figure 2A The substrate 110 may have any suitable thickness (e.g., z-dimension). For example, the substrate 110 may have a thickness between less than 1 micron and 50 microns (e.g., between 0.25 micron and 5 microns, or between 20 microns and 50 microns). In some embodiments, the substrate 110 may be almost completely removed such that the TSV 202 may be very thin (e.g., having a thickness less than 1 micron) and may provide direct contact with the transistor source / drain in the active region 112.

[0088] Figure 2C is a simplified perspective view of IC die 100. Figure 2C shows Figure 1C IC die 100, which has been rotated 90 degrees such that surfaces 114A, 114B, and 104 are on the bottom and surfaces 106A, 106B are on the sides. IC die 100 may include substrates 110A, 110B, active regions 112A, 112B, and metallization stack 102.

[0089] Figure 3A-3D shows simplified schematic cross-sections of various configurations of a microelectronic assembly 300 in accordance with embodiments of the present disclosure. Figure 3A shows a microelectronic assembly 300 that includes a plurality of IC dies 100, such as 100(1), 100(2), and 100(3), which are coupled to another IC die 302 by interconnects 304 such that surface 104 of any one of the IC dies 100 is in direct contact with surface 306 of IC die 302. As described in connection with FIGS. 1 and 2, surface 104 is orthogonal to interface 108 between the active region 112 and the metallization stack 102 in any one of the IC dies 100. In some embodiments, the IC die 100 may include active circuitry (e.g., transistors, diodes) in the active region 112. In other embodiments, one or more of the IC dies 100 may not include active circuitry in the active region 112; in such embodiments, the active region 112 may be merged with the substrate 110 (e.g., not present).

[0090] In various embodiments, the IC die 302 may include an interposer having conductive traces and / or TSVs to enable conductive coupling of the IC die 100 to other IC dies and / or a package substrate, and the IC die 302 may not have any active circuitry therein. In other embodiments, the IC die 302 may include active circuitry. In many embodiments, the IC die 100 may be conductively coupled through conductive paths in the IC die 302. For example, the IC die 302 may include a network-on-chip to interconnect the computing circuitry of the IC die 100. In various embodiments, the IC die 100 may be conductively coupled to the IC die 302 through an interconnect 304, which may include a hybrid bond. In such a configuration, the surface 114 of the substrate 110 of the IC die 100 may be in direct contact with the surface 306 of the IC die 302.

[0091] Figure 3B FIG. 4 is a schematic cross-sectional view of details of a particular one of the interconnects 304 in the microelectronic assembly 300. Note that although only the interconnect 304 is shown, the same structure and description may apply to any other such interconnects including hybrid bonds in the microelectronic assembly 300. In a general sense, the interconnect 304 may include a metal-metal bond between a bonding portion 124 of the IC die 100 and a bonding pad 308 of the IC die 302 at an interface between the surface 104 of the IC die 100 and the surface 306 of the IC die 302, and a dielectric-dielectric bond (e.g., oxide-oxide bond) in the dielectric materials 116 and 310 of the IC dies 100 and 302, respectively. The bonding portion 124 belonging to the IC die 100 may be bonded to the bonding pad 308 of the IC die 302. As described in the description of FIG. 1, the bonding portion 124 may include a portion of the conductive trace 120 exposed on the surface 104; the bonding pad 308 may include a conventional conductive structure electroplated on the surface 306. The dielectric material 116 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) in the IC die 100 may be bonded to the dielectric material 310 in the IC die 302. In some embodiments, the dielectric material 310 of the IC die 302 is the same as the dielectric material 116 of the IC die 100. In various embodiments, the dielectric material 310 includes silicon oxide, silicon nitride, silicon carbonitride, and other such inorganic materials commonly used in manufacturing semiconductor IC dies. The bonded metal and dielectric materials form the interconnect 304 (including the hybrid bond), providing electrical and mechanical coupling between the IC die 100 and the IC die 302. In various embodiments, the interconnect 304 may have a linear dimension of less than 5 microns and a pitch of less than 10 microns between adjacent interconnects.

[0092] Return to Figure 3A, the IC die 100 can be coupled to the IC die 302 such that the metallization stack 102 of one of the IC dies 100 (e.g., 100(1)) can be in direct contact with the substrate 110 of an adjacent IC die 100 (e.g., 100(2)). In such an embodiment, the IC dies 100(1) and 100(2) can be bonded to each other at least by an oxide-oxide bond. In some embodiments, the interconnect 304 (including metal-metal bonding and oxide-oxide bonding as described with reference to Figure 3B ) can be present at the planar contact interface (e.g., the corresponding surfaces 106A, 106B as shown in Figure 2A ) between the IC dies 100(1) and 100(2). In some such embodiments, the conductive contact between the active regions 112 of the IC dies 100(1) and 100(2) can be achieved through the conductive traces 120 in the IC die 100(1), the interconnect 304 at the interface between the IC dies 100(1) and 100(2), and the TSVs 202 in the IC die 100(2); in such embodiments, the TSVs 202 are in conductive contact with the interconnect 304 between the IC dies 100(1) and 100(2). In other embodiments (not shown), the metallization stacks 102 of the IC dies 100(1) and 100(2) can be in a face-to-face configuration. In still other embodiments (not shown), the substrates 110 of the IC dies 100(1) and 100(2) can be in a back-to-back configuration.

[0093] In various embodiments, the IC dies 100 can be arranged in rows parallel to each other such that there is a gap 312 between adjacent IC dies 100. In some embodiments, the gap 312 can be uniform across the microelectronic assembly 300 and can be in the range of on the order of a few millimeters (e.g., less than 5 millimeters); in other embodiments, the gap 312 can be non-uniform, with some IC dies 100 closer to other IC dies 100 than others. In some such embodiments, the IC die 100 can include circuitry that consumes power and generates heat during operation. For example, the IC die 100 can include the computing circuitry of a microprocessor. The gap 312 can be configured to allow a cooling fluid to flow therethrough. In some embodiments, the cooling fluid (not shown) can be air; in other embodiments, the cooling fluid can be a liquid coolant.

[0094] In some embodiments, the IC die 100 may include a computing circuitry and a VC circuitry, and the IC die 302 may include a network-on-chip circuitry, conductively coupling an array of IC dies 100. In some embodiments, the IC dies 100(1), 100(2) may include a memory circuitry, the IC die 100(3) may include a computing circuitry and a VC circuitry, and the IC die 302 may include a network-on-chip circuitry, conductively coupling an array of IC dies 100. In some embodiments, the IC die 100(1) may include a capacitor and / or an inductor, the IC die 100(2) may include a computing circuitry and a VC circuitry, the IC die 100(3) may include a memory circuitry, and the IC die 302 may include a network-on-chip circuitry, conductively coupling an array of IC dies 100. In other embodiments, some of the IC dies 100 may include a graphics processing circuitry, and other IC dies may include a computing circuitry and a VC circuitry, and the IC die 302 may include a VC circuitry. Any suitable circuitry configuration may be provided in the microelectronic component 300 among the IC die 100 and the IC die 302 as needed and based on specific requirements.

[0095] Figure 3C is of a portion 313 of a Figure 3A microelectronic component 300 according to some embodiments of the present disclosure. The IC die 302 may include a metallization stack 314 attached to a substrate 316 having an active region 318. The substrate 316 is attached to the metallization stack 314 along another interface 320 parallel to the surface 306. In some embodiments, the active region 318 includes active circuitry (not shown), including transistors and diodes. In these embodiments, the active region 318 may be close to the interface 320. In some embodiments, the active region 318 may be absent. The metallization stack 314 may also include conductive vias (e.g., conductive traces 322 and conductive vias 324) in a dielectric material. In some embodiments, the dielectric material of the metallization stack 314 is Figure 3B the dielectric material 310 in

[0096] Figure 3D is of a portion 313 of a Figure 3A microelectronic component 300 according to some embodiments of the present disclosure. The IC die 302 may be associated with Figure 3CThe embodiments are substantially similar, except that it is inverted (e.g., upside down) such that the substrate 316 is close to the surface 104 of the IC die 100. In such an embodiment, the IC die 302 may include an interface layer 326 (e.g., a bonding layer) on a side of the substrate 316 opposite to the metallization stack 314. The interface layer 326 includes bonding pads 308 having a dielectric material between the bonding pads 308 (e.g., surrounding the bonding pads 308), such that the interconnect 304 is formed by metal-metal bonding of the bonding portions 124 and the bonding pads 308 and oxide-oxide bonding of the dielectric material of the substrate 110 of the IC die 100(3) and the interface layer 326 of the IC die 302. In some embodiments, the dielectric material of the interface layer 326 is the same material as Figure 3B the dielectric material 310 in Figure 3B In some embodiments, the dielectric material of the interface layer 326 is the same material as the dielectric material 116 of the IC die 100 in

[0097] Figure 3E FIG. is a schematic cross-sectional view of a microelectronic component 300 according to some embodiments of the present disclosure. The embodiment shown in the figure is similar to Figure 3A the embodiment in Figure 3E except that the IC die 100(1) is coupled end-to-end with the IC die 200(2) to form a stack of IC dies. Thus, in the embodiment shown in Figure 3A any single IC die 100 of

[0098] Figure 4 is replaced by a corresponding stack of end-to-end coupled IC dies 100, as further described. The IC dies 100(1) and 100(2) may be in direct end-to-end contact along a surface 103 opposite to the surface 104 of the IC die 100(1). The conductive traces 120(1) of the IC die 100(1) may be conductively coupled to the conductive traces 120(2) of the IC die 100(2) through the interconnect 304 on the surface 103. The substrates 110(1) and 110(2) may be in direct contact at the interface 107. In some embodiments, the substrates 110(1) and 110(2) may be bonded by oxide-oxide bonding along a common interface 107. Figure 2ASimplified perspective view of an exemplary microelectronic assembly 300 of an IC die 100. Note that, for ease of illustration and to avoid cluttering the drawings, the drawings are not drawn to scale and do not show detailed features. Multiple IC dies 100 (e.g., IC dies 100(1), 100(2), 100(3), and 100(4)) can be coupled to a surface 306 of an IC die 302 at respective surfaces 104 (e.g., surfaces 104(1), 104(2), 104(3), and 104(4)). The multiple IC dies 100 can be coupled to the IC die 302 through any suitable interconnect (e.g., interconnect 304 in FIG. 3). In many embodiments, the IC die 302 can be large-sized, e.g., as large as a conventional reticle, and its footprint can be approximately 858 square millimeters (mm 2 ). Although Figure 4 shows the IC die 100 having metallization stacks 102(1), 102(2), 102(3), 102(4) facing away from each other, in some embodiments, one or more IC dies 100 can have one or more metallization stacks 102 facing each other. As Figure 4 shown, the IC dies 100(2), 100(3), and 100(4) can be vertically stacked and bonded together at respective surfaces (e.g., surfaces 106A, 106B as Figure 2A shown) by, for example, oxide-oxide bonding or inorganic dielectric-inorganic dielectric bonding. The stacked and bonded IC dies 100 can be rotated 90 degrees and electrically coupled to the IC die 302 at surface 104. The multiple IC dies 100 can be coupled to the IC die 302 through any suitable interconnect (e.g., interconnect 304 in FIG. 3). Stacking and bonding the IC dies 100 before coupling to the IC die 302 can allow for easier handling of the IC dies during assembly operations. Any suitable number of IC dies 100 can be stacked and bonded together, e.g., between 2 and 100 IC dies. Although Figure 4 shows the IC dies 100 having a particular stacking arrangement (e.g., all IC dies facing the same direction), in some embodiments, one or more IC dies 100 can have a different stacking arrangement (e.g., one or more IC dies 100 can be inverted to face the opposite direction). Additionally, although Figure 4 includes Figure 1A the IC die 100, the stack of IC dies 100 can include Figure 1A-1C any IC die.

[0099] Figure 5Ais a perspective view of an IC package 500 in accordance with some embodiments of the present disclosure. The illustrated embodiment includes an IC die 100A and a microelectronic assembly 400 electrically coupled to a surface 306 of an IC die 302 at a side surface 104. The microelectronic assembly 400 includes a plurality of IC dies 113 having TSVs 402 and electrically coupled (e.g., in a conventional pancake stack) at respective top and bottom surfaces, and the bottommost IC die chip 113 is electrically coupled to the surface 306 of the IC die 302. As used herein, the first and opposite second surfaces, or top and bottom surfaces (e.g., as shown in FIG. 6) of the IC dies 100, 113, 115 refer to the surface 106 having a larger surface area, and the side or orthogonal surfaces for the first and second surfaces / top and bottom surfaces refer to the side surfaces (e.g., the surface 104 of the IC die 100 shown in FIGS. 1-4). The microelectronic assembly 400 may also include redistribution layers (RDLs) 182 between the IC dies 113 (e.g., as Figure 5B shown in more detail in). The IC package 500 may also include dummy silicon 111 and a package substrate 404 electrically coupled to the IC die 302. The microelectronic assembly 400 may be located at the center of the IC die 302 (e.g., in the middle portion of the IC die 302), and the IC die 100A may be located on the opposite side of the microelectronic assembly 400. The dummy silicon 111 may be located on the other side of the IC die 100A. In some embodiments, the IC die 100A may be located on one side of the microelectronic assembly 400, or may be located on more than two sides of the microelectronic assembly 400, e.g., on three or four sides of the microelectronic assembly 400 (not shown). In some embodiments, the IC die 100A may include computing circuitry, and the IC dies 113 may include memory circuitry, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0100] Compared with a conventional IC package, Figure 5AThe IC package 500 can provide increased power delivery through a memory cube (e.g., the microelectronic component 400). As used herein, the microelectronic component 400 may also be referred to as a "memory cube". The microelectronic component 400 may have any suitable dimensions. For example, the microelectronic component 400 may have a height 191 between 3 millimeters (mm) and 5 mm, a width 193 between 10 mm and 20 mm, and a length 195 between 1 mm and 2 mm. The microelectronic component 400 may include IC dies 113 stacked between 30 and 40 with TSVs 402, where the TSVs 402 are part of the power delivery network. The TSVs 402 may have any suitable dimensions for power delivery. For example, the TSVs 402 may include a total metal (e.g., copper) between 80 micrometers and 100 micrometers to deliver the required current amount (e.g., approximately 100 amperes) to each IC die 100A. In some embodiments, the TSVs 402 may have a diameter between 4 micrometers and 10 micrometers.

[0101] Figure 5B is a cross-sectional view of an IC package 500 according to some embodiments of the present disclosure. Figure 5B shows Figure 5A the IC package 500 and further includes a circuit board 131. As Figure 5B shown, the IC package 500 may include an IC die 100A, dummy silicon 111, and a microelectronic component 400, which are electrically coupled to the surface 306 of the IC die 302 through an interconnect 304. The IC die 302 may be electrically coupled to a package substrate 404 through an interconnect 352, and the package substrate 404 may be electrically coupled to the circuit board 131 through an interconnect 150. The microelectronic component 400 may include a plurality of IC dies 113, which are electrically coupled to RDLs 182 between adjacent IC dies 113 at corresponding top and bottom surfaces (e.g., surfaces 106A, 106B). The RDLs 182 may include conductive traces 196 and conductive vias 198. The conductive vias 198 may be coupled to the TSVs in a single IC die 113 to form TSVs 402 extending through the microelectronic component 400. The conductive traces 196 enable lateral routing between the TSVs 402 and the IC die 100A through the interconnect 304 at the surface 106 of the IC die 100A. Compared with the TSVs 402 in the IC die 113, the conductive vias 198 in the RDLs 182 are shown as brighter and have dashed lines to allow the conductive traces 196 to be more clearly shown.

[0102] The RDL 182 may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and one or more conductive vias 196, which include conductive vias 198 passing through the dielectric material, as shown in the figure. The conductive vias 198 may be electrically coupled to the TSV 402 to form conductive vias extending through the microelectronic component 400. The conductive vias 196 may be electrically coupled to the conductive vias 198 for delivering power to the IC die 100A. In some embodiments, the insulating material of the RDL 182 may be composed of a dielectric material, a bismaleimide triazine (BT) resin, a polyimide material, an epoxy material (e.g., a glass-reinforced epoxy matrix material, an epoxy build-up film, etc.), a molding material, an oxide-based material (e.g., silicon dioxide or spin-on oxide), or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). The RDL 182 may have any suitable thickness. For example, in some embodiments, the RDL 182 may have a thickness between 2 microns and 4 microns. The RDL 182 may be manufactured using any suitable technique (e.g., PCB technology or redistribution layer technology).

[0103] The IC die 100A may be from at least in Figure 1A-1Cselected from one or more embodiments shown, and may include computing circuitry. IC die 100A may be electrically coupled to IC die 302 via conductive traces 120 (e.g., as shown in FIG. 1), and electrically coupled to IC die 113 via conductive vias 196 in RDL 182. As described above with reference to FIG. 3, IC die 302 may include an interposer having conductive vias, including TSVs 502, to effect conductive coupling of IC dies 100A, 113 to package substrate 404. The IC die 113 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and a plurality of conductive vias formed through the insulating material that are electrically coupled to conductive contacts on the top surface and / or bottom surface of IC die 113. In some embodiments, the insulating material of IC die 113 may include a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, polyimide material, glass-reinforced epoxy matrix material, or a low-k or ultra-low-k dielectric material (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymer dielectric, photoimageable dielectric, and / or benzocyclobutene-based polymer). In some embodiments, the insulating material of IC die 113 may include a semiconductor material such as silicon, germanium, or a III-V material (e.g., gallium nitride) and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive vias in IC die 113 may include conductive traces and / or conductive vias and may connect any conductive contacts on IC die 113 (e.g., conductive contacts on the top surface and conductive contacts on the bottom surface) in any suitable manner (e.g., connecting multiple conductive contacts on the same surface or different surfaces of IC die 113). The conductive vias in IC die 113 may be defined by liner materials such as adhesion liners and / or barrier liners, as appropriate. In some embodiments, IC die 113 is a wafer. In some embodiments, IC die 113 is a monolithic silicon, fan-out or fan-in package die, or a die stack (e.g., a wafer stack, a die stack, or a multi-layer die stack).

[0104] Dummy silicon 111 can be coupled to the surface 306 of the IC die 302 and to the corresponding surfaces 106 (e.g., surfaces 106A, 106B as shown in FIG. 2) of the IC die 100A. According to the present disclosure, the term "dummy silicon" or "dummy die" refers to a structure that is similar in size and shape to an IC die, but unlike an IC die chip, it does not have an active integrated circuit system. As a non-limiting example, a dummy die may have some features found on an IC die, such as bond pads, but does not include transistor circuitry capable of being powered on or processing signals. Dummy silicon 111 can include any suitable bulk material. Dummy silicon 111 can include a material that is structurally rigid and thermally conductive (e.g., silicon), which can provide mechanical support and stability to the IC package 500. In some embodiments, dummy silicon 111 can be coupled by fusion bonding (i.e., dielectric-dielectric bonding without metal-metal bonding at the interface). In some embodiments, dummy silicon 111 can be coupled by diffusion bonding (e.g., using a surface layer of a soft metal (e.g., gold or silver) on the bonding surface for metal-metal bonding at the interface). In some embodiments, dummy silicon 111 can be coupled by hybrid bonding (e.g., interconnect 304). In some embodiments, dummy silicon 111 can include a plurality of cavities (e.g., air gaps). In some embodiments, dummy silicon 111 can include a silicon wafer that is cut to fit adjacent to the IC die 100A. Dummy silicon 111 can have any suitable size. In some embodiments, dummy silicon 111, IC die 100A, and microelectronic component 400 can have the same total thickness and width (e.g., as Figure 5A shown, z-height 191 and x-dimension 193).

[0105] The IC package 500 as described herein may also include a package substrate 404. The package substrate 404 may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and one or more conductive vias to route power, ground, and signals through the dielectric material (e.g., including conductive traces and / or conductive vias as shown). In some embodiments, the insulating material of the package substrate 404 may be a dielectric material such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a BT resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric with an inorganic filler, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In particular, when the package substrate 404 is formed using a standard printed circuit board (PCB) process, the package substrate 404 may include FR-4, and the conductive vias in the package substrate 404 may be formed by patterned copper sheets separated by stacked layers of FR-4. The conductive vias in the package substrate 404 may be defined by liner materials such as adhesive liners and / or barrier liners, as appropriate. In some embodiments, the package substrate 404 may be formed using a lithographically defined via packaging process. In some embodiments, a standard organic package manufacturing process may be used to fabricate the package substrate 404, and thus the package substrate 404 may be in the form of an organic package. In some embodiments, the package substrate 404 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material and creating conductive vias and lines by laser drilling and plating. In some embodiments, any suitable technique (e.g., redistribution layer technique) may be used to form the package substrate 404 on a removable carrier. Any method known in the art for manufacturing the package substrate 404 may be used, and these methods will not be discussed further in detail herein for the sake of brevity.

[0106] The IC die 302 can be coupled to the package substrate 404 via the interconnects 352. In some embodiments, the interconnects 352 disclosed herein can have a pitch between about 90 microns and 130 microns. The interconnects 352 disclosed herein can take any suitable form. When describing an interconnect herein, the surface of a first die can include a first set of conductive contacts, and the surface of a second die or package substrate can include a second set of conductive contacts. Then, one or more conductive contacts of the first set can be electrically and mechanically coupled to some of the conductive contacts of the second set via the interconnect. In some embodiments, a set of interconnects 352 can include solder (e.g., solder bumps or solder balls that are subjected to thermal reflow to form the interconnects 352). The interconnects 352 that include solder can include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a set of interconnects 352 can include anisotropic conductive material, such as anisotropic conductive film or anisotropic conductive paste. The anisotropic conductive material can include conductive material dispersed in a non-conductive material. In some embodiments, the anisotropic conductive material can include microscopic conductive particles embedded in an adhesive or thermosetting adhesive film (e.g., thermosetting biphenyl-type epoxy resin or allyl-based material). In some embodiments, the conductive particles can include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles can include nickel-coated gold or silver-coated copper, which is in turn coated with a polymer. In another example, the conductive particles can include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other. However, when the anisotropic conductive material is sufficiently compressed (e.g., by conductive contacts on either side of the anisotropic conductive material), the conductive materials near the compressed region can contact each other, thereby forming a conductive path from one side of the film to the other in the compressed region.

[0107] The IC package 500 can also include a circuit board 131. For example, the circuit board 131 can be a main board and can have other components attached thereto. The circuit board 131 can include conductive traces and other conductive contacts for routing power, ground, and signals through the circuit board, as is known in the art. The interconnects 150 can be any suitable interconnects, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or pads in a land grid array arrangement. In some embodiments, a set of interconnects 150 can include solder (e.g., solder bumps or solder balls that are subjected to thermal reflow to form the interconnects 150). In some embodiments, the interconnects 150 disclosed herein can have a pitch between about 900 microns and 1.2 millimeters. In some embodiments, the interconnects 150 can not couple the package substrate 404 to the circuit board 131, but can couple the package substrate 402 to another IC package, an interposer, or any other suitable component.

[0108] In some embodiments, some of the interconnections in the microelectronic component 300 or the IC package 500 as described herein may be metal-to-metal interconnections (e.g., copper-to-copper interconnections or plated interconnections). In such embodiments, the conductive contacts on either side of the interconnection may be bonded together without using an intermediate solder or anisotropic conductive material (e.g., under elevated pressure and / or temperature). In some metal-to-metal interconnections, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide) may be present between the bonded metals (e.g., between the copper pads or posts providing the associated conductive contacts). In some embodiments, one side of the interconnection may include metal posts (e.g., copper posts), and the other side of the interconnection may include metal contacts recessed in the dielectric (e.g., copper contacts). In some embodiments, the metal-to-metal interconnection (e.g., copper-to-copper interconnection) may include a noble metal (e.g., gold) or a metal (e.g., silver) whose oxide is conductive. In some embodiments, the metal-to-metal interconnection may include metal nanostructures (e.g., nanorods) that may have a reduced melting point. Metal-to-metal interconnections may be capable of reliably conducting higher currents than other types of interconnections; for example, when current flows, some solder interconnections may form brittle intermetallic compounds, and the maximum current provided through such interconnections may be limited to mitigate mechanical failures.

[0109] In some embodiments, a thin solder cap may be used in the metal-to-metal interconnection to accommodate planarization, and such solder may turn into an intermetallic compound during processing. In some embodiments, the solder used in some interconnections may have a higher melting point than the solder included in other interconnections. For example, when the interconnections in an IC package are formed before other interconnections, the first-formed solder-based interconnections may use a higher-temperature solder (e.g., with a melting point above 200 degrees Celsius), while the subsequently formed interconnections may use a lower-temperature solder (e.g., with a melting point below 200 degrees Celsius). In some embodiments, the higher-temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower-temperature solder may include tin and bismuth (e.g., eutectic tin bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0110] In some embodiments, the IC package 500 may further include an underfill material 127. In some embodiments, the underfill material 127 may extend between the bottom surface of the IC die 302 and the top surface of the package substrate 404 around the associated interconnect 352 and / or between the bottom surface of the package substrate 404 and the top surface of the circuit board 131 around the associated interconnect 150. The underfill material 127 may be an insulating material, such as a suitable epoxy resin material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that facilitates soldering the IC die 302 to the package substrate 404 when forming the interconnect 352 or soldering the package substrate 404 to the circuit board 131 forming the interconnect 150, and then polymerizes and encapsulates the corresponding interconnects 352, 150. The underfill material 127 may be selected to have a coefficient of thermal expansion (CTE) that can mitigate or minimize the stress between the IC die 302 and the package substrate 404 caused by non-uniform thermal expansion in the IC package 500.

[0111] Although FIG. 5 shows a specific number and arrangement of IC dies 113 and a specific number and arrangement of IC dies 100A, IC die 302, and dummy silicon 111 in the microelectronic component 400, the IC package 500 may include any suitable number and arrangement of microelectronic components 400, IC dies 100A, IC die 302, and dummy silicon 111. For example, the IC package 500 may include four (4) IC dies 100A, one on each side of the microelectronic component 400.

[0112] Figure 6A is a schematic perspective view of another example IC package 500 according to some embodiments of the present disclosure. The embodiment shown in the figure is similar to Figure 5A the embodiment of, except that the IC package 500 includes an IC die 100B and the microelectronic component 400 does not include the TSV 402 shown in FIG. 5. The IC die 100B may be electrically coupled to the IC die 302 at the side surface 104. In some embodiments, the IC die 302 may include computing circuitry.

[0113] Figure 6B is according to some embodiments of the present disclosure Figure 6A of the IC package 500. As Figure 6B shown, the IC package 500 may include a microelectronic component 400, an IC die 100B, and dummy silicon 111 electrically coupled to the surface 306 of the IC die 302 through an interconnect 304. The IC die 100B may be from at least Figure 1A-1CSelected from one or more of the embodiments shown, and may include active circuitry, such as buffer and / or repeater circuitry, for transmitting signals at low input voltages (e.g., input voltages between 1 volt (V) and 2 V), or may not include active circuitry (e.g., may include only conductive traces 120 and conductive vias 122, as shown in FIGS. 1-3). The microelectronic assembly 400 has a plurality of IC dies 113 electrically coupled at respective top surface 106A and bottom surface 106B, and RDL 182 is located between the IC dies 113. RDL 182 may include conductive paths 196 that electrically couple the IC dies 113 to the IC die 100B through interconnects 304 at respective surfaces 106A, 106B of the IC die 100B.

[0114] Figure 6C is a schematic perspective view of another example IC package 500 in accordance with some embodiments of the present disclosure. The embodiment shown in the figure is similar to Figure 6A the embodiment of, except that the IC package 500 does not include dummy silicon 111 and the microelectronic assembly 400 further includes an IC die 115. In some embodiments, the IC package 500 may also include dummy silicon 111 (not shown).

[0115] Figure 6D is in accordance with some embodiments of the present disclosure Figure 6C of the IC package 500. As Figure 6D shown, the IC package 500 may include a microelectronic assembly 400 and a plurality of IC dies 100B on opposite sides of the microelectronic assembly 400. The plurality of IC dies 100B and the microelectronic assembly 400 may be electrically coupled to the surface 306 of the IC die 302 through interconnects 304. The plurality of IC dies 100B may be selected from at least Figure 1A-1CSelected from one or more embodiments shown, and may include active circuitry, such as buffer and / or repeater circuitry, for transmitting signals at low input voltages (e.g., input voltages between 1 volt (V) and 2 V), or may not include active circuitry. Multiple IC dies 100B may be bonded together at respective surfaces 106A, 106B (e.g., as described above with reference to FIGS. 2-4). The microelectronic assembly 400 may include multiple IC dies 113 and IC die 115 that are electrically coupled at respective top surface 106A and bottom surface 106B, with RDL 182 located between the separate IC dies 113, 115. RDL 182 may include conductive vias 196 that electrically couple IC dies 113, 115 to IC die 100B via interconnects 304 (e.g., interconnects 304 at the interface along the z-axis between IC die 100B and IC dies 113, 115). In some embodiments, IC die 115 is the top IC die and / or bottom IC die in the microelectronic assembly 400, as shown. In some embodiments, IC die 115 may be stacked between IC dies 113. The microelectronic assembly 400 may include any suitable number and arrangement of IC dies 113, 115. For example, the microelectronic assembly 400 may include between 1 and 2 IC dies 115 and between 30 and 38 IC dies 113.

[0116] Figure 6E is a schematic perspective view of another example IC package 500 according to some embodiments of the present disclosure. The embodiment shown in the figure is similar to Figure 6C the embodiment of, except that the IC package 500 further includes dummy silicon 111 between the IC die 100B at the four sides of the microelectronic assembly 400 and the multiple IC dies 100B.

[0117] Although FIG. 6 shows a specific number and arrangement of IC dies 100B and the microelectronic assembly 400, the IC package 500 may have any suitable number and arrangement of IC dies 100B and the microelectronic assembly 400, including IC dies 113, IC die 115, and dummy silicon 111.

[0118] Figure 7A is a schematic perspective view of another example IC package 500 according to some embodiments of the present disclosure. The embodiment shown in the figure is similar to Figure 6AEmbodiments, in addition to the multilayer 105 of stacked microelectronic components 400, stacked IC dies 100C, and stacked dummy silicon 111 in the IC package 500. Specifically, the first layer 105(1) may include a microelectronic component 400(1), an IC die 100C(1), and a dummy silicon 111(1), and the second layer 105(2) may include a microelectronic component 400(2), an IC die 100C(2), and a dummy silicon 111(2), where the second layer 105(2) is on the first layer 105(1). The IC die 100C(1) may be electrically coupled to the IC die 302 at the side surface 104(1). The IC die 100C may be selected from one or more of the embodiments shown at least in Figure 1A-1C and may include voltage regulator (VR) circuitry. The VR circuitry may include electronic components and circuitry for maintaining a constant voltage, such as a voltage input, a voltage output, an input capacitor, an output capacitor, an inductor, a switching transistor and / or diode, and a control circuit having multiple transistors to perform voltage regulation and control the switching transistor and / or diode. In various embodiments, the VR circuitry may include various voltage rails configured to provide current at correspondingly different voltages. The VR circuitry may be fabricated using a process specifically adapted for voltage regulator circuitry, such as a special silicon process, or a process using III-V devices (e.g., gallium nitride or silicon carbide), such as to support improved power conversion. Compared to a conventional IC package, the IC package 500 of FIG. 7 may provide increased power delivery. The IC package 500 of FIG. 7 including the IC die 100C having VR circuitry achieves a high voltage input (e.g., a voltage input of about 5V), and the current drop along the z-direction (e.g., from the top to the bottom of the IC package 500) is reduced.

[0119] Figure 7B is of an IC package 500 according to some embodiments of the present disclosure Figure 7A A cross-sectional view of the IC package 500. As Figure 7B shown, the IC package 500 may include a first layer 105(1) having a microelectronic component 400(1), an IC die 100C(1), and a dummy silicon 111(1) electrically coupled to the surface 306 of the IC die 302 through an interconnect 304. The IC package 500 may further include a second layer 105(2) located on the first layer 105(1), and the second layer 105(2) may include a microelectronic component 400(2), an IC die 100C(2), and a dummy silicon 111(2). The IC die 100C(2) may be stacked on the IC die 100(1) and coupled at the surface 103 through an interconnect 304 and bonded at the interface 107 through an oxide-to-oxide bond, as described above with reference to Figure 3EAs described above. Any suitable process can be used to bond dummy silicon 111(1) to dummy silicon 111(2), including the interconnect 304, fusion bonding, or diffusion bonding as shown in the figure, as described above with reference to FIG. 5. The microelectronic assembly 400 can include a plurality of IC dies 113 electrically coupled at respective top surfaces 106A and bottom surfaces 106B, and the RDL 182 is located between the IC dies 113. The RDL 182 can include conductive paths 196 that electrically couple the IC dies 113 to the IC die 100C through the interconnect 304 at the respective surfaces 106A, 106B of the IC die 100C. The IC dies 113 can be electrically coupled to the IC die 302 through the IC die 100C. Although FIG. 7 shows a specific number and arrangement of microelectronic assemblies 400, IC dies 100C, and dummy silicon 111, the IC package 500 can have any suitable number and arrangement of microelectronic assemblies 400, IC dies 100C, and dummy silicon 111. Additionally, although FIG. 7 shows an IC package 500 having a specific number of layers, the IC package 500 can have any suitable number of layers, including more than two layers.

[0120] Figure 8A is a schematic perspective view of another example IC package 500 according to some embodiments of the present disclosure. The embodiment shown in the figure is similar to Figure 5A the embodiment, except that the IC package 500 includes an IC die 100B and the microelectronic assembly 400 is rotated 90 degrees and electrically coupled to the surface 306 of the IC die 302 at the side surface 804. The IC die 100B is electrically coupled to the surface 306 of the IC die 302 at the side surface 104.

[0121] Figure 8B is according to some embodiments of the present disclosure Figure 8A of the IC package 500. As Figure 8B shown, the IC package 500 can include a microelectronic assembly 400 having a plurality of IC dies 113 with TSVs 402 electrically coupled (e.g., in a conventional pancake stack) at respective top surfaces 106A and bottom surfaces 106B, and the RDL 182 is located between the IC dies 113, where the microelectronic assembly 400 is rotated 90 degrees (e.g., the surface 804 is at the bottom and faces the IC die 302), and the surface 804 of the microelectronic assembly 400 is electrically coupled to the surface 306 of the IC die 302. Specifically, the conductive paths 196 in the RDL 182 are electrically coupled to the IC 302 through the interconnect 304 at the surface 804, and the TSVs 402 are coupled to the IC die 100B through the interconnect 304 at the respective surfaces 106A, 106B. The IC die 100B can be from at least Figure 1A-1Cselected from one or more of the embodiments shown, and may include active circuitry for delivering power to the IC die 113 or may not include active circuitry. The conductive vias 196 in the RDL 182 may be configured to transmit signals, and the TSVs 402 may be configured to deliver power such that signal delivery is separate from power delivery. Compared to a conventional IC package, Figure 8B the IC package 500 of

[0122] In various embodiments, any feature discussed with reference to any one of FIGS. 1-8 herein may be combined with any other feature to form a package having one or more microelectronic components and one or more IC dies as described herein, e.g., to form a modified IC package 500 or a modified microelectronic component 400. Some such combinations are described above, but in various embodiments, further combinations and modifications are possible. Within the broad scope of the embodiments, various different embodiments described in different figures may be appropriately combined based on specific requirements.

[0123] Example Devices and Components

[0124] The packages disclosed herein (e.g., any of the embodiments shown in FIGS. 1-8 or any other embodiment described herein) may be included in any suitable electronic component. Figures 9-11 Various examples of packages, components, and devices that may be used with or include any IC package as disclosed herein are shown.

[0125] Figure 9 is a side cross-sectional view of an exemplary IC package 2200 that may include components according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a SiP.

[0126] As shown, the package substrate 2252 may be formed of an insulator (e.g., ceramic, stacked film, epoxy film with filler particles therein, etc.) and may have conductive vias extending through the insulator between a first side 2272 and a second side 2274, or between different locations on the first side 2272 and / or between different locations on the second side 2274. These conductive vias may take the form of any interconnect structure including lines and / or vias.

[0127] The package substrate 2252 may include conductive contacts 2263 that are coupled to the conductive vias 2262 through the package substrate 2252, allowing circuitry within the die 2256 and / or the interposer 2257 to be electrically coupled to respective conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).

[0128] IC package 2200 may include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 shown in the figure are solder bumps, but any suitable first-level interconnects 2265 may be used, such as solder bumps, solder pillars, or bonding wires.

[0129] IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the die 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled through the interposer 2257 to conductive paths (not shown), allowing the circuitry within the die 2256 to be electrically coupled to the respective conductive contacts 2261 (or to other devices, not shown, included in the interposer 2257). The first-level interconnects 2258 shown in the figure are solder bumps, but any suitable first-level interconnects 2258 may be used, such as solder bumps, solder pillars, or bonding wires. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; the conductive contact may be recessed into the surface of the component, flush with the surface of the component, or extend away from the surface of the component, and may take any suitable form (e.g., a conductive pad or socket).

[0130] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a molding 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the molding 2268. Example materials that may be used for the underfill material 2266 and the molding 2268 are epoxy resins, as appropriate. A second-level interconnect 2270 may be coupled to the conductive contacts 2264. The second-level interconnect 2270 shown in the figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second-level interconnect 2270 may be used (e.g., pins in a pin grid array arrangement or pads in a land grid array arrangement). The second-level interconnect 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to Figure 10 discussed.

[0131] In various embodiments, any one of die 2256 can be the microelectronic component 300 as described herein. In embodiments where the IC package 2200 includes multiple die 2256, the IC package 2200 can be referred to as a multi-chip package (MCP). The die 2256 can include circuitry for performing any desired function. For example, in addition to one or more of the die 2256 being the microelectronic component 300 as described herein, one or more of the die 2256 can be logic die (e.g., silicon-based die), one or more of the die 2256 can be memory die (e.g., HBM), etc. In some embodiments, any one of the die 2256 can be implemented as discussed with reference to any of the previous figures. In some embodiments, at least some of the die 2256 may not include the implementation as described herein.

[0132] Although the IC package 2200 shown in the figures is a flip-chip package, other package architectures can also be used. For example, the IC package 2200 can be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 can be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two die 2256 are shown in the IC package 2200, the IC package 2200 can include any desired number of die 2256. The IC package 2200 can include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252, or on either side of the interposer 2257. More generally, the IC package 2200 can include any other active or passive components known in the art.

[0133] In some embodiments, the interposer 2257 may not be included in the IC package 2200; instead, the die 2256 can be directly coupled to the conductive contacts 2263 at the first side 2272 via first-level interconnects 2265.

[0134] Figure 10is a cross-sectional side view of an IC device assembly 2300 that can include components according to any of the embodiments disclosed herein. The IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302, which can be, for example, a motherboard. The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and on an opposite second side 2342 of the circuit board 2302; generally, components can be disposed on one or both of the sides 2340 and 2342. In particular, any suitable component of the IC device assembly 2300 can include any one of one or more microelectronic components 300 according to any of the embodiments disclosed herein; for example, any IC package discussed below with reference to the IC device assembly 2300 can take the form of any embodiment of the IC package 2200 discussed above with reference to Figure 9 and can be in the form of any embodiment of the IC package 2200 discussed above.

[0135] In some embodiments, the circuit board 2302 can be a PCB that includes a plurality of metal layers separated from each other by layers of an insulator and interconnected by conductive vias. Any one or more of the metal layers can be formed in a desired circuit pattern to route electrical signals (optionally in combination with other metal layers) between components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 can be a non-PCB package substrate.

[0136] As shown, in some embodiments, the IC device assembly 2300 can include an on-interposer package structure 2336 coupled to the first side 2340 of the circuit board 2302 by a coupling component 2316. The coupling component 2316 can electrically and mechanically couple the on-interposer package structure 2336 to the circuit board 2302 and can include solder balls (as shown), male and female portions of a socket, an adhesive, underfill material, and / or any other suitable electrical coupling structure and / or mechanical coupling structure.

[0137] The on-interposer package structure 2336 can include an IC package 2320 coupled to an interposer 2304 by a coupling component 2318. The coupling component 2318 can take any suitable form depending on the desired function, such as the form discussed above with reference to the coupling component 2316. In some embodiments, the IC package 2320 can be or include the IC package 2200, for example, as described above with reference to Figure 9 and as described. In some embodiments, the IC package 2320 can include at least one microelectronic component 300 as described herein. To avoid cluttering the drawings, the microelectronic component 300 is not specifically shown in the figure.

[0138] Although a single IC package 2320 is shown in the figure, multiple IC packages can be coupled to the interposer 2304; in fact, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate package substrate for bridging the circuit board 2302 and the IC package 2320. Generally, the interposer 2304 can redistribute connections to a wider pitch or reroute connections to different connections. For example, the interposer 2304 can couple the IC package 2320 to the BGA of the coupling component 2316 to couple to the circuit board 2302.

[0139] In the embodiment shown in the figure, the IC package 2320 and the circuit board 2302 are attached to opposite sides of the interposer 2304. In other embodiments, the IC package 2320 and the circuit board 2302 can be attached to the same side of the interposer 2304. In some embodiments, three or more components can be interconnected through the interposer 2304.

[0140] The interposer 2304 can be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 2304 can be formed of alternative rigid or flexible materials, which can include the same materials described above for semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 can include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. The interposer 2304 can also include embedded devices 2314, including both passive and active devices. Such devices can include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices (e.g., radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices) can also be formed on the interposer 2304. The on-interposer package structure 2336 can take the form of any of the on-interposer package structures known in the art.

[0141] In some embodiments, the IC device assembly 2300 can include an IC package 2324 coupled to the first side 2340 of the circuit board 2302 through a coupling component 2322. The coupling component 2322 can take the form of any of the embodiments discussed above with reference to the coupling component 2316, and the IC package 2324 can take the form of any of the embodiments discussed above with reference to the IC package 2320.

[0142] In some embodiments, the IC device assembly 2300 may include a stacked package structure 2334 coupled to the second side 2342 of the circuit board 2302 via a coupling component 2328. The stacked package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together via a coupling component 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may be in the form of any embodiment of the coupling component 2316 discussed above, and the IC package 2326 and / or 2332 may be in the form of any embodiment of the IC package 2320 discussed above. The stacked package structure 2334 may be configured according to any stacked package structure known in the art.

[0143] Figure 11 is a block diagram of an example computing device 2400 that may include one or more IC packages or components of an IC package according to any embodiment disclosed herein. In another example, any one or more components of the computing device 2400 may include any embodiment of the IC package 2200 (e.g., as Figure 9 shown). In yet another example, any one or more components of the computing device 2400 may include the IC device assembly 2300 (e.g., as Figure 10 shown).

[0144] The figure shows a plurality of components included in the computing device 2400, but any one or more of these components may be omitted or replicated depending on the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-chip (SOC) die.

[0145] Additionally, in various embodiments, the computing device 2400 may not include one or more of the components shown in the figure, but the computing device 2400 may include interface circuitry for coupling to one or more components. For example, the computing device 2400 may not include a display device 2406, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include an audio input device 2418 or an audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 2418 or the audio output device 2408 may be coupled.

[0146] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory. The processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and / or a hard disk drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. This memory may be used as a cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0147] In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured to manage wireless communications for transferring data to and from the computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data using modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not.

[0148] The communication chip 2412 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), LTE projects, and any amendments, updates, and / or revisions (e.g., LTE-Advanced project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an abbreviation for Worldwide Interoperability for Microwave Access and is a certification mark for products that pass the conformance and interoperability tests of the IEEE 802.16 standard. The communication chip 2412 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 2412 can operate according to Enhanced Data Rate for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communication chip 2412 can operate according to other wireless protocols. The computing device 2400 can include an antenna 2422 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0149] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, a first communication chip 2412 can be dedicated to short-range wireless communication (e.g., Wi-Fi or Bluetooth), and a second communication chip 2412 can be dedicated to long-range wireless communication (e.g., Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc.). In some embodiments, the first communication chip 2412 can be dedicated to wireless communication, and the second communication chip 2412 can be dedicated to wired communication.

[0150] The computing device 2400 may include a battery / power circuitry 2414. The battery / power circuitry 2414 may include one or more energy storage devices (e.g., a battery or a capacitor) and / or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., an AC line power source).

[0151] The computing device 2400 may include a display device 2406 (or the corresponding interface circuitry as discussed above). For example, the display device 2406 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0152] The computing device 2400 may include an audio output device 2408 (or the corresponding interface circuitry as discussed above). For example, the audio output device 2408 may include any device that produces an audible indicator, such as a speaker, headphones, or earbuds.

[0153] The computing device 2400 may include an audio input device 2418 (or the corresponding interface circuitry as discussed above). The audio input device 2418 may include any device that produces a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output).

[0154] The computing device 2400 may include a GPS device 2416 (or the corresponding interface circuitry as discussed above). The GPS device 2416 may communicate with a satellite-based system and may receive the location of the computing device 2400, as is known in the art.

[0155] The computing device 2400 may include other output devices 2410 (or the corresponding interface circuitry as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0156] The computing device 2400 may include other input devices 2420 (or the corresponding interface circuitry as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0157] The computing device 2400 can have any desired form factor, such as a handheld or mobile computing device (e.g., a phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 can be any other electronic device that processes data.

[0158] Selection Example

[0159] The description of the illustrated implementations of the present disclosure (including what is described in the abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. While specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications will be apparent to those skilled in the relevant art and may be within the scope of the present disclosure.

[0160] The following paragraphs provide various examples of the embodiments disclosed herein.

[0161] Example 1 is an integrated circuit (IC) package that includes a microelectronic component. The microelectronic component includes at least two first IC dies. The at least two first IC dies include memory circuitry. The at least two first IC dies have a first surface and a second surface opposite the first surface, wherein the at least two first IC dies are stacked and electrically coupled at the respective first and second surfaces; and at least one redistribution layer (RDL) between the at least two first IC dies, wherein the RDL includes conductive vias; a second IC die having a first surface, a second surface opposite the first surface, a third surface orthogonal to the first and second surfaces, and a conductive trace parallel to the first and second surfaces and exposed at the third surface, wherein the first surface of the second IC die is electrically coupled to some of the conductive vias in the at least one RDL; and a third IC die having a surface, wherein the second surface of the bottom die in the stack of the at least two first IC dies is electrically coupled to the surface of the third IC die, and wherein the conductive trace exposed at the third surface of the second IC die is electrically coupled to the surface of the third IC die.

[0162] Example 2 can include the subject matter of Example 1 and can further include dummy silicon at the second surface of the second IC die and coupled to the surface of the third IC die.

[0163] Example 3 can include the subject matter of Example 1 or 2 and can further specify that the second IC die is one of a plurality of second IC dies.

[0164] Example 4 may include the subject matter of Example 3 and may further specify that at least one of the at least two first IC dies includes a computing circuitry.

[0165] Example 5 may include the subject matter of Example 3 and may further specify that a plurality of second IC dies are bonded together at respective first and second surfaces.

[0166] Example 6 may include the subject matter of Example 5 and may further include dummy silicon between respective second dies of the plurality of second IC dies bonded together.

[0167] Example 7 may include the subject matter of any one of Examples 1-3 and may further specify that a third IC die includes a computing circuitry.

[0168] Example 8 may include the subject matter of any one of Examples 1-3 and may further specify that the microelectronic component further includes conductive vias passing through at least two first IC dies and the RDL, wherein the conductive vias are electrically coupled to a surface of the third IC die.

[0169] Example 9 may include the subject matter of any one of Examples 1-8 and may further specify that the surface of the third IC die is a first surface and the third IC die further includes a second surface opposite the first surface, and the IC package may further include a package substrate electrically coupled to the second surface of the third IC die.

[0170] Example 10 may include the subject matter of any one of Examples 1-9 and may further specify that the first IC die and the second IC die are electrically coupled to the third IC die by metal-to-metal bonding and dielectric-to-dielectric bonding.

[0171] Example 11 is an integrated circuit (IC) package that includes a first layer. The first layer includes a plurality of first IC die. The plurality of first IC die include memory circuitry. Each of the plurality of first IC die has a first surface and a second surface opposite the first surface. The plurality of first IC die are stacked and coupled at the respective first and second surfaces. At least one first redistribution layer (RDL) is between each of the plurality of first IC die, and the first RDL includes first conductive vias. And a second IC die that includes voltage regulator circuitry. The second IC die has a first surface, a second surface opposite the first surface, a third surface orthogonal to the first and second surfaces, a fourth surface opposite the third surface, and a first conductive trace parallel to the first and second surfaces. At least one of the first conductive traces is exposed at the third surface, and at least one of the first conductive traces is exposed at the fourth surface. And the first surface of the second IC die is electrically coupled to some of the first conductive vias in the first RDL. A second layer on the first layer. The second layer includes a plurality of third IC die. The plurality of third IC die include memory circuitry. Each of the plurality of third IC die has a first surface and a second surface opposite the first surface. The plurality of third IC die are stacked and coupled at the respective first and second surfaces. At least one second redistribution layer (RDL) is between each of the plurality of third IC die, and the second RDL includes second conductive vias. And a fourth IC die that includes voltage regulator circuitry. The fourth IC die has a first surface, a second surface opposite the first surface, a third surface orthogonal to the first and second surfaces, and a second conductive trace parallel to the first and second surfaces and exposed at the third surface. The first surface of the fourth IC die is electrically coupled to some of the second conductive vias in the second RDL. And at least one of the second conductive traces exposed at the third surface of the fourth IC die is electrically coupled to at least one of the first conductive traces exposed at the fourth surface of the second IC die. And a fifth IC die having a surface. The second surface of the first IC die at the bottom of the plurality of first IC die is electrically coupled to the surface of the fifth IC die. And at least one of the first conductive traces exposed at the third surface of the second IC die is electrically coupled to the surface of the fifth IC die.

[0172] Example 12 may include the subject matter of Example 11 and may further include a first dummy silicon at the second surface of the second IC die in the first layer and coupled to the surface of the fifth IC die. And a second dummy silicon at the second surface of the fourth IC die in the second layer.

[0173] Example 13 may include the subject matter of Example 11 or 12, and may further specify that the second IC die is one of a plurality of second IC dies, and the fourth IC die is one of a plurality of fourth IC dies.

[0174] Example 14 may include the subject matter of any one of Examples 11-13, and may further specify that the second layer is electrically coupled to the first layer by metal-metal bonding and dielectric-dielectric bonding.

[0175] Example 15 may include the subject matter of any one of Examples 11-14, and may further specify that the plurality of first IC dies includes first IC dies between thirty (30) and forty (40).

[0176] Example 16 may include the subject matter of any one of Examples 11-15, and may further specify that the plurality of third IC dies includes third IC dies between thirty (30) and forty (40).

[0177] Example 17 is an integrated circuit (IC) package including a microelectronic assembly including at least two first IC dies, the at least two first IC dies including memory circuitry, the at least two first IC dies having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, wherein the at least two first IC dies are stacked and electrically coupled at respective first and second surfaces; at least one redistribution layer (RDL) between each of the at least two first IC dies, wherein the RDL includes conductive vias; and conductive vias orthogonal to and extending through the RDL at the first and second surfaces of the at least two first IC dies; a second IC die having a first surface, a second surface opposite the first surface, a third surface orthogonal to the first and second surfaces, and a conductive trace parallel to the first and second surfaces and exposed at the third surface; and a third IC die having a surface, wherein: the third surface of at least two of the first IC dies in the microelectronic assembly faces the surface of the third die; the conductive vias in the RDL are electrically coupled to the surface of the third IC die; the conductive trace exposed at the third surface of the second IC die is electrically coupled to the surface of the third IC die; and the first surface of the second IC die is electrically coupled to some of the conductive vias in the microelectronic assembly.

[0178] Example 18 may include the subject matter of Example 17, and may further specify that the conductive vias in the RDL are configured to transmit signals, and the conductive vias are configured to conduct power.

[0179] Example 19 may include the subject matter of Example 17 or 18, and may further include dummy silicon at the second surface of the second IC die and coupled to the surface of the third IC die.

[0180] Example 20 may include the subject matter of any one of Examples 17-19 and may further specify that the second IC die is one of a plurality of second IC dies.

Claims

1. An integrated circuit (IC) package, comprising: A microelectronic assembly, the microelectronic assembly comprising: at least two first IC dies including memory circuitry, the at least two first IC dies having a first surface and a second surface opposite the first surface, wherein the at least two first IC dies are stacked and electrically coupled at the respective first and second surfaces; and at least one redistribution layer (RDL) between the at least two first IC dies, wherein the RDL includes conductive pathways; a second IC die having a first surface, a second surface opposite the first surface, a third surface orthogonal to the first and second surfaces, and conductive traces parallel to the first and second surfaces and exposed at the third surface, wherein the first surface of the second IC die is electrically coupled to some of the conductive paths in the at least one RDL; and A third IC die having a surface, wherein the second surface of the bottom die in the stack of at least two first IC dies is electrically coupled to the surface of the third IC die, and wherein the conductive traces exposed at the third surface of the second IC die are electrically coupled to the surface of the third IC die.

2. The IC package according to claim 1, further comprising: Dummy silicon is located at a second surface of the second IC die and coupled to the surface of the third IC die.

3. The IC package according to claim 1, wherein: The second IC die is one of a plurality of second IC dies.

4. The IC package according to claim 3, wherein: At least one of the at least two first IC dies includes computing circuitry.

5. The IC package according to claim 3, wherein: The plurality of second IC dies are bonded together at respective first and second surfaces.

6. The IC package of claim 5, further comprising: Dummy silicon between respective second IC dies of the plurality of second IC dies bonded together.

7. The IC package according to any one of claims 1 to 6, wherein: The third IC die includes computing circuitry.

8. The IC package according to any one of claims 1 to 6, wherein: The microelectronic assembly further comprises: A conductive via passes through the at least two first IC dies and the RDL, wherein the conductive via is electrically coupled to the surface of the third IC die.

9. The IC package according to any one of claims 1 to 6, wherein: The surface of the third IC die is a first surface, and the third IC die further includes a second surface opposite the first surface, and the IC package further includes: A packaging substrate is electrically coupled to the second surface of the third IC die.

10. The IC package according to any one of claims 1 to 6, wherein: The first IC die and the second IC die are electrically coupled to the third IC die through metal-to-metal bonds and dielectric-to-dielectric bonds.

11. An integrated circuit (IC) package, comprising: The first layer comprises: a plurality of first IC dies including memory circuitry, each of the plurality of first IC dies having a first surface and a second surface opposite the first surface, wherein the plurality of first IC dies are stacked and coupled at the respective first and second surfaces, at least one first redistribution layer (RDL) is between respective ones of the plurality of first IC dies, and wherein the first RDL comprises a first conductive path; and a second IC die including voltage regulator circuitry, the second IC die having a first surface, a second surface opposite the first surface, a third surface orthogonal to the first surface and the second surface, a fourth surface opposite the third surface, and first conductive traces parallel to the first surface and the second surface, wherein at least one of the first conductive traces is exposed at the third surface and at least one of the first conductive traces is exposed at the fourth surface, and wherein the first surface of the second IC die is electrically coupled to some of the first conductive paths in the first RDL; a second layer on the first layer, the second layer comprising: a plurality of third IC dies including memory circuitry, each of the plurality of third IC dies having a first surface and a second surface opposite the first surface, wherein the plurality of third IC dies are stacked and coupled at the respective first and second surfaces, at least one second redistribution layer (RDL) is between respective ones of the plurality of third IC dies, and wherein the second RDL includes a second conductive path; and a fourth IC die including a voltage regulator circuit system, the fourth IC die having a first surface, a second surface opposite the first surface, a third surface orthogonal to the first surface and the second surface, and second conductive traces parallel to the first surface and the second surface and exposed at the third surface, wherein the first surface of the fourth IC die is electrically coupled to some of the second conductive paths in the second RDL, and wherein the second conductive traces exposed at the third surface of the fourth IC die are electrically coupled to the at least one of the first conductive traces exposed at the fourth surface of the second IC die; and A fifth IC die having a surface, wherein a second surface of a first IC die at a bottom of the plurality of first IC die is electrically coupled to the surface of the fifth IC die, and wherein at least one of the first conductive traces exposed at a third surface of the second IC die is electrically coupled to the surface of the fifth IC die.

12. The IC package of claim 11, further comprising: a first dummy silicon in the first layer at a second surface of the second IC die and coupled to the surface of the fifth IC die; as well as Second dummy silicon in the second layer at a second surface of the fourth IC die.

13. The IC package according to claim 11, wherein: The second IC die is one of a plurality of second IC dies, and the fourth IC die is one of a plurality of fourth IC dies.

14. The IC package according to any one of claims 11 to 13, wherein: The second layer is electrically coupled to the first layer through metal-to-metal bonding and dielectric-to-dielectric bonding.

15. The IC package according to any one of claims 11 to 13, wherein: The plurality of first IC dies includes between thirty (30) and forty (40) first IC dies.

16. The IC package according to any one of claims 11 to 13, wherein: The plurality of third IC dies includes between thirty (30) and forty (40) third IC dies.

17. An integrated circuit (IC) package, comprising: A microelectronic assembly, the microelectronic assembly comprising: at least two first IC dies including memory circuitry, the at least two first IC dies having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first surface and the second surface, wherein the at least two first IC dies are stacked and electrically coupled at the respective first and second surfaces; at least one redistribution layer (RDL) between respective ones of the at least two first IC dies, wherein the RDL comprises conductive pathways; and a conductive via orthogonal to the first and second surfaces of the at least two first IC dies and extending through the RDL; a second IC die having a first surface, a second surface opposite the first surface, a third surface orthogonal to the first and second surfaces, and conductive traces parallel to the first and second surfaces and exposed at the third surface; and A third IC die having a surface wherein: third surfaces of the at least two first IC dies in the microelectronic assembly face the surface of the third die; the conductive via in the RDL being electrically coupled to the surface of the third IC die; The conductive trace exposed at a third surface of the second IC die is electrically coupled to the surface of the third IC die; and The first surface of the second IC die is electrically coupled to some of the conductive vias in the microelectronic assembly.

18. The IC package of claim 17, wherein: The conductive paths in the RDL are configured to transmit signals, and the conductive vias are configured to deliver power.

19. The IC package of claim 17, further comprising: Dummy silicon is located at a second surface of the second IC die and coupled to the surface of the third IC die.

20. The IC package according to any one of claims 17 to 19, wherein: The second IC die is one of a plurality of second IC dies.

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