Package substrate and method of manufacturing the same

Abstract

A packaging substrate and its manufacturing method, including forming a dielectric layer on a core layer with a wiring layer, and forming a recess exposing the wiring layer on the dielectric layer, and then sequentially forming a first conductive layer, a glue and a second conductive layer in the recess, so that the recess is provided with glue, thereby effectively avoiding the problems of holes, gaps, cracks, delamination and other undesirable conditions when plating copper material in a large area recess.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging technology, and more particularly to a packaging substrate that can meet the needs of automotive or aircraft applications and its manufacturing method. Background Technology

[0002] With the booming development of the electronics industry, electronic products are becoming thinner and smaller in form, and are moving towards high performance, high functionality, and high speed in terms of function.

[0003] Currently, to meet the needs of automotive or aerospace applications, packaging substrates must possess high voltage and high current specifications, thus requiring the design of thicker copper circuit layers (or electrical contact pads) and large-area grounding ports. However, thicker copper circuit layers (or pads) and large-area grounding ports are difficult to meet miniaturization requirements. Therefore, in recent years, technologies such as plasma etching or laser ablation to form large-area grooves to embed circuits (or pads) into dielectric layers have gradually matured.

[0004] like Figure 1 As shown, the existing packaging substrate 1 is manufactured by forming a wiring layer 12 on the core layer 10, and then forming a dielectric layer 14 on the core layer 12. After that, a large-area groove 160 is formed by means of plasma etching or laser ablation, so as to electroplate conductive material 16 in the groove 160 for subsequent use as circuits or solder pads.

[0005] However, in the existing manufacturing process of the packaging substrate 1, the electroplating of copper in a large area (or large aspect ratio) groove 160 can produce defects such as seams, cracks, voids, and even delamination. As a result, the yield and reliability of the packaging substrate 1 are reduced. Therefore, the existing packaging substrate 1 is difficult to apply to automotive or aircraft applications that require high voltage and high current.

[0006] Therefore, overcoming the various problems of the existing technologies has become an urgent issue to be addressed. Summary of the Invention

[0007] The purpose of this invention is to provide a packaging substrate and its manufacturing method to solve at least one of the above-mentioned problems.

[0008] In view of the deficiencies of the prior art, the present invention provides a packaging substrate, comprising: a core layer having a first side and a second side defined opposite to each other and having at least one conductive post communicating with the first side and the second side; a wiring layer formed on the first side and the second side and electrically connected to the conductive post; a dielectric layer formed on the core layer and having at least one recess exposing the wiring layer; a first conductive layer formed on the surface of the recess and electrically connected to the wiring layer; an adhesive formed on the first conductive layer to fill the recess; and a second conductive layer covering the adhesive.

[0009] The present invention also provides a method for manufacturing a packaging substrate, comprising: providing a core layer having a first side and a second side opposite to each other, and having at least one conductive post connecting the first side and the second side, and forming a wiring layer electrically connected to the conductive post on the first side and the second side respectively; forming a dielectric layer on the core layer, wherein the dielectric layer has at least one recess exposing the wiring layer; forming a first conductive layer on the surface of the recess to electrically connect the first conductive layer to the wiring layer; forming an adhesive on the first conductive layer to fill the recess; and forming a second conductive layer on the adhesive to cover the adhesive.

[0010] In some specific embodiments of the aforementioned packaging substrate and its manufacturing method, the colloid is a conductive material.

[0011] In some specific embodiments of the aforementioned packaging substrate and its manufacturing method, the colloid is a non-conductive material.

[0012] In some specific embodiments of the aforementioned packaging substrate and its manufacturing method, the second conductive layer has a protrusion at the location corresponding to the colloid to embed the first conductive layer and cover the colloid.

[0013] In some specific embodiments of the aforementioned packaging substrate and its manufacturing method, a plurality of conductive blind vias are formed in the dielectric layer and electrically connected to the wiring layer.

[0014] In some specific embodiments of the aforementioned packaging substrate, the first conductive layer is also formed on the dielectric layer, and the second conductive layer is also formed on the first conductive layer. The packaging substrate also includes a circuit layer formed on the dielectric layer by patterning the first and second conductive layers to electrically connect the plurality of conductive blind vias.

[0015] In some specific embodiments of the aforementioned method for manufacturing the packaging substrate, the first conductive layer is also formed on the dielectric layer, and the second conductive layer is also formed on the first conductive layer. The method further includes patterning the first conductive layer and the second conductive layer to form a circuit layer on the dielectric layer and electrically connect the plurality of conductive blind vias.

[0016] As can be seen from the above, in the packaging substrate and its manufacturing method of the present invention, the conductive layer (i.e., the first conductive layer and the second conductive layer) is electroplated twice in the recess by means of the configuration of the colloid. This effectively avoids the problems of voids, gaps, cracks, delamination and other defects that occur when all copper is electroplated in a large area of ​​the recess. Therefore, compared with the prior art, the packaging substrate of the present invention can effectively improve the yield and improve the reliability, so as to facilitate its application in automotive or aircraft applications that require high voltage and high current specifications. Attached Figure Description

[0017] Figure 1 This is a partial cross-sectional schematic diagram of an existing packaging substrate.

[0018] Figures 2A to 2G This is a cross-sectional schematic diagram illustrating the manufacturing method of the packaging substrate of the present invention.

[0019] The attached figures are labeled as follows:

[0020] 1,2 package substrate

[0021] 10,20 core layers

[0022] 12, 22a, 22b wiring layers

[0023] 14,24 dielectric layers

[0024] 16 Conductive materials

[0025] 160 groove

[0026] 20a First side

[0027] 20b Second side

[0028] 21 Metal Layer

[0029] 23 Conductive pillars

[0030] 230 Hole-plugging Material

[0031] 240 opening

[0032] 241 Copper Layer

[0033] 25 Line Layer

[0034] 250 conductive blind via

[0035] 251 First conductive layer

[0036] 252 Second conductive layer

[0037] 2520 convex part

[0038] 26 Colloids

[0039] 260 recess

[0040] 8. Substrate

[0041] 9. Hollow

[0042] S-shaped depression

[0043] K Crack Detailed Implementation

[0044] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0045] It should be understood that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the invention, should still fall within the scope of the disclosed technical content. Furthermore, the terms such as "above," "first," "second," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0046] Figures 2A to 2G This is a cross-sectional schematic diagram of the manufacturing method of the packaging substrate 2 of the present invention.

[0047] like Figure 2A As shown, a substrate 8 is provided, which includes a core layer 20 and a metal layer 21 formed on the core layer 20.

[0048] In this embodiment, the core layer 20 will define opposing first sides 20a and second sides 20b, and the core layer 20 is an organic polymer board such as bis(cis-butenediamide) triazine (BT), and the metal layer 21 is copper foil such as copper. For example, the substrate 8 is a copper foil substrate, and the metal layer 21 can be used as a barrier and a seed layer.

[0049] like Figure 2B As shown, a patterning process is performed on the metal layer 21 to form wiring layers 22a and 22b on the first side 20a and the second side 20b of the core layer 20, respectively, and at least one conductive post 23 electrically connected to the wiring layers 22a and 22b is formed in the core layer 20.

[0050] A perforation penetrating the core layer 20 can be formed by laser or machine drilling, and a seed layer or metal layer can be deposited on the perforation wall. In this embodiment, the conductive pillar 23 is a hollow copper pillar with a plugging material 230 formed inside. For example, the plugging material 230 can be an ink material formed by filling methods such as injection, plugging, or coating. In one embodiment, the ink material mainly comprises epoxy ink composites, which have a viscosity of 25 to 55 Pa·s, a glass transition temperature (Tg) of 145 to 180°C, and / or a Young's modulus of 3-10 GPa.

[0051] like Figure 2C As shown, a dielectric layer 24 is formed on the first side 20a and the second side 20b of the core layer 20, and a plurality of openings 240 and at least one recess 260 are formed on each of the dielectric layers 24.

[0052] In this embodiment, the dielectric layer 24 is polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials, and the dielectric layer 24 is bonded to the core layer 20 by lamination. For example, PP material is used as the dielectric layer 24, and a copper layer 241 is provided on one surface of the PP material to press the dielectric layer 24 together.

[0053] Furthermore, the dielectric layer 24 is formed by plasma etching or other methods to form the opening 240 and the recess 260.

[0054] In addition, the recess 260 has a large width-to-depth ratio, which is greater than or equal to 10:20 (≥10:20), such as 10:5 or 10:10.

[0055] like Figure 2D As shown, a first conductive layer 251 is formed on the surface of the recess 260 by electroplating the copper layer 241, and a conductive blind hole 250 electrically connected to the wiring layers 22a, 22b is formed in each of the openings 240.

[0056] In this embodiment, the first conductive layer 251 and the plurality of conductive blind holes 250 are both made of copper, so as to form an integral copper surface on the surface of the dielectric layer 24. For example, a very thin copper seed layer (about 1 to 3 μm) can be formed on the copper layer 241 and the hole wall of the hole 240 firstly, and then the first conductive layer 251 with a thickness of 8 to 10 μm can be formed, so that each hole 240 is completely electroplated with conductive material.

[0057] like Figure 2EAs shown, a plugging process is performed to form a colloid 26 in the recess 260.

[0058] In this embodiment, the colloid 26 is a conductive material, such as a conductive adhesive, to fill the recess 260. For example, the colloid 26 is a conductive adhesive containing materials such as silver, copper, or tin, and its thickness is approximately equal to the thickness of the dielectric layer 24 or coplanar with the surface of the dielectric layer 24. In another embodiment, depending on the voltage / current resistance requirements, a non-conductive material, such as an underfill, can be used as the colloid 26.

[0059] like Figure 2F As shown, a second conductive layer 252 is formed on the dielectric layer 24 to cover the colloid 26.

[0060] In this embodiment, the second conductive layer 252 is formed by covering the copper material with electroplating to achieve the purpose of covering the entire surface. In addition, the second conductive layer 252 may have a protrusion 2520 at the corresponding colloid 26 to embed the first conductive layer 251 and cover the colloid 26.

[0061] like Figure 2G As shown, a patterning process is performed to form a circuit layer 25 electrically connecting each conductive blind via 250 on each dielectric layer 24 by removing a portion of the material of the first conductive layer 251 and the second conductive layer 252.

[0062] In this embodiment, the circuit layer 25 is made of copper, such as using a redistribution layer (RDL) specification. For example, the circuit layer 25 is made by electroplating metal (such as copper) or other methods.

[0063] Therefore, the manufacturing method of the packaging substrate 2 of the present invention mainly utilizes the configuration of the colloid 26 to perform electroplating operations (the first conductive layer 251 and the second conductive layer 252) in the recess 260 in stages, so as to effectively avoid the problems of voids, gaps, cracks, delamination and other defects that occur when all copper material is electroplated in the large area (large aspect ratio) recess 260. Therefore, compared with the prior art, the packaging substrate 2 of the present invention can effectively improve the yield and improve the reliability.

[0064] Furthermore, compared to existing electroplating processes, the method of the present invention uses a multi-stage electroplating process to cover the colloid 26 with the second conductive layer 252, thereby avoiding the problem of depressions.

[0065] In addition, the manufacturing method of the present invention can effectively produce a packaging substrate 2 with a large aspect ratio recess 260, making it suitable for automotive or aircraft applications requiring high voltage and high current.

[0066] The present invention also provides a packaging substrate 2, comprising: a core layer 20, wiring layers 22a, 22b, a dielectric layer 24, a first conductive layer 251, a colloid 26, and a second conductive layer 252.

[0067] The core layer 20 is defined with a first side 20a and a second side 20b, and has at least one conductive post 23 connecting the first side 20a and the second side 20b.

[0068] The wiring layers 22a and 22b are formed on the first side 20a and the second side 20b respectively and are electrically connected to the conductive post 23.

[0069] The dielectric layer 24 is formed on the core layer 20 and has at least one recess 260 that exposes the wiring layers 22a, 22b.

[0070] The first conductive layer 251 is formed on the surface of the recess 260 and is electrically connected to the wiring layers 22a, 22b.

[0071] The colloid 26 is formed on the first conductive layer 251 to fill the recess 260.

[0072] The second conductive layer 252 covers the colloid 26.

[0073] In one embodiment, the colloid 26 is a conductive material.

[0074] In one embodiment, the colloid 26 is a non-conductive material.

[0075] In one embodiment, the second conductive layer 252 may have a protrusion 2520 at the corresponding colloid 26 to embed the first conductive layer 251 and cover the colloid 26.

[0076] In one embodiment, the packaging substrate 2 further includes a plurality of conductive blind vias 250 formed in the dielectric layer 24 and electrically connected to the wiring layers 22a, 22b.

[0077] In one embodiment, the first conductive layer 251 is further formed on the dielectric layer 24, and the second conductive layer 252 is further formed on the first conductive layer 251. The packaging substrate 2 also includes a circuit layer 25 formed on the dielectric layer 24 by patterning the first conductive layer 251 and the second conductive layer 252 to electrically connect the plurality of conductive blind vias 250.

[0078] In summary, the packaging substrate and its manufacturing method of the present invention mainly utilize the configuration of the colloid to electroplat the conductive layer in the recess twice, thereby effectively avoiding the problems of voids, gaps, cracks, delamination and other defects that occur when all copper material is electroplated in a large area of ​​the recess. Therefore, the packaging substrate of the present invention can effectively improve the yield and reliability, making it suitable for automotive or aircraft applications that require high voltage and high current specifications.

[0079] The above embodiments are illustrative of the principles and effects of the present invention and are not intended to limit the invention. Those skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A packaging substrate, comprising: The core layer is defined with a first side and a second side, and has at least one conductive post connecting the first side and the second side; A wiring layer is formed on the first side and the second side and is electrically connected to the conductive pillar; A dielectric layer is formed on the core layer and has at least one recess that exposes the wiring layer; A first conductive layer is formed on the surface of the recess and electrically connected to the wiring layer; The colloid is formed only on the first conductive layer of the recess to fill the recess and is coplanar with the surface of the dielectric layer; as well as A second conductive layer covers the colloid.

2. The packaging substrate as described in claim 1, wherein, The colloid is a conductive material.

3. The packaging substrate as described in claim 1, wherein, The colloid is a non-conductive material.

4. The packaging substrate as described in claim 1, wherein, The second conductive layer has a protrusion at the corresponding colloid to embed the first conductive layer and cover the colloid.

5. The packaging substrate as described in claim 1, wherein, The packaging substrate also includes a plurality of conductive blind vias formed in the dielectric layer and electrically connected to the wiring layer.

6. The packaging substrate as described in claim 5, wherein, The first conductive layer is also formed on the dielectric layer, and the second conductive layer is also formed on the first conductive layer. The packaging substrate also includes a circuit layer formed on the dielectric layer by patterning the first and second conductive layers to electrically connect the plurality of conductive blind vias.

7. A method for manufacturing a packaging substrate, comprising: A core layer is provided, which defines a first side and a second side opposite to each other, and has at least one conductive post connecting the first side and the second side, and a wiring layer electrically connected to the conductive post is formed on the first side and the second side respectively. A dielectric layer is formed on the core layer, wherein the dielectric layer has at least one recess that exposes the wiring layer; A first conductive layer is formed on the surface of the recess so that the first conductive layer is electrically connected to the wiring layer; A colloid is formed only on the first conductive layer of the recess, so that the colloid fills the recess and is coplanar with the surface of the dielectric layer; and A second conductive layer is formed on the colloid so that the second conductive layer covers the colloid.

8. The method for manufacturing the packaging substrate as described in claim 7, wherein, The colloid is a conductive material.

9. The method for manufacturing the packaging substrate as described in claim 7, wherein, The colloid is a non-conductive material.

10. The method for manufacturing the packaging substrate as described in claim 7, wherein, The second conductive layer has a protrusion at the corresponding colloid to embed the first conductive layer and cover the colloid.

11. The method for manufacturing the packaging substrate as described in claim 7, wherein, The manufacturing method also includes forming a plurality of conductive blind vias in the dielectric layer and electrically connecting them to the wiring layer.

12. The method for manufacturing a packaging substrate as described in claim 11, wherein, The first conductive layer is also formed on the dielectric layer, and the second conductive layer is also formed on the first conductive layer. The manufacturing method further includes patterning the first conductive layer and the second conductive layer to form a circuit layer on the dielectric layer and electrically connect the plurality of conductive blind vias.

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