Acoustic noise suppression in PFM-based buck regulators

Abstract

The present disclosure provides a method of determining a pulse frequency modulation (PFM) period of a buck regulator. The PFM period comprises a first charging phase and a first discharging phase, and wherein the buck regulator switches from the first discharging phase to the first charging phase based on comparing a feedback voltage to a low threshold voltage. The method generates a pseudo-random pulse at a pseudo-random period, where the pseudo-random period is independent of the low threshold voltage. The method then initiates a transition from a second discharge phase to a second charge phase based on the pseudo-random pulse.

Description

Technical Field

[0001] Aspects of the present disclosure relate to power converters, and more particularly, to acoustic noise suppression in pulse frequency modulation (PFM) buck regulators. Background Art

[0002] A buck regulator is a direct current - direct current (DC - DC) power converter that is designed to provide a lower voltage output from a higher voltage input. The buck regulator manages the energy transfer from the input to the output, making it a useful component in many electronic devices that utilize stable and reduced voltage levels.

[0003] The operation of a PFM buck regulator involves two main phases, namely a charging phase and a discharging phase. During the charging phase (also referred to as the 'on' phase), the control switch within the buck regulator conducts. This allows the input voltage to charge the output capacitor. During the discharging phase (also referred to as the 'off' phase), the switch turns off, and the voltage on the output capacitor discharges through the load. Brief Description of the Drawings

[0004] The described embodiments and their advantages can be best understood with reference to the following description in conjunction with the drawings. These drawings in no way limit any variations in form and detail that may be made by those skilled in the art to the described embodiments without departing from the spirit and scope of the described embodiments.

[0005] Figure 1 is a schematic diagram showing an example system for pseudo - randomly changing the PFM frequency of a buck regulator according to some embodiments of the present disclosure.

[0006] Figure 2 is a graph showing a pseudo - random pulse that triggers a buck regulator to transition from a discharging phase to a charging phase according to some embodiments of the present disclosure.

[0007] Figure 3 is a graph showing a pseudo - random pulse that generates a pseudo - random PFM period according to some embodiments of the present disclosure.

[0008] Figure 4A is a graph showing system 100 operating at a PFM frequency in the audible frequency range when the controller 160 disables pseudo - random pulse generation according to some embodiments of the present disclosure.

[0009] Figure 4B is a graph showing system 100 operating at a PFM frequency in the audible frequency range when the controller 160 enables pseudo - random pulse generation according to some embodiments of the present disclosure.

[0010] Figure 5A flowchart of a method for generating a pseudo - random pulse and providing the pseudo - random pulse to a buck regulator according to some embodiments of the present disclosure.

[0011] Figure 6 A diagram showing an example of a system according to some embodiments of the present disclosure including a power management device coupled to a Type - C USB cable.

[0012] Figure 7 A diagram showing an example of a power management device according to some embodiments of the present disclosure.

[0013] Figure 8 A block diagram showing an example of an integrated circuit (IC) controller 2100 according to some embodiments of the present disclosure including a USB - PD subsystem with a phase - controlled clock generator. Detailed Description

[0014] As described above, the buck regulator uses a charging phase and a discharging phase to regulate the output power to the load. There are several types of buck regulators, one of which is a pulse - frequency modulation (PFM) buck regulator. The PFM period (also referred to as the PFM cycle) is a complete operating cycle in a PFM buck regulator starting from the charging phase to the end of the discharging phase measured in time units (e.g., microseconds). The PFM frequency is the reciprocal of the PFM period and refers to how often the charging and discharging cycles (operating frequency) occur measured in frequency (e.g., Hertz). For example, a PFM period of 50 microseconds is equal to a PFM frequency of 20 KHz.

[0015] The PFM buck regulator uses a reference voltage to set the upper and lower limits of a hysteresis window to control the switching cycle and output voltage regulation. The hysteresis window represents a voltage range corresponding to the desired output voltage. When the buck regulator feedback voltage (e.g., a ratio of the output voltage) reaches the upper limit of the hysteresis window, the buck regulator turns off its switching transistor, thus initiating the discharging phase and reducing the output voltage. Then, when the feedback voltage drops to the lower limit of the hysteresis window, the regulator turns on the switching transistor, starts the charging phase, and increases the output voltage. The time spent during the discharging state is inversely proportional to the load current. If the load current is high, the discharging time spent is low, and vice versa.

[0016] A challenge found in PFM buck regulators is that when the load drops to a level where the PFM period falls within the operating frequency range of audible frequencies, such as making the PFM frequency between 20 Hz and 20 kHz. When the PFM buck regulator operates within the audible frequency range, the buck regulator can generate mechanical vibrations in components (e.g., inductors, capacitors, connectors, etc.) to produce fundamental frequency peaks and harmonics of audible sound. Additionally, the sudden on and off switching of the regulator also generates harmonics, which are frequencies that are integer multiples of the fundamental frequency. Both the fundamental frequency and these harmonics contribute to the overall audible noise of the buck regulator. For example, if the PFM period of the buck regulator is 333.3 microseconds, the PFM frequency is 3 kHz. Thus, the buck regulator generates audible noise at 3 kHz, 6 kHz, 9 kHz, etc. (see Figure 4A and the corresponding text).

[0017] The present disclosure addresses the above and other deficiencies by providing a method of pseudo - randomly changing the PFM period, which in turn attenuates and equalizes the PFM frequency peaks and their harmonic frequencies to form "white noise", thereby removing audible sound from the buck regulator (see more details in Figure 4B and the corresponding text).

[0018] In some embodiments, the method determines the pulse - frequency modulation (PFM) period of a buck regulator that includes a first charging phase and a first discharging phase. The buck regulator switches from the first discharging phase to the first charging phase based on comparing a feedback voltage with a low threshold voltage. The method generates pseudo - random pulses in a pseudo - random period independent of the low threshold voltage. Then, the method initiates a transition from a second discharging phase to a second charging phase based on the pseudo - random pulses. In some embodiments, the method generates pseudo - random pulses in response to determining that the PFM period corresponds to a PFM frequency within the audible frequency range.

[0019] In some embodiments, the method captures multiple PFM periods of the buck regulator and calculates an average PFM period based on the multiple PFM periods. The method generates a pseudo - random number and then calculates a pseudo - random period based on the pseudo - random number and the average PFM period. In some embodiments, the buck regulator switches from the second discharging phase to the second charging phase before the feedback voltage reaches the low threshold voltage.

[0020] In some embodiments, the method provides the pseudo - random pulses to a first input of an OR logic, which produces an OR logic output that selects a high threshold voltage as an input to a comparator. The comparator compares the high threshold voltage with the feedback voltage and generates a comparator output that initiates a transition from the second discharging phase to the second charging phase based on comparing the high threshold voltage with the feedback voltage.

[0021] In some embodiments, the comparator output is fed to a second input of the OR logic. When the feedback voltage reaches the high threshold voltage, the OR logic output then selects the low threshold voltage as the input to the comparator.

[0022] In some embodiments, the method generates a new pseudo-random number and calculates a new pseudo-random period based on the new pseudo-random number and the average PFM period. Then, the method generates a new pseudo-random pulse based on the new pseudo-random period, where the new pseudo-random period is of a duration different from that of the previous pseudo-random period. Then, the method initiates a new transition from a third discharge phase to a third charge phase based on the new pseudo-random pulse.

[0023] As discussed herein, the present disclosure provides a method for improving the operation of a computer system by attenuating PFM frequency peaks and reducing the overall noise of the computer system. Additionally, the present disclosure provides an improvement in the technical field of buck regulator power converters by pseudo-randomly modifying the operating frequency rather than shifting the operating frequency to a higher frequency.

[0024] Figure 1 is a schematic diagram showing an example system for pseudo-randomly changing the PFM frequency of a buck regulator according to some embodiments of the present disclosure.

[0025] System 100 includes a buck regulator circuit system and control logic that generates a pseudo-random pulse for triggering the buck regulator circuit to transition from a discharge cycle to a charge cycle before the feedback voltage reaches the low threshold voltage. A voltage source 105 provides an input voltage to a charging switch 110. The charging switch 110 controls when system 100 enters a charging phase (e.g., closes or conducts) or a discharge phase (e.g., opens or cuts off) and is controlled by PFM enable 150. When the charging switch 110 is in the "conducting" position of the charging phase, the voltage source 105 senses the current through inductor 115 and charges output capacitor 120. When the charging switch 110 is in the "cut-off" position of the discharge phase, the energy stored in output capacitor 120 discharges through load 122. When PFM enable 150 is high, the charging switch 110 is in the "conducting" position of the charging phase. When PFM enable is low, the charging switch 110 is in the "cut-off" position of the discharge phase.

[0026] Comparator 140 sets the state of PFM enable 150 based on comparing the feedback voltage 135 with the reference voltage 148. Resistors 125 and 130 form a voltage divider network that generates the feedback voltage 135, which is the ratio of the output voltage supplied to the load 122. The selector switch 145 selects either the high threshold voltage 146 or the low threshold voltage 147 based on the threshold selector 175. When the threshold selector 175 is high, the selector switch 145 selects the high threshold voltage 146 as the reference voltage 148. When the threshold selector 175 is low, the selector switch 145 selects the low threshold voltage 147 as the reference voltage 148.

[0027] When the system 100 is turned on (e.g., at startup), the feedback voltage 135 is low. The comparator 140 turns the PFM enable 150 to the high state because the positive terminal (reference voltage 148) is higher than the negative terminal (feedback voltage 135). The high PFM enable 150 turns the charging switch 110 to the "on" position of the charging phase and starts charging the output capacitor 120. Additionally, the PFM enable is fed into the OR logic 170 and turns the threshold selector 175 to the high state to keep the selector switch 145 in the high threshold voltage 146 selection.

[0028] The PFM enable 150 remains high until the feedback voltage 135 reaches the reference voltage 148 (high threshold voltage 146), at which point the PFM enable 150 goes low and switches the charging switch 110 to the "off" position of the discharging phase. Additionally, the low PFM enable 150 sets the threshold selector 175 to the low state (when the pseudo-random pulse 165 is low), and the selector switch 145 selects the low threshold voltage 147 as the reference voltage 148. At this time, during the discharging phase, the comparator 140 keeps the PFM enable 150 low because the feedback voltage 135 is higher than the reference voltage 148 (low threshold voltage 147). When the feedback voltage 135 decreases to the reference voltage 148, the comparator 140 turns the PFM enable 150 to high, completing the PFM cycle, and a new charging phase begins.

[0029] To pseudo-randomly change the PFM cycle, which in turn extends the PFM frequency and attenuates the fundamental peak frequency and other harmonic frequencies to form "white noise", the system 100 uses the controller 160 to inject the pseudo-random pulse 165 into the OR logic 170. The controller 160 generates the pseudo-random pulse 165 based on various factors, e.g., when the PFM frequency is within the audible frequency range (for more details see Figure 5and the corresponding text). When the pseudo - random pulse 165 goes high while the PFM enable is low (discharge phase), the OR logic 170 makes the threshold selector 175 go high and makes the selector switch 145 select the high - threshold voltage 146 as the reference voltage 148. At this time, the reference voltage 148 is higher than the feedback voltage 135 and triggers the comparator 140 to make the PFM enable 150 go high. The high PFM enable 150 turns the charge switch 110 to the "on" position of the charge phase and keeps the threshold selector 175 high even when the pseudo - random pulse 165 goes low (for more details, see Figure 2 and the corresponding text). Premature switching from the discharge phase to the discharge phase changes the PFM period and, in turn, extends the PFM frequency (for more details, see Figure 3 Figure 4 and the corresponding text).

[0030] Figure 2 is a diagram showing a pseudo - random pulse that triggers a buck regulator to transition from a discharge phase to a charge phase according to some embodiments of the present disclosure. At time t0, the pseudo - random pulse 165 and the PFM enable 150 are low (discharge phase), which causes the threshold selector 175 to be low. Therefore, the selector switch 145 selects the low - threshold voltage 147 as the reference voltage 148, and the PFM enable 150 remains low because the feedback voltage 135 is higher than the reference voltage 148.

[0031] At time t1, the controller 160 generates the pseudo - random pulse 165, which makes the threshold selector 175 go high and makes the selector switch 145 switch the reference voltage 148 to the high - threshold voltage 146. At this time, since the reference voltage 148 is now higher than the feedback voltage 135, the comparator 140 makes the PFM enable 150 go high, and the buck regulator starts a new charge phase. As can be seen at time t2, although the pseudo - random pulse 165 goes low, the PFM enable 150 remains high until the feedback voltage 135 reaches the reference voltage 148 at time t3, at which point the PFM enable 150 goes low and causes the threshold selector 175 to go low, thus switching the charge switch 110 to the "off" position of the discharge phase.

[0032] Returning to reference time t1, the buck regulator transitions from the discharge phase to the charge phase before the feedback voltage 135 reaches the low - threshold voltage 147 (normal PFM period) based on when the controller 160 generates the pseudo - random pulse 165. When the controller 160 pseudo - randomly changes the time of generating the pseudo - random pulse 165, the controller 160 effectively changes the PFM period and extends the operating frequency of the system 100 (for more details, see Figure 3 、 Figure 4A 、 Figure 4B and the corresponding text).

[0033] Figure 3is a diagram showing pseudo-random pulses that generate pseudo-random PFM periods according to some embodiments of the present disclosure. In some embodiments, the controller 160 generates a pseudo-random number and then calculates a pseudo-random (PR) period based on the pseudo-random number. For example, referring to Figure 5 , the controller 160 can calculate the average PFM period Ts_avg (blocks 510 - 520), generate a pseudo-random number Rn (block 550), and calculate the PR period using Rn and Ts_avg (block 560), where the formula PR period = (.2 * Ts_avg) + (Rn * Ts_avg *.6), which generates a PR period between 20% and 80% of the average PFM period.

[0034] Before time t0, the system 100 is in the discharge phase (PFM enable 150 is low). At time t0, the feedback voltage 135 reaches the low threshold voltage 147 and triggers the comparator 140 to raise the PFM enable 150 to high and enter the charging phase. At time t1, the pseudo-random pulse 165 goes high, but does not change the phase of the system 100 because the system 100 is already in the charging phase at 0. At time t2, the feedback voltage 135 reaches the high threshold voltage 146, and the system 100 starts the discharge phase.

[0035] At time t3, the pseudo-random pulse 165 goes high, causing the PFM enable 150 to go high and enter the charging phase before the feedback voltage 135 reaches the low threshold voltage. At time t4, the feedback voltage 135 reaches the high threshold voltage 146, triggering the PFM enable 150 to go low and enter the discharge phase. At time t5, the pseudo-random pulse 165 goes high, causing the PFM enable 150 to go high and enter the charging phase. As shown in FIG. 300, the pseudo-random pulse 165 makes the PFM period pseudo-random (PR period 1 is a different duration from PR period 2), which transforms the PFM frequency into a pseudo-random frequency (for more details, see Figure 4A , 4B and the corresponding text).

[0036] Figure 4A is a diagram showing the system 100 operating at a PFM frequency in the audible frequency range when the controller 160 disables pseudo-random pulse generation according to some embodiments of the present disclosure. FIG. 400 shows the peak 410 switching at 3 kHz from the system 100 and its corresponding harmonics generated at 6 kHz, 9 kHz, etc. As discussed herein, the peak 410 causes mechanical vibrations in the system 100, which in turn generates audible sound.

[0037] Figure 4BFIG. 450 is a diagram showing a system 100 operating at a PFM frequency in an audible frequency range when the controller 160 enables pseudo-random pulse generation, according to some embodiments of the present disclosure. FIG. 450 shows that the peak 410 is attenuated due to the pseudo-random pulses that cause the PFM period to become a pseudo-random period. Thus, the pseudo-random period is converted to white noise on FIG. 450, thereby minimizing mechanical vibrations and the corresponding audible noise from the system 100.

[0038] Figure 5 FIG. 500 is a flowchart of a method for generating pseudo-random pulses and providing the pseudo-random pulses to a buck regulator, according to some embodiments of the present disclosure. The method 500 may be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, programmable logic, a processor, a processing device, a central processing unit (CPU), a system-on-chip (SoC), etc.), software (e.g., instructions running / executed on a processing device), firmware (e.g., microcode), or a combination thereof. In some embodiments, at least a portion of the method 500 may be executed by the controller 160, Figure 6 and 7 the apparatus 620 shown in Figure 8 FIG. 6, the IC controller 2100 shown in

[0039] FIG. Figure 5 6, or a combination thereof.

[0040] Referring Figure 5 to FIG. 500, the method 500 begins at block 510, where the processing logic measures the PFM period of the buck regulator. For example, the processing logic may detect the period between the starts of the charging phases. At block 520, the processing logic calculates the average of X consecutive PFM periods. For example, the processing logic may sample five PFM periods (e.g., 50 uS, 51 uS, 52 uS, 53 uS, and 54 uS) and calculate the average of the PFM periods (e.g., 52 uS).

[0041] At block 530, the processing logic begins sampling a timer (e.g., 50 ms) to check Ts_avg. At block 540, the processing logic determines whether the average PFM period is greater than 50 microseconds, which is equivalent to less than 20 kHz PFM frequency and within the audible frequency range. If the average period is not greater than 50 microseconds, indicating that the PFM frequency is greater than 20 kHz, then block 540 branches to no branch, and thus at block 545, the processing logic waits for the sampling timer to expire. Once expired, the processing logic loops back to block 510 and repeats blocks 510 to 540.

[0042] When the average PFM period is greater than 50 microseconds, indicating that the PFM frequency is within the audible frequency range, at block 540, the processing logic branches to the "yes" branch, and thus at block 550, the processing logic generates a pseudo-random number (Rn), e.g., a number between 0 and 1. At block 560, the processing logic calculates a pseudo-random period for generating a pulse based on the random number. In some embodiments, the processing logic calculates the pseudo-random period based on the average PFM period (Ts_avg). For example, the processing logic may calculate a pseudo-random (PR) period to generate a random pulse based on the formula PR period = (.2 * Ts_avg) + (Rn * TS_avg *.6), which generates a random period between 20% and 80% of the average PFM period.

[0043] At block 570, the processing logic generates a pseudo-random pulse at the pseudo-random period and sends the pseudo-random pulse 165 to the OR logic 170, triggering the charging phase in the system 100 as discussed herein (for more details see Figure 2 、 Figure 3 and the corresponding text). At block 580, the processing logic determines whether the sampling timer has expired. In some embodiments, the processing logic executes block 580 to reduce processing resources by reusing TS-avg. If the sampling timer has not expired, then the processing logic branches to no branch and generates another (different) pseudo-random number at block 550. The processing logic then repeats blocks 560 and 570 to generate another pseudo-random period and the corresponding pseudo-random pulse at other pseudo-random periods. This loop continues until the sampling timer has expired, at which point the processing logic branches to the "yes" branch, which loops back to execute blocks 510 to 540 and determines whether the PFM frequency is still within the audible frequency range (e.g., the PFM period is greater than 50 microseconds).

[0044] Figure 6FIG. is an example of a system including a power management device coupled in a Type-C USB cable, according to some embodiments of the present disclosure. In some embodiments, the system 600 supports 3A (amp) requirements, 5A requirements, or a combination thereof. In some embodiments, the system 600 supports an Extended Power Range (EPR), where the maximum power is up to 240W (48V / 5A). In some embodiments, the system 600 is compatible and / or compliant with USB Type-C TM cables defined in various editions and / or versions of the USB Type-C TM specification (e.g., such as Edition 1.0, Edition 1.1, etc.). TM The USB Type-C TM specification defines a Type-C TM socket, a Type-C TM plug, and a Type-C TM cable that are capable of supporting USB communication and power transfer over updated USB power transfer protocols defined in various revisions / versions of the Universal Serial Bus Power Delivery (USB-PD) specification. Examples of USB Type-C TM functionality and requirements can include, but are not limited to, data and other communication according to USB 2.0 and USB 3.0 / 3.1 / 3.2, electromechanical definitions and performance requirements for Type-C TM cables, electromechanical definitions and performance requirements for Type-C TM sockets, electromechanical definitions and performance requirements for Type-C TM plugs, requirements for traditional cable assemblies and adapters, requirements for device detection and interface configuration based on Type-C TM requirements for optimized power transfer for Type-C TM connectors (also known as USB-C connectors), etc.

[0045] The system 600 includes a USB-C connector 610 and a subsystem 615. The subsystem 615 includes an inductor 115 and a capacitor 120 (shown in Figure 1 ), and a power management device 620. In some embodiments, the power management device 620 includes a controller 160, an OR logic 170, a selector switch 145, a comparator 140, and Figure 1 other circuit components as shown (for more details, see Figure 7 and the corresponding text).

[0046] Figure 7 FIG. is an example of a power management device according to some embodiments of the present disclosure. Figure 7More details of the power management device 620 are shown. It can be seen that the power management device 620 includes a buck regulator 700, which includes a controller 160, an OR logic 170, a selector switch 145, a comparator 140, and Figure 1 the other circuit components shown. In some embodiments, the power management device is configured to control (and / or otherwise operate) a power converter that is compatible and / or compliant with a particular revision and / or version of the USB-PD specification (e.g., such as Revision 1.0, Revision 2.0, Revision 3.0, etc., or subsequent revisions / versions thereof). The USB-PD specification defines a standard protocol that is designed to enable maximum functionality of USB-enabled devices by providing more flexible power delivery and data communication over a single USB Type-C TM port over a single USB Type-C TM cable. The USB-PD specification also describes the architecture, protocol, power behavior, parameters, and wiring required to manage power delivery over a USB Type-C TM cable at powers up to 100W (or higher if compliant with the Extended Power Range (EPR) technology). According to the USB-PD specification, a device with a USB Type-C TM port (e.g., a USB-enabled device) can negotiate for more current and / or higher or lower voltages over a USB Type-C TM cable compared to what was allowed in older USB specifications (e.g., USB2.0 specification, USB3.1 specification, USB Battery Charging Specification Rev.1.1 / 1.2, etc.). For example, the USB-PD specification defines the requirements for a PD contract that can be negotiated between a pair of USB-enabled devices. The PD contract can specify both the power levels that the two devices can accommodate and the direction of power transfer, and can be renegotiated dynamically (e.g., without either device being unplugged) upon request by either device and / or in response to various events and conditions (e.g., power role swap, data role swap, hard reset, power failure, etc.).

[0047] Figure 8 is a block diagram illustrating an example of an integrated circuit (IC) controller 2100 that includes a USB-PD subsystem with a phase-locked clock generator according to some embodiments of the present disclosure. The IC controller 2100 is an example semiconductor device configured according to the controller 160 and the buck regulator circuitry and functionality discussed herein. In Figure 8In the illustrated embodiment, the IC controller 2100 is a single-chip IC controller fabricated on a semiconductor die. In another example, the IC controller 2100 can be a single-chip IC fabricated as a system-on-chip (SoC). In other embodiments, the IC controller 2100 can be a multi-chip module encapsulated in a single semiconductor package. Among other components, the IC controller 2100 includes a central processing unit (CPU) subsystem 2102, a system interconnect 2112, a peripheral interconnect 2114, system resources 2116, an input / output (I / O) subsystem 2118, a USB-PD subsystem 2120, and various terminals (e.g., pins) configured to receive and transmit signals.

[0048] The CPU subsystem 2102 includes one or more CPUs 2104, a flash memory 2106, an SRAM (static random access memory) 2108, and a ROM (read-only memory) 2110 coupled to the system interconnect 2112. The CPU 2104 is a suitable processor that can operate in an IC or SoC device. The flash memory 2106 is a non-volatile memory (e.g., NAND flash, NOR flash, etc.) configured to store data, programs, and / or other firmware instructions. The flash memory 2106 is tightly coupled within the CPU subsystem 2102 to improve access time. The SRAM 2108 is a volatile memory configured to store data and firmware instructions accessed by the CPU 2104. The ROM 2110 is a read-only memory (or other suitable storage medium) configured to store boot routines, configuration parameters, and other firmware parameters and settings. The system interconnect 2112 is a system bus (e.g., a single-level or multi-level advanced high-performance bus or AHB) configured as an interface to couple the various components of the CPU subsystem 2102 to each other and as a data and control interface between the various components of the CPU subsystem and the peripheral interconnect 2114.

[0049] The peripheral interconnect 2114 is a peripheral bus (e.g., a single-level or multi-level AHB) that provides the primary data and control interface between the CPU subsystem 2102 and its peripheral devices and other resources (e.g., system resources 2116, I / O subsystem 2118, and USB-PD subsystem 2120). The peripheral interconnect 2114 can include various controller circuits (e.g., direct memory access or DMA controllers) that can be programmed to transfer data between peripheral blocks without burdening the CPU subsystem 2102. In various embodiments, each component of the CPU subsystem and the peripheral interconnect can be different from each selection or type of CPU, system bus, and / or peripheral bus.

[0050] System resources 2116 include various electronic circuits that support the operation of the IC controller 2100 in its various states and modes. For example, system resources 2116 may include a power subsystem that has analog and / or digital circuits required for each controller state / mode, such as, for example, a sleep control circuit, a wake interrupt controller (WIC), a power-on reset (POR), a voltage and / or current reference (REF) circuit, etc. In some embodiments, the power subsystem may also include circuits that allow the IC controller 2100 to draw power from and / or supply power to an external source at several different voltage and / or current levels and support controller operation in several power states 2117 (such as, for example, an active state, a sleep state, and a deep sleep state with clock off). Additionally, in some embodiments, the CPU subsystem 2102 may be optimized for low-power operation with extensive clock gating and may include various internal controller circuits that allow the CPU to operate in various power states 2117. For example, the CPU may include a wake interrupt controller that is configured to wake the CPU from a sleep state, thereby allowing power to be cut off when the IC chip is in a sleep state. System resources 2116 may also include a clock subsystem that has analog and / or digital circuits for clock generation and clock management, such as, for example, a clock control circuit, a watchdog timer (WDT) circuit, an internal low-speed oscillator (ILO) circuit, and an internal master oscillator (IMO) circuit. System resources 2116 may also include analog and / or digital circuit blocks that provide reset control and support for an external reset (XRES).

[0051] In various embodiments, the I / O subsystem 2118 may include various different types of I / O blocks and subsystems. For example, in Figure 8 the illustrated embodiment, the I / O subsystem 2118 includes a GPIO (general-purpose input / output) block 2118a, a TCPWM (timer / counter / pulse-width modulation) block 2118b, and an SCB (serial communication block) 2118c. The GPIO 2118a includes analog and / or digital circuits that are configured to implement various functions, such as, for example, pull-up, pull-down, input threshold selection, input and output buffer enable / disable, multiplexing connections to various I / O pins, etc. The TCPWM 2118b includes analog and / or digital circuits that are configured to implement a timer, a counter, a pulse-width modulator, a decoder, and various other analog / hybrid-signal components that are configured to operate on input / output signals. The SCB 2118c includes analog and / or digital circuits that are configured to implement various serial communication interfaces, such as, for example, I2C, SPI (serial peripheral interface), UART (universal asynchronous receiver / transmitter), CAN (controller area network) interface, CXPI (clock eXtension peripheral interface), etc.

[0052] The USB-PD subsystem 2120 provides an interface to the USB Type-C port and is configured to support USB communication and other USB functions such as power delivery and battery charging. The USB-PD subsystem 2120 includes the electrostatic discharge (ESD) protection circuitry required on the Type-C port. The USB-PD subsystem 2120 also includes a Type-C transceiver and a physical layer logic (PHY) that is configured to integrate a baseband PHY circuit to perform various digital encoding / decoding functions (such as differential non-return-to-zero inverted - BMC encoding / decoding, cyclic redundancy check CRC, etc.) and analog signal processing functions involved in physical layer transmission. The USB-PD subsystem 2120 also provides termination resistors (RP and RD) and their switches, as required by the USB-PD specification, to enable connection detection, plug orientation detection, and power delivery functions on the Type-C cable. The IC controller 2100 (and / or its USB-PD subsystem 2120) can also be configured to respond to communications defined in the USB-PD specification, such as, for example, SOP (Start of Packet), SOP’, and SOP” messaging. The USB-PD subsystem 2120 may also include a reference and / or phase clock controller 2101 to generate the reference clock signal and the phase-shifted clock signal as described herein.

[0053] In other circuitry, the USB-PD subsystem 2120 may also include: one or more analog-to-digital converters (ADCs) for converting various analog signals to digital signals; a VCONN FET; an error amplifier (ERROR AMP) for controlling the power voltage applied to the VBUS line according to the PD contract; a high voltage regulator (HV REG) for converting the power voltage to the precise voltage required by the IC controller 2100 (such as 3 - 5V); a current sense amplifier (CSA) and an overvoltage protection (OVP) circuit for providing overcurrent (OCP) and overvoltage (OV) protection and undervoltage (UV) protection with configurable thresholds and response times on the VBUS line; a pulse width modulator (PWM); one or more gate drivers (GATE DRV) for controlling the gates of the power switches that turn on and off the power supply on the VBUS line; a low side gate driver (LSDR); a high side gate driver (HSDR) for controlling the switches of a buck-boost converter; a communication channel PHY (CC BB PHY) logic for supporting communication on the Type-C communication channel (CC) lines; a charging protocol detection block (CHG DET) for detecting different types of PD chargers; and at least two on-die discharge (VBUSDISCH) circuits that can discharge the VBUS line voltage to any programmable voltage level within a programmable voltage level range.

[0054] Unless otherwise specifically stated, terms such as "determine", "generate", "initiate", "capture", "calculate", "provide", "produce", etc. refer to actions and processes performed or implemented by a computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computing device into other data similarly represented as physical quantities within the memories or registers of the computing device or other such information storage, transmission, or display devices. Additionally, as used herein, the terms "first", "second", "third", "fourth", etc. are meant as labels to distinguish between different elements and may not necessarily have an order meaning according to their numerical designation.

[0055] The examples described herein also relate to devices for performing the operations described herein. The device may be specially constructed for the desired purpose or it may comprise a general-purpose computing device selectively programmed by a computer program stored in a computing device. Such a computer program may be stored in a non-transitory computer-readable storage medium.

[0056] The methods and illustrative examples described herein are not inherently related to any particular computer or other device. A variety of general-purpose systems may be used in accordance with the teachings described herein, or it may prove convenient to construct a more specialized device to perform the required method steps. The required structure for various such systems will emerge as described in the above description.

[0057] The above description is intended to be illustrative, not restrictive. Although the present disclosure has been described with reference to specific illustrative examples, it will be recognized that the present disclosure is not limited to the examples described. The scope of the present disclosure should be determined with reference to the following claims and the full scope of equivalents to which the claims are entitled.

[0058] As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprises", "comprising", and / or "having" when used herein specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Thus, the terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting.

[0059] It should also be noted that in some alternative embodiments, the indicated functions / actions may occur in the order indicated in the figures. For example, two figures shown consecutively may in fact be executed substantially simultaneously or sometimes in the reverse order, depending on the functions / actions involved.

[0060] Although the method operations are described in a particular order, it should be understood that other operations may be performed between the described operations, the described operations may be adjusted so that they occur at slightly different times, or the described operations may be distributed in a system that allows the processing operations to occur at various intervals associated with the processing.

[0061] Various units, circuits, or other components may be described or claimed as “configured to” or “capable of being configured to” perform one or more tasks. In such contexts, the phrase “configured to” or “capable of being configured to” is used to label a structure by indicating that the unit / circuit / component includes the structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, a unit / circuit / component may be referred to as being configured to perform a task, or capable of being configured to perform a task, even when the specified unit / circuit / component is not currently operating (e.g., is not turned on). A unit / circuit / component that is used in conjunction with “configured to” or “capable of being configured to” language includes hardware—e.g., circuitry, a memory storing program instructions executable to implement the operations, etc. Stating that a unit / circuit / component “is configured to” perform one or more tasks, or “is capable of being configured to” perform one or more tasks, is not intended expressly to invoke 35 U.S.C. § 112(f) with respect to that unit / circuit / component. Additionally, “configured to” or “capable of being configured to” may include a general structure (e.g., a general circuitry) that is manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner that is capable of performing the task(s) being discussed. “Configured to” may also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to fabricate a device (e.g., an integrated circuit) suitable for implementing or performing one or more tasks. “Capable of being configured to” is expressly not intended to apply to a blank medium, an unprogrammed processor, or an unprogrammed general-purpose computer, or an unprogrammed programmable logic device, programmable gate array, or other unprogrammed device, unless accompanied by a programming medium that imparts to the unprogrammed device the ability to be configured to perform the disclosed functions.

[0062] For purposes of explanation, the foregoing description has been made with reference to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles of the embodiments and their practical application to thereby enable others skilled in the art to best utilize the embodiments and various modifications suitable for the particular use contemplated. Accordingly, the embodiments are considered illustrative rather than restrictive, and the disclosure is not limited to the details given herein but may be modified within the scope of the appended claims and their equivalents.

Claims

1. A method comprising: determining a pulse frequency modulation (PFM) cycle of a buck regulator, wherein the PFM cycle includes a first charging phase and a first discharging phase, and wherein the buck regulator switches from the first discharging phase to the first charging phase based on comparing a feedback voltage to a low threshold voltage; generating, by a processing device, a pseudo-random pulse at a pseudo-random period, wherein the pseudo-random period is independent of the lower threshold voltage; and A transition from a second discharge phase to a second charge phase is initiated based on the pseudo-random pulses.

2. The method according to claim 1, further comprising: The pseudo-random pulses are generated in response to determining that the PFM period corresponds to a PFM frequency within an audible frequency range.

3. The method according to claim 1, further comprising: capturing a plurality of PFM cycles of the buck regulator including the PFM cycle; calculating an average PFM cycle based on the plurality of PFM cycles; Generate pseudo-random numbers; as well as The pseudo-random period is calculated based on the pseudo-random number and the average PFM period.

4. The method according to claim 3, further comprising: Generate new pseudo-random numbers; Calculating a new pseudo-random period based on the new pseudo-random number and the average PFM period; generating a new pseudo-random pulse based on the new pseudo-random period, wherein the new pseudo-random period is a different duration than the pseudo-random period; as well as A new transition from the third discharge phase to the third charge phase is initiated based on the new pseudo-random pulses.

5. The method according to claim 1, further comprising: providing the pseudo-random pulse to a first input of an OR logic, wherein the OR logic produces an OR logic output that selects a high threshold voltage as an input to a comparator; comparing the high threshold voltage with the feedback voltage by the comparator; and A comparator output initiating the transition from the second discharge phase to the second charge phase is generated by the comparator based on comparing the high threshold voltage to the feedback voltage.

6. The method according to claim 5, wherein: The comparator output is fed to a second input of the OR logic, and wherein, when the feedback voltage reaches the high threshold voltage, the OR logic output selects the low threshold voltage as the input to the comparator.

7. The method according to claim 1, wherein: Before the feedback voltage reaches the low threshold voltage, the buck regulator switches from the second discharging stage to the second charging stage.

8. A system comprising: Processing device; as well as a memory for storing instructions that, when executed by the processing device, cause the system to: determining a pulse frequency modulation (PFM) cycle of a buck regulator, wherein the PFM cycle includes a first charging phase and a first discharging phase, and wherein the buck regulator switches from the first discharging phase to the first charging phase based on comparing a feedback voltage to a low threshold voltage; generating a pseudo-random pulse at a pseudo-random period, wherein the pseudo-random period is independent of the lower threshold voltage; and A transition from a second discharge phase to a second charge phase is initiated based on the pseudo-random pulses.

9. The system according to claim 8, wherein: In response to executing the instructions, the processing device further causes the system to: The pseudo-random pulses are generated in response to determining that the PFM period corresponds to a PFM frequency within an audible frequency range.

10. The system according to claim 8, wherein: In response to executing the instructions, the processing device further causes the system to: capturing a plurality of PFM cycles of the buck regulator including the PFM cycle; calculating an average PFM cycle based on the plurality of PFM cycles; Generate pseudo-random numbers; as well as The pseudo-random period is calculated based on the pseudo-random number and the average PFM period.

11. The system according to claim 10, wherein: In response to executing the instructions, the processing device further causes the system to: Generate new pseudo-random numbers; Calculating a new pseudo-random period based on the new pseudo-random number and the average PFM period; generating a new pseudo-random pulse based on the new pseudo-random period, wherein the new pseudo-random period is a different duration than the pseudo-random period; and A new transition from the third discharge phase to the third charge phase is initiated based on the new pseudo-random pulses.

12. The system according to claim 8, wherein: In response to executing the instructions, the processing device further causes the system to: providing the pseudo-random pulse to a first input of an OR logic, wherein the OR logic produces an OR logic output that selects a high threshold voltage as an input to a comparator; comparing the high threshold voltage with the feedback voltage by the comparator; and A comparator output initiating the transition from the second discharge phase to the second charge phase is generated by the comparator based on comparing the high threshold voltage to the feedback voltage.

13. The system according to claim 12, wherein: The comparator output is fed to a second input of the OR logic, and wherein, when the feedback voltage reaches the high threshold voltage, the OR logic output selects the low threshold voltage as the input to the comparator.

14. The system according to claim 8, wherein: The buck regulator switches from the second discharging stage to the second charging stage before the feedback voltage reaches the low threshold voltage.

15. The system according to claim 8, wherein: The system is a cable compatible with the Universal Serial Bus Type-C (USB Type-C) specification.

16. A power converter comprising: Buck regulator; as well as a controller circuit system operably coupled to the buck regulator and configured to: determining a pulse frequency modulation (PFM) cycle of the buck regulator, wherein the PFM cycle includes a first charging phase and a first discharging phase; Generates pseudo-random pulses at pseudo-random periods; as well as Comparator circuitry initiates a transition from a second discharge phase to a second charge phase based on the pseudo-random pulses.

17. The power converter according to claim 16, wherein: The controller is also configured to: The pseudo-random pulses are generated in response to determining that the PFM period corresponds to a PFM frequency within an audible frequency range.

18. The power converter according to claim 16, wherein: The controller is also configured to: capturing a plurality of PFM cycles of the buck regulator including the PFM cycle; calculating an average PFM cycle based on the plurality of PFM cycles; Generate pseudo-random numbers; as well as The pseudo-random period is calculated based on the pseudo-random number and the average PFM period.

19. The power converter according to claim 17, wherein: The controller is also configured to: Generate new pseudo-random numbers; Calculating a new pseudo-random period based on the new pseudo-random number and the average PFM period; generating a new pseudo-random pulse based on the new pseudo-random period, wherein the new pseudo-random period is a different duration than the pseudo-random period; and A new transition from the third discharge phase to the third charge phase is initiated based on the new pseudo-random pulses.

20. The power converter of claim 16, wherein: The comparator circuit system further comprises: OR logic circuitry, wherein the OR logic circuitry is configured to receive the pseudo-random pulses at a first input and to generate an OR logic output that selects a high threshold voltage; and A comparator, the comparator being configured to: receiving the high threshold voltage as input; comparing the high threshold voltage to a feedback voltage of the buck regulator; and Based on comparing the high threshold voltage to the feedback voltage, a comparator output is generated that initiates the transition from the second discharge phase to the second charge phase.

21. The power converter according to claim 20, wherein: The comparator output is fed to a second input of the OR logic circuitry, and wherein, when the feedback voltage reaches the high threshold voltage, the OR logic output selects a low threshold voltage as the input to the comparator.

22. The power converter of claim 16, wherein: The power converter is compatible with the Universal Serial Bus Power Delivery (USB-PD) specification.

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