A load transient enhancement circuit for voltage-mode DCDC converters

Abstract

An embodiment of the present invention discloses a load transient enhancement circuit for a voltage-mode DC-DC converter. The conventional Type 3 compensation network is improved by using a compensation transconductance amplifier to generate a zero-point adjustable compensation network for loop compensation, and then the zero point is adjusted by detecting the output voltage. When an overshoot current causes the output voltage to exceed the threshold, the transconductance can be increased by changing the tail current to move the zero point toward a low frequency, thereby increasing the bandwidth and improving the transient response capability. The embodiment of the present invention generates a zero-point adjustable compensation network by adding a feedback path to compensate the loop, and adjusts the adjustable zero point by detecting the output voltage. When the load jumps, the bandwidth is increased by moving the zero point toward a low frequency, thereby enhancing the load response capability and reducing the output voltage overshoot.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuits, and in particular to a load transient enhancement circuit of a voltage-mode DC-DC converter. Background Art

[0002] Voltage-mode DC-DC converters are widely used in power management. Common topologies include buck, buck-boost, and boost. The LC filter in the output stage of a voltage-mode DC-DC converter generates a double pole, requiring a compensation network for stability. The most typical compensation network is the Type 3 compensation network. This analog compensation network generates two fixed zeros to compensate for the two poles generated by the LC. A disadvantage is that voltage-mode DC-DC converters have slow load transient response, resulting in large output voltage overshoot. A common solution is to sample the inductor current and add a current loop to regulate the system. However, sampling the inductor current requires the use of a sampling resistor, increasing system power consumption. Furthermore, the addition of a current loop can generate subharmonic oscillations when the duty cycle of the DC-DC converter in PWM mode exceeds 50%, requiring harmonic compensation, which increases system complexity and power consumption. Summary of the Invention

[0003] To this end, an embodiment of the present invention provides a load transient enhancement circuit for a voltage-mode DCDC converter to solve the technical problem that the existing technology increases circuit power consumption and complexity by adding a current loop to regulate the voltage-mode DCDC converter, and requires harmonic compensation.

[0004] In order to achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0005] According to a first aspect of an embodiment of the present invention, a load transient enhancement circuit for a voltage-mode DC-DC converter is provided, wherein the load transient enhancement circuit comprises a power supply, a Buck power stage, a control loop compensation circuit, a load transient enhancement circuit, and a PWM circuit;

[0006] The control loop compensation circuit is composed of a fixed zero point compensation circuit and a zero point adjustable compensation circuit. The fixed zero point compensation circuit is a voltage divider network, and the zero point adjustable compensation circuit is composed of two feedback paths.

[0007] The Buck power stage is connected in parallel with the power supply, the output end of the Buck power stage is connected to the comparator and voltage divider circuit of the load transient enhancement circuit, the operational transconductance amplifier of the first feedback path is connected to the variable operational transconductance amplifier of the second feedback path, the operational transconductance amplifiers of the two feedback paths generate a zero-point adjustable compensation network for loop compensation, and the AND gate of the load transient enhancement circuit is connected to the PMOS transistor of the second feedback path;

[0008] The comparator of the load transient enhancement circuit is connected to the output terminal, and the comparator and the AND gate together control the on and off of the PMOS tube, thereby making the variable zero point larger and moving toward low frequency, increasing the unity gain bandwidth, and enhancing the transient response capability;

[0009] The PWM circuit is connected to the PMOS tube of the Buck power stage and is also connected to the output end of the feedback path. The output voltage of the two feedback paths controls the on and off of the PMOS tube of the Buck power stage by controlling the PWM circuit.

[0010] Furthermore, the Buck power stage is composed of a first control tube and two resistors, an inductor, a diode and a capacitor, including:

[0011] The first control tube is connected in series with the inductor L. The first control tube and the inductor L are also connected to the cathode of the diode D1. The other end of the inductor L is connected to the resistor R ESR and resistor R LOAD connected, the resistor R ESR The other end of the capacitor C0 is connected to the resistor R LOAD are connected.

[0012] Furthermore, the Buck power stage is composed of a first control tube and two resistors, an inductor, a diode and a capacitor, including:

[0013] The first control tube end of the Buck power stage is connected to the positive electrode of the voltage source and the SR latch respectively, the positive electrode of the diode D1 and the other end of the capacitor C0 are connected to the negative electrode of the voltage source respectively, and the negative electrode of the voltage source is grounded.

[0014] Furthermore, the voltage divider network is composed of three resistors and one capacitor, specifically including:

[0015] Resistor R1 is connected in series with resistor R2, and the other end of resistor R1 is grounded. Resistor R3 is connected in series with capacitor C3, and resistor R3, capacitor C3 and resistor R2 are connected in parallel. The end of resistor R2 and capacitor C3 away from ground is connected to the inductor L of the Buck power stage and the resistor R ESR and resistor R LOAD One end of the resistor R1 away from the ground is connected to the VFB end of the first operational transconductance amplifier of the first feedback path and the VFB end of the variable operational transconductance amplifier of the second feedback path respectively.

[0016] Furthermore, the first feedback path is composed of a two-stage operational transconductance amplifier, specifically comprising:

[0017] The first operational transconductance amplifier and the second operational transconductance amplifier are connected in series, the output end of the second operational transconductance amplifier is connected to the output impedance resistor ro2, the other end of the output impedance resistor ro2 is grounded, and the output end of the first operational transconductance amplifier is respectively connected to the compensation capacitor C1 and the output impedance resistor ro1, and the other ends of the compensation capacitor C1 and the output impedance resistor ro1 are grounded.

[0018] Furthermore, the second feedback path is composed of a variable operational transconductance amplifier, a first current mirror, a second current mirror, and a second control tube, and specifically includes:

[0019] The output end of the variable operational transconductance amplifier is connected to the output end of the first operational transconductance amplifier. The first current mirror and the second current mirror provide input stage bias current for the variable operational transconductance amplifier. One end of the second current mirror is connected to the second control tube and the output end of the AND gate of the load transient enhancement circuit. The VFB end of the variable operational transconductance amplifier is connected to the end of the resistor R1 in the voltage divider circuit away from the ground. The second control tube is connected to the second current mirror and the variable operational transconductance amplifier.

[0020] Furthermore, the load transient enhancement circuit is composed of a two-way multiplexer, a comparator, an AND gate and a threshold signal, and specifically includes:

[0021] The two input terminals of the AND gate are connected to the control terminal c of the 2-way multiplexer respectively. At the same time, the input terminals of the AND gate are also connected to the output terminals of the two comparators respectively. The positive input terminal of the first comparator is connected to the output terminal of the first multiplexer, and the negative input terminal of the first comparator is connected to the R LOAD One end of the resistor is connected to the positive input end of the second comparator, the negative input end of the first comparator is also connected to the resistor R2 and one end of the capacitor C3 of the voltage divider circuit, and the negative input end of the second comparator is connected to the control end of the second multiplexer.

[0022] Furthermore, the output end of the AND gate is connected to a second controller, and the second controller is a PMOS tube.

[0023] Furthermore, the first input terminal of the first comparator inputs the threshold signal VOH, and the second input terminal inputs the threshold signal VOHHYS; the first input terminal of the second comparator inputs the threshold signal VOL, and the second input terminal inputs the threshold signal VOLHYS.

[0024] Furthermore, the PWM circuit is composed of an SR latch, a pulse width modulator and an oscillator, specifically including:

[0025] The SR latch is connected to the first control tube of the Buck power stage and is also connected to the output end of the pulse width modulator. The input end of the pulse width modulator is respectively connected to the output end of the adjustable operational transconductance amplifier and the oscillator. The oscillator is also connected to the SR latch.

[0026] The embodiments of the present invention have the following advantages:

[0027] The load transient enhancement circuit of the embodiment of the present invention is composed of a power supply, a Buck power stage, a control loop compensation circuit, a load transient enhancement circuit and a PWM circuit; the control loop compensation circuit is composed of a fixed zero compensation circuit and a zero adjustable compensation circuit, the fixed zero compensation circuit is a voltage divider network, and the zero adjustable compensation circuit is composed of two feedback paths; the Buck power stage is connected in parallel with the power supply, the output end of the Buck power stage is connected to the comparator and the voltage divider circuit of the load transient enhancement circuit, the operational transconductance amplifier of the first feedback path is connected to the variable operational transconductance amplifier of the second feedback path, and the two feedback paths are connected. An operational transconductance amplifier generates a zero-point adjustable compensation network for loop compensation. The AND gate of the load transient enhancement circuit is connected to the PMOS transistor of the second feedback path. The comparator of the load transient enhancement circuit is connected to the output end. The comparator and the AND gate together control the on / off of the PMOS transistor, thereby increasing the variable zero point and moving it toward low frequencies, increasing the unity gain bandwidth, and enhancing transient response capability. The PWM circuit is connected to the PMOS transistor of the Buck power stage and also to the output end of the feedback path. The output voltages of the two feedback paths control the on / off of the PMOS transistor of the Buck power stage by controlling the PWM circuit. In this embodiment of the present invention, a zero-point adjustable compensation network is generated by adding a feedback path to compensate for the loop, and the adjustable zero point is adjusted by detecting the output voltage. When the load changes, the bandwidth is increased by shifting the zero point toward low frequencies, thereby enhancing the system's load response capability and reducing output voltage overshoot. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other implementation drawings based on the provided drawings without inventive effort.

[0029] The structures, proportions, sizes, etc. illustrated in this specification are intended only to complement the contents disclosed herein and to facilitate understanding and reading by persons familiar with the art. They are not intended to limit the conditions under which the present invention may be implemented and therefore have no substantive technical significance. Any structural modifications, changes in proportions, or adjustments in sizes, without affecting the efficacy and objectives of the present invention, shall still fall within the scope of the technical contents disclosed herein.

[0030] Figure 1 It is a schematic diagram of the structure of an existing voltage-mode DCDC converter;

[0031] Figure 2 A schematic structural diagram of a load transient enhancement circuit for a voltage-mode DCDC converter provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following describes the implementation of the present invention using specific embodiments. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. Obviously, the embodiments described are only a portion of the present invention, not all of it. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are intended to fall within the scope of protection of the present invention.

[0033] Voltage-mode DC-DC converters are widely used in power management. Common topologies include Buck, Buck-boost, and Boost. The LC filter in the output stage of a voltage-mode DC-DC converter generates a double pole, requiring a compensation network for stability. The most typical compensation network is the Type 3 compensation network. Figure 1 The type 3 analog compensation network generates two fixed zeros to compensate for the two poles generated by LC. The disadvantage is that the voltage-mode DCDC converter has a slow load transient response, resulting in a large output voltage overshoot.

[0034] The existing method samples the inductor current and then adds a current loop to regulate the system. The disadvantages of adding a current loop are: 1) Sampling the inductor current requires the use of a sampling resistor, increasing system power consumption; 2) Adding a current loop can cause subharmonic oscillations when the DC-DC duty cycle in PWM mode exceeds 50%, requiring harmonic compensation, increasing system complexity and power consumption.

[0035] In order to solve the above-mentioned problem of increasing circuit power consumption and complexity by adding a current loop to regulate the voltage-mode DCDC converter, a technical problem of harmonic compensation is required.

[0036] refer to Figure 2The present invention discloses a load transient enhancement circuit for a voltage-mode DC-DC converter. This circuit improves upon the traditional Type 3 compensation network by employing a compensation transconductance amplifier to generate a zero-point adjustable compensation network for loop compensation. The zero-point is then adjusted by detecting the output voltage. When an overshoot current causes the output voltage to exceed a threshold, the tail current is altered to increase the transconductance, shifting the zero point toward lower frequencies. This increases bandwidth and enhances transient response.

[0037] The load transient enhancement circuit consists of a power supply, a Buck power stage, a control loop compensation circuit, a load transient enhancement circuit, and a PWM circuit;

[0038] The control loop compensation circuit is composed of a fixed zero point compensation circuit and a zero point adjustable compensation circuit. The fixed zero point compensation circuit is a voltage divider network, and the zero point adjustable compensation circuit is composed of two feedback paths.

[0039] The Buck power stage is connected in parallel with the power supply, the output end of the Buck power stage is connected to the comparator and voltage divider circuit of the load transient enhancement circuit, the operational transconductance amplifier of the first feedback path is connected to the variable operational transconductance amplifier of the second feedback path, the operational transconductance amplifiers of the two feedback paths generate a zero-point adjustable compensation network for loop compensation, and the AND gate of the load transient enhancement circuit is connected to the PMOS transistor of the second feedback path;

[0040] The comparator of the load transient enhancement circuit is connected to the output terminal, and the comparator and the AND gate together control the on and off of the PMOS tube, thereby making the variable zero point larger and moving toward low frequency, increasing the unity gain bandwidth, and enhancing the transient response capability;

[0041] The PWM circuit is connected to the PMOS tube of the Buck power stage and is also connected to the output end of the feedback path. The output voltage of the two feedback paths controls the on and off of the PMOS tube of the Buck power stage by controlling the PWM circuit.

[0042] The load transient enhancement circuit proposed in the embodiment of the present invention adjusts the loop bandwidth through a zero-point adjustable compensation network when the output voltage exceeds a preset threshold voltage during light-load and heavy-load switching.

[0043] Furthermore, the Buck power stage is composed of a first control tube and two resistors, an inductor, a diode and a capacitor, including: the first control tube is connected in series with the inductor L, the first control tube and the inductor L are also connected to the cathode of the diode D1, and the other end of the inductor L is respectively connected to the resistor R ESR and resistor R LOAD connected, the resistor R ESR The other end of the capacitor C0 is connected to the resistor R LOADare connected.

[0044] Furthermore, the Buck power stage is composed of a first control tube and two resistors, an inductor, a diode and a capacitor, including: the first control tube end of the Buck power stage is respectively connected to the positive electrode of the voltage source and the SR latch, the positive electrode of the diode D1 and the other end of the capacitor C0 are respectively connected to the negative electrode of the voltage source, and the negative electrode of the voltage source is grounded.

[0045] Furthermore, the voltage divider network is composed of three resistors and one capacitor, specifically including: resistor R1 and resistor R2 are connected in series, the other end of resistor R1 is grounded, resistor R3 and capacitor C3 are connected in series, and resistor R3, capacitor C3 and resistor R2 are connected in parallel, and the ends of resistor R2 and capacitor C3 away from the ground are connected to the inductor L of the Buck power stage, resistor R ESR and resistor R LOAD One end of the resistor R1 away from the ground is connected to the VFB end of the first operational transconductance amplifier of the first feedback path and the VFB end of the variable operational transconductance amplifier of the second feedback path respectively.

[0046] The fixed zero compensation network transfer function is shown below:

[0047]

[0048] From the above formula we can get:

[0049]

[0050] Where z1 represents a fixed zero point.

[0051] Furthermore, the first feedback path is composed of a two-stage operational transconductance amplifier, specifically including: a first operational transconductance amplifier and a second operational transconductance amplifier connected in series, the output end of the second operational transconductance amplifier is connected to the output impedance resistor ro2, the other end of the output impedance resistor ro2 is grounded, and the output end of the first operational transconductance amplifier is respectively connected to the compensation capacitor C1 and the output impedance resistor ro1, and the other ends of the compensation capacitor C1 and the output impedance resistor ro1 are grounded.

[0052] Feedback path 1 is composed of two-stage operational transconductance amplifiers G1 and G2. gm1 and gm2 are the transconductances of the two-stage operational transconductance amplifiers Gm1 and Gm2 respectively. o 1 and r o 2 are the output impedances of the two-stage operational transconductance amplifiers Gm1 and Gm2, respectively, and C1 is the compensation capacitor of the first-stage operational transconductance amplifier.

[0053] Furthermore, the second feedback path is composed of a variable operational transconductance amplifier, a first current mirror, a second current mirror, and a second control tube, specifically including: the output end of the variable operational transconductance amplifier is connected to the output end of the first operational transconductance amplifier, the first current mirror and the second current mirror provide input stage bias current for the variable operational transconductance amplifier, one end of the second current mirror is connected to the second control tube and the AND gate output end of the load transient enhancement circuit, the VFB end of the variable operational transconductance amplifier is connected to the end of the resistor R1 in the voltage divider circuit away from the ground; the second control tube is connected to the second current mirror and the variable operational transconductance amplifier.

[0054] Feedback path 2 consists of a variable operational transconductance amplifier Gmx, a current mirror I1, a current mirror I2, and a control transistor PM2.

[0055] Current mirror I1 and current mirror I2 provide input stage bias current for operational transconductance amplifier Gmx. The currents provided are I C and I X .

[0056] The transconductance g of the operational transconductance amplifier Gmx mx , the relationship between current IC and current IX is:

[0057]

[0058] Where β is a coefficient related to the CMOS process, W / L is the width-to-length ratio of the input stage device of the operational transconductance amplifier Gmx, and the value of a is controlled by the gate voltage of PM2.

[0059] When the gate voltage of PM2 is at a high level, a=0, and when the gate voltage of PM2 is at a low level, a=1.

[0060] The transfer function of the zero-adjustable compensation network is shown below:

[0061]

[0062] From the above formula, we can get:

[0063]

[0064] Variable zero point z X The absolute value of g mx By increasing or decreasing the value, the zero point z can be changed. X Move toward low frequencies.

[0065] The entire control loop transfer function is shown below:

[0066]

[0067] The two zeros z1 and z2 generated by the control loopX Compensate for the two poles created by the power stage.

[0068] Furthermore, the load transient enhancement circuit is composed of a 2-way multiplexer, a comparator, an AND gate and a threshold signal, specifically comprising: the two input ends of the AND gate are respectively connected to the control end c of the 2-way multiplexer, and the input end of the AND gate is also respectively connected to the output ends of the two comparators, the positive input end of the first comparator is connected to the output end of the first multiplexer, and the negative input end of the first comparator is respectively connected to the R of the Buck power stage. LOAD One end of the resistor is connected to the positive input end of the second comparator, the negative input end of the first comparator is also connected to the resistor R2 and one end of the capacitor C3 of the voltage divider circuit, and the negative input end of the second comparator is connected to the control end of the second multiplexer.

[0069] Furthermore, the output end of the AND gate is connected to a second controller, and the second controller is a PMOS tube.

[0070] Furthermore, the first input terminal of the first comparator inputs the threshold signal VOH, and the second input terminal inputs the threshold signal VOHHYS; the first input terminal of the second comparator inputs the threshold signal VOL, and the second input terminal inputs the threshold signal VOLHYS.

[0071] The load transient enhancement circuit consists of two multiplexers, MUX1 and MUX2, comparators COMP1 and COMP2, an AND gate AND2, a PMOS transistor PM2, and threshold signals VOH, VOHHYS, VOL, and VOLHYS. The threshold signals VOH and VOHHYS represent the overvoltage threshold and overvoltage threshold hysteresis, respectively, while the threshold signals VOL and VOLHYS represent the undervoltage threshold and undervoltage threshold hysteresis, respectively.

[0072] The two-way multiplexer MUX1 or MUX2 includes input terminals 1 and 2, output terminal 3, and control terminal C. When the control terminal C input is high, output terminal 3 is connected to input terminal 1; when the control terminal C input is low, output terminal 3 is connected to input terminal 2.

[0073] When the output voltage is lower than VOH and higher than VOL, COMP1 and COMP2 output high level at the same time, AND gate AND2 outputs high level, PM2 is closed, and the transconductance g mx :

[0074]

[0075] At this time, the variable zero point z X At the set frequency, the system operates normally.

[0076] When the output voltage is higher than VOH, COMP1 outputs 0 level, AND gate AND2 outputs 0 level, PM2 turns on, and the transconductance gmx :

[0077]

[0078] Variable zero point z X Follow g mx As the frequency increases, it moves toward lower frequencies, increasing the loop bandwidth and enhancing transient response. The overvoltage threshold hysteresis, VOHHYS, is lower than VOH. When VOUT is less than VOHHYS and then increases from a low value, VOUT is compared with VOH. When VOUT is greater than VOH and then decreases from a high value, VOUT is compared with VOHHYS. This prevents VOUT from fluctuating near VOH, causing repeated switching of COMP1.

[0079] When the output voltage is lower than VOL, COMP1 outputs 0 level, AND gate AND2 outputs 0 level, PM2 turns on, and the transconductance g mx :

[0080]

[0081] Variable zero point z X Follow g mx As the frequency shifts toward lower frequencies, the loop bandwidth increases and the transient response is enhanced. The undervoltage threshold hysteresis VOLHYS is higher than VOL.

[0082] When VOUT is greater than VOLHYS and then decreases from a larger value, VOUT is compared with VOL. When VOUT is less than VOL and then increases from a smaller value, VOUT is compared with VOLHYS. This prevents VOUT from fluctuating around VOL and causing COMP2 to repeatedly switch on and off.

[0083] Therefore, when the load transient jumps, the output voltage exceeds the overvoltage or falls below the undervoltage threshold, and the variable zero point z X Follow g mx It becomes larger and moves toward low frequency, the unity gain bandwidth increases, and the transient response capability is enhanced.

[0084] Furthermore, the PWM circuit is composed of an SR latch, a pulse width modulator and an oscillator, specifically including: the SR latch is connected to the first control tube of the Buck power stage and is also connected to the output end of the pulse width modulator; the input end of the pulse width modulator is respectively connected to the output end of the adjustable operational transconductance amplifier and the oscillator; and the oscillator is also connected to the SR latch.

[0085] The embodiment of the present invention improves the traditional Type 3 compensation network by using a compensation transconductance amplifier to generate a zero-point adjustable compensation network for loop compensation, and then adjusts the zero point by detecting the output voltage. When an overshoot current causes the output voltage to exceed the threshold, the transconductance can be increased by changing the tail current, thereby shifting the zero point toward a lower frequency. This increases the bandwidth and thus improves the transient response capability. The embodiment of the present invention generates a zero-point adjustable compensation network by adding a feedback path to compensate the loop, and adjusts the adjustable zero point by detecting the output voltage. When the load changes, the bandwidth is increased by shifting the zero point toward a lower frequency, thereby enhancing the load response capability and reducing the output voltage overshoot.

[0086] Although the present invention has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications and improvements may be made thereto. Therefore, such modifications and improvements, without departing from the spirit of the present invention, are intended to be within the scope of protection claimed herein.

Claims

1. A load transient enhancement circuit for a voltage-mode DC-DC converter, characterized in that: The load transient enhancement circuit is composed of a power supply, a Buck power stage, a control loop compensation circuit, a load transient enhancement circuit and a PWM circuit; The control loop compensation circuit is composed of a fixed zero point compensation circuit and a zero point adjustable compensation circuit. The fixed zero point compensation circuit is a voltage divider network, and the zero point adjustable compensation circuit is composed of two feedback paths. The Buck power stage is connected in parallel with the power supply, the output end of the Buck power stage is connected to the comparator and voltage divider network of the load transient enhancement circuit, the operational transconductance amplifier of the first feedback path is connected to the variable operational transconductance amplifier of the second feedback path, the operational transconductance amplifiers of the two feedback paths generate a zero-point adjustable compensation network for loop compensation, and the AND gate of the load transient enhancement circuit is connected to the PMOS transistor of the second feedback path; The comparator of the load transient enhancement circuit is connected to the output terminal, and the comparator and the AND gate together control the on and off of the PMOS tube, thereby making the variable zero point larger and moving toward low frequency, increasing the unity gain bandwidth, and enhancing the transient response capability; The PWM circuit is connected to the PMOS transistor of the Buck power stage and also to the output end of the feedback path. The output voltage of the two feedback paths controls the PWM circuit and then controls the on and off of the PMOS transistor of the Buck power stage. The second feedback path is composed of a variable operational transconductance amplifier, a first current mirror, a second current mirror, and a second control tube, and specifically includes: The output end of the variable operational transconductance amplifier is connected to the output end of the first operational transconductance amplifier. The first current mirror and the second current mirror provide input stage bias current for the variable operational transconductance amplifier. One end of the second current mirror is connected to the second control tube and the output end of the AND gate of the load transient enhancement circuit. The VFB end of the variable operational transconductance amplifier is connected to the end of the resistor R1 in the voltage divider network that is away from ground. The second control tube is connected to the second current mirror and the variable operational transconductance amplifier.

2. The load transient enhancement circuit of a voltage-mode DCDC converter according to claim 1, wherein: The Buck power stage consists of a first control tube and two resistors, an inductor, a diode and a capacitor. Specifically, the first control tube is connected in series with the inductor L, and the first control tube and the inductor L are also connected to the cathode of the diode D1. The other end of the inductor L is connected to the resistor R ESR and resistor R LOAD connected, the resistor R ESR The other end of the capacitor C0 is connected to the resistor R LOAD are connected.

3. The load transient enhancement circuit of a voltage-mode DCDC converter according to claim 2, wherein: The Buck power stage consists of a first control tube, two resistors, an inductor, a diode, and a capacitor, including: The first control tube end of the Buck power stage is connected to the positive electrode of the voltage source and the SR latch respectively, the positive electrode of the diode D1 and the other end of the capacitor C0 are connected to the negative electrode of the voltage source respectively, and the negative electrode of the voltage source is grounded.

4. The load transient enhancement circuit of a voltage-mode DCDC converter according to claim 3, wherein: The voltage divider network is composed of three resistors and one capacitor, specifically including: Resistor R1 is connected in series with resistor R2, and the other end of resistor R1 is grounded. Resistor R3 is connected in series with capacitor C3, and resistor R3, capacitor C3 and resistor R2 are connected in parallel. The end of resistor R2 and capacitor C3 away from ground is connected to the inductor L of the Buck power stage and the resistor R ESR and resistor R LOAD One end of the resistor R1 away from the ground is connected to the VFB end of the first operational transconductance amplifier of the first feedback path and the VFB end of the variable operational transconductance amplifier of the second feedback path respectively.

5. The load transient enhancement circuit of a voltage-mode DCDC converter according to claim 4, wherein: The first feedback path is composed of a two-stage operational transconductance amplifier, specifically including: The first operational transconductance amplifier and the second operational transconductance amplifier are connected in series, the output end of the second operational transconductance amplifier is connected to the output impedance resistor ro2, the other end of the output impedance resistor ro2 is grounded, and the output end of the first operational transconductance amplifier is respectively connected to the compensation capacitor C1 and the output impedance resistor ro1, and the other ends of the compensation capacitor C1 and the output impedance resistor ro1 are grounded.

6. The load transient enhancement circuit of a voltage-mode DCDC converter according to claim 5, characterized in that: The load transient enhancement circuit is composed of a two-way multiplexer, a comparator, an AND gate, and a threshold signal, and specifically includes: The two input terminals of the AND gate are connected to the control terminal c of the 2-way multiplexer respectively. At the same time, the input terminals of the AND gate are also connected to the output terminals of the two comparators respectively. The positive input terminal of the first comparator is connected to the output terminal of the first multiplexer, and the negative input terminal of the first comparator is connected to the R LOAD One end of the resistor is connected to the positive input of the second comparator, the negative input of the first comparator is also connected to the resistor R2 and one end of the capacitor C3 of the voltage divider network, and the negative input of the second comparator is connected to the control end of the second multiplexer.

7. The load transient enhancement circuit of a voltage-mode DCDC converter according to claim 6, wherein: The output end of the AND gate is connected to the second controller, which is a PMOS tube.

8. The load transient enhancement circuit of a voltage-mode DCDC converter according to claim 7, wherein: The first comparator receives a threshold signal VOH at its first input terminal and a threshold signal VOHHYS at its second input terminal. The second comparator receives a threshold signal VOL at its first input terminal and a threshold signal VOLHYS at its second input terminal.

9. The load transient enhancement circuit of a voltage-mode DCDC converter according to claim 8, characterized in that: The PWM circuit is composed of an SR latch, a pulse width modulator and an oscillator, and specifically includes: The SR latch is connected to the first control tube of the Buck power stage and is also connected to the output end of the pulse width modulator. The input end of the pulse width modulator is respectively connected to the output end of the adjustable operational transconductance amplifier and the oscillator. The oscillator is also connected to the SR latch.

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