Self-Powered System-on-Chip

Abstract

The present invention provides a self-powered chip system, wherein one end of the primary winding of a power circuit in which the system is located receives an input voltage, and the other end is grounded in sequence through a J-FET upper tube, a first node, and an NMOS lower tube. The control end of the J-FET upper tube is grounded, and one end of a chip power supply capacitor of the self-powered chip system is grounded, and the other end is coupled to the first node through a constant current source and a first switch in a default on-state. The chip power supply capacitor supplies power to the power supply end of the controller. Since the power supply voltage required by the controller is less than the pinch-off voltage of the J-FET upper tube, the present invention self-powers the controller through the constant current source when power is turned on, losslessly self-powers the controller by controlling the first switch to be turned on when the voltage at the power supply end is less than or equal to the first voltage threshold, and self-powers the controller by simultaneously controlling the constant current source and the first switch to be turned on when the voltage at the power supply end is less than or equal to the third voltage threshold. This not only simplifies the power supply circuit of the controller but also improves the power supply efficiency of the circuit.

Description

Technical Field

[0001] The present invention relates to the field of circuit electronic technology, and in particular to a self-powered chip system. Background Art

[0002] In the prior art, power supply equipment generally needs to support both a wide input voltage range and a wide output voltage range. For example, a power supply device supporting the PD 3.0 protocol has an AC input voltage range of 90Vac to 264Vac and an output voltage range of 3.3V to 20V. Another example is a power supply device supporting the PD3.1 protocol, which has an AC input voltage range of 90Vac to 264Vac and an output voltage range of 5V to 28V. This wide input voltage range and output voltage range pose a significant challenge to the efficiency of the power supply device.

[0003] The primary-side control chips of current power supply devices generally adopt forward or flyback power supply methods. However, both methods make the voltage variation range of the power supply end of the primary-side control chip very large. To ensure the stable operation of the primary-side control chip, it is usually necessary to use a high-voltage process to manufacture the power supply end of the primary-side control chip, or add an external voltage stabilization circuit at the power supply end. This not only significantly increases system cost but also reduces the efficiency of the system under full load.

[0004] Therefore, how to improve the power supply efficiency of power supply equipment while reducing circuit costs has become a technical problem that urgently needs to be solved in the industry. Summary of the Invention

[0005] The present invention provides a self-powered chip system, which solves the technical problem of how to improve the power supply efficiency of power supply equipment while reducing circuit costs.

[0006] According to a first aspect of the present invention, an embodiment of the present invention provides a self-powered chip system, which is applied to a power circuit. The power circuit includes a primary circuit, the primary circuit includes a primary winding, a J-FET upper tube, and an NMOS lower tube. A first end of the primary winding receives an input voltage, and a second end thereof is grounded via the J-FET upper tube and the NMOS lower tube in sequence. A control end of the J-FET upper tube is coupled to ground, and the J-FET upper tube and the NMOS lower tube are coupled via a first node.

[0007] The self-powered chip system includes: a chip power supply capacitor, a constant current source, a first switch and a controller, wherein the constant current source is in an on state by default;

[0008] The first end of the chip power supply capacitor is grounded, and the second end thereof is coupled to the first node through the constant current source and the first switch respectively; the power supply end of the controller is coupled to the second end of the chip power supply capacitor, the first end thereof is coupled to the control end of the constant current source, and the second end thereof is coupled to the control end of the first switch;

[0009] The controller is configured to: enter a normal working state and control the constant current source to enter an off state when the voltage at the power supply end reaches a starting voltage, and the starting voltage is less than a pinch-off voltage of the J-FET upper tube;

[0010] After entering the normal working state, the working state of the constant current source and the on / off of the first switch are controlled based on the voltage of the power supply end, wherein:

[0011] When the voltage at the power supply end is less than or equal to a first voltage threshold, controlling the first switch to be turned on until the voltage at the power supply end is greater than or equal to a second voltage threshold, the starting voltage is greater than the second voltage threshold, and the second voltage threshold is greater than the first voltage threshold;

[0012] When the voltage at the power supply end is less than or equal to a third voltage threshold, the constant current source is controlled to be in an on state until the voltage at the power supply end is greater than or equal to a first voltage threshold, and the third voltage threshold is less than the first voltage threshold.

[0013] Optionally, the third terminal of the controller is coupled to the control terminal of the NMOS lower tube;

[0014] The controller is further configured to: generate an internal clock signal when the controller is in a normal working state; and control the on / off of the NMOS lower tube based on the internal clock signal.

[0015] Optionally, when the voltage at the power supply end is less than or equal to a first voltage threshold, the method of controlling the first switch to be turned on until the voltage at the power supply end is greater than or equal to a second voltage threshold includes:

[0016] In a current switching cycle of the internal clock signal, if the voltage of the power supply end is less than or equal to a first voltage threshold, controlling the first switch to remain in an off state;

[0017] When the internal clock signal enters a switching cycle after the current switching cycle, if the voltage at the power supply end is less than the second voltage threshold, performing the following steps in each switching cycle of the internal clock signal until the voltage at the power supply end is greater than or equal to the second voltage threshold:

[0018] sequentially controlling the first switch to be turned on and the NMOS lower tube to be turned on;

[0019] After the NMOS lower tube is turned on, the first switch is controlled to be turned off.

[0020] Optionally, the first switch is controlled to be turned on at the beginning of a switching cycle.

[0021] Optionally, after the NMOS lower tube is turned on, controlling the first switch to be turned off includes:

[0022] The first switch and the NMOS lower tube are controlled to be disconnected at the same time.

[0023] Optionally, after the first switch is turned off, the NMOS lower tube is controlled to be turned off.

[0024] Optionally, when the voltage at the power supply end is less than or equal to a first voltage threshold, the method of controlling the first switch to be turned on until the voltage at the power supply end is greater than or equal to the second voltage threshold includes:

[0025] In a current switching cycle of the internal clock signal, if the voltage of the power supply end is less than or equal to a first voltage threshold, controlling the first switch to remain in an off state;

[0026] When the internal clock signal enters a switching cycle after the current switching cycle, if the voltage at the power supply end is less than the second voltage threshold, performing the following steps in each switching cycle of the internal clock signal until the voltage at the power supply end is greater than or equal to the second voltage threshold:

[0027] Control the first switch to be turned on or the NMOS lower tube to be turned on.

[0028] Optionally, when the internal clock signal enters a first switching cycle after the current switching cycle, the first switch is controlled to be turned on.

[0029] Optionally, when the voltage at the power supply end is less than or equal to a third voltage threshold, controlling the constant current source to be in an on state and controlling the first switch to be turned on includes:

[0030] In a current switching cycle of the internal clock signal, if the voltage of the power supply end is less than or equal to a third voltage threshold, controlling the constant current source to be in an on state;

[0031] When the internal clock signal enters a switching cycle after the current switching cycle, the first switch is controlled to be turned on, and the first switch is turned on before the NMOS lower tube.

[0032] Optionally, the self-powered chip system further includes a first diode; the cathode of the first diode is coupled to the second end of the chip power supply capacitor,

[0033] An anode of the first diode is coupled to the first node through the first switch.

[0034] Optionally, the power circuit further includes a secondary circuit and a first circuit respectively magnetically coupled to the primary winding;

[0035] The secondary circuit is used to sense the change in magnetic flux of the primary winding and output an output voltage;

[0036] The first circuit is used to sense the change in magnetic flux of the primary winding and output a first feedback signal;

[0037] The fourth terminal of the controller receives the first feedback signal, and the controller is further configured to: control the working state of the power circuit based on the first feedback signal and the on-off state of the NMOS lower tube, wherein:

[0038] When controlling the NMOS lower tube to be turned on, obtaining a voltage value of the first feedback signal, and controlling whether the primary circuit enters a protection state based on the voltage value of the first feedback signal;

[0039] When controlling the NMOS lower tube to be disconnected, the voltage value and the current value of the first feedback signal are obtained, and when the voltage value of the first feedback signal is less than or equal to a fourth voltage threshold, the secondary circuit is controlled to enter a protection state based on the current value of the first feedback signal.

[0040] Optionally, the first circuit includes a first winding, a first voltage-dividing resistor, and a second voltage-dividing resistor;

[0041] The first output end of the first winding is coupled to the first end of the first voltage-dividing resistor, the second end of the first voltage-dividing resistor is coupled to the first end of the second voltage-dividing resistor through a second node, the second end of the second voltage-dividing resistor is coupled to the second output end of the first winding, and the second node is coupled to the fourth end of the controller for outputting the first feedback signal.

[0042] Optionally, the secondary circuit includes a secondary winding, a second diode, a first capacitor and a first resistor;

[0043] The first output end of the secondary winding is coupled to the first end of the first capacitor through the second diode, the second end of the first capacitor is coupled to the second output end of the secondary winding, and the first capacitor is connected in parallel with the first resistor.

[0044] Optionally, the first winding is an EMI shielding layer winding, and the polarity of the first winding is opposite to the polarity of the secondary winding.

[0045] Optionally, the first winding is an auxiliary winding.

[0046] Optionally, the eighth terminal of the controller receives the output voltage, and the controller is further configured to: control the frequency of the internal clock signal based on the voltage value of the output voltage.

[0047] Optionally, the secondary circuit further includes a first feedback module, and the primary circuit further includes a second feedback module;

[0048] The first feedback module is connected in parallel with the first capacitor, and the first feedback module is used to obtain the output voltage and output a second feedback signal, wherein the second feedback signal includes voltage value information of the output voltage;

[0049] The first end of the second feedback module is coupled to the eighth end of the controller, the second end of the second feedback module is grounded, the receiving end of the second feedback module receives the second feedback signal, and the second feedback module is used to transmit the voltage value information of the output voltage to the controller.

[0050] Optionally, the primary circuit further includes a current sampling module, the current sampling module being configured to obtain a magnitude of a current flowing through the first node and output a third feedback signal to a fifth terminal of the controller, the third feedback signal including current value information of the current flowing through the first node;

[0051] The controller is further configured to determine, based on the third feedback signal, a turn-on time and a turn-off time of the NMOS low-side transistor in each switching cycle of the internal clock signal.

[0052] Optionally, the current sampling module includes a first NMOS tube and a sampling resistor;

[0053] The gate of the first NMOS transistor is coupled to the control terminal of the NMOS lower transistor, the drain of the first NMOS transistor is coupled to the sixth terminal of the controller, and the source thereof is grounded; the first terminal of the sampling resistor is coupled to the fifth terminal of the controller, and the second terminal thereof is grounded;

[0054] The controller is further configured to: output a first current to the fifth terminal of the controller and obtain a voltage value of the first terminal of the sampling resistor, wherein the current value of the first current is equal to the current value of the current flowing through the sixth terminal of the controller.

[0055] Optionally, the current sampling module includes a sampling resistor, which is connected in series between the first node and the drain of the NMOS lower tube. The fifth terminal of the controller is used to obtain the voltage across the sampling resistor to obtain current value information of the current flowing through the first node.

[0056] Optionally, the primary circuit further includes an RCD absorption module, and the RCD absorption module includes a second resistor, a second capacitor, and a third diode;

[0057] The first end of the primary winding is coupled to the first end of the second capacitor and the first end of the second resistor, respectively. The second end of the second capacitor is coupled to the second end of the second resistor and the cathode of the third diode, respectively. The anode of the third diode is coupled to the second end of the primary winding.

[0058] Optionally, the primary circuit further includes a power supply side capacitor, and the first end of the primary winding is grounded through the power supply side capacitor.

[0059] Optionally, the primary circuit further includes a rectifier module and a power extraction module, the power supply side capacitor is connected in parallel to the rectifier module, the input end of the rectifier module and the input end of the power extraction module are both coupled to an AC power supply, and the output end of the power extraction module is coupled to a high-voltage power extraction end of the controller;

[0060] The controller is configured to: when the voltage value of the AC power supply is less than a fifth voltage threshold and the voltage value of the AC power supply is greater than or equal to 0, control the first switch to be turned on, or control the constant current source to be in an on state and control the first switch to be turned on.

[0061] Optionally, the AC power supply includes an AC live wire and an AC neutral wire, and the power taking module includes a fourth diode, a fifth diode and a third resistor;

[0062] The cathode of the fourth diode and the anode of the fifth diode are respectively coupled to the AC live wire and the AC neutral wire, the cathode of the fourth diode and the cathode of the fifth diode are both coupled to the first end of the third resistor, and the second end of the third resistor is coupled to the high-voltage power supply terminal of the controller.

[0063] Optionally, the self-powered chip system further includes an on-off speed control module, and the on-off speed control module includes a sixth diode and a fourth resistor;

[0064] The first end of the fourth resistor is coupled to the control end of the J-FET upper tube, and the second end thereof is coupled to the anode of the sixth diode; the cathode of the sixth diode is coupled to the second end of the fourth resistor.

[0065] Optionally, the seventh terminal of the controller is further coupled to the first node;

[0066] The controller is further configured to control whether the primary circuit enters a protection state based on a voltage value and / or a current value of the first node.

[0067] Optionally, the constant current source also has a current limiting function.

[0068] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0069] In the self-powered chip system of the technical solution of the present invention, one end of the primary winding of the power circuit in which the system is located receives the input voltage, and the other end is grounded in sequence through the J-FET upper tube, the first node and the NMOS lower tube, the control end of the J-FET upper tube is grounded, and one end of the chip power supply capacitor of the self-powered chip system is grounded, and the other end is coupled to the first node through the constant current source and the first switch in the default on state. The chip power supply capacitor supplies power to the power supply end of the controller. Since the power supply voltage required by the controller is less than the pinch-off voltage of the J-FET upper tube, the present invention self-powers the controller through the constant current source when power is turned on, and losslessly self-powers the controller by controlling the first switch to turn on when the voltage at the power supply end is less than or equal to the first voltage threshold. When the voltage at the power supply end is less than or equal to the third voltage threshold, the controller is self-powered by simultaneously controlling the constant current source and the first switch to turn on when the voltage at the power supply end is less than or equal to the third voltage threshold. This not only simplifies the power supply circuit of the controller, but also improves the power supply efficiency of the circuit.

[0070] Furthermore, the power circuit in which the self-powered chip system is located also includes a first circuit, wherein the first output end of the first winding is coupled to the first end of a first voltage-dividing resistor, the second end of the first voltage-dividing resistor is coupled to the first end of a second voltage-dividing resistor via a second node, the second end of the second voltage-dividing resistor is coupled to the second output end of the first winding, and the second node is coupled to the fourth end of the controller for outputting a first feedback signal, wherein the first winding is an EMI shielding layer winding, and the polarity of the first winding is opposite to the polarity of the secondary winding. The present invention achieves sampling of input voltage and output voltage information by reusing the EMI shielding layer winding, further simplifying the architecture of the power circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0072] Figure 1 This is a schematic diagram of the structure of the controller power supply circuit in an embodiment of the prior art;

[0073] Figure 2 corresponds to Figure 1 The working waveform of the circuit shown;

[0074] Figure 3 1 is a schematic structural diagram of a self-powered chip system provided by an embodiment of the present invention;

[0075] Figure 4 corresponds to Figure 3 Working waveform of the circuit shown Figure 1 ;

[0076] Figure 5 corresponds to Figure 3 Working waveform of the circuit shown Figure 2 ;

[0077] Figure 6 corresponds to Figure 3 Working waveform of the circuit shown Figure 3 ;

[0078] Figure 7 is a structural diagram of a self-powered chip system provided by another embodiment of the present invention;

[0079] Figure 8 3 is a schematic structural diagram of a self-powered chip system provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0080] As described in the background art, it is difficult to improve the power supply efficiency of power supply equipment while reducing circuit costs in the existing technology.

[0081] Figure 1 This is a schematic diagram of the controller power supply circuit in a flyback power supply. The flyback power supply includes:

[0082] The primary circuit includes a primary winding Np, a controller U1 and a first switch tube M1; the output end of the controller U1 is coupled to the control end of the first switch tube M1, the first end of the first switch tube M1 is coupled to the first end of the primary winding Np, and the second end of the first switch tube M1 is grounded.

[0083] The secondary circuit includes a secondary winding Ns, a second diode D2, a first capacitor C1, and a first resistor R1.

[0084] The first output end of the secondary winding Ns is coupled to the first end of the first capacitor C1 through the second diode D2. The second end of the first capacitor C1 is coupled to the second output end of the secondary winding Ns. The first capacitor C1 is connected in parallel with the first resistor R1.

[0085] The auxiliary circuit includes an auxiliary winding Naux, a first diode D1, a second capacitor C2, a second resistor R2, a first voltage-dividing resistor Rup, and a second voltage-dividing resistor Rdw; wherein:

[0086] The anode of the first diode D1 and the first end of the first voltage-dividing resistor Rup are coupled to the first output end of the auxiliary winding Naux, the cathode of the first diode D1 is respectively coupled to the first end of the second capacitor C2 and the power supply end of the controller U1, the second capacitor C2 is connected in parallel with the second resistor R2, and the second end of the second capacitor C2 is grounded, the second end of the first voltage-dividing resistor Rup is respectively coupled to the first end of the second voltage-dividing resistor Rdw and the first input end of the controller U1, the second end of the second voltage-dividing resistor Rdw is coupled to the second output end of the auxiliary winding Naux, and the second end of the second voltage-dividing resistor Rdw is grounded.

[0087] The electromagnetic shielding circuit includes an EMI shielding layer winding N-E_shield, wherein the polarity of the EMI shielding layer winding N-E_shield is opposite to the polarity of the auxiliary winding Naux, the first output end of the EMI shielding layer winding N-E_shield is suspended NC, and the second output end thereof is grounded.

[0088] As can be seen, in actual operation, the transformer needs to have at least two auxiliary windings Naux: one auxiliary winding Naux (i.e., the electromagnetic shielding circuit mentioned above) is specifically used for electromagnetic interference (EMI) shielding; the other auxiliary winding Naux is used to provide power supply voltage to the controller U1. This structure increases the manufacturing complexity and cost of the transformer.

[0089] Furthermore, in this embodiment, controller U1 utilizes auxiliary winding Naux for power supply. Due to the inherent leakage inductance of the transformer, the voltage at the power supply terminal is affected not only by variations in the input and output voltages but also by significant fluctuations depending on the severity of the output load. This results in a wide range of voltage fluctuations at the power supply terminal. Consequently, in actual designs, controller U1's power supply terminal is typically manufactured using a high-voltage withstand process or an external voltage stabilization circuit is added, further increasing the transformer's manufacturing complexity and cost.

[0090] Moreover, when the power circuit is in a fully loaded state, the power supply voltage provided by the auxiliary winding Naux also reaches its highest point, which will lead to increased power supply loss. Moreover, when the power circuit is under a heavy load, the current demand supplied to the power supply end will also be higher, further increasing the power supply loss and reducing the overall system efficiency.

[0091] Please refer to Figure 2 , Figure 2 Shown is the corresponding Figure 1 Working waveform diagram. Among them:

[0092] DRV can be understood as the control signal of the first switch M1;

[0093] Vds, which can be understood as the voltage at the drain of the first switch tube M1;

[0094] Vcc can be understood as the voltage of the power supply end;

[0095] Vo can be understood as the output voltage of the secondary circuit;

[0096] Naux / Ns can be understood as the turns ratio of the auxiliary winding Naux to the secondary winding Ns;

[0097] N can be understood as the turns ratio of the secondary winding Ns to the primary winding Np.

[0098] It can be seen that in Figure 1 In the example shown, the voltage at the power supply end is not only affected by changes in the input voltage and output voltage, but also fluctuates significantly with the severity of the output load, which makes the voltage fluctuation range at the power supply end larger. Moreover, as the load increases, the controller U1 will also increase the power supply loss of the power circuit, affecting the working efficiency of the overall system.

[0099] In order to solve the above problems, an embodiment of the present invention provides a self-powered chip system, in which one end of the primary winding of the power circuit in which the system is located receives the input voltage, and the other end is grounded in sequence through the J-FET upper tube, the first node and the NMOS lower tube, the control end of the J-FET upper tube is grounded, and one end of the chip power supply capacitor of the self-powered chip system is grounded, and the other end is coupled to the first node through the constant current source and the first switch in the default on state. The chip power supply capacitor supplies power to the power supply end of the controller. Since the power supply voltage required by the controller is less than the pinch-off voltage of the J-FET upper tube, the present invention self-powers the controller through the constant current source when power is turned on, and losslessly self-powers the controller by controlling the first switch to turn on when the voltage at the power supply end is less than or equal to the first voltage threshold. When the voltage at the power supply end is less than or equal to the third voltage threshold, the controller is self-powered by simultaneously controlling the constant current source and the first switch to turn on when the voltage at the power supply end is less than or equal to the third voltage threshold. This not only simplifies the power supply circuit of the controller, but also improves the power supply efficiency of the circuit.

[0100] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0101] The terms "first," "second," "third," "fourth," and so on (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0102] The technical solution of the present invention is described in detail below with reference to specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0103] Figure 3 A self-powered chip system according to an embodiment of the present invention is applied to a power circuit. The power circuit includes a primary circuit, the primary circuit including a primary winding Np, a J-FET upper tube Q1, and an NMOS lower tube Q2. A first end of the primary winding Np receives an input voltage Vin, and a second end thereof is grounded via the J-FET upper tube Q1 and the NMOS lower tube Q2 in sequence. A control end of the J-FET upper tube Q1 is coupled to ground, and the J-FET upper tube Q1 and the NMOS lower tube Q2 are coupled via a first node m.

[0104] The self-powered chip system includes: a chip power supply capacitor Cvcc, a constant current source Ist, a first switch Q3 and a controller U1, wherein the default working state of the constant current source Ist is on;

[0105] A first end of the chip power supply capacitor Cvcc is grounded, and a second end thereof is coupled to the first node m via the constant current source Ist and the first switch Q3, respectively. A power supply terminal VCC of the controller U1 is coupled to the second end of the chip power supply capacitor Cvcc, a first end EN of the controller U1 is coupled to the control end of the constant current source Ist, and a second end CH of the controller U1 is coupled to the control end of the first switch Q3.

[0106] The controller U1 is configured to: enter a normal working state when the voltage of the power supply terminal VCC reaches a starting voltage, and control the constant current source Ist to work in an off state, wherein the starting voltage is less than the pinch-off voltage of the J-FET upper tube Q1; and

[0107] Based on the voltage of the power supply terminal VCC, the working state of the constant current source Ist and the on / off of the first switch Q3 are controlled, wherein:

[0108] When the voltage of the power supply terminal VCC is less than or equal to a first voltage threshold VCC_L, the first switch Q3 is controlled to be turned on until the voltage of the power supply terminal VCC is greater than or equal to a second voltage threshold VCC_H, the start-up voltage is greater than the second voltage threshold VCC_H, and the second voltage threshold VCC_H is greater than the first voltage threshold VCC_L;

[0109] When the voltage of the power supply terminal VCC is less than or equal to the third voltage threshold VCC_Min, the constant current source Ist is controlled to be in the on state until the voltage of the power supply terminal VCC is greater than or equal to the first voltage threshold VCC_L, and the third voltage threshold VCC_Min is less than the first voltage threshold VCC_L.

[0110] In a preferred embodiment, the constant current source Ist also has a current limiting function. Of course, the present invention does not limit the specific implementation of this function. For example, a constant current source based on LM317, a constant current source including an operational amplifier, etc. can achieve this function, and the present invention will not go into details therein.

[0111] It is easy to understand that when the constant current source Ist is in the on-state or the first switch Q3 is turned on, the chip power supply capacitor Cvcc is charged, causing the voltage of the power supply terminal VCC to increase. By way of example, the J-FET high transistor Q1 can be a D-mode gallium nitride power device (cascode GaN), a SiC power device, or the like. This is not a limitation of the present invention, and those skilled in the art can select an appropriate normally-on device as needed.

[0112] It can be seen that the J-FET upper tube Q1 and the NMOS lower tube Q2 in the embodiment of the present invention constitute a cascode switch tube structure. The controller U1 draws power from the midpoint m of the cascode switch tube, performs lossy self-power supply when the power circuit is just powered on and during light load, and performs lossless self-power supply when the power circuit enters medium or heavy load, so that the power supply terminal VCC has a very stable supply voltage, while improving the power supply efficiency of the power circuit.

[0113] Specifically, since the J-FET top tube Q1 is a normally-on device, when the controller U1 performs lossy self-powering, the J-FET top tube Q1 needs to be close to the off state so that the voltage of the first node m is greater than the voltage of the power supply terminal VCC. In this case, both ends of the J-FET top tube Q1 will be subjected to the input voltage Vin, resulting in circuit loss.

[0114] When the controller U1 performs lossless self-powering, Vin, the inductor (i.e., the inductor Lp of the primary winding), the J-FET upper tube Q1, the first switch Q3, and the chip power supply capacitor Cvcc form a power supply loop. Because the VCC voltage (the power supply end voltage) is much lower than the J-FET pinch-off voltage, the J-FET is in a fully on state. The Vin voltage is almost entirely applied to both ends of Lp, the voltage drop across Q1 and Q3 is extremely low, the device loss is almost zero, the circuit generates almost no heat, and the circuit efficiency is relatively high.

[0115] For example, the controller U1 in the embodiment of the present invention may be a flyback controller, a forward controller, an AHB controller, an LLC controller, etc., and the control mode of the controller U1 may also include a COT fixed on-time mode, a fixed off-time mode, a voltage mode control mode, a current mode control mode, etc. The present invention is not limited to this, and those skilled in the art may select the type of controller U1 and the control mode of the controller U1 for the NMOS lower tube Q2 as needed.

[0116] In order to ensure that the charging current flows in one direction, in a preferred embodiment, please continue to refer to Figure 3 The self-powered chip system further includes a first diode D1; the cathode of the first diode D1 is coupled to the second end of the chip power supply capacitor Cvcc,

[0117] An anode of the first diode D1 is coupled to the first node m through the first switch Q3 .

[0118] In actual work, the self-powered chip system also includes an on-off speed control module, please continue to refer to Figure 3 , the on-off speed control module includes a sixth diode Ddd and a fourth resistor Rdd;

[0119] A first end of the fourth resistor Rdd is coupled to the control end of the J-FET upper tube Q1 , and a second end thereof is coupled to the anode of the sixth diode Ddd. A cathode of the sixth diode Ddd is coupled to the second end of the fourth resistor Rdd.

[0120] The fourth resistor Rdd is used to suppress the turn-on speed of the J-FET upper tube Q1, and the sixth diode Ddd is used to accelerate the turn-off speed of the J-FET upper tube Q1. It should be understood that the present invention does not limit the resistance value of the fourth resistor Rdd, and those skilled in the art can select an appropriate resistance value as needed.

[0121] In actual operation, the controller U1 will periodically turn on and off the NMOS lower tube Q2 to meet the load requirements of the power circuit. Figure 3In one embodiment, the third terminal Gate of the controller U1 is coupled to the control terminal of the NMOS lower tube Q2;

[0122] The controller U1 is further configured to: generate an internal clock signal when the controller U1 is in a normal working state; and

[0123] The on / off of the NMOS lower tube Q2 is controlled based on the internal clock signal.

[0124] In this case, to ensure that the power supply to the controller U1 does not fall below the minimum operating voltage threshold required thereof, in a preferred embodiment, when the voltage of the power supply terminal VCC is less than or equal to the third voltage threshold VCC_Min, the constant current source Ist is controlled to be in the on state, and the first switch Q3 is controlled to be turned on, including:

[0125] In the current switching cycle of the internal clock signal, if the voltage of the power supply terminal VCC is less than or equal to the third voltage threshold VCC_Min, the constant current source Ist is controlled to be in the on state;

[0126] When the internal clock signal enters a switching cycle after the current switching cycle, the first switch Q3 is controlled to be turned on, and the first switch Q3 is turned on before the NMOS lower tube.

[0127] It should be understood that when the voltage at the power supply end is less than or equal to the third voltage threshold, the constant current source Ist and the first switch Q3 will operate simultaneously, and the constant current source Ist will be turned off when the voltage at the power supply end VCC is greater than or equal to the first voltage threshold VCC_L, but the first switch Q3 will still be turned on in the subsequent switching cycle, so that the controller U1 performs lossless self-power supply until the voltage at the power supply end is greater than or equal to the second voltage threshold.

[0128] Now combined Figure 4 right Figure 3 The working effect of the power circuit shown is explained. Figure 4 yes Figure 3 The working waveform of the power circuit shown in the figure:

[0129] VCC can be understood as the voltage of the power supply terminal VCC;

[0130] VCC_ON can be understood as the startup voltage;

[0131] VCC_H, which can be understood as the second voltage threshold VCC_H;

[0132] VCC_L, which can be understood as the first voltage threshold VCC_L;

[0133] VCC_Min, which can be understood as the third voltage threshold VCC_Min;

[0134] EN can be understood as a first control signal for controlling the working state of the constant current source Ist;

[0135] Clock can be understood as the internal clock signal;

[0136] CH can be understood as the second control signal for controlling the on / off of the first switch Q3;

[0137] Gate, which can be understood as a gate control signal that controls the on / off of the NMOS lower tube Q2;

[0138] Id can be understood as the current flowing through the primary winding Np;

[0139] Ivcc, which can be understood as the current flowing through the first switch Q3;

[0140] Is can be understood as the current flowing through the D-pole of the NMOS bottom tube;

[0141] Vm can be understood as the voltage of the first node m.

[0142] It can be seen that from time t0 to t1, the power circuit is in the initial power-on stage. Since the constant current source Ist is turned on by default, the first switch Q3 is in the off state, and the input voltage Vin is charged to the chip power supply capacitor Cvcc through the J-FET upper tube Q1 and the constant current source Ist;

[0143] At time t1, the voltage of the power supply terminal VCC reaches the startup voltage VCC_ON, the controller U1 starts to work normally, and controls the working state of the constant current source Ist to be off state to reduce static loss;

[0144] At time t2, the internal clock signal is at a high level, the gate drive signal is set high, the NMOS lower tube Q2 is turned on, the voltage of the first node m drops rapidly, and the current flowing through the primary winding Np and the current flowing through the D electrode of the NMOS lower tube both increase linearly according to the slope of Vin / Lp, where Vin is the input voltage Vin and Lp is the inductance of the primary winding Np;

[0145] At time t3, the gate drive signal is turned off, turning off the NMOS lower tube Q2. When the voltage of the first node m rises above the pinch-off voltage threshold Vth of the J-FET tube, the J-FET tube is turned off, and the current flowing through the primary winding Np and the current flowing through the D-pole of the NMOS lower tube decrease to zero.

[0146] At time t4, the voltage at the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L. The controller U1 activates the self-power supply function, i.e., the second control signal is set high, turning on the first switch Q3. The voltage at the first node m is clamped to a voltage close to the power supply terminal VCC. At the same time, because the voltage at the power supply terminal VCC is lower than the pinch-off threshold Vth of the J-FET, the J-FET is turned back on. In this case, the current in the inductor Lp of the primary winding Np increases linearly with a slope of (Vin-VCC) / Lp, and charges the VCC capacitor through the first switch Q3. The voltage drop in this conductive path is extremely low, and the controller U1 achieves lossless self-power supply.

[0147] At time t5, the gate drive signal is set high again, the NMOS lower tube Q2 is turned on again, and the current of the inductor Lp continues to increase at the slope of Vin / Lp. Although the second control signal remains high, the current flowing through the first switch Q3 drops to zero, and the voltage of the first node m is pulled to nearly zero volts.

[0148] At time t6, the second control signal is turned off, and the gate drive signal is still in a high state;

[0149] At time t7, the gate drive signal turns off, turning off the NMOS lower transistor Q2. The voltage at the first node m rises again to above the pinch-off threshold Vth of the J-FET, turning off the J-FET and rapidly reducing the inductor current Id to zero.

[0150] From t7 to t8, the circuit enters CCM operation, during which the controller U1 can still be losslessly self-powered.

[0151] At time t8, the voltage of the power supply terminal VCC rises to the second voltage threshold VCC_H, completing the self-powered charging. After that, when the clock signal Clock is triggered, the CH signal is no longer turned on;

[0152] At time t8-t9, the power circuit enters a light-load state, and the controller U1 can still perform lossless self-powering when the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L;

[0153] At time t9, the lossless self-power supply cannot meet the charging demand, and the voltage of the power supply terminal VCC drops to the third voltage threshold VCC_Min (which can be understood as the minimum operating voltage threshold of the controller U1). The controller U1 starts to set the first control signal high to turn on the constant current source Ist, immediately making the controller U1 enter the lossy self-power supply mode, and when the internal clock signal enters the next switching cycle, the second control signal is set high to control the first switch Q3 to turn on.

[0154] At time t10 , the chip power supply capacitor Cvcc is charged to the first voltage threshold VCC_L, and the first control signal is controlled to be turned off, so that the controller U1 enters the lossless self-powered mode.

[0155] At time t11, the chip power supply capacitor Cvcc is charged to the second voltage threshold VCC_H, and the second control signal is controlled to be turned off to stop charging the chip power supply capacitor Cvcc.

[0156] At time t12, the internal clock signal is at a high level, the gate drive signal is set high, and the circuit enters the next period of working cycle.

[0157] In summary, the present invention only performs lossy self-powering when the power circuit has just been powered on and the lossless self-powering cannot meet the power supply requirements due to light load, and performs lossless self-powering when the power circuit enters medium or heavy load, so that the power supply end VCC has a very stable power supply voltage, while improving the power supply efficiency of the power circuit.

[0158] To coordinate the conduction timing of the first switch Q3 and the NMOS bottom tube Q2, in one embodiment, when the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, the method of controlling the first switch Q3 to be turned on until the voltage of the power supply terminal VCC is greater than or equal to the second voltage threshold VCC_H includes:

[0159] In the current switching cycle of the internal clock signal, if the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, the first switch Q3 is controlled to remain in the off state.

[0160] This is because the state of the first switch can be refreshed only when the internal clock signal enters a new cycle.

[0161] When the internal clock signal enters a switching cycle after the current switching cycle, if the voltage of the power supply terminal VCC is less than the second voltage threshold VCC_H, the following steps are performed in each switching cycle of the internal clock signal until the voltage of the power supply terminal VCC is greater than or equal to the second voltage threshold VCC_H:

[0162] The first switch Q3 and the NMOS lower tube Q2 are controlled to be turned on in sequence.

[0163] It should be understood that in each cycle, the first switch Q3 is turned on before the NMOS lower tube Q2.

[0164] After the NMOS lower tube Q2 is turned on, the first switch Q3 is controlled to be turned off.

[0165] It should be understood that the present invention does not limit the turn-on and turn-off times of the first switch Q3. The first switch Q3 and the NMOS transistor can be in the on state at the same time. As long as the first switch Q3 is in the on state before the NMOS transistor and the first switch Q3 is turned off when the NMOS transistor is in the on state, it falls within the protection scope of the present invention.

[0166] In a preferred embodiment, when the internal clock signal enters a switching cycle after the current switching cycle, if the voltage of the power supply terminal VCC is less than the second voltage threshold VCC_H, the first switch Q3 is controlled to be turned on at the beginning of each switching cycle of the internal clock signal.

[0167] In a specific embodiment, after the NMOS lower tube is turned on, controlling the first switch to be turned off includes:

[0168] The first switch and the NMOS lower tube are controlled to be disconnected at the same time.

[0169] Of course, the present invention is not limited to this. In another specific implementation, the NMOS lower tube may be controlled to be turned off after the first switch is turned off.

[0170] In this case, combined Figure 5 right Figure 3 The working effect of the power circuit shown is explained. Figure 5 yes Figure 3 The working waveform of the power circuit shown in the figure:

[0171] VCC can be understood as the voltage of the power supply terminal VCC;

[0172] VCC_H, which can be understood as the second voltage threshold VCC_H;

[0173] VCC_L, which can be understood as the first voltage threshold VCC_L;

[0174] VCC_Min, which can be understood as the third voltage threshold VCC_Min;

[0175] EN can be understood as a first control signal for controlling the working state of the constant current source Ist;

[0176] Clock can be understood as the internal clock signal;

[0177] CH can be understood as the second control signal for controlling the on / off of the first switch Q3;

[0178] Gate, which can be understood as a gate control signal that controls the on / off of the NMOS lower tube Q2;

[0179] Vm, which can be understood as the voltage of the first node m;

[0180] Id can be understood as the current flowing through the primary winding Np;

[0181] Is can be understood as the D-pole current flowing through the NMOS lower tube Q2.

[0182] It can be seen that at time t1, the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, and the first switch Q3 is kept off;

[0183] At time t2, the internal clock signal enters the next switching cycle, and the controller U1 controls the first switch Q3 to turn on;

[0184] At time t3, the NMOS lower tube Q2 is controlled to be turned on;

[0185] At time t4, the first switch Q3 is controlled to be turned off.

[0186] In summary, in this control mode, the present invention avoids unnecessary on-off switching of the J-FET Q1 switch by controlling the NMOS lower tube Q2 to be disconnected after the first switch Q3 is disconnected, thereby reducing switching loss and interference.

[0187] It should be understood that the first switch Q3 can be turned off at any time when the NMOS lower tube Q2 is turned on.

[0188] In another embodiment, when the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, the method of controlling the first switch Q3 to be turned on until the voltage of the power supply terminal VCC is greater than or equal to the second voltage threshold VCC_H includes:

[0189] In the current switching cycle of the internal clock signal, if the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, the first switch Q3 is controlled to remain in the off state;

[0190] When the internal clock signal enters a switching cycle after the current switching cycle, if the voltage of the power supply terminal VCC is less than the second voltage threshold VCC_H, the following steps are performed in each switching cycle of the internal clock signal until the voltage of the power supply terminal VCC is greater than or equal to the second voltage threshold VCC_H:

[0191] The first switch Q3 is controlled to be turned on or the NMOS lower tube Q2 is controlled to be turned on.

[0192] It can be seen that in this manner, the first switch Q3 and the NMOS lower tube Q2 adopt an either-or control strategy, and only the first switch Q3 or the NMOS lower tube Q2 can be turned on in one switching cycle.

[0193] To ensure that the chip power supply capacitor Cvcc is charged in time, in a specific implementation manner, when the internal clock signal enters the first switching cycle after the current switching cycle, the first switch Q3 is controlled to be turned on.

[0194] In this case, combined Figure 6 right Figure 3 The working effect of the power circuit shown is explained. Figure 6 yes Figure 3 The working waveform of the power circuit shown in the figure:

[0195] VCC can be understood as the voltage of the power supply terminal VCC;

[0196] VCC_H, which can be understood as the second voltage threshold VCC_H;

[0197] VCC_L, which can be understood as the first voltage threshold VCC_L;

[0198] VCC_Min, which can be understood as the third voltage threshold VCC_Min;

[0199] EN can be understood as a first control signal for controlling the working state of the constant current source Ist;

[0200] Clock can be understood as the internal clock signal;

[0201] CH can be understood as the second control signal for controlling the on / off of the first switch Q3;

[0202] Gate, which can be understood as a gate control signal that controls the on / off of the NMOS lower tube Q2;

[0203] Vm, which can be understood as the voltage of the first node m;

[0204] Id can be understood as the current flowing through the primary winding Np;

[0205] Is can be understood as the D-pole current flowing through the NMOS lower tube Q2.

[0206] It can be seen that when the chip power supply capacitor Cvcc needs to be charged, the present invention adopts a method of turning on the first switch Q3 or the NMOS lower tube Q2 within a switching cycle. This single-cycle two-choice mode switching strategy simplifies the control difficulty.

[0207] In summary, the present invention simplifies the peripheral circuits required for the power supply terminal VCC, and solves the problems of a wide power supply voltage range of the traditional power supply terminal VCC and low power supply efficiency when the power circuit outputs high voltage at full load.

[0208] In actual work, please refer to Figure 6 In one embodiment, the primary circuit further includes an RCD absorption module, and the RCD absorption module includes a second resistor R2, a second capacitor C2 and a third diode;

[0209] The first end of the primary winding Np is respectively coupled to the first end of the second capacitor C2 and the first end of the second resistor R2, the second end of the second capacitor C2 is respectively coupled to the second end of the second resistor R2 and the cathode of the third diode, and the anode of the third diode is coupled to the second end of the primary winding Np.

[0210] In practical applications, please refer to Figure 7 The primary circuit further includes a power supply side capacitor Cin, and the first end of the primary winding Np is grounded through the power supply side capacitor Cin.

[0211] Based on this, the controller U1 provided by the present invention is further explained.

[0212] In actual work, the controller U1 also has a protection function. For a specific implementation, please continue to refer to Figure 7 , the power circuit further includes a secondary circuit and a first circuit respectively magnetically coupled to the primary winding Np;

[0213] The secondary circuit is used to sense the magnetic flux change of the primary winding Np and output the output voltage Vo;

[0214] The first circuit is used to sense the magnetic flux change of the primary winding Np and output a first feedback signal VMS;

[0215] The fourth terminal VMS of the controller U1 receives the first feedback signal VMS. The controller U1 is further configured to control the working state of the power circuit based on the first feedback signal VMS and the on / off state of the NMOS lower tube Q2, wherein:

[0216] When controlling the NMOS lower tube Q2 to be turned on, obtaining a voltage value of the first feedback signal VMS, and controlling whether the primary circuit enters a protection state based on the voltage value of the first feedback signal VMS;

[0217] When controlling the NMOS lower tube Q2 to be disconnected, the voltage value and the current value of the first feedback signal VMS are obtained, and when the voltage value of the first feedback signal VMS is less than or equal to a fourth voltage threshold, the secondary circuit is controlled to enter a protection state based on the current value of the first feedback signal.

[0218] It can be seen that in this embodiment, when the NMOS lower tube Q2 is turned on, the controller U1 can monitor and protect the circuit on the input voltage Vin side. Generally, the protection status can include overvoltage monitoring protection (Brown-in) state, undervoltage monitoring protection (Brown-out) state and input overvoltage protection (OVP) state.

[0219] When the NMOS lower tube Q2 is disconnected, the controller U1 can monitor and protect the circuit on the output voltage Vo side. Generally, the protection state can include an output overvoltage protection (OVP) state and an output undervoltage protection (UVP) state.

[0220] It should be understood that the controller U1 can only determine whether the primary circuit enters the protection state when the NMOS lower tube Q2 is turned on. In a preferred embodiment, please refer to Figure 7 , the seventh terminal of the controller U1 is also coupled to the first node m;

[0221] The controller U1 is further configured to control whether the primary circuit enters a protection state based on the voltage value and / or current value of the first node m.

[0222] Specifically, the controller U1 can detect the voltage and / or current of the first node m in real time through a built-in comparator or sampling circuit, and turn off the NMOS lower tube Q2 when the voltage and / or current value exceeds the corresponding set voltage and / or set current to achieve protection and prevent system damage. This technology is prior art and will not be further described in detail in the present invention.

[0223] In a specific implementation, please refer to Figure 7 , the secondary circuit includes a secondary winding Ns, a second diode D2, a first capacitor C1 and a first resistor R1;

[0224] The first output end of the secondary winding Ns is coupled to the first end of the first capacitor C1 through the second diode D2. The second end of the first capacitor C1 is coupled to the second output end of the secondary winding Ns. The first capacitor C1 is connected in parallel with the first resistor R1.

[0225] Please continue to refer to Figure 7In one embodiment, the first circuit includes a first winding, a first voltage-dividing resistor Rup, and a second voltage-dividing resistor Rdw;

[0226] The first output end of the first winding is coupled to the first end of the first voltage-dividing resistor Rup, the second end of the first voltage-dividing resistor Rup is coupled to the first end of the second voltage-dividing resistor Rdw through a second node, the second end of the second voltage-dividing resistor Rdw is coupled to the second output end of the first winding, and the second node is coupled to the fourth end of the controller U1 for outputting the first feedback signal VMS.

[0227] In this case, when the NMOS lower tube Q2 is controlled to be turned on, the voltage value of the first feedback signal VMS is , where N1 is the number of turns of the first winding, N p is the number of turns of the primary winding Np, is the resistance of the first voltage divider resistor Rup, is the resistance of the second voltage-dividing resistor Rdw.

[0228] After the NMOS lower tube Q2 is turned off, the circuit enters the excitation inductor reset period. The controller U1 internally clamps the VMS pin voltage to a lower voltage, such as zero volts or 0.1V. In this case, the output voltage signal can be obtained by sampling the current signal of the first feedback signal VMSVMS, and the current value is related to , where Vo is the voltage value of the output voltage, and Ns is the number of turns of the secondary winding Ns.

[0229] exist Figure 7 In the example, the first winding is an auxiliary winding Naux, and the polarity of the auxiliary winding Naux is opposite to that of the secondary winding Ns.

[0230] In a preferred embodiment, the power circuit may further include an electromagnetic shielding circuit ( Figure 7 (not shown), the electromagnetic shielding circuit includes an EMI shielding layer winding, a first output end of the EMI shielding layer winding N-E_shield is suspended NC, and a second output end thereof is at a fixed potential point.

[0231] For example, the fixed potential point may be ground or an EMI quiescent point voltage, such as a relatively fixed potential point such as VCC or Vin.

[0232] In another embodiment, please refer to Figure 8 The first winding may also be an EMI shielding layer winding N-E_shield, and the polarity of the first winding is opposite to that of the secondary winding Ns.

[0233] It can be seen that the present invention cleverly utilizes the original shielding layer winding of the transformer to undertake the input voltage Vin sampling and output voltage Vo sampling functions, without adding any additional windings or optocoupler devices, further simplifying the power circuit design.

[0234] In actual work, the frequency of the internal clock signal changes with the load size. Generally, the heavier the load, the higher the frequency of the internal clock signal, and the lighter the load, the lower the frequency of the internal clock signal. On this basis, please refer to Figure 7 The eighth terminal FB of the controller U1 also receives the output voltage Vo. The controller U1 is further configured to control the frequency of the internal clock signal based on the voltage value of the output voltage Vo.

[0235] On this basis, a specific implementation method, please continue to refer to Figure 7 , the secondary circuit further includes a first feedback module 10, and the primary circuit further includes a second feedback module 20;

[0236] The first feedback module 10 is connected in parallel with the first capacitor C1, and the first feedback module 10 is used to obtain the output voltage Vo and output a second feedback signal, where the second feedback signal includes voltage value information of the output voltage Vo;

[0237] A first end of the second feedback module 20 is coupled to the eighth end FB of the controller U1, a second end of the second feedback module 20 is grounded, and a receiving end of the second feedback module 20 receives the second feedback signal. The second feedback module 20 is used to transmit the voltage value information of the output voltage Vo to the controller U1.

[0238] As an example, the first feedback module 10 may be an output end of an optocoupler, and the second feedback module 20 may be a receiving end of an optocoupler. Of course, the present invention is not limited to this, and those skilled in the art may select appropriate components as needed.

[0239] In actual operation, the controller U1 also controls the conduction time of the NMOS lower tube Q2. For a specific implementation, please refer to Figure 7 The primary circuit further includes a current sampling module, which is used to obtain the current flowing through the first node m and output a third feedback signal to the fifth terminal Vcs of the controller U1, wherein the third feedback signal includes current value information of the current flowing through the first node m;

[0240] The controller U1 is further configured to determine, based on the third feedback signal, a turn-on time and a turn-off time of the NMOS lower tube Q2 in each switching cycle of the internal clock signal.

[0241] exist Figure 7 In the example, the current sampling module includes a first NMOS transistor NM1 and a sampling resistor Rsns;

[0242] The gate of the first NMOS transistor NM1 is coupled to the control terminal of the NMOS lower transistor Q2, the drain of the first NMOS transistor NM1 is coupled to the sixth terminal of the controller U1, and the source thereof is grounded. The first terminal of the sampling resistor Rsns is coupled to the fifth terminal Vcs of the controller U1, and the second terminal thereof is grounded.

[0243] The controller U1 is further configured to: output a first current to the fifth terminal Vcs of the controller U1 and obtain a voltage value of the first terminal of the sampling resistor Rsns, wherein the current value of the first current is equal to the current value of the current flowing through the sixth terminal of the controller U1.

[0244] Of course, the present invention does not limit the method of obtaining the current flowing through the first node m. In other embodiments, please refer to Figure 8 The current sampling module includes a sampling resistor Rsns, which is connected in series between the first node m and the drain of the NMOS lower tube Q2. The fifth terminal Vcs of the controller U1 is used to obtain the voltage across the sampling resistor Rsns to obtain current value information of the current flowing through the first node m.

[0245] In actual work, please refer to Figure 8 The primary circuit also includes a rectifier module 30 and a power supply module 40. The power supply side capacitor Cin is connected in parallel with the rectifier module 30. The input end of the rectifier module 30 and the input end of the power supply module 40 are both coupled to the AC power supply. The output end of the power supply module 40 is coupled to the high-voltage power supply end of the controller U1.

[0246] In this case, the controller U1 is configured to: when the voltage value of the AC power supply is less than the fifth voltage threshold and the voltage value of the AC power supply is greater than or equal to 0, control the first switch Q3 to be turned on, or control the constant current source Ist to be in the on state and control the first switch Q3 to be turned on.

[0247] This embodiment can be understood as follows: when the chip power supply capacitor Cvcc needs to be charged, the controller U1 is configured to control the constant current source Ist to work and the first switch Q3 to be turned on only when the AC power is near zero point, so as to complete power collection.

[0248] Specifically, when the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L and the AC power of the AC power source is near a zero-crossing point, the first switch Q3 is controlled to be turned on;

[0249] When the voltage of the power supply terminal VCC is less than or equal to the third voltage threshold VCC_Min and the AC power of the AC power source is near a zero point, the first switch Q3 is controlled to be turned on and the constant current source Ist is controlled to be in an on state.

[0250] In this way, the present invention can further optimize the power supply efficiency of the power circuit.

[0251] For a specific implementation, please continue to refer to Figure 8 , the AC power supply includes an AC live wire ACL and an AC neutral wire ACN, and the power taking module 40 includes a fourth diode D4, a fifth diode D5 and a third resistor Rhv;

[0252] The cathode of the fourth diode D4 and the anode of the fifth diode D5 are coupled to the AC live line ACL and the AC neutral line ACN, respectively. The cathode of the fourth diode D4 and the cathode of the fifth diode D5 are both coupled to the first end of the third resistor Rhv. The second end of the third resistor Rhv is coupled to the high-voltage power terminal HV of the controller U1.

[0253] In summary, the embodiment of the present invention designs a primary winding of the power circuit where the self-powered chip system is located to receive the input voltage at one end, and the other end is grounded in sequence through the J-FET upper tube, the first node and the NMOS lower tube. The control end of the J-FET upper tube is grounded, and one end of the chip power supply capacitor of the self-powered chip system is grounded, and the other end is coupled to the first node through the constant current source and the first switch in the default on state. The chip power supply capacitor supplies power to the power supply end of the controller. Since the power supply voltage required by the controller is less than the pinch-off voltage of the J-FET upper tube, the present invention self-powers the controller through the constant current source when power is turned on, and losslessly self-powers the controller by controlling the first switch to turn on when the voltage at the power supply end is less than or equal to the first voltage threshold. When the voltage at the power supply end is less than or equal to the third voltage threshold, the controller is self-powered by simultaneously controlling the constant current source and the first switch to turn on when the voltage at the power supply end is less than or equal to the third voltage threshold. This not only simplifies the power supply circuit of the controller, but also improves the power supply efficiency of the circuit.

[0254] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A self-powered chip system, characterized in that: The system is applied to a power circuit, wherein the power circuit includes a primary circuit, the primary circuit including a primary winding, a J-FET upper tube, and an NMOS lower tube. A first end of the primary winding receives an input voltage, and a second end thereof is grounded via the J-FET upper tube and the NMOS lower tube in sequence. A control end of the J-FET upper tube is coupled to ground, and the J-FET upper tube and the NMOS lower tube are coupled via a first node. The self-powered chip system includes: a chip power supply capacitor, a constant current source, a first switch and a controller, wherein the constant current source is in an on state by default; The first end of the chip power supply capacitor is grounded, and the second end thereof is coupled to the first node through the constant current source and the first switch respectively; the power supply end of the controller is coupled to the second end of the chip power supply capacitor, the first end thereof is coupled to the control end of the constant current source, and the second end thereof is coupled to the control end of the first switch; The controller is configured to: enter a normal working state and control the constant current source to enter an off state when the voltage at the power supply end reaches a starting voltage, and the starting voltage is less than a pinch-off voltage of the J-FET upper tube; After entering the normal working state, the working state of the constant current source and the on / off of the first switch are controlled based on the voltage of the power supply end, wherein: When the voltage at the power supply end is less than or equal to a first voltage threshold, controlling the first switch to be turned on until the voltage at the power supply end is greater than or equal to a second voltage threshold, the starting voltage is greater than the second voltage threshold, and the second voltage threshold is greater than the first voltage threshold; When the voltage at the power supply end is less than or equal to a third voltage threshold, the constant current source is controlled to be in an on state until the voltage at the power supply end is greater than or equal to a first voltage threshold, and the third voltage threshold is less than the first voltage threshold.

2. The self-powered chip system according to claim 1, wherein: The third terminal of the controller is coupled to the control terminal of the NMOS lower tube; The controller is further configured to: generate an internal clock signal when the controller is in a normal working state; and The on / off of the NMOS lower tube is controlled based on the internal clock signal.

3. The self-powered chip system according to claim 2, wherein: The method of controlling the first switch to be turned on when the voltage at the power supply end is less than or equal to a first voltage threshold until the voltage at the power supply end is greater than or equal to a second voltage threshold includes: In a current switching cycle of the internal clock signal, if the voltage of the power supply end is less than or equal to a first voltage threshold, controlling the first switch to remain in an off state; When the internal clock signal enters a switching cycle after the current switching cycle, if the voltage at the power supply end is less than the second voltage threshold, performing the following steps in each switching cycle of the internal clock signal until the voltage at the power supply end is greater than or equal to the second voltage threshold: Controlling the first switch to be turned on and the NMOS lower tube to be turned on in sequence; After the NMOS lower tube is turned on, the first switch is controlled to be turned off.

4. The self-powered chip system according to claim 3, wherein: The first switch is controlled to be turned on at the beginning of a switching cycle.

5. The self-powered chip system according to claim 3, wherein: After the NMOS lower tube is turned on, controlling the first switch to be turned off includes: The first switch and the NMOS lower tube are controlled to be disconnected at the same time.

6. The self-powered chip system according to claim 3, wherein: After the first switch is turned off, the NMOS lower tube is controlled to be turned off.

7. The self-powered chip system according to claim 2, wherein: The method of controlling the first switch to be turned on when the voltage at the power supply end is less than or equal to a first voltage threshold until the voltage at the power supply end is greater than or equal to a second voltage threshold includes: In a current switching cycle of the internal clock signal, if the voltage of the power supply end is less than or equal to a first voltage threshold, controlling the first switch to remain in an off state; When the internal clock signal enters a switching cycle after the current switching cycle, if the voltage at the power supply end is less than the second voltage threshold, performing the following steps in each switching cycle of the internal clock signal until the voltage at the power supply end is greater than or equal to the second voltage threshold: Control the first switch to be turned on or the NMOS lower tube to be turned on.

8. The self-powered chip system according to claim 7, wherein: When the internal clock signal enters a first switching cycle after the current switching cycle, the first switch is controlled to be turned on.

9. The self-powered chip system according to claim 2, wherein: When the voltage at the power supply end is less than or equal to a third voltage threshold, controlling the constant current source to be in an on state comprises: In a current switching cycle of the internal clock signal, if the voltage of the power supply end is less than or equal to a third voltage threshold, controlling the constant current source to be in an on state; When the internal clock signal enters a switching cycle after the current switching cycle, the first switch is controlled to be turned on, and the first switch is turned on before the NMOS lower tube.

10. The self-powered chip system according to claim 2, wherein: The self-powered chip system further includes a first diode; the cathode of the first diode is coupled to the second end of the chip power supply capacitor, An anode of the first diode is coupled to the first node through the first switch.

11. The self-powered chip system according to any one of claims 2 to 10, characterized in that: The power circuit further includes a secondary circuit and a first circuit respectively magnetically coupled to the primary winding; The secondary circuit is used to sense the change in magnetic flux of the primary winding and output an output voltage; The first circuit is used to sense the change in magnetic flux of the primary winding and output a first feedback signal; The fourth terminal of the controller receives the first feedback signal, and the controller is further configured to: control the working state of the power circuit based on the first feedback signal and the on-off state of the NMOS lower tube, wherein: When controlling the NMOS lower tube to be turned on, obtaining a voltage value of the first feedback signal, and controlling whether the primary circuit enters a protection state based on the voltage value of the first feedback signal; When controlling the NMOS lower tube to be disconnected, the voltage value and the current value of the first feedback signal are obtained, and when the voltage value of the first feedback signal is less than or equal to a fourth voltage threshold, the secondary circuit is controlled to enter a protection state based on the current value of the first feedback signal.

12. The self-powered chip system according to claim 11, wherein: The first circuit includes a first winding, a first voltage-dividing resistor, and a second voltage-dividing resistor; The first output end of the first winding is coupled to the first end of the first voltage-dividing resistor, the second end of the first voltage-dividing resistor is coupled to the first end of the second voltage-dividing resistor through a second node, the second end of the second voltage-dividing resistor is coupled to the second output end of the first winding, and the second node is coupled to the fourth end of the controller for outputting the first feedback signal.

13. The self-powered chip system according to claim 12, wherein: The secondary circuit includes a secondary winding, a second diode, a first capacitor and a first resistor; The first output end of the secondary winding is coupled to the first end of the first capacitor through the second diode, the second end of the first capacitor is coupled to the second output end of the secondary winding, and the first capacitor is connected in parallel with the first resistor.

14. The self-powered chip system according to claim 13, wherein: The first winding is an EMI shielding layer winding, and the polarity of the first winding is opposite to the polarity of the secondary winding.

15. The self-powered chip system according to claim 13, wherein: The first winding is an auxiliary winding.

16. The self-powered chip system according to claim 13, wherein: An eighth terminal of the controller receives the output voltage, and the controller is further configured to control the frequency of the internal clock signal based on a voltage value of the output voltage.

17. The self-powered chip system according to claim 16, wherein: The secondary circuit further includes a first feedback module, and the primary circuit further includes a second feedback module; The first feedback module is connected in parallel with the first capacitor, and the first feedback module is used to obtain the output voltage and output a second feedback signal, wherein the second feedback signal includes voltage value information of the output voltage; The first end of the second feedback module is coupled to the eighth end of the controller, the second end of the second feedback module is grounded, the receiving end of the second feedback module receives the second feedback signal, and the second feedback module is used to transmit the voltage value information of the output voltage to the controller.

18. The self-powered chip system according to any one of claims 2 to 10, wherein: The primary circuit further includes a current sampling module, which is used to obtain the magnitude of the current flowing through the first node and output a third feedback signal to the fifth terminal of the controller, wherein the third feedback signal includes current value information of the current flowing through the first node; The controller is further configured to determine, based on the third feedback signal, a turn-on time and a turn-off time of the NMOS low-side transistor in each switching cycle of the internal clock signal.

19. The self-powered chip system according to claim 18, wherein: The current sampling module includes a first NMOS tube and a sampling resistor; The gate of the first NMOS transistor is coupled to the control terminal of the NMOS lower transistor, the drain of the first NMOS transistor is coupled to the sixth terminal of the controller, and the source thereof is grounded; the first terminal of the sampling resistor is coupled to the fifth terminal of the controller, and the second terminal thereof is grounded; The controller is further configured to: output a first current to the fifth terminal of the controller and obtain a voltage value of the first terminal of the sampling resistor, wherein the current value of the first current is equal to the current value of the current flowing through the sixth terminal of the controller.

20. The self-powered chip system according to claim 18, wherein: The current sampling module includes a sampling resistor, which is connected in series between the first node and the drain of the NMOS lower tube. The fifth terminal of the controller is used to obtain the voltage across the sampling resistor to obtain current value information of the current flowing through the first node.

21. The self-powered chip system according to claim 1, wherein: The primary circuit further includes an RCD absorption module, and the RCD absorption module includes a second resistor, a second capacitor and a third diode; The first end of the primary winding is coupled to the first end of the second capacitor and the first end of the second resistor, respectively. The second end of the second capacitor is coupled to the second end of the second resistor and the cathode of the third diode, respectively. The anode of the third diode is coupled to the second end of the primary winding.

22. The self-powered chip system according to claim 1, wherein: The primary circuit further includes a power supply side capacitor, and the first end of the primary winding is grounded via the power supply side capacitor.

23. The self-powered chip system according to claim 22, wherein: The primary circuit further includes a rectifier module and a power-taking module. The power-side capacitor is connected in parallel to the rectifier module. The input end of the rectifier module and the input end of the power-taking module are both coupled to an AC power supply. The output end of the power-taking module is coupled to a high-voltage power-taking end of the controller. The controller is configured to: when the voltage value of the AC power supply is less than a fifth voltage threshold and the voltage value of the AC power supply is greater than or equal to 0, control the first switch to be turned on, or control the constant current source to be in an on state and control the first switch to be turned on.

24. The self-powered chip system according to claim 23, wherein: The AC power supply includes an AC live wire and an AC neutral wire, and the power taking module includes a fourth diode, a fifth diode and a third resistor; The cathode of the fourth diode and the anode of the fifth diode are respectively coupled to the AC live wire and the AC neutral wire, the cathode of the fourth diode and the cathode of the fifth diode are both coupled to the first end of the third resistor, and the second end of the third resistor is coupled to the high-voltage power supply terminal of the controller.

25. The self-powered chip system according to claim 1, wherein: The self-powered chip system further includes an on-off speed control module, wherein the on-off speed control module includes a sixth diode and a fourth resistor; The first end of the fourth resistor is coupled to the control end of the J-FET upper tube, and the second end thereof is coupled to the anode of the sixth diode; the cathode of the sixth diode is coupled to the second end of the fourth resistor.

26. The self-powered chip system according to claim 1, wherein: The seventh terminal of the controller is further coupled to the first node; The controller is further configured to control whether the primary circuit enters a protection state based on a voltage value and / or a current value of the first node.

27. The self-powered chip system according to claim 1, wherein: The constant current source also has a current limiting function.

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