Electronic component, filter, and multiplexer

Abstract

The invention provides an electronic component, a filter, and a multiplexer. The electronic component suppresses the occurrence of cracks toward the sealing part. The electronic component is provided with: a support substrate (10); an element provided on the support substrate (10); a cover (30) provided on the support substrate (10) so as to sandwich a gap from which the component is exposed with the support substrate (10); a metal layer (42), which is positioned between the support substrate (10) and the cover (30), has an annular structure provided around the element when the support substrate (10) is viewed from the element side, and has a thickness equal to or greater than 1 / 2 of the interval (D) between the support substrate (10) and the cover (30); and a metal layer (41) located between the metal layer (42) and the support substrate (10), the electrical conductivity of the metal layer (41) being lower than the electrical conductivity of the metal layer (42), the metal layer (41) being thinner than the metal layer (42), and the Young's modulus of the metal layer (41) being greater than the Young's modulus of the metal layer (42).

Description

Technical Field

[0001] The present invention relates to an electronic component, a filter, and a multiplexer. Background Art

[0002] There is known an electronic component in which an element is provided on a substrate, a frame is provided so as to surround the element, and a lid is provided on the frame, whereby the element is sealed in a gap (for example, Patent Document 1, Patent Document 2).

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2005-317568

[0004] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2006-185966

[0005] The frame surrounding the element is sometimes formed of a plurality of metal layers. In this case, cracks sometimes occur between the metal layers due to thermal stress. When cracks occur, the sealing performance deteriorates. Summary of the Invention

[0006] The present invention has been made in view of the above problems, and an object thereof is to suppress the occurrence of cracks.

[0007] The present invention is an electronic component having: a substrate; an element provided on the substrate; a lid provided on the substrate so as to sandwich a gap exposing the element with the substrate; a first metal layer located between the substrate and the lid, having an annular structure provided around the element when the substrate is viewed from the element side, and having a thickness of 1 / 2 or more of the interval between the substrate and the lid; and a second metal layer located between the first metal layer and the substrate, having a lower conductivity than the first metal layer, being thinner than the first metal layer, and having a larger Young's modulus than the first metal layer.

[0008] In the above structure, it may be configured such that the coefficient of linear expansion of the second metal layer is greater than the coefficient of linear expansion of the substrate and less than the coefficient of linear expansion of the first metal layer.

[0009] In the above structure, it may be configured such that the thickness of the second metal layer is 1 / 200 or more and 1 / 10 or less of the thickness of the first metal layer.

[0010] In the above structure, it may be configured such that the electronic component further has a third metal layer located between the substrate and the second metal layer, and the difference in coefficient of linear expansion between the third metal layer and the first metal layer is greater than the difference in coefficient of linear expansion between the first metal layer and the second metal layer.

[0011] In the above structure, it may also be configured such that the substrate is silicon or sapphire, the first metal layer is copper, the second metal layer is nickel, and the third metal layer is titanium.

[0012] In the above structure, it may also be configured such that the electronic component further includes: a solder layer located between the first metal layer and the lid; and a barrier layer located between the first metal layer and the solder layer to inhibit diffusion between the first metal layer and the solder layer.

[0013] In the above structure, it may also be configured such that the element is a surface acoustic wave element.

[0014] The present invention is a filter including the electronic component described above.

[0015] The present invention is a multiplexer including the filter described above.

[0016] According to the present invention, generation of cracks can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 (a) of is a cross-sectional view of the electronic component of Example 1, Figure 1 and (b) of is a plan view.

[0018] Figure 2 is a cross-sectional view showing the layer structure of the housing of Example 1.

[0019] Figure 3 (a) of is a plan view of the surface acoustic wave element of Example 1, Figure 3 and (b) of is a cross-sectional view of another example of the surface acoustic wave element of Example 1.

[0020] Figure 4 (a) to Figure 4 (d) of are cross-sectional views showing the manufacturing method of the electronic component of Example 1.

[0021] Figure 5 is a cross-sectional view showing the layer structure of the housing of the comparative example.

[0022] Figure 6 (a) and Figure 6 (b) of are cross-sectional views showing the housing after the temperature cycle test of the comparative example and Example 1.

[0023] Figure 7 (a) of is a plan view of the model for which simulation has been performed, Figure 7 (b) of is along Figure 7 (a) of is a cross-sectional view taken along line A-A.

[0024] Figure 8 is a diagram showing the result of Simulation 1.

[0025] Figure 9 It is a diagram showing the results of Simulation 2.

[0026] Figure 10 (a) thereof is a diagram obtained based on the results of Simulation 2, Figure 10 (b) thereof and Figure 10 (c) thereof are diagrams obtained based on the results of Simulation 1.

[0027] Figure 11 (a) is a circuit diagram of the filter of Example 2, Figure 11 (b) thereof is a circuit diagram of the duplexer of a modified example of Example 2.

[0028] Reference Numeral Explanation

[0029] 10: Support substrate; 12: Piezoelectric layer; 14: Terminal; 16: Via wiring; 18: Housing; 20: Wiring; 22: Gap; 30: Cover; 40: Metal layer; 41: Metal layer; 42: Metal layer; 43: Metal layer; 44: Solder layer; 50: Surface acoustic wave device; 51: IDT; 52: Reflector; 53: Comb-shaped electrode; 54: Electrode finger; 55: Bus bar; 56: Lower electrode; 57: Upper electrode; 58: Gap; 59: Resonant region; 60: Metal layer; 61: Metal layer; 62: Metal layer; 63: Solder layer; 65: Crack; 70: Support substrate; 72: Housing; 74: Cover; 76: Metal layer; 78: Solder layer; 80: Transmit filter; 82: Receive filter; 100: Electronic component; 200: Filter; 210: Duplexer. Detailed Description of the Invention

[0030] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0031]

Example 1

[0032] Figure 1 (a) thereof is a cross-sectional view of the electronic component 100 of Example 1, Figure 1 (b) thereof is a plan view. The thickness direction of the support substrate 10 is set as the Z direction, and the directions perpendicular to each other in the plane direction of the support substrate 10 are set as the X direction and the Y direction. In Figure 1 (b) thereof, the support substrate 10, the piezoelectric layer 12, the housing 18, and the surface acoustic wave device 50 are schematically illustrated, and the piezoelectric layer 12, the housing 18, and the surface acoustic wave device 50 are hatched for clarity of the drawing.

[0033] As Figure 1 (a) thereof and Figure 1As shown in (b), a piezoelectric layer 12 is bonded to the upper surface of a support substrate 10 (substrate). The support substrate 10 is, for example, a sapphire substrate, an alumina substrate, a silicon substrate, a spinel substrate, a quartz substrate, a quartz substrate, or a silicon carbide substrate. The sapphire substrate is a single crystal Al2O3 substrate, the alumina substrate is a polycrystalline or amorphous Al2O3 substrate, and the silicon substrate is a single crystal or polycrystalline silicon substrate. The spinel substrate is a polycrystalline or amorphous MgAl2O4 substrate, the quartz substrate is a single crystal SiO2 substrate, the quartz substrate is a polycrystalline or amorphous SiO2 substrate, and the silicon carbide substrate is a polycrystalline or single crystal SiC substrate.

[0034] The piezoelectric layer 12 is, for example, a single crystal lithium tantalate (LiTaO3) layer or a single crystal lithium niobate (LiNbO3) layer, for example, a rotated Y-cut X-propagating lithium tantalate layer or a rotated Y-cut X-propagating lithium niobate layer. An insulating layer such as silicon oxide, aluminum oxide, and / or aluminum nitride may be provided between the support substrate 10 and the piezoelectric layer 12. In this way, the piezoelectric layer 12 is bonded to the support substrate 10 directly or indirectly.

[0035] An elastic wave element 50 and a wiring 20 are provided on the piezoelectric layer 12. The elastic wave element 50 is, for example, a surface acoustic wave element. The wiring 20 is electrically connected to the elastic wave element 50. A via wiring 16 penetrating the support substrate 10 is provided. Terminals 14 are provided on the lower surface of the support substrate 10. The terminals 14 are bottom pads for electrically connecting the elastic wave element 50 to the outside. The via wiring 16 electrically connects the wiring 20 and the terminals 14. The terminals 14, the via wiring 16, and the wiring 20 are, for example, metal layers containing titanium, copper, aluminum, platinum, nickel, and / or gold.

[0036] The piezoelectric layer 12 is not provided in the peripheral region of the support substrate 10. When viewed from the Z direction, a frame 18 is provided on the support substrate 10 so as to surround the piezoelectric layer 12 and the elastic wave element 50. A cover 30 is provided on the frame 18 so as to form a gap 22 exposing the elastic wave element 50 between the cover 30 and the support substrate 10. The frame 18 connects between the support substrate 10 and the cover 30. The elastic wave element 50 is sealed in the gap 22 by the frame 18 and the cover 30. The cover 30 includes a metal plate such as a kovar plate, an insulating plate such as a silicon plate or a sapphire plate, or a piezoelectric plate such as a lithium tantalate plate or a lithium niobate plate.

[0037] Figure 2 is a cross-sectional view showing the layer structure of the frame 18 of Example 1. As Figure 2As shown, the housing 18 has a metal layer 40, a metal layer 41, a metal layer 42, a metal layer 43, and a solder layer 44 (metal layer) laminated in sequence from the support substrate 10 side. The metal layer 40 is a titanium layer with a thickness of, for example, 0.05 μm, and is an adhesion layer between the support substrate 10 and the housing 18. The metal layer 40 is formed by sputtering. The metal layer 41 is a nickel layer with a thickness of, for example, 0.2 μm. The metal layer 41 is formed by sputtering. The metal layer 42 is a copper layer with a thickness of, for example, 21 μm, and is the thickest and highest conductivity layer in the housing 18. The thickness of the metal layer 42 is 50% or more, or 60% or more, or 70% or more of the distance D between the support substrate 10 and the cover 30. The metal layer 42 includes a seed layer formed by sputtering and a plating layer formed by electroplating. The metal layer 43 is a nickel layer with a thickness of, for example, 2.5 μm, and is a barrier layer (diffusion prevention layer) that inhibits diffusion between the metal layer 42 and the solder layer 44. The metal layer 43 is formed by electroplating. The solder layer 44 is a gold-tin solder layer with a thickness of, for example, 4 μm. The solder layer 44 is formed by electroplating.

[0038] In addition, the housing 18 may include other metal layers in addition to or instead of the above. For example, it may include a gold layer, a silver layer, a tungsten layer, etc. Also, the solder layer 44 may be a silver-tin solder layer or a silver-copper-tin solder layer.

[0039] Regarding the width of the housing 18, as an example, it is 20 μm, for example, 10 μm to 40 μm. Regarding the height of the housing 18, as an example, it is 27.75 μm as described above, for example, 20 μm to 40 μm. The thickness of the support substrate 10 is, for example, 50 μm to 300 μm, the thickness of the piezoelectric layer 12 is, for example, 0.5 μm to 30 μm, and the thickness of the cover 30 is, for example, 10 μm to 200 μm.

[0040] Figure 3 (a) is a plan view of the surface acoustic wave device 50 of Example 1. As Figure 3As shown in (a) of [description], the elastic wave element 50 is a surface acoustic wave resonator. An IDT (Interdigital Transducer) 51 and a reflector 52 are provided on the piezoelectric layer 12. The IDT 51 has a pair of opposed comb-shaped electrodes 53. The comb-shaped electrodes 53 have a plurality of electrode fingers 54 and bus bars 55 connected to the plurality of electrode fingers 54. The reflectors 52 are provided on both sides of the IDT 51. The plurality of electrode fingers 54 excite surface acoustic waves in the piezoelectric layer 12. The pitch of the electrode fingers 54 of one of the pair of comb-shaped electrodes 53 is approximately the wavelength λ of the elastic wave. Twice the pitch D of the plurality of electrode fingers 54 is approximately the wavelength λ of the elastic wave. The IDT 51 and the reflectors 52 are formed of a metal film such as aluminum, copper, or molybdenum, for example. A protective film or a temperature compensation film covering the IDT 51 and the reflectors 52 may also be provided on the piezoelectric layer 12. The comb-shaped electrodes 53 may also have dummy electrode fingers.

[0041] Figure 3 (b) is a cross-sectional view of another example of the elastic wave element 50 of Embodiment 1. As Figure 3 shown in (b) of [description], the elastic wave element 50 may also be a piezoelectric thin film resonator. A piezoelectric layer 12 is provided on a support substrate 10, and a lower electrode 56 and an upper electrode 57 are provided so as to sandwich the piezoelectric layer 12. A gap 58 is formed between the lower electrode 56 and the support substrate 10. The region where at least a part of the piezoelectric layer 12 is sandwiched and the lower electrode 56 and the upper electrode 57 are opposed to each other is a resonance region 59. In the resonance region 59, the lower electrode 56 and the upper electrode 57 excite elastic waves in the piezoelectric layer 12. The lower electrode 56 and the upper electrode 57 are metal films including a ruthenium film, for example. The piezoelectric layer 12 is an aluminum nitride layer, a zinc oxide layer, a single crystal lithium tantalate layer, or a single crystal lithium niobate layer, for example. An acoustic reflection film that reflects elastic waves may be provided instead of the gap 58.

[0042] [Manufacturing Method]

[0043] Figure 4 (a) to Figure 4 (d) are cross-sectional views showing the manufacturing method of the electronic component 100 of Embodiment 1. As Figure 4As shown in (a) of [reference], for example, a laser is irradiated onto the upper surface of the support substrate 10 to form vias, and a metal layer such as copper is formed in the vias using, for example, a plating method. Then, the metal layer is planarized using a CMP (Chemical Mechanical Polishing) method so that the upper surface of the support substrate 10 is exposed, and via wirings 16 are formed on the support substrate 10. Next, the piezoelectric substrate is bonded to the upper surface of the support substrate 10 at room temperature using, for example, a surface activation method. The support substrate 10 and the piezoelectric substrate may be directly bonded via an amorphous layer of several nm or the like, or may be indirectly bonded via an insulating layer. After that, the piezoelectric substrate is polished using, for example, a CMP method to form a piezoelectric layer 12 that is directly or indirectly bonded to the upper surface of the support substrate 10.

[0044] As Figure 4 As shown in (b) of [reference], a part of the piezoelectric layer 12 is removed using, for example, an etching method. Thus, the piezoelectric layer 12 in the peripheral region of the support substrate 10 is removed. Next, an elastic wave element 50 is formed on the piezoelectric layer 12. A wiring 20 connected to the elastic wave element 50 is formed.

[0045] As Figure 4 As shown in (c) of [reference], a frame 18 is formed on the support substrate 10 so as to surround the piezoelectric layer 12. Next, a lid 30 is bonded to the frame 18. Thus, the elastic wave element 50 is sealed in the gap 22 by the frame 18 and the lid 30.

[0046] As Figure 4 As shown in (d) of [reference], the lower surface of the support substrate 10 is polished using, for example, a CMP method. Thus, the via wirings 16 are exposed from the lower surface of the support substrate 10. Terminals 14 connected to the via wirings 16 are formed on the lower surface of the support substrate 10. Thus, the electronic component 100 of Example 1 is formed.

[0047] [Comparative Example]

[0048] Figure 5 It is a cross-sectional view showing the layer structure of the frame 18 of the comparative example. As Figure 5As shown, in the comparative example, the housing 18 has a metal layer 60, a metal layer 61, a metal layer 62, and a solder layer 63 from the side of the support substrate 10. The metal layer 60 is a titanium layer with a thickness of 0.05 μm as an example, and is the bonding layer between the support substrate 10 and the housing 18. The metal layer 61 is a copper layer with a thickness of 21 μm as an example, and is the thickest and highest conductivity layer in the housing 18. The thickness of the metal layer 61 is more than 50% of the interval D between the support substrate 10 and the cover 30. The metal layer 62 is a nickel layer with a thickness of 2.5 μm as an example, and is the barrier layer between the metal layer 61 and the solder layer 63. The solder layer 63 is a gold-tin solder layer with a thickness of 4 μm as an example. The other structures of the electronic component in the comparative example are the same as those in Example 1, so the illustration and description are omitted.

[0049] The following temperature cycle test was performed on the electronic components of Example 1 and the comparative example: The temperature was changed between -65°C and +150°C, and held at -65°C and +150°C for 15 minutes respectively. Figure 6 of (a) and Figure 6 of (b) are cross-sectional views showing the housing 18 after the temperature cycle test of the comparative example and Example 1. As Figure 6 shown in (a), in the comparative example, cracks 65 occurred at the interface between the metal layer 60 and the metal layer 61 in the housing 18. On the other hand, as Figure 6 shown in (b), in Example 1, no cracks occurred in the housing 18.

[0050] [Simulation]

[0051] Figure 7 of (a) is a plan view of the model on which the simulation was performed, Figure 7 of (b) is a cross-sectional view along the Figure 7 A-A line of (a). As Figure 7 shown in (a) and Figure 7 shown in (b), the model on which the simulation was performed has a housing 72 provided at the periphery of the support substrate 70. A cover 74 is provided on the housing 72. The housing 72 is composed of a metal layer 76 and a solder layer 78. For models A to E having the Figure 7 structure shown in (a) and Figure 7 shown in (b), a 2D simulation 1 equivalent to the temperature cycle test was performed, and the cumulative strain applied to the metal layer 76 was measured. The conditions of simulation 1 are as follows.

[0052] Common conditions for models A to E

[0053] Support substrate 70: A sapphire substrate with a length L1 of 0.45 mm and a length L2 of 0.075 mm

[0054] Cover 74: A kovar alloy plate with a length L1 of 0.45 mm and a length L2 of 0.03 mm

[0055] Conditions of Model A

[0056] Metal layer 76 of the housing 72: A copper layer with a thickness of 10 μm

[0057] Solder layer 78 of the housing 72: A gold - tin layer with a thickness of 4 μm

[0058] Width W of the housing 72: 23 μm

[0059] Conditions of Model B

[0060] Metal layer 76 of the housing 72: A copper layer with a thickness of 20 μm

[0061] Solder layer 78 of the housing 72: A gold - tin layer with a thickness of 4 μm

[0062] Width W of the housing 72: 23 μm

[0063] Conditions of Model C

[0064] Metal layer 76 of the housing 72: A copper layer with a thickness of 30 μm

[0065] Solder layer 78 of the housing 72: A gold - tin layer with a thickness of 4 μm

[0066] Width W of the housing 72: 23 μm

[0067] Conditions of Model D

[0068] Metal layer 76 of the housing 72: A copper layer with a thickness of 20 μm

[0069] Solder layer 78 of the housing 72: A gold - tin layer with a thickness of 14 μm

[0070] Width W of the housing 72: 23 μm

[0071] Conditions of Model E

[0072] Metal layer 76 of the housing 72: A copper layer with a thickness of 20 μm

[0073] Solder layer 78 of the housing 72: A gold - tin layer with a thickness of 4 μm

[0074] Width W of the housing 72: 46 μm

[0075] Table 1 is a table showing the Young's modulus and coefficient of linear expansion of each material used in Simulation 1.

[0076]

Table 1

[0077]

[0078] Figure 8 is a graph showing the results of Simulation 1. In Figure 8In [the figure], the horizontal axis represents steps, the left vertical axis represents the maximum value of the cumulative strain applied to the metal layer 76, and the right vertical axis represents temperature. Table 2 is a table showing the results of Simulation 1.

[0079]

Table 2

[0080]

[0081] As Figure 8 shown in [the figure] and Table 2, the cumulative strain of Model B is less than that of Model A. The cumulative strain of Model C is less than that of Model B. Models A, B, and C differ only in the thickness of the metal layer 76 (copper layer). From this result, the following result was obtained: the thicker the metal layer 76, the smaller the cumulative strain. Also, compared with Model B, the cumulative strain of Model E is larger. Models B and E differ only in the width W of the frame 72. From this result, the following result was obtained: when the width W of the frame 72 increases, the cumulative strain of the metal layer 76 increases. The ratio of the thickness of the copper layer to the width W of the frame 72 is 0.43 in the case of Model A, 0.87 in the cases of Models B and D, 1.30 in the case of Model C, and 0.43 in the case of Model E. In all cases of Models A to E, the cumulative strain is the largest at the inner side of the lower end of the frame 72 shown in Region A of (b) in Figure 7 [the figure].

[0082] Based on the results of Simulation 1, it is considered that the crack 65 occurred at the interface between the metal layer 60 and the metal layer 61 in the comparative example for the following reasons. When performing the temperature cycle test, the support substrate 10 and the cover 30 thermally expand and contract corresponding to their respective coefficients of linear expansion. For example, when the support substrate 10 is a sapphire substrate and the cover 30 is a kovar alloy plate, the coefficient of linear expansion of sapphire is greater than that of kovar alloy. Therefore, when the support substrate 10 and the cover 30 thermally expand and contract corresponding to their coefficients of linear expansion, the strain becomes large at the connection part of the frame 18 with Figure 7 the support substrate 10 as shown in Region A of (b) in [[the figure]]. Since the frame 18 preferably has a high conductivity, the thickness of the metal layer 61, which is the copper layer with the highest conductivity in the frame 18, is 50% or more of the interval D between the support substrate 10 and the cover 30. The Young's modulus of copper is relatively small. Thus, with a thick metal layer 61 and a small Young's modulus, the metal layer 61 is likely to bend due to the thermal expansion and contraction of the support substrate 10 and the cover 30 respectively. Since the metal layer 61 is located near the connection part of the frame 18 and the support substrate 10, the strain applied to the metal layer 61 is large, and it is considered that the crack 65 occurred at the interface between the metal layer 60 and the metal layer 61 due to the superimposed effect of this large strain and the bending of the metal layer 61.

[0083] Next, simulations 2 on the cumulative strain were performed for models F to I in which the stacked structure of the metal layer 76 was changed. The conditions of simulation 2 are as follows. Other conditions are the same as those of the above simulation 1.

[0084] Conditions of Model F

[0085] Metal layer 76 of the housing 72: A copper layer with a thickness of 20 μm

[0086] Solder layer 78 of the housing 72: A gold - tin layer with a thickness of 4 μm

[0087] Width W of the housing 72: 23 μm

[0088] Conditions of Model G

[0089] Metal layer 76 of the housing 72: A stack of a nickel layer with a thickness of 1 μm and a copper layer with a thickness of 19 μm provided on the nickel layer

[0090] Solder layer 78 of the housing 72: A gold - tin layer with a thickness of 4 μm

[0091] Width W of the housing 72: 23 μm

[0092] Conditions of Model H

[0093] Metal layer 76 of the housing 72: A stack of a nickel layer with a thickness of 3 μm and a copper layer with a thickness of 17 μm provided on the nickel layer

[0094] Solder layer 78 of the housing 72: A gold - tin layer with a thickness of 4 μm

[0095] Width W of the housing 72: 23 μm

[0096] Conditions of Model I

[0097] Metal layer 76 of the housing 72: A stack of a nickel layer with a thickness of 5 μm and a copper layer with a thickness of 15 μm provided on the nickel layer

[0098] Solder layer 78 of the housing 72: A gold - tin layer with a thickness of 4 μm

[0099] Width W of the housing 72: 23 μm

[0100] Table 3 is a table showing the Young's modulus and coefficient of linear expansion of each material used in Simulation 2.

[0101]

Table 3

[0102]

[0103] Further, in Simulation 2, with respect to the cumulative strain, the maximum value of the cumulative strain applied to the copper layer in the metal layer 76 is obtained. The cumulative strain of the copper layer is obtained because, as described above, in order to increase the conductivity of the frame, the copper layer is made thick, and in addition, since the Young's modulus is relatively small, it is prone to bending. Therefore, when the strain of the copper layer becomes large, cracks are likely to occur at the interface.

[0104] Figure 9 is a diagram showing the results of Simulation 2. In Figure 9 , the horizontal axis represents the step, the left vertical axis represents the maximum value of the cumulative strain applied to the copper layer, and the right vertical axis represents the temperature. Table 4 is a table showing the results of Simulation 2.

[0105]

Table 4

[0106]

[0107] As Figure 9 and Table 4 show, the cumulative strain applied to the copper layer in Models G - I is less than the cumulative strain applied to the copper layer in Model F. From this result, it can be seen that by providing a nickel layer under the copper layer, the cumulative strain applied to the copper layer can be reduced. The reduction of the cumulative strain applied to the copper layer by providing the nickel layer is considered to be for the following reason. By providing the nickel layer, the copper layer is located at a position far from the connection portion between the frame 72 and the support substrate 70. Since the cumulative strain applied to the frame 72 becomes large at the connection portion with the support substrate 70 as shown in region A of Figure 7 (b), it is considered that by sandwiching the nickel layer between the copper layer and the support substrate 70, the cumulative strain applied to the copper layer becomes small.

[0108] Based on the results of Simulation 2, in Example 1, the fact that no cracks occurred in the frame 18 as in Figure 6 (b) is considered to be for the following reason. In Example 1, a metal layer 41 as a nickel layer is provided between the support substrate 10 and the metal layer 42 as a copper layer. The Young's modulus of nickel is larger than that of copper. Also, the metal layer 42 is the thickest in the frame 18, so the metal layer 41 is thinner than the metal layer 42. In this way, since the metal layer 41 is thin and has a large Young's modulus, even if the support substrate 10 and the cover 30 thermally expand and contract corresponding to the coefficient of linear expansion, the metal layer 41 is not prone to bending. Therefore, it is considered that even if the metal layer 41 is provided near the support substrate 10 and is applied with a large strain, cracks are not likely to occur at the interface between the metal layer 41 and other layers. On the other hand, the metal layer 42 as a copper layer is located at a position far from the support substrate 10 by providing the metal layer 41 between it and the support substrate 10. The strain applied to the frame 18 becomes large at the connection portion with the support substrate 10, so the strain applied to the metal layer 42 becomes small. Therefore, it is considered that cracks are not likely to occur at the interface between the metal layer 42 and other layers either. It is considered that due to the above reasons, no cracks occurred in the frame 18 in Example 1.

[0109] Figure 10 The (a) of [] is a graph obtained based on the results of Simulation 2, Figure 10 the (b) of [] and Figure 10 the (c) of [] are graphs obtained based on the results of Simulation 1. Figure 10 For the (a) of [], the horizontal axis is the ratio of the thickness of the nickel layer in the metal layer 76 to the thickness of the copper layer, and the vertical axis is the maximum value of the cumulative strain applied to the copper layer. As Figure 10 shown in the (a) of [], when the thickness of the nickel layer increases to a certain extent, the change in the strain applied to the copper layer becomes smaller. For example, when the ratio of the thickness of the nickel layer to the thickness of the copper layer is 18% or more, the change in the strain applied to the copper layer becomes smaller. It is considered that this is because: at the connection part with the support substrate 70 shown in the area A of the (b) of [], the strain becomes larger, so by moving the copper layer away from the support substrate 70 by a certain amount or more, the change in the strain becomes smaller. Figure 7 For the (b) of [], the horizontal axis is the thickness of the copper layer in the metal layer 76, and the vertical axis is the maximum value of the cumulative strain applied to the copper layer.

[0110] Figure 10 For the (c) of [], the horizontal axis is the width of the frame 72, and the vertical axis is the maximum value of the cumulative strain applied to the copper layer. As Figure 10 shown in the (b) of [] and Figure 10 the (c) of [], the thinner the copper layer or the larger the width of the frame 72, the greater the strain applied to the copper layer. Figure 10

[0111] According to Embodiment 1, as Figure 2 shown, the frame 18 has: a metal layer 42 (first metal layer) having a thickness of more than 1 / 2 of the interval D between the support substrate 10 and the cover 30 and having the highest conductivity among the plurality of metal layers; and a metal layer 41 (second metal layer) located between the metal layer 42 and the support substrate 10, thinner than the metal layer 42 and having a Young's modulus larger than that of the metal layer 42. Thus, by providing a metal layer 41 that is thinner and has a larger Young's modulus than the metal layer 42 between the metal layer 42 and the support substrate 10, as described above, it is possible to suppress the generation of cracks in the frame 18. Thereby, it is possible to suppress the deterioration of the sealing performance. The Young's modulus of the metal layer 41 is preferably 1.2 times or more, more preferably 1.4 times or more, and further preferably 1.5 times or more of the Young's modulus of the metal layer 42.

[0112] ​In order to suppress the cracking of the housing 18, from the viewpoint of suppressing the bending of the metal layer 41, the thickness of the metal layer 41 is preferably 1 / 10 or less of the thickness of the metal layer 42, more preferably 1 / 25 or less, and still more preferably 1 / 50 or less. From the viewpoint of suppressing the strain applied to the metal layer 42, the thickness of the metal layer 41 is preferably 1 / 200 or more of the thickness of the metal layer 42, more preferably 1 / 150 or more, and still more preferably 1 / 100 or more. Further, from the viewpoint of suppressing the bending of the metal layer 41, the Young's modulus of the metal layer 41 is preferably 1.2 times or more, more preferably 1.3 times or more, and still more preferably 1.4 times or more of the Young's modulus of the metal layer 42.

[0113] Moreover, in Example 1, the linear expansion coefficient of the metal layer 41 (nickel: 14.0 ppm / °C) is greater than that of the support substrate 10 (sapphire: 7.7 ppm / °C) and less than that of the metal layer 42 (copper: 17.7 ppm / °C). Thus, by setting the linear expansion coefficient of the metal layer 41 between the support substrate 10 and the metal layer 42 to be a value between the linear expansion coefficients of the support substrate 10 and the metal layer 42, cracking is not likely to occur at the interface between the metal layer 41 and the metal layer 42.

[0114] Moreover, in Example 1, as Figure 2 shown, a metal layer 40 (third metal layer) is provided between the support substrate 10 and the metal layer 41. The difference between the linear expansion coefficient of the metal layer 42 (copper: 17.7 ppm / °C) and the linear expansion coefficient of the metal layer 40 (titanium: 8.4 ppm / °C) is greater than the difference between the linear expansion coefficient of the metal layer 42 (copper: 17.7 ppm / °C) and the linear expansion coefficient of the metal layer 41 (nickel: 14.0 ppm / °C). Thus, in the housing 18, the linear expansion coefficients increase in the order of the metal layer 40, the metal layer 41, and the metal layer 42, and therefore cracking is not likely to occur in the housing 18.

[0115] Moreover, in Example 1, the support substrate 10 is a sapphire substrate, the metal layer 40 is a titanium layer, the metal layer 41 is a nickel layer, and the metal layer 42 is a copper layer. By providing the metal layer 40 as a titanium layer between the support substrate 10 and the metal layer 41, the adhesion between the support substrate 10 and the housing 18 can be improved. Since the metal layer 41 between the metal layer 40 and the metal layer 42 is a nickel layer, the adhesion between the metal layer 41 and the metal layer 40 and the metal layer 42 is improved. Therefore, from this point of view, cracking is not likely to occur in the housing 18 either. The same applies when a silicon substrate is used instead of the sapphire substrate.

[0116] In addition, in Embodiment 1, as an element, the case of the elastic wave element 50 (surface acoustic wave resonator or piezoelectric thin film resonator) has been described as an example, but the element may also be a passive element such as an inductor or a capacitor, an active element including a transistor, or a MEMS (Micro Electro Mechanical System) element, etc.

[0117]

Embodiment 2

[0118] Figure 11 FIG. (a) is a circuit diagram of the filter 200 of Embodiment 2. As Figure 11 shown in FIG. (a), one or more series resonators S1 to S4 are connected in series between the input terminal Tin and the output terminal Tout. One or more parallel resonators P1 to P3 are connected in parallel between the input terminal Tin and the output terminal Tout. At least one of the series resonators S1 to S4 and the parallel resonators P1 to P3 can be the elastic wave element 50 of Embodiment 1. The number of the series resonators and the parallel resonators, etc. can be set appropriately. As the filter, a ladder filter is exemplified, but the filter may also be a multi-mode type filter.

[0119] Figure 11 FIG. (b) is a circuit diagram of the duplexer 210 which is a modification of Embodiment 2. As Figure 11 shown in FIG. (b), a transmit filter 80 is connected between the common terminal Ant and the transmit terminal Tx. A receive filter 82 is connected between the common terminal Ant and the receive terminal Rx. The transmit filter 80 allows the signal in the transmit band among the high-frequency signals input from the transmit terminal Tx to pass through the common terminal Ant as a transmit signal, and suppresses signals of other frequencies. The receive filter 82 allows the signal in the receive band among the high-frequency signals input from the common terminal Ant to pass through the receive terminal Rx as a receive signal, and suppresses signals of other frequencies. At least one of the transmit filter 80 and the receive filter 82 can be the filter of Embodiment 2. As the multiplexer, a duplexer is exemplified, but it may also be a triplexer or a quadruplexer.

[0120] As described above, the embodiments of the present invention have been described in detail, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

Claims

1. An electronic component comprising: substrate; an element disposed on the substrate; a cover disposed on the substrate so as to sandwich a gap between the cover and the substrate to expose the element; a first metal layer located between the substrate and the cover, and having a ring-shaped structure provided around the element when the substrate is viewed from the element side, and having a thickness of at least 1 / 2 of the distance between the substrate and the cover; as well as A second metal layer is located between the first metal layer and the substrate, the conductivity of the second metal layer is lower than the conductivity of the first metal layer, the second metal layer is thinner than the first metal layer, and the Young's modulus of the second metal layer is larger than the Young's modulus of the first metal layer.

2. The electronic component according to claim 1, wherein The linear expansion coefficient of the second metal layer is larger than the linear expansion coefficient of the substrate and smaller than the linear expansion coefficient of the first metal layer.

3. The electronic component according to claim 2, wherein: The thickness of the second metal layer is not less than 1 / 200 and not more than 1 / 10 of the thickness of the first metal layer.

4. The electronic component according to claim 1 or 2, wherein: The electronic component further includes a third metal layer located between the substrate and the second metal layer, wherein a difference in linear expansion coefficient between the third metal layer and the first metal layer is greater than a difference in linear expansion coefficient between the first metal layer and the second metal layer.

5. The electronic component according to claim 4, wherein The substrate is silicon or sapphire, The first metal layer is copper, The second metal layer is nickel, The third metal layer is titanium.

6. The electronic component according to claim 1 or 2, wherein: The electronic component also has: a solder layer located between the first metal layer and the cover; and The barrier layer is located between the first metal layer and the solder layer and suppresses diffusion between the first metal layer and the solder layer.

7. The electronic component according to claim 1 or 2, wherein: The element is an elastic wave element. A filter comprising the electronic component according to claim 7.

9. A multiplexer comprising the filter according to claim 8.

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