Low-jitter clock fan-out buffer with frequency division and delay adjustment

Abstract

The invention discloses a low-jitter clock fan-out buffer with frequency division and delay adjustment. A clock input buffer module is used for buffering single-ended or differential clock frequency; the clock fan-out module is used for fan-out of the clock signal generated by the clock input buffer module to four frequency division amp; a time delay module; frequency division amp is carried out; the delay module is used for carrying out frequency division on the signal of the clock input buffer module to a required output signal and carrying out delay adjustment; the output driver module divides the frequency into amp; an output signal generated by the delay module is converted into one of three output formats of HSTL, LVDS and LVCMOS to drive an output load; the reference module is used for providing reference current for the clock input buffer module and the clock fan-out module. The multi-mode fan-out clock circuit has the functions of adjustable fan-out frequency and delay, low output jitter and multi-mode signal output, and can achieve excellent fan-out clock precision in a wide frequency range. And the method has excellent jitter performance and is suitable for fan-out buffer application of infrastructure clocks with strict requirements.

Description

Technical Field

[0001] The present invention relates to integrated circuit signal processing technology, and particularly to a low-jitter clock fan-out buffer circuit with frequency division and delay adjustment. Background Art

[0002] As science and technology become more and more mature, modern communication systems have achieved various technological leaps, from the original analog modulation signal communication, narrowband voice communication, and wired transmission communication to digital modulation signal communication, broadband integrated service communication, and wireless mobile communication. The electronic communication system has become increasingly rich. The communication system is constantly developing towards large capacity and high speed, and the requirements for radio frequency communication technology are more critical. The radio frequency signal extends to higher frequencies and larger ranges.

[0003] The implementation of wireless communication systems mainly relies on radio frequency communication circuits. After years of continuous research and accumulation, the radio frequency communication system has basically formed a typical composition structure, mainly including modulation, frequency conversion, amplification, and demodulation. In recent years, the application fields of radio frequency communication circuits mainly include aerospace communication, radar satellite communication, shipborne communication, personal mobile communication, wireless local area network, Internet of Things, and Internet of Vehicles.

[0004] The application requirements of communication technology are getting higher and more demanding. This urgently requires wireless communication devices to be able to provide safe and reliable communication functions at any time and anywhere, and to be lighter in weight, smaller in size, and lower in power consumption. For these reasons, the design of radio frequency communication circuits faces more requirements and challenges. The clock fan-out buffer circuit is applied to various fields of communication technology, and its frequency range and jitter performance determine the performance of the communication circuit. There are multiple different clocks inside the current communication system, and the traditional single structure has caused great difficulties for the application of high-performance clock fan-out buffer circuits. Summary of the Invention

[0005] The purpose of the present invention is to propose a low-jitter clock fan-out buffer with frequency division and delay adjustment.

[0006] The technical solution to achieve the purpose of the present invention is: a low-jitter clock fan-out buffer with frequency division and delay adjustment, including:

[0007] A clock input buffer module for buffering single-ended or differential clock frequencies to generate a clock signal;

[0008] A clock fan-out module for fan-out the clock signal generated by the clock input buffer module to 4 frequency division & delay modules;

[0009] A frequency division & delay module for frequency division and delay adjustment of the clock signal generated by the clock input buffer module;

[0010] An output driver module for converting the output signal generated by the frequency division & delay module into HSTL, LVDS or LVCMOS to drive the output load;

[0011] A reference module for providing a reference current for the clock input buffer module and the clock fan-out module.

[0012] Further, the clock input buffer module includes an input positive port one VINP1, an input negative port one VINN1, an output positive port one VOUTP1, an output negative port one VOUTN1, an input reference port one VREF1, an input reference port two VREF2, a first N-type MOS transistor N1 to a sixth N-type MOS transistor N6, a first resistor R1 to a tenth resistor R10, where:

[0013] The gate of the first N-type MOS transistor N1 is respectively connected to the differential input positive port one VINP1, one end of the third resistor R3 and one end of the fourth resistor R4. The other end of the third resistor R3 is connected to the positive power supply terminal VDD, and the other end of the fourth resistor R4 is connected to the negative power supply terminal GND. The gate of the second N-type MOS transistor N2 is respectively connected to the differential input negative port one VINN1, one end of the first resistor R1 and one end of the second resistor R2. The other end of the first resistor R1 is connected to the positive power supply terminal VDD, and the other end of the second resistor R2 is connected to the negative power supply terminal GND. The gate of the third N-type MOS transistor N3 is connected to the input reference port one VREF1. The source of the third N-type MOS transistor N3 is connected to the negative power supply terminal GND. The drain of the third N-type MOS transistor N3 is connected to the source of the first N-type MOS transistor N1 and the source of the second N-type MOS transistor N2. The drain of the first N-type MOS transistor N1 is connected to one end of the fifth resistor R5 and the gate of the fourth N-type MOS transistor N4. The drain of the second N-type MOS transistor N2 is connected to one end of the sixth resistor R6 and the gate of the fifth N-type MOS transistor N5. The other ends of the fifth resistor R5 and the sixth resistor R6 are commonly connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to the positive power supply terminal VDD. The gate of the sixth N-type MOS transistor N6 is connected to the input reference port two VREF2. The source of the sixth N-type MOS transistor N6 is connected to the negative power supply GND. The drain of the sixth N-type MOS transistor N6 is connected to the source of the fourth N-type MOS transistor N4 and the source of the fifth N-type MOS transistor N5. The drain of the fourth N-type MOS transistor N4 is connected to one end of the eighth resistor R8 and the output positive port one VOUTP1. The drain of the fifth N-type MOS transistor N5 is connected to one end of the ninth resistor R9 and the output negative port one VOUTN1. The other ends of the eighth resistor R8 and the ninth resistor R9 are commonly connected to one end of the tenth resistor R10. The other end of the tenth resistor R10 is connected to the positive power supply terminal VDD.

[0014] Further, the clock fan-out module includes buffer I1, D flip-flop D1, D flip-flop D2, D flip-flop D3, D flip-flop D4, NOR gate Q1, NOR gate Q2, NOR gate Q3, NOR gate Q4, D flip-flop D5, D flip-flop D6, D flip-flop D7, D flip-flop D8, input port IN1, output port OUT1, output port OUT2, output port OUT3, output port OUT4, synchronization port SYNC, channel selection port AN1, channel selection port AN2, channel selection port AN3, and channel selection port AN4, where:

[0015] Input port IN1 is connected to the input terminal of buffer I1. The output terminal of buffer I1 is connected to the clock input terminals of D flip-flop D1, D flip-flop D2, D flip-flop D3, D flip-flop D4, D flip-flop D5, D flip-flop D6, D flip-flop D7, and D flip-flop D8. The D terminal of D flip-flop D1 is connected to the positive power supply terminal VDD. The CLR terminal of D flip-flop D1 is connected to synchronization port SYNC. The Q terminal of D flip-flop D1 is connected to input terminal 1 of NOR gate Q1. Input terminal 2 of NOR gate Q1 is connected to channel selection port AN1. The D terminal of D flip-flop D2 is connected to the positive power supply terminal VDD. The CLR terminal of D flip-flop D2 is connected to synchronization port SYNC. The Q terminal of D flip-flop D2 is connected to input terminal 1 of NOR gate Q2. Input terminal 2 of NOR gate Q2 is connected to channel selection port AN2. The D terminal of D flip-flop D3 is connected to the positive power supply terminal VDD. The CLR terminal of D flip-flop D3 is connected to synchronization port SYNC. The Q terminal of D flip-flop D3 is connected to input terminal 1 of NOR gate Q3. Input terminal 2 of NOR gate Q3 is connected to channel selection port AN3. The D terminal of D flip-flop D4 is connected to the positive power supply terminal VDD. The CLR terminal of D flip-flop D4 is connected to synchronization port SYNC. The Q terminal of D flip-flop D4 is connected to input terminal 1 of NOR gate Q4. Input terminal 2 of NOR gate Q4 is connected to channel selection port AN4. The output terminal of NOR gate Q1 is connected to the D terminal of D flip-flop D5. The Q terminal of D flip-flop D5 is connected to output port OUT1. The output terminal of NOR gate Q2 is connected to the D terminal of D flip-flop D6. The Q terminal of D flip-flop D6 is connected to output port OUT2. The output terminal of NOR gate Q3 is connected to the D terminal of D flip-flop D7. The Q terminal of D flip-flop D7 is connected to output port OUT3. The output terminal of NOR gate Q4 is connected to the D terminal of D flip-flop D8. The Q terminal of D flip-flop D8 is connected to output port OUT4.

[0016] Further, the frequency division & delay module includes transmission gate T1, transmission gate T2, inverter I1, inverter I2, inverter I3, inverter I4, inverter I5, inverter I6, inverter I7, inverter I8, inverter I9, inverter I10, inverter I11, inverter I12, inverter I13, sample and hold unit circuit C1, sample and hold unit circuit C2, sample and hold unit circuit C3, sample and hold unit circuit C4, sample and hold unit circuit C5, sample and hold unit circuit C6, sample and hold unit circuit C7, sample and hold unit circuit C8, selector M1, selector M2, selector M3, NOR gate O1, XOR gate O2, OR gate O3, AND gate O4, input port IN2, output port OUT, control port A1, control port A2, control port A3, where:

[0017] The input end of transmission gate T1 is connected to the input end of inverter I1 and input port IN2. The output end of transmission gate T1 is connected to the output end of inverter I1, the input end of inverter I2, the clock input port of sample and hold unit circuit C2, the clock input port of sample and hold unit circuit C4, the clock input port of sample and hold unit circuit C6, and the clock input port of sample and hold unit circuit C8. The output end of inverter I2 is connected to the clock input port of sample and hold unit circuit C1, the clock input port of sample and hold unit circuit C3, the clock input port of sample and hold unit circuit C5, and the clock input port of sample and hold unit circuit C7. The input port 1 of selector M1 is connected to control port A1. The positive output port of selector M1 is connected to the positive input port of sample and hold unit circuit C1, and the negative output port of selector M1 is connected to the negative input port of sample and hold unit circuit C1. The positive output port of sample and hold unit circuit C1 is connected to the negative input port of sample and hold unit circuit C2, and the negative output port of sample and hold unit circuit C1 is connected to the positive input port of sample and hold unit circuit C2. The positive output port of sample and hold unit circuit C2 is connected to the input port of inverter I4, and the negative output port of sample and hold unit circuit C2 is connected to the input port of inverter I5. The output port of inverter I4 is connected to input port 1 of NOR gate O1 and input port 1 of OR gate O3. The output port of inverter I5 is connected to input port 2 of selector M1 and input port 1 of XOR gate O2. The input port 1 of selector M2 is connected to control port A2. The positive output port of selector M2 is connected to the positive input port of sample and hold unit circuit C3, and the negative output port of selector M2 is connected to the negative input port of sample and hold unit circuit C3. The positive output port of sample and hold unit circuit C3 is connected to the negative input port of sample and hold unit circuit C4, and the negative output port of sample and hold unit circuit C3 is connected to the positive input port of sample and hold unit circuit C4. The positive output port of sample and hold unit circuit C4 is connected to the input port of inverter I6, and the negative output port of sample and hold unit circuit C4 is connected to the input port of inverter I7. The output port of inverter I6 is connected to input port 2 of NOR gate O1, input port 2 of XOR gate O2, and input port 2 of OR gate O3. The output port of XOR gate O2 is connected to input port 2 of selector M2. The input port 1 of selector M3 is connected to control port A3. The positive output port of selector M3 is connected to the positive input port of sample and hold unit circuit C5, and the negative output port of selector M3 is connected to the negative input port of sample and hold unit circuit C5. The positive output port of sample and hold unit circuit C5 is connected to the negative input port of sample and hold unit circuit C6, and the negative output port of sample and hold unit circuit C5 is connected to the positive input port of sample and hold unit circuit C6. The positive output port of sample and hold unit circuit C6 is connected to the input port of inverter I8, and the negative output port of sample and hold unit circuit C6 is connected to the input port of inverter I9. The output port of inverter I8 is connected to input port 3 of NOR gate O1 and input port 2 of AND gate O4.The output port of AND gate O4 is connected to the input port 2 of selector three M3. The output terminal of OR gate O3 is connected to the input port 1 of AND gate O4. The output port of NOR gate O1 is connected to the control port of inverter one I1, the negative control port of selector one M1, the negative control port of selector two M2, the negative control port of selector three M3, the input terminal of transmission gate two T2, the input terminal of inverter three I3, and the input terminal of inverter ten I10. The output terminal of inverter three I3 is connected to the control port of transmission gate one T1, the positive control port of selector one M1, the positive control port of selector two M2, and the positive control port of selector three M3. The output terminal of transmission gate two T2 is connected to the positive input port of sample and hold unit circuit seven C7. The output terminal of inverter ten I10 is connected to the negative input port of sample and hold unit circuit seven C7. The positive output port of sample and hold unit circuit seven C7 is connected to the negative input port of sample and hold unit circuit eight C8. The negative output port of sample and hold unit circuit seven C7 is connected to the positive input port of sample and hold unit circuit eight C8. The positive output port of sample and hold unit circuit eight C8 is connected to the input port of inverter eleven I11. The negative output port of sample and hold unit circuit eight C8 is connected to the input port of inverter twelve I12. The output port of inverter twelve I12 is connected to the input port of inverter thirteen I13. The output port of inverter thirteen I13 is connected to the output port OUT.,

[0018] Further, the output driver module consists of two parts, namely the HSTL, LVDS driver module and the LVCMOS driver module, where:

[0019] The HSTL and LVDS driver module includes the input positive port three VINP3, the input negative port three VINN3, the output positive port three VOUTP3, the output negative port three VOUTN3, the input reference three-port VREF3, the input reference four-port VREF4, the first N-type MOS transistor N1, the second N-type MOS transistor N2, the third N-type MOS transistor N3, the first P-type MOS transistor P1, the second P-type MOS transistor P, and the third P-type MOS transistor P3. The input positive port three VINP3 is respectively connected to the gates of the second N-type MOS transistor N2 and the first P-type MOS transistor P1. The input negative port three VINN3 is respectively connected to the gates of the first N-type MOS transistor N1 and the second P-type MOS transistor P2. The output positive port three VOUTP3 is respectively connected to the drains of the first N-type MOS transistor N1 and the first P-type MOS transistor P1. The output negative port three VOUTN3 is respectively connected to the drains of the second N-type MOS transistor N2 and the second P-type MOS transistor P2. The drain of the third N-type MOS transistor N3 is respectively connected to the sources of the first N-type MOS transistor N1 and the second N-type MOS transistor N2. The drain of the third P-type MOS transistor P3 is respectively connected to the sources of the first P-type MOS transistor P1 and the second P-type MOS transistor P2. The gate of the third N-type MOS transistor N3 is connected to the input reference three-port VREF3. The gate of the third P-type MOS transistor P3 is connected to the input reference four-port VREF4. The source of the third N-type MOS transistor N3 is connected to the negative power supply terminal GND. The source of the third P-type MOS transistor P3 is connected to the positive power supply terminal VDD.

[0020] The LVCMOS driver module includes the input positive port three VINP3, the input negative port three VINN3, the output positive port three VOUTP3, the output negative port three VOUTN3, the fourth N-type MOS transistor N4, the fifth N-type MOS transistor N5, the fourth P-type MOS transistor P4, and the fifth P-type MOS transistor P5. The input positive port three VINP3 is respectively connected to the gates of the fourth N-type MOS transistor N4 and the fourth P-type MOS transistor P4. The input negative port three VINN3 is respectively connected to the gates of the fifth N-type MOS transistor N5 and the fifth P-type MOS transistor P5. The output positive port three VOUTP3 is respectively connected to the drains of the fourth N-type MOS transistor N4 and the fourth P-type MOS transistor P4. The output negative port three VOUTN3 is respectively connected to the drains of the fifth N-type MOS transistor N5 and the fifth P-type MOS transistor P5. The positive power supply terminal VDD is respectively connected to the sources of the fourth P-type MOS transistor P4 and the fifth P-type MOS transistor P5. The negative power supply terminal GND is respectively connected to the sources of the fourth N-type MOS transistor N4 and the fifth N-type MOS transistor N5.

[0021] Compared with the prior art, the present invention has the following remarkable advantages: adding a frequency division & delay module greatly expands the application scope of the chip. One chip can cover the clock frequencies of multiple commonly used communication systems, and the output jitter is reduced in combination with the synchronization function; the output driver module adopts an integrated method of three drive circuits, so that the output signal can be driven to the output load after being converted into one of the three output formats of HSTL, LVDS, and LVCMOS. Description of the Drawings

[0022] Figure 1 is a schematic structural diagram of a low-jitter clock fan-out buffer with frequency division and delay adjustment according to the present invention;

[0023] Figure 2 is a schematic circuit diagram of the input module in a low-jitter clock fan-out buffer with frequency division and delay adjustment;

[0024] Figure 3 is a schematic structural diagram of the clock fan-out module in a low-jitter clock fan-out buffer with frequency division and delay adjustment;

[0025] Figure 4 is a schematic circuit diagram of the sample and hold unit circuit in the frequency division & delay module of a low-jitter clock fan-out buffer with frequency division and delay adjustment;

[0026] Figure 5 is a schematic structural diagram of the 8-mode frequency divider and delay unit in the frequency division & delay module of a low-jitter clock fan-out buffer with frequency division and delay adjustment;

[0027] Figure 6 is a schematic equivalent circuit diagram of the LVDS / HSTL driver in the output driver module of a low-jitter clock fan-out buffer with frequency division and delay adjustment;

[0028] Figure 7 is a schematic equivalent circuit diagram of the CMOS driver in the output driver module of a low-jitter clock fan-out buffer with frequency division and delay adjustment. Detailed Embodiment

[0029] The following further describes in detail a low-jitter clock fan-out buffer with frequency division and delay adjustment proposed by the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will be clearer according to the following description and the claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0030] A low-jitter clock fan-out buffer with frequency division and delay adjustment includes:

[0031] A clock input buffer module for buffering single-ended or differential clock frequencies;

[0032] A clock fan-out module for fan-out of the clock signal generated by the clock input buffer module to 4 frequency division & delay modules;

[0033] A frequency division & delay module for dividing the signal of the clock input buffer module into the required output signal and performing delay adjustment;

[0034] An output driver module for converting the output signal generated by the frequency division & delay module into one of the three output formats of HSTL, LVDS, and LVCMOS and then driving the output load;

[0035] A reference module for providing a reference current for the above-mentioned clock input buffer module and clock fan-out module.

[0036] Further, the frequency division & delay module further includes a frequency division module and a delay module, wherein the frequency division module is used for dividing the signal of the clock input buffer module into the required output signal; the delay module is used for performing delay adjustment on the signal of the clock input buffer module.

[0037] Further, the clock input buffer module includes a positive power supply terminal VDD, a negative power supply terminal GND, a positive input port one VINP1, a negative input port one VINN1, a positive output port one VOUTP1, a negative output port one VOUTN1, an input reference port one VREF1, an input reference port two VREF2, a first N-type MOS transistor N1 to a sixth N-type MOS transistor N6, a first resistor R1 to a tenth resistor R10. The gate of the first N-type MOS transistor N1 is respectively connected to the differential positive input port one VINP1, one end of the third resistor R3, and one end of the fourth resistor R4. The other end of the third resistor R3 is connected to the positive power supply terminal VDD, and the other end of the fourth resistor R4 is connected to the negative power supply terminal GND. The gate of the second N-type MOS transistor N2 is respectively connected to the differential negative input port one VINN1, one end of the first resistor R1, and one end of the second resistor R2. The other end of the first resistor R1 is connected to the positive power supply terminal VDD, and the other end of the second resistor R2 is connected to the negative power supply terminal GND. The gate of the third N-type MOS transistor N3 is connected to the input reference port one VREF1. The source of the third N-type MOS transistor N3 is connected to the negative power supply terminal GND. The drain of the third N-type MOS transistor N3 is connected to the source of the first N-type MOS transistor N1 and the source of the second N-type MOS transistor N2. The drain of the first N-type MOS transistor N1 is connected to one end of the fifth resistor R5 and the gate of the fourth N-type MOS transistor N4. The drain of the second N-type MOS transistor N2 is connected to one end of the sixth resistor R6 and the gate of the fifth N-type MOS transistor N5. The other ends of the fifth resistor R5 and the sixth resistor R6 are commonly connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to the positive power supply terminal VDD. The gate of the sixth N-type MOS transistor N6 is connected to the input reference port two VREF2. The source of the sixth N-type MOS transistor N6 is connected to the negative power supply terminal GND. The drain of the sixth N-type MOS transistor N6 is connected to the source of the fourth N-type MOS transistor N4 and the source of the fifth N-type MOS transistor N5. The drain of the fourth N-type MOS transistor N4 is connected to one end of the eighth resistor R8 and the positive output port one VOUTP1. The drain of the fifth N-type MOS transistor N5 is connected to one end of the ninth resistor R9 and the negative output port one VOUTN1. The other ends of the eighth resistor R8 and the ninth resistor R9 are commonly connected to one end of the tenth resistor R10. The other end of the tenth resistor R10 is connected to the positive power supply terminal VDD.

[0038] Further, the clock fan-out module includes a positive power supply terminal VDD, a negative power supply terminal GND, a first input port IN1, a first output port OUT1, a second output port OUT2, a third output port OUT3, a fourth output port OUT4, a synchronization port SYNC, a first channel selection port AN1, a second channel selection port AN2, a third channel selection port AN3, and a fourth channel selection port AN4. The first input port IN1 is connected to the input terminal of a buffer I1. The output terminal of the buffer I1 is connected to the clock input terminals of a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a sixth D flip-flop D6, a seventh D flip-flop D7, and an eighth D flip-flop D8. The D terminal of the first D flip-flop D1 is connected to the positive power supply terminal VDD. The CLR terminal of the first D flip-flop D1 is connected to the synchronization port SYNC. The Q terminal of the first D flip-flop D1 is connected to the first input terminal of a NOR gate Q1. The second input terminal of the NOR gate Q1 is connected to the first channel selection port AN1. The D terminal of the second D flip-flop D2 is connected to the positive power supply terminal VDD. The CLR terminal of the second D flip-flop D2 is connected to the synchronization port SYNC. The Q terminal of the second D flip-flop D2 is connected to the first input terminal of a second NOR gate Q2. The second input terminal of the second NOR gate Q2 is connected to the second channel selection port AN2. The D terminal of the third D flip-flop D3 is connected to the positive power supply terminal VDD. The CLR terminal of the third D flip-flop D3 is connected to the synchronization port SYNC. The Q terminal of the third D flip-flop D3 is connected to the first input terminal of a third NOR gate Q3. The second input terminal of the third NOR gate Q3 is connected to the third channel selection port AN3. The D terminal of the fourth D flip-flop D4 is connected to the positive power supply terminal VDD. The CLR terminal of the fourth D flip-flop D4 is connected to the synchronization port SYNC. The Q terminal of the fourth D flip-flop D4 is connected to the first input terminal of a fourth NOR gate Q4. The second input terminal of the fourth NOR gate Q4 is connected to the fourth channel selection port AN4. The output terminal of the NOR gate Q1 is connected to the D terminal of the fifth D flip-flop D5. The Q terminal of the fifth D flip-flop D5 is connected to the first output port OUT1. The output terminal of the second NOR gate Q2 is connected to the D terminal of the sixth D flip-flop D6. The Q terminal of the sixth D flip-flop D6 is connected to the second output port OUT2. The output terminal of the third NOR gate Q3 is connected to the D terminal of the seventh D flip-flop D7. The Q terminal of the seventh D flip-flop D7 is connected to the third output port OUT3. The output terminal of the fourth NOR gate Q4 is connected to the D terminal of the eighth D flip-flop D8. The Q terminal of the eighth D flip-flop D8 is connected to the fourth output port OUT4.

[0039] Further, the sampling and holding unit circuit in the frequency division & delay module includes a positive power supply terminal VDD, a negative power supply terminal GND, a positive input port a negative input port 2VINN2, a positive output port 2VOUTP2, a negative output port 2VOUTN2, an enable port EN, a clock input port CLK, a first N-type MOS transistor N1 to a sixth N-type MOS transistor N6, a first P-type MOS transistor P1 to a third MOS transistor P3, first resistor R1, and second resistor R2. The gate of the first N-type MOS transistor N1 is connected to the differential input positive port 2VINP2, the gate of the second N-type MOS transistor N2 is connected to the differential input negative port 2VINN2, the gate of the third N-type MOS transistor N3 is connected to the clock input port CLK, the source of the third N-type MOS transistor N3 is connected to the negative power supply terminal GND, the drain of the third N-type MOS transistor N3 is respectively connected to the sources of the first N-type MOS transistor N1 and the second N-type MOS transistor N2, the drain of the first N-type MOS transistor N1 is respectively connected to the source of the first P-type MOS transistor P1, the source of the third P-type MOS transistor P3, the output positive port 2VOUTP2, the gate of the fourth N-type MOS transistor N4, and the drain of the fifth N-type MOS transistor N5, the drain of the second N-type MOS transistor N2 is respectively connected to the drain of the second P-type MOS transistor P2, the drain of the sixth N-type MOS transistor N6, the output negative port 2VOUTN2, the gate of the fifth N-type MOS transistor N5, and the drain of the fourth N-type MOS transistor N4, the sources of the first P-type MOS transistor P1 and the second P-type MOS transistor P2 are commonly connected to the positive power supply terminal VDD, the gates of the first P-type MOS transistor P1 and the second P-type MOS transistor P2 are commonly connected to the enable port EN, the sources of the fourth N-type MOS transistor N4 and the fifth N-type MOS transistor N5 are commonly connected to the negative power supply terminal GND, the gate of the third P-type MOS transistor P3 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the positive power supply terminal VDD, the source of the third P-type MOS transistor P3 is connected to the positive power supply terminal VDD, the gate of the sixth N-type MOS transistor N6 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the negative power supply terminal GND, and the source of the sixth N-type MOS transistor N6 is connected to the negative power supply terminal GND.

[0040] Further, the frequency division & delay module includes a positive power supply terminal VDD, a negative power supply terminal GND, an input port two IN2, an output port OUT, a control port one A1, a control port two A2, and a control port three A3. The input end of transmission gate one T1 is connected to the input end of inverter one I1 and input port two IN2. The output end of transmission gate one T1 is connected to the output end of inverter one I1, the input end of inverter two I2, the clock input port of sample and hold unit circuit two C2, the clock input port of sample and hold unit circuit four C4, the clock input port of sample and hold unit circuit six C6, and the clock input port of sample and hold unit circuit eight C8. The output end of inverter two I2 is connected to the clock input port of sample and hold unit circuit one C1, the clock input port of sample and hold unit circuit three C3, the clock input port of sample and hold unit circuit five C5, and the clock input port of sample and hold unit circuit seven C7. The input port 1 of selector one M1 is connected to control port one A1. The positive output port of selector one M1 is connected to the positive input port of sample and hold unit circuit one C1. The negative output port of selector one M1 is connected to the negative input port of sample and hold unit circuit one C1. The positive output port of sample and hold unit circuit one C1 is connected to the negative input port of sample and hold unit circuit two C2. The negative output port of sample and hold unit circuit one C1 is connected to the positive input port of sample and hold unit circuit two C2. The positive output port of sample and hold unit circuit two C2 is connected to the input port of inverter four I4. The negative output port of sample and hold unit circuit two C2 is connected to the input port of inverter five I5. The output port of inverter four I4 is connected to input port 1 of nor gate O1 and input port 1 of or gate O3. The output port of inverter five I5 is connected to input port 2 of selector one M1 and input port 1 of exclusive - or gate O2. The input port 1 of selector two M2 is connected to control port two A2. The positive output port of selector two M2 is connected to the positive input port of sample and hold unit circuit three C3. The negative output port of selector two M2 is connected to the negative input port of sample and hold unit circuit three C3. The positive output port of sample and hold unit circuit three C3 is connected to the negative input port of sample and hold unit circuit four C4. The negative output port of sample and hold unit circuit three C3 is connected to the positive input port of sample and hold unit circuit four C4. The positive output port of sample and hold unit circuit four C4 is connected to the input port of inverter six I6. The negative output port of sample and hold unit circuit four C4 is connected to the input port of inverter seven I7. The output port of inverter six I6 is connected to input port 2 of nor gate O1, input port 2 of exclusive - or gate O2, and input port 2 of or gate O3. The output port of exclusive - or gate O2 is connected to input port 2 of selector two M2. The input port 1 of selector three M3 is connected to control port three A3. The positive output port of selector three M3 is connected to the positive input port of sample and hold unit circuit five C5. The negative output port of selector three M3 is connected to the negative input port of sample and hold unit circuit five C5. The positive output port of sample and hold unit circuit five C5 is connected to the negative input port of sample and hold unit circuit six C6. The negative output port of sample and hold unit circuit five C5 is connected to the positive input port of sample and hold unit circuit six C6. The positive output port of sample and hold unit circuit six C6 is connected to the input port of inverter eight I8,The negative output port of the sampling and holding unit circuit six C6 is connected to the input port of the inverter nine I9. The output port of the inverter eight I8 is connected to the input port 3 of the NOR gate O1 and the input port 2 of the AND gate O4. The output port of the AND gate O4 is connected to the input port 2 of the selector three M3. The output of the OR gate O3 is connected to the input port 1 of the AND gate O4. The output port of the NOR gate O1 is connected to the control port of the inverter one I1, the negative control port of the selector one M1, the negative control port of the selector two M2, the negative control port of the selector three M3, the input end of the transmission gate two T2, the input end of the inverter three T3, and the input end of the inverter ten T10. The output end of the inverter three T3 is connected to the control port of the transmission gate one T1, the positive control port of the selector one M1, the positive control port of the selector two M2, and the positive control port of the selector three M3. The output end of the transmission gate two T2 is connected to the positive input port of the sampling and holding unit circuit seven C7. The output end of the inverter ten I10 is connected to the negative input port of the sampling and holding unit circuit seven C7. The positive output port of the sampling and holding unit circuit seven C75 is connected to the negative input port of the sampling and holding unit circuit eight C8. The negative output port of the sampling and holding unit circuit seven C7 is connected to the positive input port of the sampling and holding unit circuit eight C8. The positive output port of the sampling and holding unit circuit eight C8 is connected to the input port of the inverter eleven I11. The negative output port of the sampling and holding unit circuit eight C8 is connected to the input port of the inverter twelve I12. The output port of the inverter twelve I12 is connected to the input port of the inverter thirteen I13. The output port of the inverter thirteen I13 is connected to the output port OUT.

[0041] Further, the output driver module consists of two parts, namely the HSTL, LVDS driver module and the LVCMOS driver module.

[0042] The HSTL and LVDS driver module includes a positive power supply terminal VDD, a negative power supply terminal GND, a positive input port three VINP3, a negative input port three VINN3, a positive output port three VOUTP3, a negative output port three VOUTN3, a reference input port three VREF3, and a reference input port four VREF4. The positive input port three VINP3 is respectively connected to the gates of the second N-type MOS transistor N2 and the first P-type MOS transistor P1. The negative input port three VINN3 is respectively connected to the gates of the first N-type MOS transistor N1 and the second P-type MOS transistor P2. The positive output port three VOUTP3 is respectively connected to the drains of the first N-type MOS transistor N1 and the first P-type MOS transistor P1. The negative output port three VOUTN3 is respectively connected to the drains of the second N-type MOS transistor N2 and the second P-type MOS transistor P2. The drain of the third N-type MOS transistor N3 is respectively connected to the sources of the first N-type MOS transistor N1 and the second N-type MOS transistor N2. The drain of the third P-type MOS transistor P3 is respectively connected to the sources of the first P-type MOS transistor P1 and the second P-type MOS transistor P2. The gate of the third N-type MOS transistor N3 is connected to the reference input port three VREF3. The gate of the third P-type MOS transistor P3 is connected to the reference input port four VREF4. The source of the third N-type MOS transistor N3 is connected to the negative power supply terminal GND. The source of the third P-type MOS transistor P3 is connected to the positive power supply terminal VDD.

[0043] The LVCMOS driver module includes a positive power supply terminal VDD, a negative power supply terminal GND, a positive input port three VINP3, a negative input port three VINN3, a positive output port three VOUTP3, and a negative output port three VOUTN3. The positive input port three VINP3 is respectively connected to the gates of the fourth N-type MOS transistor N4 and the fourth P-type MOS transistor P4. The negative input port three VINN3 is respectively connected to the gates of the fifth N-type MOS transistor N5 and the fifth P-type MOS transistor P5. The positive output port three VOUTP3 is respectively connected to the drains of the fourth N-type MOS transistor N4 and the fourth P-type MOS transistor P4. The negative output port three VOUTN3 is respectively connected to the drains of the fifth N-type MOS transistor N5 and the fifth P-type MOS transistor P5. The positive power supply terminal VDD is respectively connected to the sources of the fourth P-type MOS transistor P4 and the fifth P-type MOS transistor P5. The negative power supply terminal GND is respectively connected to the sources of the fourth N-type MOS transistor N4 and the fifth N-type MOS transistor N5.

[0044] Embodiment

[0045] A low-jitter clock fan-out buffer with frequency division and delay adjustment according to the present invention has a structure as Figure 1 shown, and includes a clock input buffer module, a clock fan-out module, a frequency division & delay module, an output driver module, and a reference module, and can buffer and fan out a clock signal of one of the three output formats of HSTL, LVDS up to 1650 MHz, and LVCMOS up to 250 MHz at most.

[0046] The clock input buffer module can control single-ended input or differential input through the IN_SEL pin. As Figure 2 shown, it improves the compatibility of the circuit input interface.

[0047] The clock fan-out module can fan out 1 input signal to 4 outputs. The fan-out circuit also adds a synchronization function to synchronize the output signal to an external signal. As Figure 3 shown, it reduces the jitter of the output signal.

[0048] The frequency division & delay module also includes a frequency division module and a delay module, and its structure is as Figure 4 、 Figure 5 shown. The traditional clock fan-out buffer has a single function and can only buffer and fan out clock signals. By adding a frequency division & delay module in the present invention, 4 clock signals with different frequencies can be fanned out, and the delay of the fanned-out signals can be adjusted. It can cover the clock frequency ranges of various common communication systems, greatly reducing the complexity of the clock tree of multi-system circuits. The frequency division circuit adopts a combination of an 8-mode frequency divider and a counter, which is controlled by a 10-bit register and can achieve frequency division from 1 to 1024.

[0049] The input signal of the 8-mode frequency divider is connected with a buffer and an inverter. Through the DLY signal, one of the two is selected. The signal passing through the buffer has no delay, and the signal passing through the inverter is equivalent to a half-cycle delay. In the present invention, the half-cycle delay is the minimum delay unit. By matching with a counter, the delay that is a multiple of the minimum delay unit can be achieved. The adjustment of 2047 minimum delay units can be realized by the control of an 11-bit register. At the same time, a synchronization function is set at the output, reducing the jitter of the output signal again. The last-stage output adopts an output driver module, and its structure is as Figure 6 、 Figure 7 shown. The present invention only needs to configure 2 external pins of the circuit to drive the output load after converting the output signal into one of the three output formats of HSTL, LVDS, and LVCMOS, expanding the applicable range of the circuit.

[0050] The low-jitter clock fan-out buffer with frequency division and delay adjustment proposed by the present invention is designed and taped out using CMOS technology. In this embodiment, the power supply voltage is 3.3V, and the clock frequency fan-out can cover up to 1650MHz. In the range of 12kHz - 20MHz, its output additional jitter is 40fs, featuring excellent jitter performance and being simple and easy to use.

[0051] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure fall within the protection scope of the claims.

Claims

1. A low jitter clock fan-out buffer with frequency division and delay adjustment, characterized in that: include: Clock input buffer module, used to buffer single-ended or differential clock frequency and generate clock signal; The clock fan-out module is used to fan out the clock signal generated by the clock input buffer module to four frequency division & delay modules; The frequency division & delay module is used to divide the frequency and delay the clock signal generated by the clock input buffer module; Output driver module, used to convert the output signal generated by the frequency division & delay module into HSTL, LVDS or LVCMOS to drive the output load; The reference module is used to provide reference current for the clock input buffer module and the clock fan-out module.

2. The low-jitter clock fan-out buffer with frequency division and delay adjustment according to claim 1, characterized in that: The clock input buffer module includes an input positive port VINP1, an input negative port VINN1, an output positive port VOUTP1, an output negative port VOUTN1, an input reference port VREF1, an input reference port VREF2, a first N-type MOS transistor N1 to a sixth N-type MOS transistor N6, and a first resistor R1 to a tenth resistor R10, wherein: The gate of the first N-type MOS transistor N1 is respectively connected to the differential input positive port VINP1, one end of the third resistor R3 and one end of the fourth resistor R4, the other end of the third resistor R3 is connected to the positive end of the power supply VDD, and the other end of the fourth resistor R4 is connected to the negative end of the power supply GND. The gate of the second N-type MOS transistor N2 is respectively connected to the differential input negative port VINN1, one end of the first resistor R1 and one end of the second resistor R2, the other end of the first resistor R1 is connected to the positive end of the power supply VDD, and the other end of the second resistor R2 is connected to the negative end of the power supply GND. The gate of the third N-type MOS transistor N3 is connected to the input reference port VREF1, the source of the third N-type MOS transistor N3 is connected to the negative end of the power supply GND, the drain of the third N-type MOS transistor N3 is connected to the source of the first N-type MOS transistor N1 and the source of the second N-type MOS transistor N2, the drain of the first N-type MOS transistor N1 is connected to one end of the fifth resistor R5 and the gate of the fourth N-type MOS transistor N4, and the The drain of the second N-type MOS transistor N2 is connected to one end of the sixth resistor R6 and the gate of the fifth N-type MOS transistor N5, the other end of the fifth resistor R5 and the other end of the sixth resistor R6 are commonly connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is connected to the positive power supply terminal VDD, the gate of the sixth N-type MOS transistor N6 is connected to the input reference port VREF2, the source of the sixth N-type MOS transistor N6 is connected to the negative power supply GND, the drain of the sixth N-type MOS transistor N6 is connected to the source of the fourth N-type MOS transistor N4 and the source of the fifth N-type MOS transistor N5, the drain of the fourth N-type MOS transistor N4 is connected to one end of the eighth resistor R8 and the output positive port 1 VOUTP1, the drain of the fifth N-type MOS transistor N5 is connected to one end of the ninth resistor R9 and the output negative port 1 VOUTN1, the other end of the eighth resistor R8 and the other end of the ninth resistor R9 are commonly connected to one end of the tenth resistor R10, and the other end of the tenth resistor R10 is connected to the positive power supply terminal VDD.

3. The low-jitter clock fan-out buffer with frequency division and delay adjustment according to claim 1, characterized in that: The clock fan-out module includes a connection buffer I1, a D flip-flop 1 D1, a D flip-flop 2 D2, a D flip-flop 3 D3, a D flip-flop 4 D4, a NOR gate 1 Q1, a NOR gate 2 Q2, a NOR gate 3 Q3, a NOR gate 4 Q4, a D flip-flop 5 D5, a D flip-flop 6 D6, a D flip-flop 7 D7, a D flip-flop 8 D8, an input port 1 IN1, an output port 1 OUT1, an output port 2 OUT2, an output port 3 OUT3, an output port 4 OUT4, a synchronization port SYNC, a channel selection port 1 AN1, a channel selection port 2 AN2, a channel selection port 3 AN3, and a channel selection port 4 AN4, wherein: The input port IN1 is connected to the input end of the buffer I1, the output end of the buffer I1 is connected to the clock input end of the D flip-flop D1, the clock input end of the D flip-flop D2, the clock input end of the D flip-flop D3, the clock input end of the D flip-flop D4, the clock input end of the D flip-flop D5, the clock input end of the D flip-flop D6, the clock input end of the D flip-flop D7, and the clock input end of the D flip-flop D8. The D end of the D flip-flop D1 is connected to the positive power supply terminal VDD, the CLR end of the D flip-flop D1 is connected to the synchronization port SYNC, the Q end of the D flip-flop D1 is connected to the input terminal 1 of the NOR gate Q1, and the input terminal 2 of the NOR gate Q1 is connected to the channel selection port AN1, the D end of the D flip-flop D2 is connected to the positive power supply terminal VDD, the CLR end of the D flip-flop D2 is connected to the synchronization port SYNC, the Q end of the D flip-flop D2 is connected to the input terminal 1 of the NOR gate Q2, and the input terminal 2 of the NOR gate Q2 is connected to the channel selection port AN2, the D end of the D flip-flop D3 is connected to the positive power supply terminal VDD, and the D flip-flop D The CLR terminal of D flip-flop D3 is connected to the synchronization port SYNC, the Q terminal of D flip-flop D3 is connected to the input terminal 1 of NOR gate Q3, the input terminal 2 of NOR gate Q3 is connected to the channel selection port AN3, the D terminal of D flip-flop D4 is connected to the positive power supply terminal VDD, the CLR terminal of D flip-flop D4 is connected to the synchronization port SYNC, the Q terminal of D flip-flop D4 is connected to the input terminal 1 of NOR gate Q4, the input terminal 2 of NOR gate Q4 is connected to the channel selection port AN4, and the output terminal of NOR gate Q1 is connected to the positive power supply terminal VDD. The D terminal of D flip-flop five D5 is connected to the Q terminal of D flip-flop five D5, and the Q terminal of D flip-flop five D5 is connected to output port one OUT1; the output terminal of NOR gate two Q2 is connected to the D terminal of D flip-flop six D6, and the Q terminal of D flip-flop six D6 is connected to output port two OUT2; the output terminal of NOR gate three Q3 is connected to the D terminal of D flip-flop seven D7, and the Q terminal of D flip-flop seven D7 is connected to output port three OUT3; the output terminal of NOR gate four Q4 is connected to the D terminal of D flip-flop eight D8, and the Q terminal of D flip-flop eight D8 is connected to output port four OUT4.

4. The low-jitter clock fan-out buffer with frequency division and delay adjustment according to claim 1, characterized in that: The frequency division & delay module includes a transmission gate 1 T1, a transmission gate 2 T2, an inverter 1 I1, an inverter 2 I2, an inverter 3 I3, an inverter 4 I4, an inverter 5 I5, an inverter 6 I6, an inverter 7 I7, an inverter 8 I8, an inverter 9 I9, an inverter 10 I10, an inverter 11 I11, an inverter 12 I12, an inverter 13 I13, a sampling and holding unit circuit 1 C1, a sampling and holding unit circuit 2 C2, a sampling and holding unit circuit Circuit 3 C3, sampling and holding unit circuit 4 C4, sampling and holding unit circuit 5 C5, sampling and holding unit circuit 6 C6, sampling and holding unit circuit 7 C7, sampling and holding unit circuit 8 C8, selector 1 M1, selector 2 M2, selector 3 M3, NOR gate O1, XOR gate O2, OR gate O3, AND gate O4, input port 2 IN2, output port OUT, control port 1 A1, control port 2 A2, control port 3 A3, where: The input end of transmission gate 1 T1 is connected to the input end of inverter 1 I1 and input port 2 IN2. The output end of transmission gate 1 T1 is connected to the output end of inverter 1 I1, the input end of inverter 2 I2, the clock input port of sampling and holding unit circuit 2 C2, the clock input port of sampling and holding unit circuit 4 C4, the clock input port of sampling and holding unit circuit 6 C6, the clock input port of sampling and holding unit circuit 8 C8. The output end of inverter 2 I2 is connected to the clock input port of sampling and holding unit circuit 1 C1, the clock input port of sampling and holding unit circuit 3 C3, the clock input port of sampling and holding unit circuit 5 C5, the clock input port of sampling and holding unit circuit 7 C7. The input port 1 of selector 1 M1 is connected to control port 1 A1. The positive output port of selector 1 M1 is connected to sampling The positive input port of the sample holding unit circuit C1, the negative output port of the selector M1 is connected to the negative input port of the sample holding unit circuit C1, the positive output port of the sample holding unit circuit C1 is connected to the negative input port of the sample holding unit circuit C2, the negative output port of the sample holding unit circuit C1 is connected to the positive input port of the sample holding unit circuit C2, the positive output port of the sample holding unit circuit C2 is connected to the input port of the inverter four I4, the negative output port of the sample holding unit circuit C2 is connected to the input port of the inverter five I5, the output port of the inverter four I4 is connected to the input port 1 of the NOR gate O1 and the input port 1 of the OR gate O3, the output port of the inverter five I5 is connected to the input port 2 of the selector M1 and the input port 1 of the XOR gate O2, the input port 1 of the selector two M2 Connected to control port 2 A2, selector 2 M2 output positive port connected to sampling and holding unit circuit 3 C3 input positive port, selector 2 M2 output negative port connected to sampling and holding unit circuit 3 C3 input negative port, sampling and holding unit circuit 3 C3 output positive port connected to sampling and holding unit circuit 4 C4 input negative port, sampling and holding unit circuit 3 C3 output negative port connected to sampling and holding unit circuit 4 C4 input positive port, sampling and holding unit circuit 4 C4 output positive port connected to inverter 6 I6 input port, sampling and holding unit circuit 4 C4 output negative port connected to inverter 7 I7 input port, inverter 6 I6 output port connected to NOR gate O1 input port 2, XOR gate O2 input port 2, OR gate O3 input port 2, XOR gate O2 output port connected Selector 2 M2 input port 2, selector 3 M3 input port 1 is connected to control port 3 A3, selector 3 M3 output positive port is connected to sampling and holding unit circuit 5 C5 input positive port, selector 3 M3 output negative port is connected to sampling and holding unit circuit 5 C5 input negative port, sampling and holding unit circuit 5 C5 output positive port is connected to sampling and holding unit circuit 6 C6 input negative port, sampling and holding unit circuit 5 C5 output negative port is connected to sampling and holding unit circuit 6 C6 input positive port, sampling and holding unit circuit 6 C6 output positive port is connected to inverter 8 I8 input port, sampling and holding unit circuit 6 C6 output negative port is connected to inverter 9 I9 input port, inverter 8 I8 output port is connected to NOR gate O1 input port 3 and AND gate O4 input port 2,The output port of AND gate O4 is connected to input port 2 of selector 3 M3, the output terminal of OR gate O3 is connected to input port 1 of AND gate O4, the output port of NOR gate O1 is connected to control port of inverter 1 I1, negative port of selector 1 M1, negative port of selector 2 M2, negative port of selector 3 M3, input terminal of transmission gate 2 T2, input terminal of inverter 3 I3, input terminal of inverter 10 I10, output terminal of inverter 3 I3 is connected to control port of transmission gate 1 T1, positive port of selector 1 M1, positive port of selector 2 M2, positive port of selector 3 M3, output terminal of transmission gate 2 T2 is connected to input terminal of sampling and holding unit circuit 7 C7 Input positive port, inverter ten I10 output terminal connected to sampling and holding unit circuit seven C7 input negative port, sampling and holding unit circuit seven C7 output positive port connected to sampling and holding unit circuit eight C8 input negative port, sampling and holding unit circuit seven C7 output negative port connected to sampling and holding unit circuit eight C8 input positive port, sampling and holding unit circuit eight C8 output positive port connected to inverter eleven I11 input port, sampling and holding unit circuit eight C8 output negative port connected to inverter twelve I12 input port, inverter twelve I12 output port connected to inverter thirteen I13 input port, inverter thirteen I13 output port connected to output port OUT. , 5. The low-jitter clock fan-out buffer with frequency division and delay adjustment according to claim 1, characterized in that: The output driver module consists of two parts, namely HSTL, LVDS driver module and LVCMOS driver module, among which: The HSTL and LVDS driver module includes three positive input ports VINP3, three negative input ports VINN3, three positive output ports VOUTP3, three negative output ports VOUTN3, three input reference ports VREF3, four input reference ports VREF4, a first N-type MOS tube N1, a second N-type MOS tube N2, a third N-type MOS tube N3, a first P-type MOS tube P1, a second P-type MOS tube P, and a third P-type MOS tube P3. The three positive input ports VINP3 are respectively connected to the gate of the second N-type MOS tube N2 and the gate of the first P-type MOS tube P1. The three negative input ports VINN3 are respectively connected to the gate of the first N-type MOS tube N1 and the gate of the second P-type MOS tube P2. The three positive output ports VOUTP 3 are respectively connected to the drain of the first N-type MOS tube N1 and the drain of the first P-type MOS tube P1, the output negative port three VOUTN3 are respectively connected to the drain of the second N-type MOS tube N2 and the drain of the second P-type MOS tube P2, the drain of the third N-type MOS tube N3 is respectively connected to the source of the first N-type MOS tube N1 and the source of the second N-type MOS tube N2, the drain of the third P-type MOS tube P3 is respectively connected to the source of the first P-type MOS tube P1 and the source of the second P-type MOS tube P2, the gate of the third N-type MOS tube N3 is connected to the input reference three-port VREF3, the gate of the third P-type MOS tube P3 is connected to the input reference four-port VREF4, the source of the third N-type MOS tube N3 is connected to the negative terminal GND of the power supply, and the source of the third P-type MOS tube P3 is connected to the positive terminal VDD of the power supply. The LVCMOS driving module includes three positive input ports VINP3, three negative input ports VINN3, three positive output ports VOUTP3, three negative output ports VOUTN3, a fourth N-type MOS tube N4, a fifth N-type MOS tube N5, a fourth P-type MOS tube P4, and a fifth P-type MOS tube P5. The three positive input ports VINP3 are respectively connected to the gate of the fourth N-type MOS tube N4 and the gate of the fourth P-type MOS tube P4, the three negative input ports VINN3 are respectively connected to the gate of the fifth N-type MOS tube N5 and the gate of the fifth P-type MOS tube P5, the three positive output ports VOUTP3 are respectively connected to the drain of the fourth N-type MOS tube N4 and the drain of the fourth P-type MOS tube P4, the three negative output ports VOUTN3 are respectively connected to the drain of the fifth N-type MOS tube N5 and the drain of the fifth P-type MOS tube P5, the positive power supply terminal VDD is respectively connected to the source of the fourth P-type MOS tube P4 and the source of the fifth P-type MOS tube P5, and the negative power supply terminal GND is respectively connected to the source of the fourth N-type MOS tube N4 and the source of the fifth N-type MOS tube N5.

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