Analog multiplexer

Abstract

The invention discloses an analog multiplexer which comprises a plurality of data input buffers, a clock input buffer, a core multiplexer and a data output buffer, the input end of each data input buffer is electrically connected with the output end of a digital-to-analog conversion module, and the output end of each data input buffer is electrically connected with one data input end of the core multiplexer; the output end of the clock input buffer is electrically connected with the clock input end of the core multiplexer, and the output end of the core multiplexer is electrically connected with the input end of the data output buffer; wherein the analog multiplexer is manufactured based on a SiGe BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process, and the digital-to-analog conversion module is manufactured based on a CMOS process; each data input buffer is used for shifting and isolating a signal of the digital-to-analog conversion module to obtain a group of differential input signals, the clock input buffer is used for obtaining a clock input signal, and the core multiplexer is used for selecting a group of differential input signals to output according to the clock input signal. And the requirement of high transmission rate of the optical communication system is met.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and particularly relates to an analog multiplexer. Background Art

[0002] With the rapid expansion of broadband services and applications such as video streams and cloud computing, the communication traffic in optical networks is accelerating. To sustain the growing traffic, the transmission capacity per channel is expected to exceed 1 Tb / s in the near future. The channel capacity is defined as the product of the symbol rate and the signal modulation order. Therefore, the channel capacity can be increased by increasing the symbol rate or the modulation order. Considering the limitation of the optical signal-to-noise ratio faced by high-order modulation with increasing transmission distance, it is more beneficial to increase the symbol rate while maintaining a low modulation order. To achieve a single-channel data transmission rate of 400 Gb / s and maintain a modulation order of 4 bit / symbol (coding rate), the symbol rate needs to reach above 120 Gbaud (baud rate). Correspondingly, this requires the ADC (Analog-to-Digital Converter) module and DAC (Digital-to-Analog Converter) module in the optical transceiver to have a sampling rate of at least 120 GS / s and an analog bandwidth of 60 GHz.

[0003] However, so far, the existing ADCs and DACs fabricated only based on the CMOS process can reach a maximum sampling rate of 97 GS / s and an analog bandwidth of 40 GHz, which is far from sufficient for the communication rate to be achieved. By designing and fabricating ADCs and DACs through the SiGe BiCMOS process and InP (Indium Phosphide) Heterojunction Bipolar Transistor (HBT) process, higher sampling rates and larger analog bandwidths can be obtained, which can meet the communication requirements. The DSP (Digital Signal Processing) module is often used in optical communication devices. Usually, the DSP module and the ADC / DAC module need to be integrated together, and the DSP module is generally fabricated using the CMOS process. Since components fabricated using different processes cannot be integrated together, the ADCs and DACs fabricated using these two manufacturing processes and the DSP module fabricated using the CMOS process cannot be integrated together, which cannot meet the requirements of the current optical communication system for the transmission rate. Summary of the Invention

[0004] In view of this, this application provides an analog multiplexer, mainly aiming to solve the problem that the existing digital-to-analog converters fabricated using the CMOS process cannot meet the transmission rate of the optical communication system.

[0005] To solve the above problems, this application provides an analog multiplexer, which includes a plurality of data input buffers, a clock input buffer, a core multiplexer, and a data output buffer, wherein,

[0006] The input end of each data input buffer is electrically connected to the output end of a digital-to-analog conversion module, and the output end of each data input buffer is electrically connected to a data input end of the core multiplexer; the input end of the clock input buffer is electrically connected to the output end of the clock signal module, the output end of the clock input buffer is electrically connected to the clock input end of the core multiplexer, the output end of the core multiplexer is electrically connected to the input end of the data output buffer, and the output end of the data output buffer is electrically connected to the input end of the optoelectronic device; wherein, the analog multiplexer is fabricated based on the SiGeBiCMOS process, and the digital-to-analog conversion module is fabricated based on the CMOS process;

[0007] Each of the data input buffers is configured to perform shifting and isolation processing on the signal output by the digital-to-analog conversion module to obtain a set of differential input signals, the clock input buffer is configured to perform amplification processing on the signal output by the clock signal module to obtain a clock input signal, the core multiplexer is configured to select one set of signals from multiple sets of differential input signals for output according to the clock input signal, and the data output buffer is configured to perform amplification processing on the signal output by the core multiplexer to obtain an output signal and output it to the optoelectronic device.

[0008] In an embodiment of the present application, optionally, the triode included in the data input buffer is a SiGe heterojunction bipolar transistor, and the data input buffer includes a first shifting and isolation module, a first amplification module, a first bias module, a second bias module, and a first tail current source module, wherein,

[0009] The first input end of the first shifting and isolation module is electrically connected to the first output end of the digital-to-analog conversion module, the second input end of the first shifting and isolation module is electrically connected to the second output end of the digital-to-analog conversion module, the first output end of the first shifting and isolation module is respectively electrically connected to the first input end of the first amplification module and the first input end of the first tail current source module, the second output end of the first shifting and isolation module is respectively electrically connected to the second input end of the first amplification module and the second input end of the first tail current source module, the first output end of the first amplification module is electrically connected to the data input end of the core multiplexer, and the second output end of the first amplification module is electrically connected to the third input end of the first tail current source module; the output end of the second bias module is respectively electrically connected to the fourth input end of the first tail current source module and the input end of the first bias module, and the output end of the first bias module is electrically connected to the third input end of the first amplification module.

[0010] In an embodiment of the present application, optionally, the first shifting and isolation module includes a first triode and a second triode, wherein,

[0011] The collector of the first triode is electrically connected to the positive power supply, the base of the first triode is electrically connected to the first output terminal of the digital-to-analog conversion module, and the emitter of the first triode is respectively electrically connected to the first input terminal of the first tail current source module and the first input terminal of the first amplification module;

[0012] The collector of the second triode is electrically connected to the positive power supply, the base of the second triode is electrically connected to the second output terminal of the digital-to-analog conversion module, and the emitter of the second triode is electrically connected to the second input terminal of the first tail current source module and the second input terminal of the first amplification module.

[0013] In an embodiment of the present application, optionally, the first amplification module includes a third triode, a fourth triode, a fifth triode, a sixth triode, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein,

[0014] The first end of the first resistor is electrically connected to the positive power supply, the second end of the first resistor is respectively electrically connected to the first input terminal of the core multiplexer and the collector of the third triode, the base of the third triode is respectively electrically connected to the base of the fourth triode and the output terminal of the first bias module, the emitter of the third triode is electrically connected to the collector of the fifth triode, the base of the fifth triode is electrically connected to the emitter of the first triode, the emitter of the fifth triode is electrically connected to the first end of the third resistor, and the second end of the third resistor is electrically connected to the third input terminal of the first tail current source module;

[0015] The first end of the second resistor is electrically connected to the positive power supply, the second end of the second resistor is respectively electrically connected to the second input terminal of the core multiplexer and the collector of the fourth triode, the emitter of the fourth triode is electrically connected to the collector of the sixth triode, the base of the sixth triode is electrically connected to the emitter of the second triode, the emitter of the sixth triode is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is electrically connected to the third input terminal of the first tail current source module.

[0016] In an embodiment of the present application, optionally, the first bias module includes a seventh triode, an eighth triode, a ninth triode, and a fifth resistor, the second bias module includes a thirteenth triode and a sixth resistor, and the first tail current source module includes an eleventh triode, a twelfth triode, a thirteenth triode, a fourteenth triode, and a fifteenth triode, wherein,

[0017] The first end of the fifth resistor is electrically connected to the positive power supply terminal. The second end of the fifth resistor is electrically connected to the collector and the base of the seventh triode. The emitter of the seventh triode is electrically connected to the collector and the base of the eighth triode. The emitter of the eighth triode is electrically connected to the collector of the ninth triode. The emitter of the ninth triode is electrically connected to the negative power supply terminal;

[0018] The first end of the sixth resistor is electrically connected to the positive power supply terminal. The second end of the sixth resistor is electrically connected to the collector, the base of the thirteenth triode, the base of the ninth triode, the base of the eleventh triode, the base of the twelfth triode, and the base of the thirteenth triode respectively. The emitter of the thirteenth triode is electrically connected to the negative power supply terminal;

[0019] The collector of the fourteenth triode is electrically connected to its base and the first output terminal of the first shift and isolation module respectively. The emitter of the fourteenth triode is electrically connected to the collector of the eleventh triode. The emitter of the eleventh triode is electrically connected to the negative power supply terminal; The collector of the fifteenth triode is electrically connected to its base and the second output terminal of the first shift and isolation module respectively. The collector of the fifteenth triode is electrically connected to the collector of the twelfth triode. The emitter of the twelfth triode is electrically connected to the negative power supply terminal; The collector of the thirteenth triode is electrically connected to the second output terminal of the first amplification module. The emitter of the thirteenth triode is electrically connected to the negative power supply terminal.

[0020] In an embodiment of the present application, optionally, the triode included in the clock input buffer is a SiGe heterojunction bipolar transistor. The clock input buffer includes a second shift and isolation module, a second amplification module, a third shift and isolation module, a third amplification module, a fourth shift and isolation module, a third bias module, a fourth bias module, and a second tail current source module, where,

[0021] The input end of the second shift and isolation module is electrically connected to the output end of the clock signal module. The output end of the second shift and isolation module is respectively electrically connected to the first input end of the second amplification module and the first input end of the second tail current source module. The first output end of the second amplification module is electrically connected to the input end of the third shift and isolation module. The output end of the third shift and isolation module is respectively electrically connected to the first input end of the third amplification module and the second input end of the second tail current source module. The first output end of the third amplification module is electrically connected to the input end of the fourth shift and isolation module. The output end of the fourth shift and isolation module is respectively electrically connected to the clock input end of the core multiplexer and the third input end of the second tail current source module. The second output end of the second amplification module is electrically connected to the fourth input end of the second tail current source module. The second output end of the third amplification module is electrically connected to the fifth input end of the second tail current source module;

[0022] The output end of the fourth bias module is respectively electrically connected to the sixth input end of the second tail current source module and the input end of the third bias module. The output end of the third bias module is respectively electrically connected to the second input end of the second amplification module and the second input end of the third amplification module.

[0023] In an embodiment of the present application, optionally, the triode included in the data output buffer is a SiGe heterojunction bipolar transistor. The data output buffer includes a fifth shift and isolation module, a fourth amplification module, a sixth shift and isolation module, a fifth amplification module, a fifth bias module, a sixth bias module, and a third tail current source module, where

[0024] The input end of the fifth shift and isolation module is electrically connected to the output end of the core multiplexer. The output end of the fifth shift and isolation module is respectively electrically connected to the first input end of the fourth amplification module and the first input end of the third tail current source module. The first output end of the fourth amplification module is electrically connected to the input end of the sixth shift and isolation module. The output end of the sixth shift and isolation module is respectively electrically connected to the first input end of the fifth amplification module and the second input end of the third tail current source module. The first output end of the fifth amplification module is electrically connected to the input end of the optoelectronic device. The second output end of the fourth amplification module is electrically connected to the third input end of the third tail current source module. The fourth input end of the third tail current source module is electrically connected to the second output end of the fifth amplification module;

[0025] The output terminals of the sixth bias module are respectively electrically connected to the fifth input terminal of the third tail current source module and the input terminal of the fifth bias module. The output terminals of the fifth bias module are respectively electrically connected to the second input terminal of the fourth amplification module and the second input terminal of the fifth amplification module.

[0026] In an embodiment of the present application, optionally, the triode included in the core multiplexer is a SiGe heterojunction bipolar transistor. The core multiplexer includes a first input module, a second input module, a switch control module, a seventh bias module, a fourth tail current source module, and a load module, where

[0027] The output terminal of the load module is respectively electrically connected to the first input terminal of the first input module, the first input terminal of the second input module, and the input terminal of the optoelectronic device. The output terminals of the first input module and the second input module are respectively electrically connected to the first input terminal of the switch control module. The output terminal of the switch control module is electrically connected to the first input terminal of the fourth tail current source module. The second input terminal of the fourth tail current source module is electrically connected to the output terminal of the seventh bias module. The second input terminals of the first input module and the second input module are respectively electrically connected to the output terminals of a plurality of data input buffers in one-to-one correspondence. The second input terminal of the switch control module is electrically connected to the output terminal of the clock signal module.

[0028] In an embodiment of the present application, optionally, the load module includes a seventh resistor and an eighth resistor. The first input module includes a sixteenth triode, a seventeenth triode, a ninth resistor, and a tenth resistor. The second input module includes an eighteenth triode, a nineteenth triode, an eleventh resistor, and a twelfth resistor, where

[0029] The first end of the seventh resistor is electrically connected to the positive power supply. The second end of the seventh resistor is respectively electrically connected to the collector of the sixteenth triode, the collector of the eighteenth triode, and the first input terminal of the data output buffer. The emitter of the sixteenth triode is electrically connected to the first end of the ninth resistor. The second end of the ninth resistor is electrically connected to the first input terminal of the switch control module. The base of the sixteenth triode is electrically connected to the first output terminal of a data input buffer.

[0030] The first end of the eighth resistor is electrically connected to the positive power supply. The second end of the eighth resistor is electrically connected to the collector of the seventeenth triode, the collector of the nineteenth triode, and the second input terminal of the data output buffer. The emitter of the seventeenth triode is electrically connected to the first end of the tenth resistor. The second end of the tenth resistor is electrically connected to the first input terminal of the switch control module. The base of the seventeenth triode is electrically connected to the second output terminal of a data input buffer.

[0031] The base of the eighteenth triode is electrically connected to the first output terminal of another data input buffer. The emitter of the eighteenth triode is electrically connected to the first end of the eleventh resistor. The second end of the eleventh resistor is electrically connected to the second input terminal of the switch control module. The base of the nineteenth triode is electrically connected to the second output terminal of another data input buffer. The emitter of the nineteenth triode is electrically connected to the first end of the twelfth resistor. The second end of the twelfth resistor is electrically connected to the second input terminal of the switch control module.

[0032] In an embodiment of the present application, optionally, the switch control module includes a twenty-third triode, a twenty-first triode, a thirteenth resistor, and a fourteenth resistor. The seventh bias module includes a twenty-second triode and a fifteenth resistor. The fourth tail current source module is the twenty-third triode, where

[0033] The base of the twenty-third triode is electrically connected to the first output terminal of the clock input buffer. The emitter of the twenty-third triode is electrically connected to the first end of the thirteenth resistor. The second end of the thirteenth resistor is electrically connected to the collector of the twenty-third triode. The base of the twenty-first triode is electrically connected to the second output terminal of the clock input buffer. The emitter of the twenty-first triode is electrically connected to the first end of the fourteenth resistor. The second end of the fourteenth resistor is electrically connected to the collector of the twenty-third triode. The collector of the twenty-third triode is electrically connected to the second end of the ninth resistor and the second end of the tenth resistor respectively. The collector of the twenty-first triode is electrically connected to the second end of the eleventh resistor and the second end of the twelfth resistor respectively.

[0034] The first end of the fifteenth resistor is electrically connected to the positive power supply. The second end of the fifteenth resistor is electrically connected to the collector, base of the twenty-second triode, and the base of the twenty-third triode. The emitter of the twenty-second triode is electrically connected to the negative power supply. The emitter of the twenty-third triode is electrically connected to the negative power supply.

[0035] Advantages of the present application: An analog multiplexer provided by the present application is manufactured using the SiGeBiCMOS process and is connected between a digital-to-analog conversion module manufactured using the CMOS process and an optoelectronic device. By connecting multiple data input buffers to a digital-to-analog conversion module respectively, each data input buffer processes the signal of a digital-to-analog conversion module through offset and amplification and then uses it as a set of differential input data, which is sent to the data input end of the core multiplexer. The clock buffer processes the clock initial signal of the clock signal module through amplification and then uses it as a clock signal, which is sent to the core multiplexer. The core multiplexer selects different sets of differential input signals as outputs according to the high and low levels of the clock signal and transmits them to the optoelectronic device through the data output buffer, improving the analog bandwidth of the data, further increasing the sampling rate, and meeting the requirements of high transmission rate in the optical communication system.

[0036] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the following specifically gives the specific implementation manners of the present application. Brief Description of the Drawings

[0037] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present application. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0038] Figure 1 It is a structural block diagram of an analog multiplexer according to an exemplary embodiment of the present application;

[0039] Figure 2 It is a structural connection diagram of an analog multiplexer according to an exemplary embodiment of the present application;

[0040] Figure 3 It is a schematic circuit structure diagram of a data input buffer of an analog multiplexer according to an exemplary embodiment of the present application;

[0041] Figure 4 It is a schematic circuit structure diagram of a clock input buffer of an analog multiplexer according to an exemplary embodiment of the present application;

[0042] Figure 5 It is a schematic circuit structure diagram of a data output buffer of an analog multiplexer according to an exemplary embodiment of the present application;

[0043] Figure 6 It is a schematic circuit structure diagram of a core multiplexer of an analog multiplexer according to an exemplary embodiment of the present application;

[0044] Figure 7 Schematic diagram of frequency-domain interpretation of a 2:1 analog multiplexer according to an exemplary embodiment of the present application

[0045] Figure 8 Schematic diagram of frequency-domain interpretation of bandwidth expansion of digital-to-analog conversion of an analog multiplexer according to an exemplary embodiment of the present application.

[0046] Among them,

[0047] Figures 1-6 The reference numerals of are as follows: 11 - data input buffer; 12 - clock input buffer; 13 - core multiplexer; 14 - data output buffer; 20 - optoelectronic device; 30 - digital-to-analog conversion module; 40 - clock signal module 40; 111 - first shift and isolation module; 112 - first amplification module; 113 - first bias module; 114 - second bias module; 115 - first tail current source module; 121 - second shift and isolation module; 122 - second amplification module; 123 - third shift and isolation module; 124 - third amplification module; 125 - fourth shift and isolation module; 126 - third bias module; 127 - fourth bias module; 128 - second tail current source module; 141 - fifth shift and isolation module; 142 - fourth amplification module; 143 - sixth shift and isolation module; 144 - fifth amplification module; 145 - fifth bias module; 146 - sixth bias module; 147 - third tail current source module; 131 - first input module; 132 - second input module; 133 - switch control module; 134 - seventh bias module; 135 - load module; 136 - fourth tail current source module; Q1 - Q23 - first triode - twenty-third triode; R1 - R14 - first resistor - fourteenth resistor. Detailed implementation manners

[0048] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other.

[0049] To further elaborate on the technical means and effects adopted by the present application to achieve the intended invention purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation manners, structures, features, and their effects of the present application. In the following description, different "one embodiment" or "embodiment" do not necessarily refer to the same embodiment. In addition, the specific features, structures, or characteristics in one or more embodiments may be combined in any suitable form.

[0050] The following will be combined with Figures 1 to 6 Describe an analog multiplexer proposed according to some embodiments of the present application.

[0051] In one embodiment, asFigure 1 As shown in the figure, a simulation multiplexer includes a plurality of data input buffers 11, a clock input buffer 12, a core multiplexer 13, and a data output buffer 14. Among them,

[0052] The input end of each data input buffer 11 is electrically connected to the output end of a digital-to-analog conversion module 30, and the output end of each data input buffer 11 is electrically connected to a data input end of the core multiplexer 13; the input end of the clock input buffer 12 is electrically connected to the output end of the clock signal module, the output end of the clock input buffer 12 is electrically connected to the clock input end of the core multiplexer 13, the output end of the core multiplexer 13 is electrically connected to the input end of the data output buffer 14, and the output end of the data output buffer 14 is electrically connected to the input end of the optoelectronic device 20; among them, the simulation multiplexer is fabricated based on the SiGe BiCMOS process, and the digital-to-analog conversion module 30 is fabricated based on the CMOS process;

[0053] Each data input buffer 11 is used to perform shifting and isolation processing on the signal output by the digital-to-analog conversion module 30 to obtain a set of differential input signals. The clock input buffer 12 is used to amplify the signal output by the clock signal module to obtain a clock input signal. The core multiplexer 13 is used to select and output one set of signals from multiple sets of differential input signals according to the clock input signal. The data output buffer 14 is used to amplify the signal output by the core multiplexer 13 to obtain an output signal and output it to the optoelectronic device 20.

[0054] Specifically, taking Figure 2 shown as an example, there are two data input buffers and two digital-to-analog conversion modules. Each digital-to-analog conversion module is connected to a data input buffer. The analog signal of the digital-to-analog conversion module is connected to the core multiplexer through the data input buffer, and the clock signal is connected to the core multiplexer through the clock input buffer. The above three output signals enter the core multiplexer for interleaved sampling operation, and the output signal obtains a multiplexed combined output signal through the data output buffer. For example, when the clock signal is a high-level signal, the switch control module controls the input signal of the first input module as the output signal. When the clock signal is a low-level signal, the switch control module controls the input signal of the second input module as the output signal. This circuit module is based on the IHP130 nm SiGe BiCMOS process, the power supply voltage is 3.3V, and a SiGe heterojunction bipolar transistor with a high characteristic frequency is used. The emitter width of the SiGe HBT is fixed at 70nm, and the emitter length is adjustable. When the emitter length is 1μm and biased at 2.6mA (the emitter current density is 37mA / μm 2 ) the maximum f T can be obtained.

[0055] In one embodiment, there are four data input buffers, four digital-to-analog conversion modules, three clock input buffers, and three core multiplexers. Each digital-to-analog conversion module is connected to one data input buffer. Two of the data input buffers are connected to the first core multiplexer, and the other two data input buffers are connected to the second core multiplexer. Each clock input buffer is connected to one core multiplexer. The outputs of the first core multiplexer and the second core multiplexer are connected to the inputs of the third core multiplexer. The output of the third core multiplexer is connected to the data output buffer. Different groups of differential input signals are output through three clock signals, implementing a 4:1 analog multiplexer.

[0056] Compared with the prior art, an analog multiplexer provided by the present application is fabricated using the SiGe BiCMOS process and is connected between a digital-to-analog conversion module fabricated using the CMOS process and an optoelectronic device. By connecting each of multiple data input buffers to one digital-to-analog conversion module, each data input buffer processes the signal of a digital-to-analog conversion module through offset and amplification as a group of differential input data and sends it to the data input terminal of the core multiplexer. The clock buffer processes the clock initial signal of the clock signal module through amplification as the clock signal and sends it to the core multiplexer. The core multiplexer selects different groups of differential input signals as the output according to the high and low levels of the clock signal and transmits them to the optoelectronic device through the data output buffer, improving the analog bandwidth of the data, further increasing the sampling rate, and meeting the requirements of high transmission rate in the optical communication system.

[0057] In one embodiment, referring to Figure 3 , the triode included in the data input buffer 11 is a SiGe heterojunction bipolar transistor. The data input buffer 11 includes a first shift and isolation module 111, a first amplification module 112, a first bias module 113, a second bias module 114, and a first tail current source module 115. Among them,

[0058] The first input terminal of the first shift and isolation module 111 is electrically connected to the first output terminal of the digital-to-analog conversion module 30, the second input terminal of the first shift and isolation module 111 is electrically connected to the second output terminal of the digital-to-analog conversion module 30, the first output terminal of the first shift and isolation module 111 is respectively electrically connected to the first input terminal of the first amplification module 112 and the first input terminal of the first tail current source module 115, the second output terminal of the first shift and isolation module 111 is respectively electrically connected to the second input terminal of the first amplification module 112 and the second input terminal of the first tail current source module 115, the first output terminal of the first amplification module 112 is electrically connected to the data input terminal of the core multiplexer 13, and the second output terminal of the first amplification module 112 is electrically connected to the third input terminal of the first tail current source module 115; the output terminal of the second bias module 114 is respectively electrically connected to the fourth input terminal of the first tail current source module 115 and the input terminal of the first bias module 113, and the output terminal of the first bias module 113 is electrically connected to the third input terminal of the first amplification module 112.

[0059] In this embodiment, after the signal of the digital-to-analog conversion module enters the data input buffer, the data input buffer performs shift and isolation processing and amplification processing on the input signal level to obtain a set of differential input signals, and sends the set of amplified differential input signals to the core multiplexer to drive the subsequent core multiplexer.

[0060] In one embodiment, as Figure 3 shown, the first shift and isolation module 111 includes a first triode Q1 and a second triode Q2, where

[0061] The collector of the first triode Q1 is electrically connected to the positive power supply, the base of the first triode Q1 is electrically connected to the first output terminal of the digital-to-analog conversion module 30, and the emitter of the first triode Q1 is respectively electrically connected to the first input terminal of the first tail current source module 115 and the first input terminal of the first amplification module 112;

[0062] The collector of the second triode Q2 is electrically connected to the positive power supply, the base of the second triode Q2 is electrically connected to the second output terminal of the digital-to-analog conversion module 30, and the emitter of the second triode Q2 is electrically connected to the second input terminal of the first tail current source module 115 and the second input terminal of the first amplification module 112.

[0063] Specifically, the resistor R101 and the resistor R102 form an input terminal matching resistor for matching with the previous-stage circuit; the triodes Q1 and Q2 form the first shift and isolation module, serving as an emitter follower of the data input buffer, for shifting the input differential signal and isolating it from the subsequent circuit.

[0064] In one embodiment, refer to Figure 3, the first amplification module 112 includes a third triode Q3, a fourth triode Q4, a fifth triode Q5, a sixth triode Q6, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, where

[0065] The first end of the first resistor R1 is electrically connected to the positive power supply. The second end of the first resistor R1 is respectively electrically connected to the first input terminal of the core multiplexer 13 and the collector of the third triode Q3. The base of the third triode Q3 is respectively electrically connected to the base of the fourth triode Q4 and the output terminal of the first bias module 113. The emitter of the third triode Q3 is electrically connected to the collector of the fifth triode Q5. The base of the fifth triode Q5 is electrically connected to the emitter of the first triode Q1. The emitter of the fifth triode Q5 is electrically connected to the first end of the third resistor R3. The second end of the third resistor R3 is electrically connected to the third input terminal of the first tail current source module 115;

[0066] The first end of the second resistor R2 is electrically connected to the positive power supply. The second end of the second resistor R2 is respectively electrically connected to the second input terminal of the core multiplexer 13 and the collector of the fourth triode Q4. The emitter of the fourth triode Q4 is electrically connected to the collector of the sixth triode Q6. The base of the sixth triode Q6 is electrically connected to the emitter of the second triode Q2. The emitter of the sixth triode Q6 is electrically connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 is electrically connected to the third input terminal of the first tail current source module 115.

[0067] Specifically, the triodes Q5, Q6, resistor R1, and resistor R2 form the first amplification module, which is a current-mode logic (CML) type amplifier of the data input buffer, used to amplify the input differential signal and provide relatively fast speed and large driving ability. The triodes Q3 and Q4 are inserted thereon to eliminate the influence of the Miller effect of the gate-drain parasitic capacitance of the triodes Q5 and Q6 on the circuit speed. The resistors R3 and R4 are the emitter resistors of the amplifier, used to increase the small-signal linear gain range of the circuit. The capacitor adopts the emitter peaking technique to generate a low-frequency zero point, improve the amplitude-frequency response of the circuit, and expand the bandwidth. In order to prevent the output signal from clipping distortion, the differential input swing of the data input linear buffer should be less than 700 mV. In this circuit, the emitter length of the triode serving as the amplifier is 1 μm, and the bias current magnitude is 2.6 mA, so that the transistor is biased near the maximum f T to obtain the theoretically maximum bandwidth.

[0068] In one embodiment, refer to Figure 3, the first bias module 113 includes a seventh triode Q7, an eighth triode Q8, a ninth triode Q9, and a fifth resistor R5. The second bias module 114 includes a tenth triode Q10 and a sixth resistor R6. The first tail current source module 115 includes an eleventh triode Q11, a twelfth triode Q12, a thirteenth triode Q13, a fourteenth triode Q14, and a fifteenth triode Q15. Among them,

[0069] The first end of the fifth resistor R5 is electrically connected to the positive power supply. The second end of the fifth resistor R5 is electrically connected to the collector and base of the seventh triode Q7. The emitter of the seventh triode Q7 is electrically connected to the collector and base of the eighth triode Q8. The emitter of the eighth triode Q8 is electrically connected to the collector of the ninth triode. The emitter of the ninth triode Q9 is electrically connected to the negative power supply;

[0070] The first end of the sixth resistor R6 is electrically connected to the positive power supply. The second end of the sixth resistor R6 is electrically connected to the collector, base of the tenth triode Q10, the base of the ninth triode Q9, the base of the eleventh triode Q11, the base of the twelfth triode Q12, and the base of the thirteenth triode Q13 respectively. The emitter of the tenth triode Q10 is electrically connected to the negative power supply;

[0071] The collector of the fourteenth triode Q14 is electrically connected to its base and the first output terminal of the first shift and isolation module 111 respectively. The emitter of the fourteenth triode Q14 is electrically connected to the collector of the eleventh triode Q11. The emitter of the eleventh triode Q11 is electrically connected to the negative power supply; The collector of the fifteenth triode Q15 is electrically connected to its base and the second output terminal of the first shift and isolation module 111 respectively. The collector of the fifteenth triode Q15 is electrically connected to the collector of the twelfth triode Q12. The emitter of the twelfth triode Q12 is electrically connected to the negative power supply; The collector of the thirteenth triode Q13 is electrically connected to the second output terminal of the first amplification module 112. The emitter of the thirteenth triode Q13 is electrically connected to the negative power supply.

[0072] Specifically, the resistor R5, the triode Q7, the triode Q8, and the triode Q9 constitute a first bias circuit for providing voltage bias to the gates of the triodes Q3 and Q4. The triodes Q7 and Q8 are connected in a diode connection manner to prevent the collector-emitter voltage drop of the triode Q9 from being too large and being broken down; The resistor R6 and the triode Q10 constitute a second bias circuit for providing bias current to other branches; The triodes Q11, Q12, and Q13 constitute a first tail current source module; The triodes Q14 and Q15 are connected in a diode connection manner to prevent the collector-emitter voltage drop of the triodes Q11 and Q12 from being too large and being broken down. In this circuit, the emitter length of the triode used as a bias is 1μm, and the bias current is 2.6mA.

[0073] In one embodiment, referring to Figure 4 , the triode included in the clock input buffer 12 is a SiGe heterojunction bipolar transistor. The clock input buffer 12 includes a second shift and isolation module 121, a second amplification module 122, a third shift and isolation module 123, a third amplification module 124, a fourth shift and isolation module 125, a third bias module 126, a fourth bias module 127, and a second tail current source module 128. Among them,

[0074] The input end of the second shift and isolation module 121 is electrically connected to the output end of the clock signal module. The output end of the second shift and isolation module 121 is respectively electrically connected to the first input end of the second amplification module 122 and the first input end of the second tail current source module 128. The first output end of the second amplification module 122 is electrically connected to the input end of the third shift and isolation module 123. The output end of the third shift and isolation module 123 is respectively electrically connected to the first input end of the third amplification module 124 and the second input end of the second tail current source module 128. The first output end of the third amplification module 124 is electrically connected to the input end of the fourth shift and isolation module 125. The output end of the fourth shift and isolation module 125 is respectively electrically connected to the clock input end of the core multiplexer 13 and the third input end of the second tail current source module 128. The second output end of the second amplification module 122 is electrically connected to the fourth input end of the second tail current source module 128. The second output end of the third amplification module 124 is electrically connected to the fifth input end of the second tail current source module 128;

[0075] The output end of the fourth bias module 127 is respectively electrically connected to the sixth input end of the second tail current source module 128 and the input end of the third bias module 126. The output end of the third bias module 126 is respectively electrically connected to the second input end of the second amplification module 122 and the second input end of the third amplification module 124.

[0076] In this embodiment, the circuit function is to shift, isolate, and amplify the input clock level signal. Resistors R71 and R72 form an input terminal matching resistor for matching with the previous-stage circuit; transistors Q75 and Q78 form a second shift and isolation module, which serves as the first-stage emitter follower of this clock input buffer, for performing the first shift on the input differential signal and isolating it from the subsequent circuit; transistors Q83, Q84, resistor R75, and resistor R76 form a second amplification module, which serves as the first-stage CML-type amplifier of this clock input buffer, for performing the first amplification on the input differential signal and providing a relatively fast speed and a large driving capability; transistors Q81 and Q82 are inserted thereon to eliminate the influence of the Miller effect of the gate-drain parasitic capacitance of transistors Q83 and Q84 on the circuit speed; transistors Q86 and Q89 form a third shift and isolation module, which serves as the second-stage emitter follower of this clock input buffer, for performing the second shift on the input differential signal and isolating it from the subsequent circuit; transistors Q94, Q95, resistor R79, and resistor R80 form a third amplification module, which serves as the second-stage CML-type amplifier of this clock input buffer, for performing the second amplification on the input differential signal and providing a relatively fast speed and a large driving capability; transistors Q92 and Q93 are inserted thereon to eliminate the influence of the Miller effect of the gate-drain parasitic capacitance of transistors Q94 and Q95 on the circuit speed; transistors Q97 and Q100 form a fourth shift and isolation module, which serves as the third-stage emitter follower of this clock input buffer, for performing the third shift on the input differential signal and isolating it from the subsequent circuit; resistor R73, transistors Q71, Q72, and Q73 form a third bias circuit to provide voltage bias for the gates of transistors Q81, Q82, Q92, and Q93; transistors Q71 and Q72 are connected in a diode configuration to prevent the collector-emitter voltage drop of transistor Q73 from being too large and causing breakdown; resistor R74 and transistor Q74 form a fourth bias circuit to provide bias current for other branches; transistors Q77, Q80, Q85, Q88, Q91, Q96, Q99, and Q102 form a second tail current source module; transistors Q76, Q79, Q87, Q90, Q98, and Q101 are connected in a diode configuration to prevent the collector-emitter voltage drop of transistors Q77, Q80, Q88, Q91, Q99, and Q102 from being too large and causing breakdown; resistors R77 and R78 are the emitter resistors of the first-stage amplifier, and resistors R81 and R82 are the emitter resistors of the second-stage amplifier, which are used to increase the small-signal linear gain range of the circuit;The capacitor adopts emitter peaking technology to generate low-frequency zeros, improve the amplitude-frequency response of the circuit and expand the bandwidth. To enable full-switching operation of the clock pair transistors in the core multiplexer, the differential input swing of the clock input limiting buffer should be greater than 300 mV. In this circuit, the emitter length of the triodes serving as bias, emitter follower and differential pair transistors is 1 μm, and the bias current is 2.6 mA. The emitter length of the triode serving as the tail current source of the differential pair transistor is 2 μm, and the bias current is 5.2 mA, so that the transistor is biased at the maximum f under static conditions; T nearby to obtain the theoretically maximum bandwidth.

[0077] In one embodiment, as Figure 5 shown, the triodes included in the data output buffer 14 are SiGe heterojunction bipolar transistors. The data output buffer 14 includes a fifth shift and isolation module 141, a fourth amplification module 142, a sixth shift and isolation module 143, a fifth amplification module 144, a fifth bias module 145, a sixth bias module 146 and a third tail current source module 147. Among them,

[0078] The input end of the fifth shift and isolation module 141 is electrically connected to the output end of the core multiplexer 13. The output end of the fifth shift and isolation module 141 is respectively electrically connected to the first input end of the fourth amplification module 142 and the first input end of the third tail current source module 147. The first output end of the fourth amplification module 142 is electrically connected to the input end of the sixth shift and isolation module 143. The output end of the sixth shift and isolation module 143 is respectively electrically connected to the first input end of the fifth amplification module 144 and the second input end of the third tail current source module 147. The first output end of the fifth amplification module 144 is electrically connected to the input end of the optoelectronic device 20. The second output end of the fourth amplification module 142 is electrically connected to the third input end of the third tail current source module 147. The fourth input end of the third tail current source module 147 is electrically connected to the second output end of the fifth amplification module 144;

[0079] The output end of the sixth bias module 146 is respectively electrically connected to the fifth input end of the third tail current source module 147 and the input end of the fifth bias module 145. The output end of the fifth bias module 145 is respectively electrically connected to the second input end of the fourth amplification module 142 and the second input end of the fifth amplification module 144.

[0080] Specifically, the circuit function is to shift and amplify the output signal level of the core multiplexer and drive the optoelectronic load behind it. Resistors R41 and R42 form an input terminal matching resistor for matching with the previous-stage circuit; transistors Q45 and Q48 form a fifth shift and isolation module, which is the first-stage emitter follower of the data output buffer, used to perform the first shift on the input differential signal and isolate it from the subsequent circuit; transistors Q53, Q54, resistor R45, and resistor R46 form a fourth amplification module, which is the first-stage CML-type amplifier of the data output buffer, used to perform the first amplification on the input differential signal and provide a relatively fast speed and a large driving ability; transistors Q51 and Q52 are inserted thereon to eliminate the influence of the Miller effect of the gate-drain parasitic capacitance of transistors Q53 and Q54 on the circuit speed; transistors Q56 and Q59 form a sixth shift and isolation module, which is the second-stage emitter follower of the data output buffer, used to perform the second shift on the input differential signal and isolate it from the subsequent circuit; transistors Q64, Q65, resistor R49, and resistor R50 form a fifth amplification module, which is the second-stage CML-type amplifier of the data output buffer, used to perform the second amplification on the input differential signal and provide a relatively fast speed and a large driving ability; transistors Q62 and Q63 are inserted thereon to eliminate the influence of the Miller effect of the gate-drain parasitic capacitance of transistors Q64 and Q65 on the circuit speed; resistors R43, transistors Q41, Q42, and Q43 form a fifth bias circuit to provide voltage bias for the gates of transistors Q51, Q52, Q52, and Q53; transistors Q41 and Q42 are connected in a diode configuration to prevent the collector-emitter voltage drop of transistor Q43 from being too large and causing breakdown; resistors R44 and transistor Q44 form a sixth bias circuit to provide bias current for other branches; transistors Q47, Q50, Q55, Q58, Q61, and Q66 form a third tail current source module; transistors Q46, Q49, Q57, and Q60 are connected in a diode configuration to prevent the collector-emitter voltage drop of transistors Q47, Q50, Q58, and Q61 from being too large and causing breakdown; resistors R47 and R48 are the emitter resistors of the first-stage amplifier, and resistors R51 and R52 are the emitter resistors of the second-stage amplifier, used to increase the small-signal linear gain range of the circuit; in order to improve its driving ability and output swing, the emitter length and bias current of the transistors in this circuit are doubled compared with those of the input buffer.

[0081] In one embodiment, participate in Figure 6, the triode included in the core multiplexer 13 is a SiGe heterojunction bipolar transistor. The core multiplexer 13 includes a first input module 131, a second input module 132, a switch control module 133, a seventh bias module 134, a fourth tail current source module 136, and a load module 135. Among them,

[0082] The output end of the load module 135 is electrically connected to the first input end of the first input module 131, the first input end of the second input module 132, and the input end of the optoelectronic device 20 respectively. The output ends of the first input module 131 and the second input module 132 are electrically connected to the first input end of the switch control module 133 respectively. The output end of the switch control module 133 is electrically connected to the first input end of the fourth tail current source module 136. The second input end of the fourth tail current source module 136 is electrically connected to the output end of the seventh bias module 134. The second input ends of the first input module 131 and the second input module 132 are electrically connected to the output ends of a plurality of data input buffers 11 in one-to-one correspondence respectively. The second input end of the switch control module 133 is electrically connected to the output end of the clock signal module.

[0083] Specifically, the essence of the core multiplexer is a linear selection circuit, which alternately passes two analog signals under clock selection. For example, when the clock signal is a high-level signal, the switch control module controls the input signal of the first input module as the output signal. When the clock signal is a low-level signal, the switch control module controls the input signal of the second input module as the output signal.

[0084] In one embodiment, see Figure 6 , the load module 135 includes a seventh resistor R7 and an eighth resistor R8. The first input module 131 includes a sixteenth triode Q16, a seventeenth triode Q17, a ninth resistor R9, and a tenth resistor R10. The second input module 132 includes an eighteenth triode Q18, a nineteenth triode Q19, an eleventh resistor R11, and a twelfth resistor R12. Among them,

[0085] The first end of the seventh resistor R7 is electrically connected to the positive power supply. The second end of the seventh resistor R7 is electrically connected to the collector of the sixteenth triode Q16, the collector of the eighteenth triode Q18, and the first input end of the data output buffer 14 respectively. The emitter of the sixteenth triode Q16 is electrically connected to the first end of the ninth resistor R9. The second end of the ninth resistor R9 is electrically connected to the first input end of the switch control module 133. The base of the sixteenth triode Q16 is electrically connected to the first output end of a data input buffer 11.

[0086] The first end of the eighth resistor R8 is electrically connected to the positive power supply, and the second end of the eighth resistor R8 is respectively electrically connected to the collector of the seventeenth triode Q17, the collector of the nineteenth triode Q19, and the second input terminal of the data output buffer 14. The emitter of the seventeenth triode Q17 is electrically connected to the first end of the tenth resistor R10, and the second end of the tenth resistor R10 is electrically connected to the first input terminal of the switch control module 133; the base of the seventeenth triode Q17 is electrically connected to the second output terminal of a data input buffer 11;

[0087] The base of the eighteenth triode Q18 is electrically connected to the first output terminal of another data input buffer 11. The emitter of the eighteenth triode Q18 is electrically connected to the first end of the eleventh resistor R11, and the second end of the eleventh resistor R11 is electrically connected to the second input terminal of the switch control module 133; the base of the nineteenth triode Q19 is electrically connected to the second output terminal of another data input buffer 11, and the emitter of the nineteenth triode Q19 is electrically connected to the first end of the twelfth resistor R12, and the second end of the twelfth resistor R12 is electrically connected to the second input terminal of the switch control module 133.

[0088] Specifically, the triodes Q16 and Q14 are the first input pair of transistors, the triodes Q18 and Q19 are the second input pair of transistors, the resistors R7 and R8 are load resistors, and the resistor R1 and the triode Q7 form a bias circuit to provide a bias current for the triode Q8; the signal pair of transistors introduces emitter resistors R9, R10, R11, and R12 to increase the small-signal linear gain range. The emitter length of the differential pair of transistors in this circuit is 1 μm.

[0089] In one embodiment, participating Figure 6 , the switch control module 133 includes a twenty-third triode Q20, a twenty-first triode Q21, a thirteenth resistor R13, and a fourteenth resistor R14. The seventh bias module 134 includes a twenty-second triode Q22 and a fifteenth resistor. The fourth tail current source module 136 is the twenty-third triode Q23, where

[0090] The base of the twenty-third triode Q20 is electrically connected to the first output terminal of the clock input buffer 12. The emitter of the twenty-third triode Q20 is electrically connected to the first end of the thirteenth resistor R13. The second end of the thirteenth resistor R13 is electrically connected to the collector of the twenty-third triode Q23. The base of the twenty-first triode Q21 is electrically connected to the second output terminal of the clock input buffer 12. The emitter of the twenty-first triode Q21 is electrically connected to the first end of the fourteenth resistor R14. The second end of the fourteenth resistor R14 is electrically connected to the collector of the twenty-third triode Q23. The collector of the twenty-third triode Q20 is respectively electrically connected to the second end of the ninth resistor R9 and the second end of the tenth resistor R10. The collector of the twenty-first triode Q21 is respectively electrically connected to the second end of the eleventh resistor R11 and the second end of the twelfth resistor R12.

[0091] The first end of the fifteenth resistor is electrically connected to the positive power supply. The second end of the fifteenth resistor is electrically connected to the collector and the base of the twenty-second triode Q22 and the base of the twenty-third triode Q23. The emitter of the twenty-second triode Q22 is electrically connected to the negative power supply. The emitter of the twenty-third triode Q23 is electrically connected to the negative power supply.

[0092] Specifically, the clock pair transistors Q20 and Q21 are used as switches and normally operate in the saturation region. The resistor R15 and the transistor Q22 form a bias circuit to provide a bias current for the transistor Q23. The emitter resistors R13 and R14 are introduced for both clock pair transistors to increase the small-signal linear gain range. The emitter length of the differential pair transistors in this circuit is 1 μm, the emitter length of the transistor serving as the bias and tail current source is 2 μm, and the tail current magnitude is 5.2 mA, such that the input signal pair transistors are biased near the maximum f T to obtain the theoretically maximum bandwidth.

[0093] As Figure 7 shown, the 2:1 analog multiplexer can be represented as an equivalent model consisting of two multipliers and a linear adder. In the time domain, the two analog inputs are multiplexed in two paths by the differential clock signal, and finally the analog multiplexer outputs a sum signal. In the frequency domain, the clock has two components: direct current (DC) and f clk , and the impulse amplitude ratio r between f clk and DC depends on the waveform of the clock signal. If it is a square-wave clock, then r = 2 / π; if it is a sine-wave clock, then r = 1 / 2. Meanwhile, the bandwidth of each analog input signal is f clk / 2. The output signal of each multiplier is the convolution of the analog input signal and the spectrum of the clock signal. Then, the analog multiplexer outputs a sum signal containing all the frequency components from these two multipliers.

[0094] As Figure 8As shown, through digital preprocessing, the target signal with a bandwidth of f B is divided into a lower-band signal and an upper-band signal. Then, the upper-band signal is flipped with f B / 2 as the boundary and multiplied by the amplitude factor 1 / r. The processed upper and lower-band signals are respectively subjected to addition and subtraction operations. The obtained signals respectively pass through two DACs with an analog bandwidth of f B / 2. The signals after DAC processing enter a 2:1 analog multiplexer and are multiplexed in two channels under the control of a clock signal with a frequency of f B . The input signal and the signal after convolution of the clock signal are linearly added to obtain the output signal. The signal exceeding f B is filtered by a low-pass filter to obtain the target signal, which is twice the analog bandwidth of the DAC.

[0095] It should be understood that various modifications can be made to the embodiments claimed herein. Therefore, the above description should not be regarded as limiting, but merely as an example of the embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the present application.

[0096] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0097] These and other features of the present application will become apparent from the following description of the preferred forms of the embodiments given as non-limiting examples with reference to the accompanying drawings.

[0098] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art can surely implement many other equivalent forms of the present application.

[0099] When combined with the accompanying drawings, the above and other aspects, features, and advantages of the present application will become more apparent in view of the following detailed description.

[0100] Specific embodiments of the present application will be described hereinafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of the present application and can be implemented in various ways. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present application with unnecessary or redundant details. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely as a basis and representative basis for the claims to teach those skilled in the art to use the present application in substantially any suitable detailed structure in a diverse manner.

[0101] This specification may use phrases such as "in one embodiment", "in another embodiment", "in yet another embodiment", or "in other embodiments", all of which may refer to one or more of the same or different embodiments according to the present application.

[0102] The above embodiments are only exemplary embodiments of the present application and are not used to limit the present application. The protection scope of the present application is defined by the claims. Those skilled in the art can make various modifications or equivalent replacements within the essence and protection scope of the present application, and such modifications or equivalent replacements should also be regarded as falling within the protection scope of the present application.

Claims

1. An analog multiplexer, characterized in that, The analog multiplexer includes a plurality of data input buffers, a clock input buffer, a core multiplexer, and a data output buffer. Among them, The input end of each data input buffer is electrically connected to the output end of a digital-to-analog conversion module, and the output end of each data input buffer is electrically connected to a data input end of the core multiplexer; the input end of the clock input buffer is electrically connected to the output end of the clock signal module, the output end of the clock input buffer is electrically connected to the clock input end of the core multiplexer, the output end of the core multiplexer is electrically connected to the input end of the data output buffer, and the output end of the data output buffer is electrically connected to the input end of the optoelectronic device; among them, the analog multiplexer is fabricated based on the SiGeBiCMOS process, and the digital-to-analog conversion module is fabricated based on the CMOS process; Each of the data input buffers is configured to perform shifting and isolation processing on the signal output by the digital-to-analog conversion module to obtain a set of differential input signals, the clock input buffer is configured to perform amplification processing on the signal output by the clock signal module to obtain a clock input signal, the core multiplexer is configured to select one set of signals from multiple sets of differential input signals for output according to the clock input signal, and the data output buffer is configured to perform amplification processing on the signal output by the core multiplexer to obtain an output signal and output it to the optoelectronic device.

2. The analog multiplexer according to claim 1, characterized in that, The triode included in the data input buffer is a SiGe heterojunction bipolar transistor. The data input buffer includes a first shifting and isolation module, a first amplification module, a first bias module, a second bias module, and a first tail current source module. Among them, The first input end of the first shifting and isolation module is electrically connected to the first output end of the digital-to-analog conversion module, the second input end of the first shifting and isolation module is electrically connected to the second output end of the digital-to-analog conversion module, the first output end of the first shifting and isolation module is respectively electrically connected to the first input end of the first amplification module and the first input end of the first tail current source module, the second output end of the first shifting and isolation module is respectively electrically connected to the second input end of the first amplification module and the second input end of the first tail current source module, the first output end of the first amplification module is electrically connected to the data input end of the core multiplexer, and the second output end of the first amplification module is electrically connected to the third input end of the first tail current source module; the output end of the second bias module is respectively electrically connected to the fourth input end of the first tail current source module and the input end of the first bias module, and the output end of the first bias module is electrically connected to the third input end of the first amplification module.

3. The analog multiplexer according to claim 2, characterized in that, The first shifting and isolation module includes a first triode and a second triode. Among them, The collector of the first triode is electrically connected to the positive power supply, the base of the first triode is electrically connected to the first output end of the digital-to-analog conversion module, and the emitter of the first triode is respectively electrically connected to the first input end of the first tail current source module and the first input end of the first amplification module; The collector of the second triode is electrically connected to the positive power supply terminal. The base of the second triode is electrically connected to the second output terminal of the digital-to-analog conversion module. The emitter of the second triode is electrically connected to the second input terminal of the first tail current source module and the second input terminal of the first amplification module.

4. The analog multiplexer according to claim 3, characterized in that, The first amplification module includes a third triode, a fourth triode, a fifth triode, a sixth triode, a first resistor, a second resistor, a third resistor, and a fourth resistor. Among them, The first end of the first resistor is electrically connected to the positive power supply terminal. The second end of the first resistor is electrically connected to the first input terminal of the core multiplexer and the collector of the third triode respectively. The base of the third triode is electrically connected to the base of the fourth triode and the output terminal of the first bias module respectively. The emitter of the third triode is electrically connected to the collector of the fifth triode. The base of the fifth triode is electrically connected to the emitter of the first triode. The emitter of the fifth triode is electrically connected to the first end of the third resistor. The second end of the third resistor is electrically connected to the third input terminal of the first tail current source module; The first end of the second resistor is electrically connected to the positive power supply terminal. The second end of the second resistor is electrically connected to the second input terminal of the core multiplexer and the collector of the fourth triode respectively. The emitter of the fourth triode is electrically connected to the collector of the sixth triode. The base of the sixth triode is electrically connected to the emitter of the second triode. The emitter of the sixth triode is electrically connected to the first end of the fourth resistor. The second end of the fourth resistor is electrically connected to the third input terminal of the first tail current source module.

5. The analog multiplexer according to claim 2, characterized in that, The first bias module includes a seventh triode, an eighth triode, a ninth triode, and a fifth resistor. The second bias module includes a thirteenth triode and a sixth resistor. The first tail current source module includes an eleventh triode, a twelfth triode, a thirteenth triode, a fourteenth triode, and a fifteenth triode. Among them, The first end of the fifth resistor is electrically connected to the positive power supply terminal. The second end of the fifth resistor is electrically connected to the collector and the base of the seventh triode. The emitter of the seventh triode is electrically connected to the collector and the base of the eighth triode. The emitter of the eighth triode is electrically connected to the collector of the ninth triode. The emitter of the ninth triode is electrically connected to the negative power supply terminal; The first end of the sixth resistor is electrically connected to the positive power supply terminal. The second end of the sixth resistor is electrically connected to the collector, the base of the thirteenth triode, the base of the ninth triode, the base of the eleventh triode, the base of the twelfth triode, and the base of the thirteenth triode respectively. The emitter of the thirteenth triode is electrically connected to the negative power supply terminal; The collector of the fourteenth triode is electrically connected to its base and the first output terminal of the first shift and isolation module respectively. The emitter of the fourteenth triode is electrically connected to the collector of the eleventh triode, and the emitter of the eleventh triode is electrically connected to the negative power supply terminal; the collector of the fifteenth triode is electrically connected to its base and the second output terminal of the first shift and isolation module respectively. The collector of the fifteenth triode is electrically connected to the collector of the twelfth triode, and the emitter of the twelfth triode is electrically connected to the negative power supply terminal; the collector of the thirteenth triode is electrically connected to the second output terminal of the first amplification module, and the emitter of the thirteenth triode is electrically connected to the negative power supply terminal.

6. The analog multiplexer according to claim 1, characterized in that, The triode included in the clock input buffer is a SiGe heterojunction bipolar transistor. The clock input buffer includes a second shift and isolation module, a second amplification module, a third shift and isolation module, a third amplification module, a fourth shift and isolation module, a third bias module, a fourth bias module and a second tail current source module. Among them, The input terminal of the second shift and isolation module is electrically connected to the output terminal of the clock signal module. The output terminal of the second shift and isolation module is electrically connected to the first input terminal of the second amplification module and the first input terminal of the second tail current source module respectively. The first output terminal of the second amplification module is electrically connected to the input terminal of the third shift and isolation module. The output terminal of the third shift and isolation module is electrically connected to the first input terminal of the third amplification module and the second input terminal of the second tail current source module respectively. The first output terminal of the third amplification module is electrically connected to the input terminal of the fourth shift and isolation module. The output terminal of the fourth shift and isolation module is electrically connected to the clock input terminal of the core multiplexer and the third input terminal of the second tail current source module respectively; the second output terminal of the second amplification module is electrically connected to the fourth input terminal of the second tail current source module; the second output terminal of the third amplification module is electrically connected to the fifth input terminal of the second tail current source module; The output terminal of the fourth bias module is electrically connected to the sixth input terminal of the second tail current source module and the input terminal of the third bias module respectively. The output terminal of the third bias module is electrically connected to the second input terminal of the second amplification module and the second input terminal of the third amplification module respectively.

7. The analog multiplexer according to claim 1, characterized in that, The triode included in the data output buffer is a SiGe heterojunction bipolar transistor. The data output buffer includes a fifth shift and isolation module, a fourth amplification module, a sixth shift and isolation module, a fifth amplification module, a fifth bias module, a sixth bias module and a third tail current source module. Among them, The input end of the fifth shift and isolation module is electrically connected to the output end of the core multiplexer. The output end of the fifth shift and isolation module is respectively electrically connected to the first input end of the fourth amplification module and the first input end of the third tail current source module. The first output end of the fourth amplification module is electrically connected to the input end of the sixth shift and isolation module. The output end of the sixth shift and isolation module is respectively electrically connected to the first input end of the fifth amplification module and the second input end of the third tail current source module. The first output end of the fifth amplification module is electrically connected to the input end of the optoelectronic device. The second output end of the fourth amplification module is electrically connected to the third input end of the third tail current source module. The fourth input end of the third tail current source module is electrically connected to the second output end of the fifth amplification module. The output end of the sixth bias module is respectively electrically connected to the fifth input end of the third tail current source module and the input end of the fifth bias module. The output end of the fifth bias module is respectively electrically connected to the second input end of the fourth amplification module and the second input end of the fifth amplification module.

8. The analog multiplexer according to claim 1, characterized in that, The triode included in the core multiplexer is a SiGe heterojunction bipolar transistor. The core multiplexer includes a first input module, a second input module, a switch control module, a seventh bias module, a fourth tail current source module, and a load module. Among them, The output end of the load module is respectively electrically connected to the first input end of the first input module, the first input end of the second input module, and the input end of the optoelectronic device. The output ends of the first input module and the second input module are respectively electrically connected to the first input end of the switch control module. The output end of the switch control module is electrically connected to the first input end of the fourth tail current source module. The second input end of the fourth tail current source module is electrically connected to the output end of the seventh bias module. The second input ends of the first input module and the second input module are respectively electrically connected to the output ends of a plurality of data input buffers in one-to-one correspondence. The second input end of the switch control module is electrically connected to the output end of the clock signal module.

9. The analog multiplexer according to claim 8, characterized in that, The load module includes a seventh resistor and an eighth resistor. The first input module includes a sixteenth triode, a seventeenth triode, a ninth resistor, and a tenth resistor. The second input module includes an eighteenth triode, a nineteenth triode, an eleventh resistor, and a twelfth resistor. Among them, The first end of the seventh resistor is electrically connected to the positive power supply. The second end of the seventh resistor is respectively electrically connected to the collector of the sixteenth triode, the collector of the eighteenth triode, and the first input end of the data output buffer. The emitter of the sixteenth triode is electrically connected to the first end of the ninth resistor. The second end of the ninth resistor is electrically connected to the first input end of the switch control module. The base of the sixteenth triode is electrically connected to the first output end of a data input buffer. The first end of the eighth resistor is electrically connected to the positive power supply. The second end of the eighth resistor is electrically connected to the collector of the seventeenth triode, the collector of the nineteenth triode, and the second input terminal of the data output buffer. The emitter of the seventeenth triode is electrically connected to the first end of the tenth resistor. The second end of the tenth resistor is electrically connected to the first input terminal of the switch control module. The base of the seventeenth triode is electrically connected to the second output terminal of a data input buffer. The base of the eighteenth triode is electrically connected to the first output terminal of another data input buffer. The emitter of the eighteenth triode is electrically connected to the first end of the eleventh resistor. The second end of the eleventh resistor is electrically connected to the second input terminal of the switch control module. The base of the nineteenth triode is electrically connected to the second output terminal of another data input buffer. The emitter of the nineteenth triode is electrically connected to the first end of the twelfth resistor. The second end of the twelfth resistor is electrically connected to the second input terminal of the switch control module.

10. The analog multiplexer according to claim 9, characterized in that, The switch control module includes a twenty-third triode, a twenty-first triode, a thirteenth resistor, and a fourteenth resistor. The seventh bias module includes a twenty-second triode and a fifteenth resistor. The fourth tail current source module is the twenty-third triode. Among them, The base of the twenty-third triode is electrically connected to the first output terminal of the clock input buffer. The emitter of the twenty-third triode is electrically connected to the first end of the thirteenth resistor. The second end of the thirteenth resistor is electrically connected to the collector of the twenty-third triode. The base of the twenty-first triode is electrically connected to the second output terminal of the clock input buffer. The emitter of the twenty-first triode is electrically connected to the first end of the fourteenth resistor. The second end of the fourteenth resistor is electrically connected to the collector of the twenty-third triode. The collector of the twenty-third triode is electrically connected to the second end of the ninth resistor and the second end of the tenth resistor respectively. The collector of the twenty-first triode is electrically connected to the second end of the eleventh resistor and the second end of the twelfth resistor respectively. The first end of the fifteenth resistor is electrically connected to the positive power supply. The second end of the fifteenth resistor is electrically connected to the collector, base of the twenty-second triode, and the base of the twenty-third triode. The emitter of the twenty-second triode is electrically connected to the negative power supply. The emitter of the twenty-third triode is electrically connected to the negative power supply.

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