Sampling method and device for source synchronous communication, terminal equipment and storage medium

Abstract

The invention discloses a sampling method and device for source synchronous communication, terminal equipment and a storage medium. The sampling method comprises the following steps: acquiring a Slave path initial delay value and a Master path initial delay value of a communication receiver; according to the initial delay value of the Slave path and the initial delay value of the Master path, window sweeping and ping-pong switching operation are repeatedly executed, when the time for executing the window sweeping and ping-pong switching operation is larger than a time threshold value, adjustment of a communication receiver is completed, and sampling of source synchronous communication is carried out based on the adjusted communication receiver. According to the invention, based on the burr-free data duration of the Slave path and the burr-free data duration of the Master path, the Slave path and the Master path are controlled to carry out switching output, thereby ensuring that the communication equipment can transmit stable burr-free transmission data, and improving the stability of data transmission when source synchronous communication is at an optimal sampling position.

Description

Technical Field

[0001] The present invention relates to the technical fields of data transmission, communication, and control, and particularly to a sampling method, device, terminal device, and storage medium for source synchronous communication. Background Art

[0002] Source synchronous communication is a common method for devices to communicate using Low-Voltage Differential Signaling (LVDS for short). This means that the clock is transmitted on one differential pair, the data is transmitted on one or several other differential pairs, and the clock is equal to the data stream frequency. At the receiver, the synchronous clock is used to capture the data, which is called source synchronous communication.

[0003] For source synchronous communication, the existing delay line scheme involves a window-sweeping calibration algorithm: using the underlying IO resources of the device to construct two copies of the received data, namely the Master and Slave paths. The Master path samples the real data, and the Slave path samples the monitored data. By adjusting the value of the delay line in the Slave path to perform window-sweeping to obtain the position of the sampling clock edge relative to the data bit, and then dynamically adjusting the value of the delay line in the Master path to adjust the position of the data bit to the optimal sampling point, that is, the position of the sampling clock edge is close to the middle area of the data bit.

[0004] As can be seen from the above, the prior art calibrates by adjusting the value of the delay line in the Master path. However, when adjusting the value of the delay line of different devices, glitches may be introduced into the data, resulting in incorrect data sampling, which is never allowed during the communication process. Therefore, the prior art cannot solve the problem of bit errors caused by glitches during the adjustment of the delay value, resulting in instability in the data transmission of source synchronous communication at the optimal sampling position.

[0005] Therefore, there is an urgent need for a sampling strategy for source synchronous communication to solve the problem of instability in the data transmission of source synchronous communication at the optimal sampling position. Summary of the Invention

[0006] Embodiments of the present invention provide a sampling method, device, terminal device, and storage medium for source synchronous communication to solve the problem of instability in the data transmission of source synchronous communication at the optimal sampling position.

[0007] To solve the above problems, an embodiment of the present invention provides a sampling method for source synchronous communication, including:

[0008] Obtaining the initial delay value of the Slave path and the initial delay value of the Master path of the communication receiver;

[0009] Repeat the window sweeping and ping-pong switching operations according to the initial delay value of the Slave path and the initial delay value of the Master path. When the time for performing the window sweeping and ping-pong switching operations is greater than the time threshold, complete the adjustment of the communication receiver, and perform source-synchronous communication sampling based on the communication receiver after the adjustment is completed.

[0010] Among them, use the initial delay value of the Slave path as the Slave path delay value for the first window sweeping and ping-pong switching operation, and use the initial delay value of the Master path as the Master path delay value for the first window sweeping and ping-pong switching operation; in each window sweeping and ping-pong switching operation, based on the delay line window sweeping operation, and the current Slave path delay value and Master path delay value, generate the glitch-free data duration of the Slave path and the glitch-free data duration of the Master path, and switch the output of the Slave path and the Master path according to the glitch-free data duration of the Slave path and the glitch-free data duration of the Master path.

[0011] As an improvement to the above solution, the window sweeping and ping-pong switching operation includes:

[0012] Based on the current Slave path delay value, perform a delay line window sweeping operation on the Slave path to obtain a first left offset and a first right offset;

[0013] According to the first left offset and the first right offset, through the delay value adjustment operation, determine the first optimal delay value of the current window sweeping and ping-pong switching operation, and adjust the current Slave path delay value of the Slave path to the first optimal delay value;

[0014] According to the obtained glitch-free data duration of the Slave path, switch the output of the Slave path to output the data collected by the Slave path, and adjust the current Master path delay value of the Master path to the first optimal delay value;

[0015] Based on the first optimal delay value of the Master path, perform a delay line window sweeping operation on the Master path to obtain a second left offset and a second right offset;

[0016] According to the second left offset and the second right offset, through the delay value adjustment operation, determine the second optimal delay value of the current window sweeping and ping-pong switching operation, and adjust the first optimal delay value of the Master path to the second optimal delay value of the current window sweeping and ping-pong switching operation;

[0017] According to the duration of the glitch-free data of the Master path obtained, switch the Master path to output the data collected by the Master path, and use the second best delay value of the current window sweep and ping-pong switching operations as the Slave path delay value and the Master path delay value for the next window sweep and ping-pong switching operations respectively;

[0018] Perform the next window sweep and ping-pong switching operations.

[0019] As an improvement to the above solution, the delay line window sweep operation includes:

[0020] Obtain input data;

[0021] Judge the input;

[0022] If the input data is the Slave path delay value, step up the delay value corresponding to the input data, and generate a first left offset when the data of the Slave path and the Master path at the same time are different; step down the delay value corresponding to the input data, and generate a first right offset when the data of the Slave path and the Master path at the same time are different;

[0023] If the input data is the first best delay value of the Master path, step up the delay value corresponding to the input data, and generate a second left offset when the data of the Slave path and the Master path at the same time are different; step down the delay value corresponding to the input data, and generate a second offset when the data of the Slave path and the Master path at the same time are different.

[0024] As an improvement to the above solution, the operation of adjusting the delay value includes:

[0025] Obtain offset data;

[0026] Judge the offset data;

[0027] If the offset data is the first left offset and the first right offset, calculate the first average value between the first left offset and the first right offset, and determine the first best delay value based on the first average value;

[0028] If the offset data is the second left offset and the second right offset, calculate the second average value between the second left offset and the second right offset, and determine the second best delay value based on the second average value.

[0029] As an improvement to the above solution, the operation of switching the Slave path to output the data collected by the Slave path according to the duration of the glitch-free data of the Slave path obtained includes:

[0030] According to the glitch-free data duration of the Slave path, when the glitch-free data duration is greater than the duration threshold, switch the output of the Slave path to the data collected by the Slave path.

[0031] As an improvement to the above solution, the step of switching the output of the Master path to the data collected by the Master path according to the obtained glitch-free data duration of the Master path includes:

[0032] According to the glitch-free data duration of the Master path, when the glitch-free data duration is greater than the duration threshold, switch the output of the Master path to the data collected by the Master path.

[0033] As an improvement to the above solution, the initial delay value of the Slave path and the initial delay value of the Master path are respectively the intermediate values of the delay lines configured by the user.

[0034] Correspondingly, an embodiment of the present invention further provides a sampling device for source synchronous communication, including: a data acquisition module and an adjustment module;

[0035] The data acquisition module is used to acquire the initial delay value of the Slave path and the initial delay value of the Master path of the communication receiver;

[0036] The adjustment module is used to repeatedly perform window sweeping and ping-pong switching operations according to the initial delay value of the Slave path and the initial delay value of the Master path. When the time for performing the window sweeping and ping-pong switching operations is greater than the time threshold, complete the adjustment of the communication receiver, and perform source synchronous communication sampling based on the communication receiver whose adjustment is completed;

[0037] Wherein, the initial delay value of the Slave path is used as the delay value of the Slave path for the first window sweeping and ping-pong switching operation, and the initial delay value of the Master path is used as the delay value of the Master path for the first window sweeping and ping-pong switching operation; in each window sweeping and ping-pong switching operation, based on the window sweeping operation of the delay line, as well as the current delay value of the Slave path and the delay value of the Master path, generate the glitch detection data and glitch-free data duration of the Slave path and the glitch detection data and glitch-free data duration of the Master path, and switch the outputs of the Slave path and the Master path according to the glitch detection data and glitch-free data duration of the Slave path and the glitch detection data and glitch-free data duration of the Master path.

[0038] Correspondingly, an embodiment of the present invention further provides a computer terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements a sampling method for source synchronous communication as described in the present invention.

[0039] Correspondingly, an embodiment of the present invention further provides a computer-readable storage medium. The computer-readable storage medium includes a stored computer program. When the computer program runs, it controls the device where the computer-readable storage medium is located to execute a sampling method for source synchronous communication as described in the present invention.

[0040] As can be seen from the above, the present invention has the following beneficial effects:

[0041] The present invention provides a sampling method for source synchronous communication, which performs window sweeping and ping-pong switching operations on the obtained initial delay values of the Slave path and the Master path. Each time the window sweeping and ping-pong switching operations are executed, based on the window sweeping operation of the delay line and the current delay values of the Slave path and the Master path, it ensures that the Slave path and the Master path are in the optimal sampling positions. By the duration of the glitch-free data of the Slave path and the duration of the glitch-free data of the Master path, glitch detection of the Slave path and the Master path is realized, and based on the duration of the glitch-free data of the Slave path and the duration of the glitch-free data of the Master path, the Slave path and the Master path are controlled to perform switching output, thereby ensuring that the communication device can transmit stable and glitch-free transmission data, and improving the stability of data transmission in the optimal sampling position of source synchronous communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a schematic flowchart of a sampling method for source synchronous communication provided by an embodiment of the present invention;

[0043] Figure 2 is a schematic structural diagram of a sampling device for source synchronous communication provided by an embodiment of the present invention;

[0044] Figure 3 is a schematic structural diagram of a terminal device provided by an embodiment of the present invention;

[0045] Figure 4 is a schematic diagram of the glitch introduced by the time value adjustment provided by an embodiment of the present invention;

[0046] Figure 5 is a schematic diagram of the dynamic switching of the Master path and the Slave path provided by an embodiment of the present invention;

[0047] Figure 6 It is a schematic flowchart of a sampling method for source synchronous communication provided by another embodiment of the present invention;

[0048] Figure 7 It is a schematic structural diagram of a communication receiver provided by an embodiment of the present invention;

[0049] Figure 8 It is a schematic flowchart of a delay line window sweeping operation provided by an embodiment of the present invention;

[0050] Figure 9 It is a schematic flowchart of a window sweeping and ping-pong switching operation provided by an embodiment of the present invention. Detailed implementation manners

[0051] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0052] Embodiment 1

[0053] Refer to Figure 1 , Figure 1 which is a schematic flowchart of a sampling method for source synchronous communication provided by an embodiment of the present invention. As Figure 1 shown, this embodiment includes steps 101 to 102, and the specific steps are as follows:

[0054] Step 101: Obtain the initial delay value of the Slave path and the initial delay value of the Master path of the communication receiver.

[0055] In this embodiment, the initial delay value of the Slave path and the initial delay value of the Master path are respectively the intermediate values of the delay lines configured by the user.

[0056] For better illustration, refer to Figure 4 , when the delay value of the device delayline component is adjusted, the output data may introduce glitches in a relatively short time subsequently, which may lead to incorrect data sampling, and this is absolutely not allowed during the data transmission process.

[0057] Step 102: According to the initial delay value of the Slave path and the initial delay value of the Master path, repeatedly execute the window sweeping and ping-pong switching operations. When the time for executing the window sweeping and ping-pong switching operations is greater than the time threshold, complete the adjustment of the communication receiver, and perform sampling for source synchronous communication based on the communication receiver after the adjustment is completed;

[0058] Among them, the initial delay value of the Slave path is used as the delay value of the Slave path for the first window sweeping and ping-pong switching operation, and the initial delay value of the Master path is used as the delay value of the Master path for the first window sweeping and ping-pong switching operation; in each window sweeping and ping-pong switching operation, based on the delay line window sweeping operation, and the current delay values of the Slave path and the Master path, the duration of glitch-free data of the Slave path and the duration of glitch-free data of the Master path are generated, and the Slave path and the Master path are switched and output according to the duration of glitch-free data of the Slave path and the duration of glitch-free data of the Master path.

[0059] As an improvement to the above solution, the window sweeping and ping-pong switching operation includes:

[0060] Based on the current delay value of the Slave path, perform a delay line window sweeping operation on the Slave path to obtain a first left offset and a first right offset;

[0061] According to the first left offset and the first right offset, through a delay value adjustment operation, determine the first optimal delay value of the current window sweeping and ping-pong switching operation, and adjust the current delay value of the Slave path of the Slave path to the first optimal delay value;

[0062] According to the obtained duration of glitch-free data of the Slave path, switch the Slave path to output the data collected by the Slave path, and adjust the current delay value of the Master path of the Master path to the first optimal delay value;

[0063] Based on the first optimal delay value of the Master path, perform a delay line window sweeping operation on the Master path to obtain a second left offset and a second right offset;

[0064] According to the second left offset and the second right offset, through a delay value adjustment operation, determine the second optimal delay value of the current window sweeping and ping-pong switching operation, and adjust the first optimal delay value of the Master path to the second optimal delay value of the current window sweeping and ping-pong switching operation;

[0065] According to the obtained duration of glitch-free data of the Master path, switch the Master path to output the data collected by the Master path, and use the second optimal delay value of the current window sweeping and ping-pong switching operation as the delay value of the Slave path for the next window sweeping and ping-pong switching operation and the delay value of the Master path for the next window sweeping and ping-pong switching operation respectively;

[0066] Execute the next window sweeping and ping-pong switching operation.

[0067] As an improvement to the above solution, the delayed line sweep window operation includes:

[0068] Obtain input data;

[0069] Judge the input;

[0070] If the input data is the Slave path delay value, step up the delay value corresponding to the input data. When the data of the Slave path and the Master path at the same time are different, generate a first left offset; step down the delay value corresponding to the input data. When the data of the Slave path and the Master path at the same time are different, generate a first right offset;

[0071] If the input data is the first optimal delay value of the Master path, step up the delay value corresponding to the input data. When the data of the Slave path and the Master path at the same time are different, generate a second left offset; step down the delay value corresponding to the input data. When the data of the Slave path and the Master path at the same time are different, generate a second offset.

[0072] As an improvement to the above solution, the operation of adjusting the delay value includes:

[0073] Obtain offset data;

[0074] Judge the offset data;

[0075] If the offset data is the first left offset and the first right offset, calculate the first average value between the first left offset and the first right offset, and determine the first optimal delay value based on the first average value;

[0076] If the offset data is the second left offset and the second right offset, calculate the second average value between the second left offset and the second right offset, and determine the second optimal delay value based on the second average value.

[0077] As an improvement to the above solution, the operation of switching the Slave path to output the data collected by the Slave path according to the obtained duration of the glitch-free data of the Slave path includes:

[0078] According to the duration of the glitch-free data of the Slave path, when the duration of the glitch-free data is greater than the duration threshold, switch the Slave path to output the data collected by the Slave path.

[0079] As an improvement to the above solution, the operation of switching the Master path to output the data collected by the Master path according to the obtained duration of the glitch-free data of the Master path includes:

[0080] According to the duration of the glitch-free data on the Master path, when the duration of the glitch-free data is greater than the duration threshold, switch the output of the Master path to the data collected by the Master path.

[0081] In this embodiment, the transmitted data is matched with a preset glitch data feature library. The transmitted data segments that match successfully are identified as glitches, and the number of glitches included in the entire transmitted data is counted as the glitch detection data.

[0082] In a specific embodiment, the glitch threshold can be 0.

[0083] In a specific embodiment, to solve the problem of error codes caused by glitches during the adjustment of the delay value, the present invention adopts an algorithm that combines delay line window scanning and two-branch ping-pong switching calibration. The principle of the solution is as Figure 5 and Figure 6 shown. The local sampling clock is derived from the clock on the same path. The local sampling clock is related to the frequency of the captured serial data stream but not to the phase. The real data is sampled on the Master branch, and the monitoring data is sampled on the Slave branch. The solution process is as follows:

[0084] 1. Set the initial delay value of the Slave path and the initial delay value of the Master path to the middle value of the delay line. It should be noted that: the delay line is a built-in hardcore unit resource of the device, and generally the user configures the delay line value for application.

[0085] 2. The Slave path starts to increase step by step from the current initial delay value. When the data on the Master path and the data on the Slave path are equal, continue to increase the delay of the Slave path step by step. Stop when the delay of the Slave path increases step by step through the jitter region between two monitoring data bits at the clock edge. The data on the Master path and the data on the Slave path are no longer equal. At this time, subtract the initial value from the delay value to obtain left_margin (i.e., the first left offset. When the processing object changes from the Slave path to the Master path, this is the second left offset), that is, the position of the clock edge relative to the left edge of the real data bit on the Master path. Similarly, the right_margin (i.e., the first right offset. When the processing object changes from the Slave path to the Master path, this is the second right offset) can be obtained by decreasing the delay of the Slave path step by step from the initial delay value. That is, the position of the clock edge relative to the data bit edge is obtained by scanning the window on the left and right. It should be noted that: from the perspective of data processing, the jitter region of the monitoring data bit is identified based on the encoded data or pseudo-random code data; this means that in the long run, the encoded data is DC balanced, and the number of 1s and 0s should each account for 50%.

[0086] 3. Calculate the best delay position based on left_margin and right_margin to ensure left_magin=right_magin, adjust the Slave path delay value to the best delay position best_delay_value (i.e., the first best delay value, when the object to be processed changes from Slave path to Master path, it is the second best delay value at this time), so that the position of the data sampling clock edge is close to the middle area of ​​the data bit.

[0087] 4. After the slave data is stable and glitch-free, the master and slave channels are switched: (the delay line is a hard-core unit resource of the device. Due to the characteristics of some devices, glitches will be introduced in a short period of time when the delay line value is adjusted. It only takes a period of time longer than this period of time according to the device characteristics to ensure that the data is stable and glitch-free).

[0088] 1) The Slave route is converted to the Master route. At this time, the Slave route that serves as the Master route outputs the real and stable data to the next-level application;

[0089] 2) The Master road is converted to a Slave road, and the delay value of the Master road serving as the Slave road is adjusted to best_delay_value. After the Master road is adjusted to the Slave road, execute step 5.

[0090] It should be noted that the condition for converting the Master route to the Slave route is that the line conversion is automatically triggered after the real stable data is sent; the ping-pong switching adjustment between the Master route and the Slave route needs to meet two conditions. One is to meet the adjustment to the optimal delay position in step 3 to ensure left_magin=right_magin, and the other is to meet the need to wait for the data to be stable without glitch time greater than the glitch time introduced when adjusting the delay line value (that is, the duration threshold). As long as there is no glitch in the transmitted data that successfully matches the preset glitch data feature library, it means that there is no glitch.

[0091] 5. Repeat steps 2 to 4 above.

[0092] The Master and Slave paths are constantly ping-pong switched throughout the entire process, and each time the switch is made after the Slave path is adjusted to the optimal delay position and the data is stable and glitch-free; the Master path data is stable in each calibration cycle, cleverly avoiding the glitch problem while ensuring that the sampling clock is always at the optimal sampling point, that is, the middle area of ​​the data bit. This embodiment ignores changes in the external environment and can adapt to high-speed data transmission scenarios, improving the stability and reliability of data transmission.

[0093] The present invention ignores changes in the external environment and can adapt to high-speed data transmission scenarios, thereby improving the stability and reliability of data transmission.

[0094] In a specific embodiment, 1.25 Gbps synchronous communication is taken as an implementation case, which is as follows:

[0095] This implementation case is based on the delay-controllable IO and serial-to-parallel conversion hardcore unit resources of the device. As Figure 7 shown, the detailed information of the corresponding circuit of the communication receiver is displayed. Among them, the serial-to-parallel conversion hardcore unit is configured in the iDDRx5 mode, and the serial-to-parallel conversion ratio is 1:10; the initial delay value of the IO input delay unit is set at the middle position of the delay line;

[0096] 1) The function of the Sample window monitor circuit is to continuously perform the window sweeping operation on the delay line to obtain the left_margin and right_margin, so that the Calibration circuit can calculate the best delay position best_delay_value. For details, see Figure 8 ;

[0097] 2) The function of the Calibration circuit is to calculate the best delay position best_delay_value according to the left_margin and right_margin values, and perform the window sweeping and ping-pong switching operations on the Master path and Slave path channels. For details, see Figure 9 。

[0098] As Figure 8 shown, the processing flow of the ample_window_monitor circuit is as follows:

[0099] 1. Each time when powering on or resetting, the initial delay values of the Master path and Slave path are set at the middle value of the delay line. Except for the first window sweeping, the initial delay value is set to the best delay value calculated in the previous calibration cycle.

[0100] 2. When using the window sweeping operation of the delay line, the Slave path starts from the initial delay value and steps forward incrementally until the data of the Master path and the Slave path are not equal. At this time, subtract the initial delay value from the current delay value to obtain the left_margin, which is the position of the clock edge relative to the left edge of the data bit.

[0101] 3. Similarly, the Slave path steps backward from the initial delay value to obtain the right_magin.

[0102] 4. The finally obtained left_magin and right_margin represent the position of the sampling clock edge relative to the data bit edge, and are output to the calibration module for further calibration processing.

[0103] 5. Return to the initial state and wait for the calibration circuit to complete calibration before performing the next window scanning process.

[0104] As Figure 9 shown, the processing flow of the Calibration circuit is as follows:

[0105] 1. The Master path performs initialization calibration according to the window scanning result. When left_magin ≠ right_magin, the delay value is traversed and adjusted until left_magin = right_magin to complete the initialization calibration. It shows that data transmission can ensure absolute stability and reliability after initialization is completed.

[0106] 2. Perform the next step of processing according to the window scanning result in the idle state: when left_magin = right_magin, stay in the current state; when left_magin ≠ right_magin, perform the next calibration process.

[0107] 3. Calculate the best delay position best_delay_value based on the left_margin and right_margin values obtained from window scanning to ensure left_magin = right_magin, and adjust the delay value of the Slave path to the best delay position best_delay_value, so that the position of the data sampling clock edge is close to the middle area of the data bit.

[0108] 4. After the data of the Slave path is stable and free of glitches, switch the channels of the Master path and the Slave path:

[0109] 1) The Slave path is converted to the Master path to output real and stable data rx_data;

[0110] 2) The Master path is converted to the Slave path and the delay value is adjusted to best_delay_value;

[0111] 5. Repeat the above steps 2 to 4.

[0112] See Figure 2 , Figure 2 FIG.

[0113] The data acquisition module is used to acquire the initial delay value of the Slave path and the initial delay value of the Master path of the communication receiver;

[0114] The adjustment module is configured to repeatedly perform window sweeping and ping-pong switching operations according to the Slave path initial delay value and the Master path initial delay value. When the time for performing the window sweeping and ping-pong switching operations is greater than the time threshold, the adjustment of the communication receiver is completed, and sampling for source synchronous communication is performed based on the communication receiver after the adjustment is completed.

[0115] Among them, the Slave path initial delay value is used as the Slave path delay value for the first window sweeping and ping-pong switching operation, and the Master path initial delay value is used as the Master path delay value for the first window sweeping and ping-pong switching operation; in each window sweeping and ping-pong switching operation, based on the delay line window sweeping operation, as well as the current Slave path delay value and Master path delay value, the glitch-free data duration of the Slave path and the glitch-free data duration of the Master path are generated, and the Slave path and the Master path are switched and output according to the glitch-free data duration of the Slave path and the glitch-free data duration of the Master path.

[0116] It can be understood that the above system item embodiments correspond to the method item embodiments of the present invention, and can implement the sampling method for source synchronous communication provided by any one of the above method item embodiments of the present invention.

[0117] In this embodiment, by performing window sweeping and ping-pong switching operations on the obtained Slave path initial delay value and Master path initial delay value, in each execution of the window sweeping and ping-pong switching operation, based on the delay line window sweeping operation, as well as the current Slave path delay value and Master path delay value, it is ensured that the Slave path and the Master path are in the best sampling positions, and glitch detection of the Slave path and the Master path is achieved through the glitch-free data duration of the Slave path and the glitch-free data duration of the Master path, and the Slave path and the Master path are controlled to be switched and output based on the glitch-free data duration of the Slave path and the glitch-free data duration of the Master path, thereby ensuring that the communication device can transmit stable glitch-free transmission data and improving the stability of data transmission in source synchronous communication at the best sampling position.

[0118] Embodiment 2

[0119] See Figure 3 , Figure 3 which is a schematic structural diagram of a terminal device provided by an embodiment of the present invention.

[0120] A terminal device in this embodiment includes: a processor 301, a memory 302, and a program stored in the memory 302 and executable on the processor 301. When the processor 301 executes the program, it implements the steps in the above-described various sampling methods for source synchronous communication in the embodiment, such as Figure 1 all the steps of the sampling method for source synchronous communication shown. Alternatively, when the processor executes the program, it implements the functions of each module in the above-described device embodiments, such as: Figure 2 all the modules of the sampling device for source synchronous communication shown.

[0121] In addition, an embodiment of the present invention further provides a computer-readable storage medium, which includes a stored computer program. When the computer program runs, it controls the device where the computer-readable storage medium is located to execute the sampling method for source synchronous communication described in any one of the above embodiments.

[0122] Those skilled in the art can understand that the schematic diagram is only an example of the terminal device, and does not constitute a limitation on the terminal device. It may include more or fewer components than shown, or combine some components, or different components. For example, the terminal device may further include input / output devices, network access devices, buses, etc.

[0123] The so-called processor 301 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The processor 301 is the control center of the terminal device, and connects various parts of the entire terminal device through various interfaces and lines.

[0124] The memory 302 can be used to store the computer programs and / or modules. By running or executing the computer programs and / or modules stored in the memory, and by invoking the data stored in the memory 302, the processor 301 realizes various functions of the terminal device. The memory 302 may mainly include a program storage area and a data storage area. Among them, the program storage area may store an operating system, application programs required for at least one function (such as a sound playback function, an image playback function, etc.); the data storage area may store data created according to the use of the mobile phone (such as audio data, phone book, etc.). In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0125] Among them, if the modules / units integrated in the terminal device are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, to implement all or part of the processes in the above-mentioned embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-mentioned various method embodiments can be realized. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disc, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0126] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the attached drawings of the device embodiments provided by the present invention, the connection relationships between the modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those of ordinary skill in the art can understand and implement without creative efforts.

[0127] The above is the preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A sampling method for source synchronous communication, characterized in that: include: Obtain the initial delay value of the slave path and the initial delay value of the master path of the communication receiver; According to the initial delay value of the slave path and the initial delay value of the master path, repeatedly performing window sweeping and ping-pong switching operations, when the time for performing the window sweeping and ping-pong switching operations is greater than a time threshold, completing the adjustment of the communication receiver, and performing source synchronous communication sampling based on the communication receiver that has completed the adjustment; Among them, the initial delay value of the Slave road is used as the Slave road delay value for the first window scanning and ping-pong switching operation, and the initial delay value of the Master road is used as the Master road delay value for the first window scanning and ping-pong switching operation; in each window scanning and ping-pong switching operation, based on the delay line window scanning operation, and the current Slave road delay value and Master road delay value, the glitch-free data duration of the Slave road and the glitch-free data duration of the Master road are generated, and according to the glitch-free data duration of the Slave road and the glitch-free data duration of the Master road, the Slave road and the Master road are switched and output.

2. The sampling method for source synchronous communication according to claim 1, characterized in that: The window scanning and ping-pong switching operations include: Based on the current Slave road delay value, perform a delay line window scanning operation on the Slave road to obtain a first left offset and a first right offset; According to the first left offset and the first right offset, a first optimal delay value of the current window scanning and ping-pong switching operation is determined through a delay value adjustment operation, and the current Slave path delay value of the Slave path is adjusted to the first optimal delay value; According to the acquired glitch-free data duration of the Slave road, the Slave road is switched to output the data collected by the Slave road, and the current Master road delay value of the Master road is adjusted to the first optimal delay value; Based on the first optimal delay value of the Master road, a delay line window scanning operation is performed on the Master road to obtain a second left offset and a second right offset; According to the second left offset and the second right offset, a second optimal delay value of the current window scanning and ping-pong switching operation is determined through a delay value adjustment operation, and the first optimal delay value of the Master path is adjusted to the second optimal delay value of the current window scanning and ping-pong switching operation; According to the obtained glitch-free data duration of the Master road, the Master road is switched to output the data collected by the Master road, and the second best delay value of the current window scanning and ping-pong switching operation is used as the Slave road delay value of the next window scanning and ping-pong switching operation and the Master road delay value of the next window scanning and ping-pong switching operation respectively; Execute the next window scan and ping-pong switching operation.

3. The sampling method for source synchronous communication according to claim 2, characterized in that: The delay line window scanning operation includes: Get input data; Judge the input; If the input data is a delay value of a slave path, the delay value corresponding to the input data is increased step by step, and when the data of the slave path and the master path at the same time are different, a first left offset is generated; the delay value corresponding to the input data is decreased step by step, and when the data of the slave path and the master path at the same time are different, a first right offset is generated; If the input data is the first optimal delay value of the Master path, the delay value corresponding to the input data is increased in steps, and when the data of the Slave path and the Master path at the same time are different, a second left offset is generated; the delay value corresponding to the input data is decreased in steps, and when the data of the Slave path and the Master path at the same time are different, a second offset is generated.

4. The sampling method for source synchronous communication according to claim 3, characterized in that: The delay value adjustment operation includes: Get offset data; Determine the offset data; If the offset data is a first left offset and a first right offset, a first average value between the first left offset and the first right offset is calculated, and a first optimal delay value is determined based on the first average value; If the offset data is a second left offset and a second right offset, a second average value between the second left offset and the second right offset is calculated, and a second optimal delay value is determined based on the second average value.

5. The sampling method for source synchronous communication according to claim 4, characterized in that: The step of switching the Slave path to output the data collected by the Slave path according to the acquired glitch-free data duration of the Slave path includes: According to the glitch-free data duration of the Slave path, when the glitch-free data duration is greater than the duration threshold, the Slave path is switched to output the data collected by the Slave path.

6. The sampling method for source synchronous communication according to claim 5, characterized in that: The step of switching the Master path to output the data collected by the Master path according to the acquired glitch-free data duration of the Master path includes: According to the glitch-free data duration of the Master path, when the glitch-free data duration is greater than a duration threshold, the Master path is switched to output the data collected by the Master path.

7. The sampling method for source synchronous communication according to claim 6, characterized in that: The initial delay value of the slave path and the initial delay value of the master path are respectively the middle values ​​of the delay lines configured by the user.

8. A sampling device for source synchronous communication, characterized in that: include: Data acquisition module and adjustment module; The data acquisition module is used to acquire the initial delay value of the Slave path and the initial delay value of the Master path of the communication receiver; The adjustment module is used to repeatedly perform window sweeping and ping-pong switching operations according to the initial delay value of the Slave path and the initial delay value of the Master path, complete the adjustment of the communication receiver when the time for performing the window sweeping and ping-pong switching operations is greater than the time threshold, and perform source synchronous communication sampling based on the communication receiver that has completed the adjustment; Among them, the initial delay value of the Slave road is used as the Slave road delay value for the first window scanning and ping-pong switching operation, and the initial delay value of the Master road is used as the Master road delay value for the first window scanning and ping-pong switching operation; in each window scanning and ping-pong switching operation, based on the delay line window scanning operation, and the current Slave road delay value and Master road delay value, the glitch-free data duration of the Slave road and the glitch-free data duration of the Master road are generated, and according to the glitch-free data duration of the Slave road and the glitch-free data duration of the Master road, the Slave road and the Master road are switched and output.

9. A terminal device, characterized in that: The system comprises a processor, a memory, and a program stored in the memory and configured to be executed by the processor, wherein when the processor executes the program, a sampling method for source synchronous communication according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute a sampling method for source synchronous communication according to any one of claims 1 to 7.

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